Storage device and control method and control device thereof

Abstract

The embodiment of the present invention discloses a storage device and a control method and a control device thereof. The storage device includes a plurality of storage chips. The control method includes: if at least two first operation instructions are received, determining at least two storage chips to be operated corresponding to the at least two first operation instructions; and controlling at least two storage chips to be operated to execute the corresponding first operation instructions in time-sharing. In the embodiment of the present invention, the first operation instructions are executed in time-sharing, and the time periods of peak currents of different storage chips are shifted, so that the problem of peak current superposition caused by the simultaneous operation of multiple storage chips will not occur, and the peak current of the storage device is effectively reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to storage technology, and more particularly to a storage device and a control method and a control apparatus thereof. Background Art

[0002] eMMC (Embedded Multi Media Card) chips are embedded memories mainly for mobile phones or tablets. The eMMC chip integrates a controller that provides a standard interface and manages flash memory, so that mobile phone manufacturers using eMMC chips can focus on other parts of product development and shorten the time to market.

[0003] The eMMC chip is mainly composed of a controller and flash memory particles. Data is stored in the flash memory particles through write operations and read from the flash memory particles through read operations. The mainstream flash memory in the market is NAND flash, which has the advantages of small size, large capacity, and fast rewrite speed. It is suitable for storing large amounts of data and has been increasingly widely used in the industry.

[0004] Existing eMMC chips are mainly packaged using multi-chip stacking technology, which can realize programming operations on multiple flash memory particles at the same time. When multiple flash memory particles are programmed at the same time, the peak current generated by the eMMC chip at the beginning of charging is the sum of the peak currents generated by multiple flash memory particles at the beginning of charging, resulting in excessive peak current of the eMMC chip. Summary of the invention

[0005] The embodiment of the present invention provides a storage device and a control method and a control device thereof, so as to reduce the peak current of an eMMC chip.

[0006] An embodiment of the present invention provides a control method for a storage device, wherein the storage device includes a plurality of storage chips, and the control method includes:

[0007] If at least two first operation instructions are received, determining at least two storage chips to be operated corresponding to the at least two first operation instructions;

[0008] The at least two storage chips to be operated are controlled to execute the corresponding first operation instruction in a time-sharing manner.

[0009] Furthermore, the two first operation instructions are both erase operation instructions or program operation instructions.

[0010] Furthermore, one of the two first operation instructions is an erase operation instruction, and the other is a program operation instruction.

[0011] Furthermore, before determining at least two storage chips to be operated corresponding to the at least two first operation instructions, the method further includes: controlling the switching to a peak current reduction mode.

[0012] Further, controlling the at least two storage chips to be operated to execute the corresponding first operation instruction in a time-sharing manner includes:

[0013] Generate and output a restart instruction according to a set rule, triggering the storage chip to be operated to execute the i-th operation of the corresponding first operation instruction, i=1, 2, 3, . . .

[0014] Furthermore, the setting rule includes: at least one operation start time of at least two of the storage chips to be operated is different.

[0015] Further, controlling the at least two storage chips to be operated to execute the corresponding first operation instruction in a time-sharing manner includes:

[0016] The at least two storage chips to be operated are controlled to execute the first operation of the corresponding first operation instruction in time-sharing.

[0017] Based on the same inventive concept, an embodiment of the present invention further provides a control device for a storage device, wherein the storage device includes a plurality of storage chips, and the control device includes:

[0018] A chip determination module, configured to determine at least two storage chips to be operated corresponding to the at least two first operation instructions if at least two first operation instructions are received;

[0019] The operation control module is used to control the at least two storage chips to be operated to execute the corresponding first operation instruction in a time-sharing manner.

[0020] Furthermore, the two first operation instructions are both erase operation instructions or program operation instructions.

[0021] Furthermore, one of the two first operation instructions is an erase operation instruction, and the other is a program operation instruction.

[0022] Furthermore, the chip determination module includes: a mode switching unit, which is used to control switching to a peak current reduction mode before determining at least two storage chips to be operated corresponding to the at least two first operation instructions.

[0023] Furthermore, the operation control module includes:

[0024] The restart trigger unit is used to generate and output a restart instruction according to a set rule, triggering the storage chip to be operated to perform the i-th operation of the corresponding first operation instruction, i=1, 2, 3,...

[0025] Furthermore, the setting rule includes: at least one operation start time of at least two of the storage chips to be operated is different.

[0026] Furthermore, the operation control module includes:

[0027] The first operating unit is used to control the at least two storage chips to be operated to perform the first operation of the corresponding first operating instruction in time-sharing.

[0028] Based on the same inventive concept, an embodiment of the present invention further provides a storage device, including:

[0029] one or more processors;

[0030] A storage module, used for storing one or more programs;

[0031] When the one or more programs are executed by the one or more processors, the one or more processors implement the control method of the storage device as described above.

[0032] In the embodiment of the present invention, if at least two first operation instructions are received, at least two storage chips to be operated corresponding to the at least two first operation instructions are determined, and the at least two storage chips to be operated are controlled to execute the corresponding first operation instructions in time-sharing. In the embodiment of the present invention, the first operation instructions are executed in time-sharing, and the time periods of peak currents of different storage chips are shifted, so the problem of peak current superposition caused by simultaneous operation of multiple storage chips will not occur, and the peak current of the storage device is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 is a schematic diagram of a storage device provided by an embodiment of the present invention;

[0035] Figure 2 is a flow chart of a storage device control method provided by an embodiment of the present invention;

[0036] Figure 3 is a schematic diagram of a storage device control method provided by an embodiment of the present invention;

[0037] Figure 4 is a schematic diagram of a control device for a storage device provided by an embodiment of the present invention;

[0038] Figure 5 A schematic diagram of a programming method provided by the prior art. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described through implementation methods with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] refer to Figure 1 FIG. 1 is a schematic diagram of a storage device provided by an embodiment of the present invention, referring to FIG. Figure 2 As shown, it is a flow chart of a control method of a storage device provided in an embodiment of the present invention. The storage device provided in this embodiment can be optionally a storage device integrated with multiple storage chips, such as an eMMC chip integrated with multiple Nand flashes. The storage device provided in this embodiment includes multiple storage chips 1, and the storage chip 1 includes multiple physical blocks. The control device 2 in the storage device performs an operation on at least one storage chip 1 according to the operation instruction input by the user. The control device 2 can be implemented in software and / or hardware, and the control device 2 is used to execute the control method of the storage device.

[0041] The control method of the storage device provided in this embodiment specifically includes the following steps:

[0042] S1. If at least two first operation instructions are received, determine at least two storage chips to be operated corresponding to the at least two first operation instructions.

[0043] In this embodiment, the memory chip in the optional storage device is packaged using a multi-chip stacking technology. At this time, the user can input multiple operation instructions at the same time. The memory chip addresses carried in the multiple operation instructions are different, and the control device can implement operations on multiple memory chips. The first operation instruction includes a memory chip address and operation data. The memory chip address is the address of the memory chip to be operated, and the operation data is the data to be operated. The control device can address the corresponding memory chip to be operated according to the first operation instruction and perform the corresponding operation. In this embodiment, the memory chip addresses of at least two first operation instructions received by the control device are different and the operation data may be different. For example, three first operation instructions are received, and the content of one first operation instruction is to write data data1 into chip M, and the content of another first operation instruction is to write data data8 into chip B, and the content of the last first operation instruction is to write data data5 into chip E.

[0044] S2. Control at least two storage chips to be operated to execute the corresponding first operation instruction in time-sharing.

[0045] In this embodiment, the control device can address at least two storage chips to be operated corresponding to the at least two first operation instructions according to the received at least two first operation instructions, and then the control device will execute each first operation instruction in a time-sharing manner.

[0046] like Figure 3 As shown, the control device receives 4 first operation instructions at the same time, the first first operation instruction is cmd:80h+chip1addr1+data1+cmd:10h, the second first operation instruction is cmd:80h+chip2addr2+data2+cmd:10h, the third first operation instruction is cmd:80h+chip3addr3+data3+cmd:10h, and the fourth first operation instruction is cmd:80h+chip4addr4+data4+cmd:10h. Among them, cmd:80h+…+cmd:10h represents the programming instruction, chip addr represents the storage chip address, and data represents the data to be programmed. Obviously, the control device executes the 4 first operation instructions in time-sharing.

[0047] It is known that when each memory chip is programmed, the memory device will generate a large peak current at the beginning of programming charging, and when multiple memory chips are programmed at the same time, the peak current of the memory device is the sum of the peak currents generated by multiple memory chips. Figure 5 The figure shows a programming diagram provided by the prior art. In each program loop stage, the storage device controls chips 1 to 4 to simultaneously perform corresponding programming operations. The peak current of the storage device in the program loop 0 stage is ICC1+ICC2+ICC3+ICC4, where ICC1 is the peak current of chip 1 in the program loop 0 stage, ICC2 is the peak current of chip 2 in the program loop 0 stage, ICC3 is the peak current of chip 3 in the program loop 0 stage, and ICC4 is the peak current of chip 4 in the program loop 0 stage. Similarly, the peak current of the storage device in the program loop 1 stage and the peak current of the storage device in the program loop 2 stage can be obtained.

[0048] In this embodiment, Figure 3When the control device shown receives four first operation instructions, it executes the four first operation instructions in time-sharing, so that the charging start phases of the four storage chips do not overlap. For example, chip1 first enters the programming charging start phase, at which time the peak current of the storage device is equal to the peak current of chip1; chip2 then enters the programming charging start phase, at which time the charging start phase of chip1 has ended, and the peak current of the storage device is equal to the peak current of chip2; chip3 then enters the programming charging start phase, at which time the charging start phases of chips1 and 2 have ended, and the peak current of the storage device is equal to the peak current of chip3; chip4 finally enters the programming charging start phase, at which time the charging start phases of chips1 to 3 have ended, and the peak current of the storage device is equal to the peak current of chip4. Obviously, executing the first operation instruction in time-sharing can significantly reduce the peak current of the storage device.

[0049] The control method of the storage device provided in this embodiment, if receiving at least two first operation instructions, determines at least two storage chips to be operated corresponding to the at least two first operation instructions, and controls the at least two storage chips to be operated to execute the corresponding first operation instructions in time-sharing. In this embodiment, the first operation instructions are executed in time-sharing, and the time periods of peak currents of different storage chips are shifted, so that the problem of peak current superposition caused by the simultaneous operation of multiple storage chips will not occur, and the peak current of the storage device is effectively reduced.

[0050] Exemplarily, based on the above technical solution, two first operation instructions can be selected to be erase operation instructions or programming operation instructions. One of the two first operation instructions can be an erase operation instruction and the other can be a programming operation instruction. It should be noted that the multiple first operation instructions simultaneously received by the control device can be selected to be erase operation instructions, or all programming operation instructions, or one of them can be an erase operation instruction and the other can be a programming operation instruction.

[0051] Optionally, before determining at least two storage chips to be operated corresponding to at least two first operation instructions, it also includes: controlling the switch to reduce peak current mode. In this embodiment, a command CMD1 is introduced to control whether the mode of the current storage device is set to reduce peak current mode (reducepeak current, RPC). An RPC mode is set in each storage device, and the RPC mode of each storage device is in an invalid mode in the initial state. When the storage device is a multi-chip stacked package, the storage device can operate multiple storage chips at the same time. In order to reduce the peak current, the control device of the storage device will generate a command CMD1 to convert the RPC mode to a valid mode, that is, the storage device is switched to reduce peak current mode, and the subsequent process is time-sharing controlled to execute multiple first operation instructions.

[0052] Optionally, controlling at least two storage chips to be operated to execute the corresponding first operation instruction in time-sharing includes: generating and outputting a restart instruction according to a set rule, triggering the storage chip to be operated to execute the i-th operation of the corresponding first operation instruction, i=1,2,3,…. The optional setting rules include: at least one operation start time of at least two storage chips to be operated is different. In this embodiment, a restart instruction CMD2 is also introduced, and CMD2 is used to control the start of the next operation cycle. For example, when a programming instruction is issued, it may be necessary to execute multiple programming loops to allow all data to be written into the storage chip, and a programming loop is a program loop.

[0053] There are multiple stacked memory chips, such as Figure 5 As shown in the figure, when receiving 4 programming instructions, the corresponding chip1~chip4 will start the programming loop at the same time, and execute multiple programming loops in sequence without gaps, marked as loop0, loop1, loop2 respectively, until the programming is completed. Obviously, the peak current superposition of multiple storage chips in each programming loop causes the peak current to be too high.

[0054] In this embodiment, one operation is an operation cycle, and the ith operation is the ith operation cycle. An operation cycle includes a startup operation cycle stage and a stable operation cycle stage. Taking the programming operation as an example, the startup programming operation cycle stage of the memory chip refers to the rising edge stage of the programming charge of the memory chip, and the stable programming operation cycle stage of the memory chip refers to the stage when the rising edge stage of the programming charge of the memory chip ends and enters the stable charging stage. When an operation cycle of the memory chip is completed, the next operation cycle will not be executed immediately, but the control device first detects whether there is a memory chip in the startup operation cycle stage. If so, the control device does not generate a restart instruction, and the corresponding memory chip is in the waiting stage wait, which avoids the memory chip and other memory chips being in the startup operation cycle stage at the same time, and correspondingly avoids the peak current superposition phenomenon of the memory chip; until there is no memory chip in the startup operation cycle stage, at this time, the control device generates a restart instruction and outputs it to trigger the corresponding memory chip to end the waiting and enter the next operation cycle.

[0055] Obviously, if Figure 3As shown, in the multi-chip stacked storage device provided by this embodiment, the operation start times of multiple storage chips to be operated are at different time points, so that the number of storage chips in the startup operation cycle stage at the same time is greatly reduced, and the peak current superposition of multiple storage chips causes excessive peak current to affect the surrounding circuits and cause the circuit short circuit. It should be noted that in order to improve programming efficiency, in this embodiment, the operation start time of two storage chips to be operated can also be selected to be the same, but the number of storage chips should be less than the number of first operation instructions received by the storage device. At the same time, it is also possible to select that the operation start time of each of the two storage chips to be operated is different, and it is also possible to select that the operation start time of at least one of the two storage chips to be operated is different. This solution is not only applicable to two storage chips to be operated, but also to the case where there are more than two storage chips to be operated.

[0056] Optionally, controlling at least two storage chips to be operated to execute the corresponding first operation instruction in time-sharing includes: controlling at least two storage chips to be operated to execute the first operation of the corresponding first operation instruction in time-sharing. In this embodiment, when the first operation cycle is optionally executed, the control device directly controls the multiple storage chips to execute the first operation cycle in time-sharing, without using restart execution to trigger the first operation cycle.

[0057] Based on the same inventive concept, an embodiment of the present invention further provides a control device for a storage device, the control device is integrated in the storage device, and is used to execute the control method described in any of the above embodiments, the storage device includes a plurality of storage chips. Figure 4 As shown, the control device provided in this embodiment includes: a chip determination module 10, which is used to determine at least two storage chips to be operated corresponding to the at least two first operation instructions if at least two first operation instructions are received; an operation control module 20, which is used to control at least two storage chips to be operated to execute the corresponding first operation instructions in time-sharing.

[0058] Optionally, the two first operation instructions are both erase operation instructions or programming operation instructions. Optionally, one of the two first operation instructions is an erase operation instruction, and the other is a programming operation instruction. Optionally, the chip determination module 10 includes: a mode switching unit, which is used to control the switch to a reduced peak current mode before determining at least two storage chips to be operated corresponding to at least two first operation instructions. Optionally, the operation control module 20 includes: a restart trigger unit, which is used to generate and output a restart instruction according to a set rule, triggering the storage chip to be operated to perform the i-th operation of the corresponding first operation instruction, i=1,2,3,…. Optionally, the setting rule includes: the start time of at least one operation of at least two storage chips to be operated is different. Optionally, the operation control module 20 includes: a first operation unit, which is used to control at least two storage chips to be operated to perform the first operation of the corresponding first operation instruction in time-sharing.

[0059] In this embodiment, two commands are introduced, one command CMD1 controls whether to set the current mode to RPC mode, and the other command CMD2 is used to control the start of the next program loop. The specific operation is as follows: in the case of multiple chips stacked, the control device first generates and sends command CMD1 to set the RPC mode to be valid, that is, switch to the peak current reduction mode; then send a programming instruction to the memory chip to be programmed, and perform a programming operation on the selected memory chip to be programmed; each time a program loop is completed inside the memory chip, it will automatically stop and wait for the user to input a restart instruction, and the restart instruction also carries the chip address of the memory chip to be programmed; when the restart instruction is input, the control device performs the next program loop on the currently selected chip according to the input chip address; then wait, and repeat this process until the programming operation is completed.

[0060] Compared with the existing solutions, in this embodiment, a restart instruction is required before each next program loop, so that the peak currents of different chips are shifted, which can avoid the problem of excessive peak current at the same time.

[0061] Based on the same inventive concept, an embodiment of the present invention further provides a storage device, including: one or more processors; a storage module for storing one or more programs; when the one or more programs are executed by one or more processors, the one or more processors implement the control method of the storage device described in any of the above embodiments. The storage device may be an eMMC chip.

[0062] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for controlling a storage device, characterized in that: The storage device includes a plurality of storage chips, and the control method includes: If at least two first operation instructions are received, determining at least two storage chips to be operated corresponding to the at least two first operation instructions; Controlling the at least two storage chips to be operated to execute the corresponding first operation instruction in time-sharing; Before determining at least two storage chips to be operated corresponding to the at least two first operation instructions, the method further includes: controlling switching to a peak current reduction mode; The peak current reduction mode of the storage device is initially in an invalid mode, and the control device of the storage device generates a command to convert the peak current reduction mode into an effective mode; Controlling the at least two storage chips to be operated to execute the corresponding first operation instruction in a time-sharing manner includes: Generate and output a restart instruction according to a set rule, triggering the storage chip to be operated to execute the i-th operation of the corresponding first operation instruction, i=1,2,3,...; One operation is an operation cycle. When an operation cycle of a memory chip is completed, the control device first detects whether there are other memory chips in the startup operation cycle stage. If so, the control device does not generate a restart instruction, and the memory chip is in the waiting stage. The first operation instruction includes a storage chip address and operation data; the storage chip address and the operation data of at least two of the first operation instructions are different.

2. The control method according to claim 1, characterized in that: The two first operation instructions are both erase operation instructions or program operation instructions.

3. The control method according to claim 1, characterized in that: One of the two first operation instructions is an erase operation instruction, and the other is a program operation instruction.

4. The control method according to claim 1, characterized in that: The setting rule includes: at least one operation start time of at least two of the storage chips to be operated is different.

5. The control method according to claim 1, characterized in that: Controlling the at least two storage chips to be operated to execute the corresponding first operation instruction in a time-sharing manner includes: The at least two storage chips to be operated are controlled to execute the first operation of the corresponding first operation instruction in time-sharing.

6. A control device for a storage device, characterized in that: The storage device includes a plurality of storage chips, and the control device includes: A chip determination module, configured to determine at least two storage chips to be operated corresponding to the at least two first operation instructions if at least two first operation instructions are received; An operation control module, used for controlling the at least two storage chips to be operated to execute the corresponding first operation instruction in a time-sharing manner; The chip determination module comprises: a mode switching unit, configured to control switching to a peak current reduction mode before determining at least two storage chips to be operated corresponding to the at least two first operation instructions; The peak current reduction mode of the storage device is in an invalid mode in an initial state, and the control device of the storage device generates a command to make the peak current reduction mode a valid mode; The operation control module comprises: The restart trigger unit is used to generate and output a restart instruction according to a set rule, triggering the storage chip to be operated to perform the i-th operation of the corresponding first operation instruction, i=1,2,3,… One operation is an operation cycle. When an operation cycle of a memory chip is completed, the control device first detects whether there are other memory chips in the startup operation cycle stage. If so, the control device does not generate a restart instruction, and the memory chip is in the waiting stage. The first operation instruction includes a storage chip address and operation data; the storage chip address and the operation data of at least two of the first operation instructions are different.

7. The control device according to claim 6, characterized in that: The two first operation instructions are both erase operation instructions or program operation instructions.

8. The control device according to claim 6, characterized in that One of the two first operation instructions is an erase operation instruction, and the other is a program operation instruction.

9. The control device according to claim 6, characterized in that: The setting rule includes: at least one operation start time of at least two of the storage chips to be operated is different.

10. The control device according to claim 6, characterized in that: The operation control module comprises: The first operating unit is used to control the at least two storage chips to be operated to perform the first operation of the corresponding first operating instruction in time-sharing.

11. A storage device, characterized in that: include: one or more processors; A storage module, used for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the storage device control method according to any one of claims 1 to 5.

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