Method of operating a storage system

Abstract

An operating method of a storage system, comprising: pre-programming multi-page data in a storage controller to a non-volatile memory device; generating state group codes based on multi-bit data in the multi-page data, and a number of bits of each state group data in the state group codes is less than a number of bits of the corresponding multi-bit data; detecting whether a sudden power loss occurs after the pre-programming; in response to detecting that the sudden power loss occurs, backing up the state group codes to the non-volatile memory device; after power is recovered from the sudden power loss, recovering the multi-page data from the non-volatile memory device based on the state group codes; re-programming the multi-page data to the non-volatile memory device; and in response to detecting that the sudden power loss does not occur, re-programming the multi-page data in the storage controller to the non-volatile memory device.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefits of Korean Patent Application No. 10-2019-0153551, filed on November 26, 2019, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2020-0068602, filed on June 5, 2020, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to semiconductor devices, and more specifically, to a method of operation for a memory system for efficiently completing a programming operation when a sudden power failure (SPO) occurs while data is being programmed into a non-volatile memory device. Background Technology

[0004] Flash memory devices, as examples of non-volatile memory devices, include memory cells with different threshold voltages depending on the programming state. In single-level cell (SLC) mode, the memory cell can be programmed to have a threshold voltage corresponding to one of the erase and programming states. In multi-level cell (MLC) mode, the memory cell can be programmed to have a threshold voltage corresponding to one of multiple programming states or an erase state.

[0005] When a Single Point of Existence (SPO) occurs in a non-volatile storage device, it may be necessary to back up the data of the memory cell that has undergone the programming operation. The amount of data to be backed up for memory cells programmed in MLC mode is greater than that for memory cells programmed in SLC mode; therefore, the capacity of the auxiliary power supply required for data backup increases. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a method of operating a storage system including a storage controller and a non-volatile storage device includes: pre-programming multi-page data in the storage controller into a plurality of storage cells in the non-volatile storage device connected to a word line, wherein the multi-page data includes a plurality of multi-bit data, wherein each of the plurality of storage cells is pre-programmed to have a threshold voltage based on a corresponding multi-bit data among the plurality of multi-bit data, and wherein the threshold voltage corresponds to one of a plurality of pre-programmed states; generating a state group code based on the plurality of multi-bit data in the multi-page data, wherein the state group code includes a plurality of state group data, and its In the process, the number of bits in each of the plurality of state group data is less than the number of bits in the corresponding multi-bit data in the plurality of multi-bit data in the multi-page data; the state group code is backed up to the non-volatile storage device; after power is restored from the sudden power outage, the multi-page data is restored by reading the pre-programmed plurality of storage cells based on the state group code; the multi-page data restored from the pre-programmed plurality of storage cells is reprogrammed to the pre-programmed plurality of storage cells; and if no sudden power outage occurs after the state group code is backed up, the multi-page data of the storage controller is reprogrammed to the pre-programmed plurality of storage cells.

[0007] According to an exemplary embodiment of the present invention, a method of operating a storage system including a storage controller and a non-volatile storage device includes: pre-programming multi-page data in the storage controller into a plurality of storage cells in the non-volatile storage device connected to a word line, wherein the multi-page data includes a plurality of multi-bit data, wherein each of the plurality of storage cells is pre-programmed to have a threshold voltage based on a corresponding multi-bit data among the plurality of multi-bit data, and wherein the threshold voltage corresponds to one of a plurality of pre-programmed states; generating a state group code based on the plurality of multi-bit data in the multi-page data, wherein the state group code includes a plurality of state group data, and wherein each of the plurality of state group data... The number of bits in a state group data is less than the number of bits in a corresponding multi-bit data among the plurality of multi-bit data in the multi-page data; the state group code is backed up to the non-volatile storage device; after the state group code is backed up, a sudden power failure is detected; after power is restored from the sudden power failure that occurred after the state group code was backed up, the multi-page data is restored by reading the plurality of pre-programmed storage cells based on the state group code; the multi-page data restored from the plurality of pre-programmed storage cells is reprogrammed into the plurality of storage cells; and if the sudden power failure did not occur after the state group code was backed up, the multi-page data in the storage controller is reprogrammed into the plurality of pre-programmed storage cells.

[0008] According to an exemplary embodiment of the present invention, a method of operating a storage system including a storage controller and a non-volatile storage device, the non-volatile storage device including a storage cell region and a peripheral circuit region, the storage cell region including a first metal pad, the peripheral circuit region including a second metal pad and connected to the storage cell region in a vertical direction via the first metal pad and the second metal pad, the method of operating comprising: pre-programming multi-page data in the storage controller to a plurality of storage cells in the non-volatile storage device connected to a first word line, wherein the multi-page data includes a plurality of multi-bit data, wherein each of the plurality of storage cells is pre-programmed to have a threshold voltage according to a corresponding multi-bit data in the plurality of multi-bit data, and wherein the threshold voltage corresponds to one of a plurality of pre-programmed states; based on the multi-page data The plurality of multi-bit data in the multi-page data generate a status group code, wherein the status group code includes a plurality of status group data, and wherein the number of bits of each status group data is less than the number of bits of the corresponding multi-bit data in the plurality of multi-bit data in the multi-page data; when a sudden power failure occurs after the storage cell is pre-programmed, the status group code is backed up to the non-volatile storage device; after power is restored from the sudden power failure, the multi-page data is restored by reading the plurality of pre-programmed storage cells based on the status group code; the multi-page data restored from the plurality of pre-programmed storage cells is reprogrammed into the plurality of pre-programmed storage cells; and when no sudden power failure occurs after the storage cell is pre-programmed, the multi-page data in the storage controller is reprogrammed into the plurality of pre-programmed storage cells.

[0009] According to an exemplary embodiment of the present invention, a method of operating a storage system including a storage controller and a non-volatile storage device includes: pre-programming multi-page data in the storage controller into a plurality of first storage cells connected to a first word line in the non-volatile storage device, wherein the multi-page data includes a plurality of multi-bit data, wherein each of the plurality of first storage cells is pre-programmed to have a threshold voltage based on a corresponding multi-bit data among the plurality of multi-bit data, and wherein the threshold voltage corresponds to one of the plurality of pre-programmed states; generating a state group code based on the plurality of multi-bit data in the multi-page data, wherein the state group code includes a plurality of state group data, and wherein the number of bits in each of the plurality of state group data is less than that in the multi-page data. The number of bits of a corresponding multi-bit data in the plurality of multi-bit data in the face data; backing up the state group code to the non-volatile storage device; after power is restored from the sudden power outage, restoring the multi-page data by reading the pre-programmed plurality of first storage cells based on the state group code; pre-programming the multi-page data restored from the pre-programmed plurality of first storage cells to a plurality of second storage cells in the non-volatile storage device connected to a second word line; reprogramming the multi-page data restored from the pre-programmed plurality of first storage cells to the pre-programmed plurality of second storage cells; and if no sudden power outage occurs after the state group code is backed up, reprogramming the multi-page data of the storage controller to the pre-programmed plurality of first storage cells.

[0010] According to an exemplary embodiment of the present invention, a method of operating a storage system including a memory controller and a non-volatile storage device includes: performing a first pre-programming operation to pre-program multi-page data in the memory controller to a plurality of memory cells connected to a word line in the non-volatile storage device, wherein the multi-page data includes a plurality of multi-bit data, wherein each of the plurality of memory cells is pre-programmed to have a threshold voltage based on a corresponding multi-bit data among the plurality of multi-bit data, and wherein the threshold voltage corresponds to one of a plurality of pre-programmed states; generating a first state group code based on the plurality of multi-bit data in the multi-page data, wherein the first state group code includes a plurality of first state group data, and wherein the number of bits of each of the plurality of first state group data is less than the number of bits of the corresponding multi-bit data among the plurality of multi-bit data in the multi-page data; backing up the first state group code to the non-volatile storage device; and, after power is restored from a sudden power outage, reading the data... The process involves: restoring the multi-page data by pre-programming the plurality of storage units with the first pre-programming operation; performing a second pre-programming operation on the plurality of storage units pre-programmed with the first pre-programming operation based on the multi-page data restored from the plurality of storage units pre-programmed with the first pre-programming operation; generating a second state group code based on the plurality of multi-bit data in the multi-page data, wherein the second state group code includes a plurality of second state group data, and wherein the number of bits in each of the plurality of second state group data is less than the number of bits in the corresponding multi-bit data in the plurality of multi-bit data in the multi-page data; backing up the second state group code to the non-volatile storage device; restoring the multi-page data by reading the plurality of storage units pre-programmed with the second pre-programming operation after power is restored from the sudden power outage; and reprogramming the multi-page data restored from the storage units pre-programmed with the second pre-programming operation back to the plurality of storage units pre-programmed with the second pre-programming operation. Attached Figure Description

[0011] The embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram of a storage system according to an embodiment;

[0013] Figure 2 yes Figure 1 A diagram illustrating example programming operations of a storage system in the event of a sudden power outage (SPO).

[0014] Figure 3A graph illustrating the threshold voltage distribution of a non-volatile memory device according to an embodiment is shown;

[0015] Figure 4 yes Figure 1 Example block diagram of a storage controller;

[0016] Figure 5 yes Figure 1 Example block diagram of a non-volatile storage device;

[0017] Figure 6 This is a circuit diagram illustrating a memory block according to an embodiment;

[0018] Figure 7 An example of generating state group codes according to an embodiment is shown;

[0019] Figure 8 According to the embodiments Figure 1 A flowchart of the operation method of the storage system;

[0020] Figure 9 This is a flowchart illustrating the operation between the memory controller and the non-volatile storage device when an SPO occurs, according to an embodiment.

[0021] Figure 10 This is a flowchart illustrating the operation between the memory controller and the non-volatile storage device when an SPO occurs, according to an embodiment.

[0022] Figure 11 This is a flowchart illustrating the operation between the storage controller and the non-volatile storage device when power is restored from an SPO, according to an embodiment.

[0023] Figure 12 It is used to describe Figure 5 A diagram illustrating read operations for non-volatile storage devices;

[0024] Figure 13 This is a block diagram of the page buffer according to an embodiment;

[0025] Figure 14 The graphs showing examples of read voltage in normal read mode and read voltage in recovery read mode according to an embodiment are shown.

[0026] Figure 15 This is a table illustrating examples of read voltages in normal read mode according to an embodiment;

[0027] Figure 16 This is a table illustrating examples of read voltages in recovery read mode according to an embodiment;

[0028] Figure 17A and Figure 17BAn example of adjusting the recovery read voltage according to an embodiment is shown;

[0029] Figure 18 This is a flowchart of an operation method of a storage system according to an embodiment;

[0030] Figure 19 This is a flowchart of an operation method of a storage system according to an embodiment;

[0031] Figure 20 This is a flowchart of an operation method of a storage system according to an embodiment;

[0032] Figure 21 A memory device having a chip-to-chip structure according to an embodiment is shown;

[0033] Figure 22 This is a block diagram illustrating an example of applying a storage system to a solid-state drive (SSD) system according to an embodiment; and

[0034] Figure 23 This is a block diagram of a network system using a storage system according to an embodiment. Detailed Implementation

[0035] The embodiments will be clearly described in detail below to enable those skilled in the art to readily implement the inventive concept.

[0036] Figure 1 This is a block diagram of a storage system according to an embodiment. (Refer to...) Figure 1 The storage system 10 may include a storage controller 100 and a non-volatile memory (NVM) device 200. For example, the storage system 10 may be implemented as a storage device such as a solid-state drive (SSD).

[0037] Storage controller 100 can control the operation of NVM device 200. Storage controller 100 can provide control signals CTRL, commands CMD, and / or addresses ADDR to NVM device 200 to control NVM device 200. In an example embodiment, storage controller 100 can control NVM device 200 to program data DATA to it or read data DATA from it in response to a request from an external host device.

[0038] In the example embodiment, the same input / output channel as the data DATA can be used to send the command CMD and address ADDR from the storage controller 100 to the NVM device 200. Alternatively, the first input / output channel can be used to send the command CMD and address ADDR from the storage controller 100 to the NVM device 200, while the second input / output channel can be used to send the data DATA from the storage controller 100 to the NVM device 200.

[0039] The storage controller 100 may include a power detector 110, a programming manager 120, and a buffer memory 130. The power detector 110 can detect the power status of the storage controller 100. For example, the power detector 110 can detect a sudden power outage (SPO) and power recovery from an SPO based on the voltage supplied to the storage controller 100. When the voltage supplied to the storage controller 100 is less than a reference voltage, the power detector 110 can determine that an SPO has occurred. When the voltage supplied to the storage controller 100 is greater than the reference voltage, the power detector 110 can determine that power has been restored.

[0040] Programming manager 120 manages the programming operations of NVM device 200. Programming manager 120 provides control signals CTRL, commands CMD, addresses ADDR, and / or data DATA to NVM device 200 according to a predetermined schedule for the programming operations. In an example embodiment, when a SPO occurs during a programming operation, programming manager 120 provides control signals CTRL, commands CMD, addresses ADDR, and / or data DATA to NVM device 200 according to the predetermined schedule to ensure the programming operation completes normally.

[0041] The buffer memory 130 can temporarily store data. In an example embodiment, the buffer memory 130 can temporarily store data DATA to be provided to the NVM device 200 during programming operations, or it can temporarily store data DATA provided from the NVM device 200 during read operations.

[0042] The NVM device 200 can operate under the control of the storage controller 100. In an example embodiment, under the control of the storage controller 100, the NVM device 200 can output data DATA stored therein or store data DATA provided from the storage controller 100.

[0043] NVM device 200 may include a memory cell array 210. The memory cell array 210 may include a plurality of memory cells. For example, the memory cells may include flash memory cells. However, embodiments are not limited thereto, and the memory cells may include at least one of resistive random access memory (RRAM) cells, ferroelectric RAM (FRAM) cells, phase-change RAM (PRAM) cells, thyristor RAM (TRAM) cells, and magnetic RAM (MRAM) cells. Hereinafter, embodiments in which the memory cells include NAND flash memory cells will be described.

[0044] In the example embodiment, each storage cell of the storage cell array 210 can store N bits of data, where N is a positive integer. When N is 2 or greater, the storage cell can be referred to as a multi-level cell (MLC), and the N bits of data can be referred to as multi-bit data. For example, when N is 3, the storage cell can be referred to as a third-level cell (TLC). For example, when N is 4, the storage cell can be referred to as a fourth-level cell (QLC). However, when N is 2 or greater, the N bits of data will be referred to as “multi-bit data” in the following text.

[0045] According to an embodiment, when a SPO occurs during a programming operation on multi-bit data, the storage system 10 can back up a small amount of data compared to the multi-bit data, and restore the multi-bit data based on the backup data after power is restored. Therefore, the auxiliary power supply and storage capacity required for such data backup can be reduced. Hereinafter, embodiments for efficiently completing programming operations on multi-bit data when an SPO occurs during programming operations will be described in detail.

[0046] Figure 2 yes Figure 1 A diagram illustrating example programming operations of storage system 10 in the state of SPO. Figure 3 A graph illustrating the threshold voltage distribution of an NVM memory device according to an embodiment is shown.

[0047] Reference Figure 2 and Figure 3 When programming begins, the storage system 10 can pre-program (or coarsely program) multiple bits of data into the memory cells of the NVM device 200. For example, when the multiple bits of data are 4 bits, the pre-programmed memory cells can have 16 threshold voltage distributions (i.e., 16 states (e.g., such as...)). Figure 3 As shown, the threshold voltage corresponds to one of the threshold voltage distributions (i.e., one pre-programmed state) in the erase state E and the first programming states P1 to the fifteenth programming states P15. The 16 threshold voltage distributions can each correspond to one of the 16 possible values ​​for 4-bit data. Based on the multi-bit data value, the pre-programmed memory cell can correspond to one of the 16 threshold voltage distributions. During pre-programming, the threshold voltage of adjacent memory cells may change due to capacitive coupling between adjacent memory cells; therefore, the width of each threshold voltage distribution may increase. As a result, adjacent threshold voltage distributions may overlap. After pre-programming multiple bits of data into the memory cell, the pre-programmed memory cell can have a threshold voltage within a corresponding threshold voltage distribution among the sixteen threshold voltage distributions (i.e., sixteen pre-programmed states), and two adjacent threshold voltage distributions (i.e., two adjacent pre-programmed states) may overlap. The threshold voltage of a pre-programmed state may fall into the overlapping region between two adjacent threshold voltage distributions.

[0048] The threshold voltage distribution of pre-programmed memory cells can be classified into multiple state groups. For example, such as Figure 3 As shown, the threshold voltage distributions corresponding to the erase state E and the first programming states P1 to P15 can be classified into a first state group GROUP1 and a second state group GROUP2. In an example embodiment, the state groups may include threshold voltage distributions that are different from each other, and the threshold voltage distributions of each state group do not overlap. For example, the first state group GROUP1 may include threshold voltage distributions corresponding to the erase state E, the second programming state P2, the fourth programming state P4, the sixth programming state P6, the eighth programming state P8, the tenth programming state P10, the twelfth programming state P12, and the fourteenth programming state P14, respectively, while the second state group GROUP2 may include threshold voltage distributions corresponding to the first programming state P1, the third programming state P3, the fifth programming state P5, the seventh programming state P7, the ninth programming state P9, the eleventh programming state P11, the thirteenth programming state P13, and the fifteenth programming state P15, respectively. In an example embodiment, the erase state E and each of the programming states P1 to P15 can be mapped to Gray code and can represent 4-bit multi-bit data. In Gray code mapping, among the erase state E and the first programming (or preprogramming) states P1 to the fifteenth programming (or preprogramming) state P15, programming states (or preprogramming) with an odd number of "1" bits and programming states (or preprogramming) states with an even number of "1" bits can be alternated. (See below for further details.) Figure 14 Describe the programming state (or preprogrammed state) using Gray code mapping.

[0049] Each state group can be represented by state group data (i.e., a state group identifier). For example, the first state group GROUP1 and the second state group GROUP2 can be represented by 1 bit of state group data. For example, the state group data representing the first state group GROUP1 can be represented as "0", while the state group data representing the second state group GROUP2 can be represented as "1". However, the embodiments are not limited to this, and the number of bits in the state group data can vary with the number of state groups. For example, when the threshold voltage distribution is classified into four state groups, the state group data can be 2 bits. In this case, the number of bits in the state group data can be less than the number of bits in the multi-bit data, and when the multi-bit data includes N bits, the state group data can include (N-1) bits.

[0050] Based on the pre-programmed multi-bit data values, the pre-programmed multi-bit data can correspond to state group data representing one of multiple state groups. For example, such as... Figure 3As shown, the multi-bit data corresponding to the erase state E can correspond to the state group data representing the first state group GROUP1, while the multi-bit data corresponding to the first programming state P1 can correspond to the state group data representing the second state group GROUP2.

[0051] When an SPO occurs after the pre-programming operation is completed, the storage system 10 can back up the state group data corresponding to the pre-programmed storage cell to the NVM device 200. For example, as Figure 3 As shown, when multiple bits of data corresponding to the first programming state P1 are pre-programmed, the storage system 10 can back up the state group data representing the second state group GROUP2 corresponding to the pre-programmed storage cell to the NVM device 200.

[0052] When power is restored from the SPO, storage system 10 can recover multiple bits of data based on backed-up state group data. For example, storage system 10 can read multiple bits of data from pre-programmed storage cells based on state group data. Figure 3 As shown, even when there are overlapping regions in the threshold voltage distributions of pre-programmed memory cells, the threshold voltage distribution including the overlapping regions can be identified when a read operation is performed on each state group based on state group data. Therefore, the reliability of recovered multi-bit data can be improved.

[0053] Storage system 10 can reprogram (or finely program) multi-bit data into storage cells based on the recovered multi-bit data. The programming operation on the multi-bit data can be completed through the reprogramming operation. For example... Figure 3 As shown, the width of the threshold voltage distribution in a memory cell can be reduced due to the reprogramming operation. Because the increase in threshold voltage of a memory cell via reprogramming is less than the increase via preprogramming, the threshold voltage distribution involved in the reprogramming operation is less affected by coupling. Therefore, after reprogramming, the memory cell can have a narrower threshold voltage distribution compared to after preprogramming, and the overlap between threshold voltage distributions can be reduced. Consequently, the reliability of reading multiple bits of data from a reprogrammed memory cell can be improved.

[0054] In an example embodiment, the reprogramming verification voltage used to reprogram multi-bit data can be higher than the preprogramming verification voltage used to preprogram multi-bit data. For example, a preprogramming operation can be performed using a preprogramming verification voltage corresponding to a threshold voltage below a desired threshold voltage, while in the reprogramming operation, a reprogramming verification voltage higher than the preprogramming verification voltage can be used to program the memory cell to the desired threshold voltage.

[0055] As shown above (refer to the reference) Figure 2As described, storage system 10 can back up state group data after an SPO occurs, but the embodiments are not limited thereto. For example, storage system 10 can back up state group data before an SPO occurs.

[0056] As described above, in the case of SPO, the storage system 10 can back up state group data corresponding to multi-bit data, and can perform programming operations on the multi-bit data based on the backed-up state group data. In this case, because the number of bits in the state group data is less than the number of bits in the multi-bit data, the auxiliary power supply and storage capacity required for the backup operation can be reduced compared to the operation of directly backing up the multi-bit data.

[0057] The following text will focus on, for example Figure 3 The embodiments shown are illustrated with examples where the multi-bit data is 4 bits and the status group data is 1 bit, but are not limited thereto.

[0058] Figure 4 yes Figure 1 Example block diagram of storage controller 100. (Refer to...) Figure 4 The storage controller 100 may include a power detector 110, a programming manager 120, a buffer memory 130, a processor 140, an error correction code (ECC) circuit 150, a host interface 160, a non-volatile memory (NVM) interface 170, and a bus 180. In the following text, the above-mentioned details will be omitted. Figure 1 The given description is repetitive.

[0059] The power detector 110 can detect the occurrence of a spontaneous electrical outburst (SPO) or power recovery from an SPO by sensing the voltage supplied to the storage controller 100. For example, the power detector 110 may include a voltage sensor.

[0060] The programming manager 120 can manage programming operations on multi-bit data. For example, as shown above... Figure 2 As described, the programming manager 120 can generate control signals CTRL, commands CMD, and / or addresses ADDR to perform programming operations on multi-bit data through pre-programming and reprogramming. When an SPO is detected during a programming operation on multi-bit data, the programming manager 120 can generate control signals CTRL, commands CMD, and / or addresses ADDR according to a predetermined schedule to complete the programming operation on the multi-bit data.

[0061] In the example embodiment, the programming manager 120 can manage address information, which includes first address information for programming multi-bit data and second address information for backing up state group data. The address information can be stored in a buffer memory 130 within the storage controller 100 or in a separate memory. When an SPO occurs, the address information can be backed up to the NVM device 200 along with the state group data.

[0062] In the example embodiment, the programming manager 120 may be implemented by software or firmware such as a flash translation layer (FTL). In this case, the programming manager 120 may be loaded into memory (e.g., buffer memory 130 or separate memory) in the storage controller 100 and executed by the processor 140. However, the embodiment is not limited to this, and the programming manager 120 may be implemented in hardware.

[0063] Buffer memory 130 can temporarily store data provided from the host, data generated in storage controller 100, or data provided from NVM device 200. For example, buffer memory 130 can temporarily store multiple bits of data to be provided to NVM device 200 during programming operations. When a Service Point Out (SPO) occurs during programming operations, the multiple bits of data stored in buffer memory 130 may be lost. After power is restored from the SPO, the multiple bits of data read from NVM device 200 can be temporarily stored in buffer memory 130. For example, buffer memory 130 may include dynamic RAM (DRAM) or static RAM (SRAM), but embodiments are not limited to these.

[0064] Processor 140 can control all operations of storage controller 100. For example, processor 140 can drive programming manager 120. Therefore, programming operations can be performed on multi-bit data.

[0065] ECC circuit 150 can correct errors in the data read from NVM device 200. For example, when power is restored from SPO, ECC circuit 150 can correct errors in multi-bit data read from NVM device 200. When reprogramming is performed based on the error-corrected multi-bit data, the reliability of the multi-bit data programmed into NVM device 200 can be improved.

[0066] Host interface 160 provides a physical connection between the host and storage controller 100. For example, host interface 160 may include various interfaces such as Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, External SATA (e-SATA) interface, Small Computer System Interface (SCSI) interface, Serial Attached SCSI (SAS) interface, Peripheral Component Interconnect (PCI) interface, Fast PCI (PCI-E) interface, Institute of Electrical and Electronics Engineers (IEEE) 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, and Compact Flash (CF) card interface.

[0067] The NVM interface 170 provides a physical connection between the storage controller 100 and the NVM device 200. For example, control signals CTRL, commands CMD, addresses ADDR, and data DATA can be transmitted between the storage controller 100 and the NVM device 200 via the NVM interface 170. The bus 180 can be configured to provide a channel between components of the storage controller 100.

[0068] Figure 5 yes Figure 1 Example block diagram of the NVM device 200. (Refer to...) Figure 5 The NVM device 200 may include a memory cell array 210, a page buffer unit 220, control logic circuitry 230, a voltage generator 240, and a row decoder 250. Although not shown, the NVM device 200 may also include data input / output circuitry or an input / output interface. The NVM device 200 may also include column logic, a pre-decoder, a temperature sensor, a command decoder, or an address decoder.

[0069] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz (where "z" is a positive integer). Each memory block BLK1 to BLKz may include multiple memory cells. Memory blocks BLK1 to BLKz may be included in a single memory plane, but the embodiments are not limited thereto. In an example embodiment, the NVM device 200 may include two or more independently controlled memory planes. The memory cell array 210 can be connected to the page buffer unit 220 via bit lines BL and can be connected to the row decoder 250 via word lines WL, serial select lines SSL, and ground select lines GSL.

[0070] In an example embodiment, the memory cell array 210 may include a three-dimensional (3D) memory cell array, which may include multiple NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. These will be referenced below. Figure 6 A detailed description is provided. The disclosures of U.S. Patent Publications No. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application No. 2011 / 0233648 are incorporated herein by reference. In an example embodiment, the memory cell array 210 may include a two-dimensional (2D) memory cell array, which may include multiple NAND strings in both row and column directions.

[0071] Page buffer unit 220 may include multiple page buffers, such as first page buffer PB1 to nth page buffer PBn (where "n" is an integer of 3 or greater). First page buffer PB1 to nth page buffer PBn may be connected to the memory cell via bit line BL, respectively. Page buffer unit 220 may respond to at least one bit line in the column address Y-ADDR select bit line BL. Page buffer unit 220 may be used as a write driver or a read amplifier depending on the operating mode. For example, during a programming operation, page buffer unit 220 may apply a bit line voltage corresponding to the data to be programmed to the select bit line. During a read operation, page buffer unit 220 may sense the data stored in the memory cell by sensing the current or voltage of the select bit line. Reference will be made below. Figure 13 Let us describe in detail each of the page buffers from the first page buffer PB1 to the nth page buffer PBn.

[0072] Control logic circuit 230 can control various operations of NVM device 200. Control logic circuit 230 can respond to control signals CTRL, commands CMD, and / or addresses ADDR, outputting various control signals for programming data to memory cell array 210, reading data from memory cell array 210, or erasing data stored in memory cell array 210. For example, control logic circuit 230 can output voltage control signal CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0073] In an example embodiment, the control logic circuit 230 can output control signals for programming multi-bit data based on the control signal CTRL, the command CMD, and / or the address ADDR. For example, the control logic circuit 230 can output control signals for pre-programming and re-programming operations, control signals for backing up status group data, or control signals for reading pre-programmed multi-bit data.

[0074] Voltage generator 240 can generate various voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 240 can generate programming voltage, reading voltage, and programming verification voltage as word line voltage VWL. For example, incremental step pulse programming (ISPP) can be used to generate the programming voltage.

[0075] In programming operations involving multi-bit data, voltage generator 240 can generate a pre-programming verification voltage for pre-programming and a reprogramming verification voltage for reprogramming. In this case, the pre-programming verification voltage can be less than the reprogramming verification voltage.

[0076] The row decoder 250 can select one of the word lines WL and one of the string select lines SSL in response to the row address X-ADDR. For example, the row decoder 250 can apply a programming voltage and a programming verification voltage to the selected word line during a programming operation, and can apply a read voltage to the selected word line during a read operation.

[0077] Figure 6 This is a circuit diagram illustrating a memory block according to an embodiment. (Refer to...) Figure 6 The storage block BLK can correspond to Figure 5 One of the memory blocks BLK1 to BLKz in the memory. Memory block BLK may include NAND strings NS11 to NS33. Each string (e.g., NS11) may include a string select transistor SST, multiple memory cells MC and a ground select transistor GST connected in series with each other.

[0078] NAND strings NS11, NS21, and NS31 can be located between the first bit line BL1 and the common source line CSL; NAND strings NS12, NS22, and NS32 can be located between the second bit line BL2 and the common source line CSL; NAND strings NS13, NS23, and NS33 can be located between the third bit line BL3 and the common source line CSL. A string select transistor SST can be connected to a corresponding string select line among the string select lines SSL1 to SSL3. Memory cells MC can be connected to corresponding word lines WL1 to WL8. A ground select transistor GST can be connected to a corresponding ground select line among the ground select lines GSL1 to GSL3. String select transistor SST can be connected to a corresponding bit line among the first bit line BL1 to the third bit line BL3, and ground select transistor GST can be connected to the common source line CSL. The number of NAND strings, word lines, bit lines, ground select lines, and string select lines can vary depending on the embodiment.

[0079] Figure 7 An example of generating state group codes according to an embodiment is shown. (Refer to...) Figure 7 Multi-page data can include first multi-bit data MD1 to nth multi-bit data MDn to be programmed into "n" memory cells connected to a word line. For example, when the multi-bit data is 4 bits, the multi-page data can include first page data PD1 to fourth page data PD4. Each memory block can include multiple pages. Each page is the smallest unit for programming or reading operations in SLC mode. In QLC mode programming operations, the 4-bit data corresponding to four pages in the multi-bit data can be stored in page buffer unit 220, and then programmed into the desired threshold voltage among sixteen programming states (i.e., sixteen threshold voltage distributions) via at least two programming operations including pre-programming (i.e., coarse programming) and reprogramming (i.e., fine programming).

[0080] The state group code can include first state group data SD1 to nth state group data SDn generated based on first multi-bit data MD1 to nth multi-bit data MDn. For example, the state group data can be generated based on the number of "1" bits (or "0" bits) in the multi-bit data. For example, when there are an odd number of "1" bits, the state group data can be generated as 1, and when there are an even number of "1" bits, the state group data can be generated as 0. For example, when generating 1-bit state group data based on multi-bit data, the first state group data SD1 "0" can be generated based on the first multi-bit data MD1 "1001", and the second state group data SD2 "1" can be generated based on the second multi-bit data MD2 "1000". Therefore, the state group code can be generated based on multi-page data.

[0081] The number of bits in the status group code can be less than the number of bits in the multipage data. For example, when generating 1-bit status group data from 4-bit multipage data, the number of bits in the status group code can be 1 / 4 of the number of bits in the multipage data.

[0082] The following text will describe the process based on multi-page data and state group codes. Figure 1 Detailed operation of storage system 10.

[0083] Figure 8 According to the embodiments Figure 1 A flowchart illustrating the operation method of the storage system 10. (Refer to...) Figure 1 and Figure 8 In operation S110, the storage system 10 can pre-program multi-page data into the storage cells. In operation S120, the storage system 10 can generate a status group code based on the multi-page data. The status group code can be generated in the storage controller 100 or the NVM device 200. For example, the status group code can be generated by performing logical operations on the bits of multi-bit data.

[0084] In operation S130, the storage system 10 can determine whether an SPO has occurred. If an SPO has occurred, in operation S140, the storage system 10 can back up the status group code to the NVM device 200. In this case, the status group code can be backed up to the same storage board as the storage board that has been pre-programmed with multi-page data, but the embodiment is not limited to this.

[0085] In operation S150, after power is restored, the storage system 10 can read multi-page data from the pre-programmed storage cells based on the backup status group code. To perform the read operation based on the status group code, the NVM device 200 can read the multi-page data in a manner different from normal read operations. For example, the NVM device 200 can use a different read voltage level than that used in normal read operations to read the multi-page data.

[0086] In operation S160, the storage system 10 can reprogram the multi-page data into the storage cells based on the read multi-page data. In this case, the reprogrammed storage cells can be the same as the pre-programmed storage cells.

[0087] When no SPO occurs after pre-programming, in operation S170, storage system 10 can reprogram the multi-page data to the storage cell without backing up the state group code. When no SPO occurs, the multi-page data in buffer memory 130 can be retained; therefore, storage system 10 can reprogram the multi-page data based on the multi-page data stored in buffer memory 130 of storage controller 100.

[0088] Although it has been referenced Figure 8 An example of generating state group codes after pre-programming multi-page data is described, but the example is not limited thereto. For example, state group codes may be generated before or during the pre-programming operation.

[0089] according to Figure 8 In one embodiment, when an SPO occurs during programming operations, storage system 10 can back up the state group code instead of the multipage data. Storage system 10 can then restore the original multipage data from the pre-programmed storage cells based on the backed-up state group code, without needing to back up the original multipage data. Therefore, the size and capacity of the auxiliary power supply required for data backup can be reduced, and consequently, the manufacturing cost and size of storage system 10 can also be reduced.

[0090] The following will refer to Figure 9 and Figure 10 The operation of storage system 10 during an SPO is described in detail.

[0091] Figure 9 This is a flowchart illustrating the operations between the memory controller and the NVM device when an SPO occurs, according to an embodiment. In detail, Figure 9 An example of generating state group codes by an NVM device 200 is shown.

[0092] Reference Figure 9In operation S210, the storage controller 100 can send a pre-programming command for multi-page data to the NVM device 200. The storage controller 100 can also send the multi-page data along with the pre-programming command to the NVM device 200. For example, when the multi-page data comprises four pages, the storage controller 100 can send the command CMD and address ADDR to the NVM device 200 to pre-program the multi-page data in QLC mode.

[0093] In operation S220, the NVM device 200 can preprogram multi-page data in response to a preprogramming command. For example, the NVM device 200 can preprogram multi-page data to the memory cell indicated by address ADDR based on a preprogramming verification voltage.

[0094] In operation S230, the storage controller 100 may send a status group code generation command to the NVM device 200. For example, the storage controller 100 may send a command CMD to the NVM device 200 for generating a status group code. In operation S240, the NVM device 200 may generate a status group code in response to the status group code generation command. The NVM device 200 may generate a status group code based on multi-page data.

[0095] In the example embodiment, the NVM device 200 can be based on loaded to Figure 5 The state group data is generated by processing each multi-bit data entry in the multi-page data of the page buffer unit 220. For example, the NVM device 200 can generate state group data by performing logical operations on the bits in the multi-bit data. The generated state group data can be temporarily stored in the page buffer unit 220.

[0096] In operation S250, the storage controller 100 may send a status group code output command to the NVM device 200. In operation S260, the NVM device 200 may send a status group code to the storage controller 100 in response to the status group code output command. For example, the NVM device 200 may output a status group code temporarily stored in the page buffer unit 220. The status group code provided by the NVM device 200 may be stored in the buffer memory 130 of the storage controller 100. According to an embodiment, operation S250 may be skipped. For example, in response to a status group code generation command, the NVM device 200 may generate a status group code and send it to the storage controller 100.

[0097] In operation S270, the storage controller 100 can detect the State Group Code (SPO). Based on the detected SPO, in operation S280, the storage controller 100 can send a State Group Code backup command to the NVM device 200. The storage controller 100 can send the State Group Code along with the State Group Code backup command to the NVM device 200. For example, the storage controller 100 can send the command CMD and the address ADDR to the NVM device 200 to program the State Group Code in SLC mode. In this case, the storage controller 100 can send another command CMD to the NVM device 200 to change the mode of the NVM device 200 to SLC mode, but the embodiment is not limited to this.

[0098] In operation S290, the NVM device 200 can back up the state group code in response to a state group code backup command. For example, the NVM device 200 can program the state group code to the memory cell corresponding to address ADDR in SLC mode. However, the embodiment is not limited to this, and the NVM device 200 can program the state group code in MLC mode in response to a command CMD from the memory controller 100.

[0099] although Figure 9 The operation method includes operations S250 and S260, which output the status group code from the NVM device 200 via commands from the storage controller 100, but operations S250 and S260 can be skipped. In this case, the status group code can be backed up to the NVM device 200 according to the copyback command of the storage controller 100.

[0100] Figure 10 This is a flowchart illustrating the operations between the memory controller and the NVM device when an SPO occurs, according to an embodiment. In detail, Figure 10 An example of generating state group codes by storage controller 100 is shown.

[0101] Reference Figure 10 In operation S310, the memory controller 100 can send a pre-programming command for multi-page data to the NVM device 200. In operation S320, the NVM device 200 can pre-program the multi-page data into the memory cell in response to the pre-programming command.

[0102] In operation S330, the storage controller 100 can generate a status group code. The storage controller 100 can generate the status group code based on multi-page data. In an example embodiment, the storage controller 100 can generate the status group code based on multi-page data stored in the buffer memory 130. For example, the storage controller 100 can generate status group data by performing logical operations on bits in multi-bit data. The generated status group data can be temporarily stored in the buffer memory 130.

[0103] In operation S340, the storage controller 100 can detect the Status Group Code (SPO). Based on the detected SPO, in operation S350, the storage controller 100 can send a Status Group Code backup command to the NVM device 200. The storage controller 100 can send the generated Status Group Code along with the Status Group Code backup command to the NVM device 200. For example, the storage controller 100 can send the command CMD and address ADDR to the NVM device 200 to program the Status Group Code in SLC mode.

[0104] In operation of S360, NVM device 200 can back up the state group code in response to a state group code backup command. For example, NVM device 200 can program the state group code into the memory cell corresponding to address ADDR in SLC mode.

[0105] The following will refer to Figures 11 to 17B The operation of the storage system 10 when power is restored from the SPO is described in detail.

[0106] Figure 11 This is a flowchart illustrating the operations between the storage controller and the non-volatile storage device when power is restored from an SPO, according to an embodiment. (Refer to...) Figure 11 In operation S401, the storage controller 100 can detect power being applied. When power is detected, the storage controller 100 can determine that the power of the storage controller 100 has been restored.

[0107] In operation S402, the storage controller 100 can send a status group code read command to the NVM device 200. The storage controller 100 can send the status group code read command based on address information corresponding to the pre-programmed storage cell. For example, the storage controller 100 can send the command CMD and address ADDR to the NVM device 200 to read the status group code in SLC mode. In this case, the storage controller 100 can send another command CMD to the NVM device 200 to change the mode of the NVM device 200 to SLC mode.

[0108] In operation S403, the NVM device 200 can read the status group code in response to a status group code read command. For example, the NVM device 200 can read the status group code from the memory cell corresponding to address ADDR in SLC mode. The read status group code can be stored... Figure 5 In page buffer unit 220.

[0109] Although not in Figure 11As shown, however, when the status group code and multi-page data are stored on different storage boards, or when a request is made to correct the status group code, the read status group code can be sent to the storage controller 100 according to the output command of the storage controller 100. In this case, the status group code provided to the storage controller 100 can be provided by... Figure 4 The ECC circuit 150 in the device performs error correction and is then resent to the NVM device 200.

[0110] In operation S404, the memory controller 100 may send a recovery read mode change command to the NVM device 200. For example, the memory controller 100 may send the recovery read mode change command via the control signal CTRL or the command CMD. In operation S405, the NVM device 200 may change to recovery read mode in response to the recovery read mode change command. The NVM device 200 may perform read operations in recovery read mode in a manner different from that in normal read mode. For example, the NVM device 200 may perform read operations in recovery read mode using a different read voltage than in normal read mode.

[0111] In operation S406, the storage controller 100 can send a multi-page data read command to the NVM device 200. For example, the storage controller 100 can send the command CMD and the address ADDR to the NVM device 200 to read multi-page data in QLC mode.

[0112] In operation S407, the NVM device 200 can read pre-programmed multi-page data in response to a multi-page data read command. In recovery read mode, the NVM device 200 can perform the read operation based on the status group code. For example, the NVM device 200 can read multi-page data from each pre-programmed memory cell using a read voltage corresponding to the status group data. For example, the read multi-page data can be stored... Figure 5 In page buffer unit 220. The following will refer to... Figures 12 to 17B Let's describe in detail the read operation based on the state group code.

[0113] In operation S408, the storage controller 100 may send a multi-page data output command to the NVM device 200. In operation S409, the NVM device 200 may output the read multi-page data in response to the multi-page data output command. For example, the NVM device 200 may send the multi-page data stored in the page buffer unit 220 to the storage controller 100. According to an embodiment, operation S408 may be skipped. For example, in response to a multi-page data read command, the NVM device 200 may perform a read operation and send the read multi-page data to the storage controller 100.

[0114] In operation S410, the storage controller 100 can correct errors in the multi-page data. When there are no errors in the multi-page data, the storage controller 100 does not perform error correction. Therefore, the multi-page data can be recovered, and the reliability of the recovered multi-page data can be improved. In the example embodiment, error correction in operation S410 can be skipped.

[0115] In the example embodiment, operations S406 to S410 can be performed on each page. For example, the storage controller 100 can provide a read command to the NVM device 200 for each of the four pages, and can also provide an output command to the NVM device 200 for each of the four pages.

[0116] In operation S411, the memory controller 100 can send a normal read mode change command to the NVM device 200. For example, the memory controller 100 can send the normal read mode change command via the control signal CTRL or the command CMD. In operation S412, the NVM device 200 can change to normal read mode in response to the normal read mode change command. The NVM device 200 can perform read operations in normal read mode using a predetermined read voltage, regardless of the status group code.

[0117] In operation S413, the storage controller 100 can send a multi-page data reprogramming command to the NVM device 200. The storage controller 100 can also send the multi-page data recovered in operation S410 along with the multi-page data reprogramming command to the NVM device 200. For example, when the multi-page data comprises four pages, the storage controller 100 can send the command CMD and address ADDR to the NVM device 200 to reprogram the multi-page data in QLC mode.

[0118] In operation S414, the NVM device 200 can reprogram multi-page data in response to a multi-page data reprogramming command. For example, the NVM device 200 can program multi-page data to the memory cell indicated by address ADDR based on a reprogramming verification voltage. The address ADDR provided for reprogramming can be the same as the address ADDR provided for pre-programming.

[0119] Figure 12 It is used to describe Figure 5 A diagram illustrating the read operation of the NVM device 200. (Refer to...) Figure 12 The NVM device 200 may include NAND strings SS1 to SSn and first page buffers PB1 to nth page buffers PBn. The NAND strings SS1 to SSn may be connected to the first page buffers PB1 to nth page buffers PBn via bit lines BL1 to BLn, respectively.

[0120] NAND strings SS1 to SSn may include ground select transistors GST1 to GSTn, memory cells MC10 to MCnm, and string select transistors SST1 to SSTn. Ground select transistors GST1 to GSTn may be connected to the common source line CSL and the ground select line GSL, and memory cells MC10 to MCnm may be connected to the zero word line WL0 to the m word line WLm. String select transistors SST1 to SSTn may be connected to the string select line SSL and the bit lines BL1 to BLn.

[0121] Memory cells MC11 to MCn1, which are connected to the first word line WL1, among memory cells MC10 to MCnm, can be in a pre-programmed state. (Refer to the above.) Figures 8 to 10 As described, multi-page data can be pre-programmed into storage cells MC11 to MCn1 according to pre-programming commands from storage controller 100. For example, when the multi-page data includes first multi-bit data MD1 to nth multi-bit data MDn, such as... Figure 7 As shown, the first multi-bit data MD1 can be preprogrammed into the storage unit MC11, and the second multi-bit data MD2 can be preprogrammed into the storage unit MC21.

[0122] First page buffers PB1 to nth page buffers PBn can store state group codes including first state group data SD1 to nth state group data SDn. First state group data SD1 to nth state group data SDn can respectively correspond to pre-programmed memory cells MC11 to MCn1. When a state group code read command or state group code is received from the memory controller 100, the state group code can be stored in the first page buffers PB1 to nth page buffers PBn. For example, first page buffer PB1 can store first state group data SD1 corresponding to memory cell MC11, and second page buffer PB2 can store second state group data SD2 corresponding to memory cell MC21.

[0123] When performing a read operation on pre-programmed memory cells MC11 to MCn1 in normal read mode, a normal read voltage can be applied to the first word line WL1, and multiple pages of data can be read from memory cells MC11 to MCn1.

[0124] When performing a read operation on pre-programmed memory cells MC11 to MCn1 in recovery read mode, a recovery read voltage can be applied to the first word line WL1, and multi-page data can be read from memory cells MC11 to MCn1. The level of the recovery read voltage can be different from the level of the normal read voltage. For example, to read multiple bits of data pre-programmed into memory cell MC11, a first recovery read voltage corresponding to the first state group data SD1 can be applied to the first word line WL1. To read multiple bits of data pre-programmed into memory cell MC21, a second recovery read voltage corresponding to the second state group data SD2 can be applied to the first word line WL1. When the second state group data SD2 is the same as the first state group data SD1, the second recovery read voltage can be the same as the first recovery read voltage. When the second state group data SD2 is different from the first state group data SD1, the second recovery read voltage can be different from the first recovery read voltage. In other words, when the recovery read voltage corresponding to each value (e.g., "0" and "1") that the first state group data SD1 to the nth state group data SDn can have is applied to the first word line WL1, multi-page data can be read from the memory cells MC11 to MCn1.

[0125] Figure 13 This is a block diagram of a page buffer according to an embodiment. (Refer to...) Figure 13 Page buffer 221 may include a sensing latch (e.g., S latch) 201, a forced latch (e.g., F latch) 202, a high-order bit latch (e.g., M latch) 203, a middle-order bit latch (e.g., U latch) 204, a low-order bit latch (e.g., L latch) 205, and a cache latch (e.g., C latch) 206 connected to sensing node SO. Page buffer 221 may also include a first transistor TR1 connected between bit line BL and sensing node SO.

[0126] The sensing latch 201 can store the result of sensing data stored in the memory cell or the result of sensing the threshold voltage of the memory cell during a read operation or a program verification operation. The sensing latch 201 can also be used to apply a programming bit line voltage or a programming disable voltage to the bit line BL during a programming operation.

[0127] The forced latch 202 can be used to mitigate threshold voltage variations during programming operations. The value stored in the forced latch 202 can vary with the threshold voltage of the memory cell during programming operations, and the voltage applied to the bit line BL during programming operations can vary with the value stored in the forced latch 202.

[0128] The high-order bit latch 203, intermediate bit latch 204, low-order bit latch 205, and cache latch 206 can be used to store externally input data during programming operations and can be referred to as data latches. The number of data latches can vary depending on the embodiment. For example, when 4 bits of data are programmed into a single memory cell, the 4 bits of the 4 bits of data can be stored in the high-order bit latch 203, intermediate bit latch 204, low-order bit latch 205, and cache latch 206, respectively. For example, when 5 bits of data are programmed into a single memory cell, the page buffer 221 may also include a second intermediate bit latch, and the 5 bits of the 5 bits of data can be stored in the high-order bit latch 203, intermediate bit latch 204, second intermediate bit latch, low-order bit latch 205, and cache latch 206, respectively. However, the embodiment is not limited to this, and the page buffer 221 may also include at least two data latches. Before programming is complete, the high-order bit latch 203, the intermediate bit latch 204, the low-order bit latch 205, and the cache latch 206 can retain the data stored therein. Additionally, the cache latch 206 can receive data read from the memory cell from the sensing latch 201 during a read operation and output the data to the outside of the page buffer 221 via the data output line DOUT.

[0129] In an example embodiment, at least one of the data latches (i.e., high-order bit latch 203, middle-order bit latch 204, low-order bit latch 205, and cache latch 206) may temporarily store state group data. Alternatively, the page buffer 221 may also include at least one state group data latch for temporarily storing state group data.

[0130] The first transistor TR1 can be driven by the bit-line shutdown signal BLSHF, which controls the connection between the bit line BL and the sensing node SO, and therefore can be called a "bit-line shutdown transistor". For example, when data is read from the memory cell, the first transistor TR1 is turned on and electrically connects the bit line BL to the sensing latch 201. Conversely, the first transistor TR1 can be turned off when data stored in the sensing latch 201 is sent to the cache latch 206, or when data stored in the cache latch 206 is sent to the forced latch 202.

[0131] Figure 14 A diagram illustrating examples of read voltage in normal read mode and read voltage in recovery read mode according to an embodiment is shown. (Refer to...) Figure 12 and Figure 14Based on multiple data values, each of the pre-programmed memory cells MC11 to MCn1 can correspond to one of multiple threshold voltage distributions (e.g., erase state E and first programming states P1 to fifteenth programming states P15). For example, when the multiple data "1111" is pre-programmed into memory cell MC11, memory cell MC11 can be in erase state E. When the multiple data "1110", "1010", "1000", "1001", "0001", "0000", "0010", "0110", "0100", "1100", "1101", "0101", "0111", "0011", or "1011" is pre-programmed into memory cell MC11, memory cell MC11 can be in one of the first programming states P1 to fifteenth programming states P15. However, the embodiments are not limited to this, and the multi-bit data values ​​corresponding to each threshold voltage distribution (e.g., erase state E and first programming states P1 to fifteenth programming states P15) can be varied. In the example embodiment, states with an odd number of "1" bits (e.g., states P1, P3, P5, P7, P9, P11, P13, and P15) and states with an even number of "1" bits (e.g., erase state E and states P2, P4, P6, P8, P10, P12, and P14) can be arranged alternately.

[0132] Each of the pre-programmed memory cells MC11 to MCn1 can correspond to, for example, one of the threshold voltage distributions of the erase state E in the first state group GROUP1 and the second programming state P2, the fourth programming state P4, the sixth programming state P6, the eighth programming state P8, the tenth programming state P10, the twelfth programming state P12 and the fourteenth programming state P14, or one of the threshold voltage distributions of the first programming state P1, the third programming state P3, the fifth programming state P5, the seventh programming state P7, the ninth programming state P9, the eleventh programming state P11, the thirteenth programming state P13 and the fifteenth programming state P15 in the second state group GROUP2. For example, a memory cell MC11 pre-programmed with multiple bits of data "1111", "1010", "1001", "0000", "0110", "1100", "0101", or "0011" can correspond to the first state group GROUP1; while a memory cell MC11 pre-programmed with multiple bits of data "1110", "1000", "0001", "0010", "0100", "1101", "0111", or "1011" can correspond to the second state group GROUP2. For example, the first state group GROUP1 can correspond to state group data "0", while the second state group GROUP2 can correspond to state group data "1".

[0133] In normal read mode, the first normal read voltage V1n to the fifteenth normal read voltage V15n can be used to read multi-page data from pre-programmed memory cells MC11 to MCn1. For example, as Figure 14 As shown, the first normal read voltage V1n to the fifteenth normal read voltage V15n can be used to read multi-page data from memory cells that have undergone reprogramming. When reading multi-page data from memory cells MC11 to MCn1 using the first normal read voltage V1n to the fifteenth normal read voltage V15n after preprogramming and before reprogramming, the state of each memory cell in the preprogrammed memory cells MC11 to MCn1 may not be accurately identified due to the overlap between the threshold voltage distributions of two adjacent states, and the read multi-bit data values ​​may differ from the data values ​​stored in the preprogrammed memory cells. The reliability of the read multi-bit data may be reduced. Therefore, when reprogramming continues, after power is restored from SPO, the reliability of the preprogrammed multi-page data may be reduced based on the multi-page data read in normal read mode.

[0134] In the recovery read mode, the first recovery read voltages V1, V3, V5, V7, V9, V11, and V13, and the second recovery read voltages V2, V4, V6, V8, V10, V12, and V14 can be used to read multi-page data from pre-programmed memory cells MC11 to MCn1. In an example embodiment, the first recovery read voltages V1, V3, V5, V7, V9, V11, and V13, and the second recovery read voltages V2, V4, V6, V8, V10, V12, and V14 are different from each other. The first recovery read voltages V1, V3, V5, V7, V9, V11, and V13 can be used to read multi-page data from the memory cells corresponding to the first state group GROUP1 among the pre-programmed memory cells MC11 to MCn1. Multi-page data can be read from the memory cells corresponding to the second state group GROUP2 among the pre-programmed memory cells MC11 to MCn1 using the second recovery read voltages V2, V4, V6, V8, V10, V12, and V14. For example, when one of the multiple bits of data "1111", "1010", "1001", "0000", "0110", "1100", "0101", or "0011" has been pre-programmed... Figure 12When accessing the memory cell MC11, for example, multiple bits of data can be read from the memory cell MC11 based on first recovery read voltages V1, V3, V5, V7, V9, V11, and V13. For example, when one of the multiple bits of data "1110", "1000", "0001", "0010", "0100", "1101", "0111", or "1011" has been pre-programmed into the memory cell MC11, multiple bits of data can be read from the memory cell MC11 based on second recovery read voltages V2, V4, V6, V8, V10, V12, and V14. In the example embodiment, first state group data SD1 is used to determine whether to use the first or second recovery read voltage to read the memory cell MC11. For example, when the first state group data SD1 is "0", memory cell MC1 can correspond to the first state group GROUP1, and in recovery read mode, the first recovery read voltages V1, V3, V5, V7, V9, V11, and V13 can be used to read the multi-bit data pre-programmed in memory cell MC11. Memory cell MC11 of the first state group GROUP1 can have one of the even-numbered states P2, P4, P6, P8, P10, P12, and P14, and an erase state E. Two adjacent states among erase state E and even-numbered states P2, P4, P6, P8, P10, P12, and P14 can be spaced apart without overlapping, therefore, memory cell MC11 can be read using the first recovery read voltages V1, V3, V5, V7, V9, V11, and V13. For example, when the first state group data SD1 is "1", memory cell MC11 can correspond to the second state group GROUP2, and in recovery read mode, the second recovery read voltages V2, V4, V6, V8, V10, V12, and V14 can be used to read the multi-bit data pre-programmed in memory cell MC11. Memory cell MC11 of the second state group GROUP2 can have one of the odd-numbered states P1, P3, P5, P7, P9, P11, and P13. Two adjacent states among the odd-numbered states P1, P3, P5, P7, P9, P11, and P13 can be spaced apart without overlapping, therefore, memory cell MC11 can be read using the second recovery read voltages V2, V4, V6, V8, V10, V12, and V14.

[0135] At this time, the first recovery read voltages V1, V3, V5, V7, V9, V11, and V13 corresponding to the first state group GROUP1 can be different from the second recovery read voltages V2, V4, V6, V8, V10, V12, and V14 corresponding to the second state group GROUP2. Furthermore, the recovery read voltages used in recovery read mode (e.g., the first recovery read voltages V1, V3, V5, V7, V9, V11, and V13, and the second recovery read voltages V2, V4, V6, V8, V10, V12, and V14) can be different from the normal read voltages used in normal read mode (e.g., the first normal read voltages V1n to the fifteenth normal read voltage V15n).

[0136] As described above, in recovery read mode, recovery read voltages different from normal read voltages (e.g., first recovery read voltages V1, V3, V5, V7, V9, V11, and V13, and second recovery read voltages V2, V4, V6, V8, V10, V12, and V14) can be used. The state of each of the pre-programmed memory cells MC11 to MCn1 can be identified relatively accurately, and the read multi-bit data value can be identical to the data value stored in the pre-programmed memory cell. The reliability of the read multi-bit data can be improved. Therefore, when reprogramming is performed based on multi-page data read in recovery read mode, the reliability of the pre-programmed multi-page data can be improved.

[0137] Figure 15 This is a table illustrating examples of read voltages in normal read mode according to an embodiment. (Refer to...) Figures 12 to 15 When reading multi-page data from memory cells MC11 to MCn1 that have been pre-programmed in normal read mode, a read voltage can be applied to the first word line WL1 based on the normal read voltage meter NRVT. A different read voltage can be applied to each page.

[0138] For example, when the threshold voltage distribution corresponds to, as Figure 14When dealing with multiple data values, the first normal read voltage V1n, the fourth normal read voltage V4n, the sixth normal read voltage V6n, and the eleventh normal read voltage V11n can be applied to the first word line WL1 to read the first page data in the multi-page data. The third normal read voltage V3n, the seventh normal read voltage V7n, the ninth normal read voltage V9n, and the thirteenth normal read voltage V13n can be applied to the first word line WL1 to read the second page data in the multi-page data. The second normal read voltage V2n, the eighth normal read voltage V8n, and the fourteenth normal read voltage V14n can be applied to the first word line WL1 to read the third page data in the multi-page data. The fifth normal read voltage V5n, the tenth normal read voltage V10n, the twelfth normal read voltage V12n, and the fifteenth normal read voltage V15n can be applied to the first word line WL1 to read the fourth page data in the multi-page data. In this case, the read voltages can be applied in ascending order, but the order in which the read voltages are applied can be varied.

[0139] Figure 16 This is a table illustrating examples of read voltages in recovery read mode according to an embodiment. (Refer to...) Figures 12 to 16 When reading multi-page data from memory cells MC11 to MCn1 that have been pre-programmed in recovery read mode, a read voltage can be applied to the first word line WL1 based on the recovery read voltage meter RRVT. In this case, a different read voltage can be applied to each page.

[0140] For example, when the threshold voltage distribution corresponds to, as Figure 14When displaying multiple data values, the first recovery read voltages V1, V3, V5, and V11 corresponding to the first state group GROUP1 and the second recovery read voltages V4, V6, and V10 corresponding to the second state group GROUP2 can be applied to the first word line WL1 to read the first page data in the multi-page data. The first page data can be read from the memory cell corresponding to the first state group GROUP1 using the first recovery read voltages V1, V3, V5, and V11, and from the memory cell corresponding to the second state group GROUP2 using the second recovery read voltages V4, V6, and V10. The first recovery read voltages V3, V7, V9, and V13 corresponding to the first state group GROUP1 and the second recovery read voltages V2, V6, V8, and V12 corresponding to the second state group GROUP2 can be applied to the first word line WL1 to read the second page data in the multi-page data. The second page data can be read from the memory cell corresponding to the first state group GROUP1 using the first recovery read voltages V3, V7, V9, and V13, and from the memory cell corresponding to the second state group GROUP2 using the second recovery read voltages V2, V6, V8, and V12. Similarly, the first recovery read voltages V1, V7, and V13 corresponding to the first state group GROUP1 and the second recovery read voltages V2, V8, and V14 corresponding to the second state group GROUP2 can be applied to the first word line WL1 to read the third page data in the multi-page data; and the first recovery read voltages V5, V9, and V11 corresponding to the first state group GROUP1 and the second recovery read voltages V4, V10, V12, and V14 corresponding to the second state group GROUP2 can be applied to the first word line WL1 to read the fourth page data in the multi-page data. In this case, the read voltages can be applied in ascending order, but the order in which the read voltages are applied can be varied.

[0141] As described above, in recovery read mode, a recovery read voltage corresponding to each state group can be applied to the first word line WL1 to read a single page.

[0142] In an example embodiment, each of the first page buffers PB1 to the nth page buffer PBn can output only the data sensed by the recovery read voltage corresponding to the state group data stored therein. For example, first data can be sensed from the memory cell MC11 by the recovery read voltage corresponding to the first state group GROUP1, and second data can be sensed from the memory cell MC11 by the recovery read voltage corresponding to the second state group GROUP2. The sensed first and second data can be stored in... Figure 13The sensor latch 201, the forced latch 202, the high-order bit latch 203, the intermediate bit latch 204, and the low-order bit latch 205 are included. The first page buffer PB1 can output only the first data or the second data through the cache latch 206 based on the state group data stored in at least one of the latches among the sensor latch 201, the forced latch 202, the high-order bit latch 203, the intermediate bit latch 204, and the low-order bit latch 205.

[0143] In an example embodiment, each of the first page buffers PB1 to the nth page buffer PBn can output data sensed by a recovery read voltage corresponding to all state group data. For example, first data can be sensed from memory cell MC11 by a recovery read voltage corresponding to the first state group GROUP1, and second data can be sensed from memory cell MC11 by a recovery read voltage corresponding to the second state group GROUP2. The sensed first and second data can be stored in... Figure 13 The first page buffer PB1 can output first and second data through cache latch 206. In this case, the memory controller 100 can select one of the first and second data provided from the NVM device 200 based on the state group data stored therein.

[0144] In an example embodiment, a command CMD and an address ADDR can be provided for each page to read multi-page data in recovery read mode. For example, four command CMDs can be provided to read all multi-page data including four pages. In this case, the number of recovery read voltage levels applied according to a single command CMD can be greater than the number of normal read voltage levels applied according to a single command CMD in normal read mode. For example, first recovery read voltages V1, V3, V5, and V11 corresponding to the first state group GROUP1 and second recovery read voltages V4, V6, and V10 corresponding to the second state group GROUP2 can be applied according to the command CMD used to read the first page data in recovery read mode. First normal read voltages V1n, fourth normal read voltage V4n, sixth normal read voltage V6n, and eleventh normal read voltage V11n can be applied according to the command CMD used to read the first page data in normal read mode. In this case, the number of recovery read voltage levels applied according to a single command CMD can be seven, and the number of normal read voltage levels applied according to a single command CMD can be four.

[0145] Figure 17A and Figure 17BAn example of adjusting the recovery read voltage according to an embodiment is shown. (Refer to...) Figure 17A The NAND string 211 may include memory cells 0 through m through m. In programming operations on memory cells 0 through m, programming can be performed sequentially from m to 0. Memory cells closer to the string select transistor SST can be programmed earlier, while those further from the SST can be programmed later. For example, after the first memory cell MC1 is pre-programmed, the zeroth memory cell MC0 can be pre-programmed.

[0146] When power is restored from SPO after the first memory cell MC1, which is connected to the first word line WL1 of NAND string 211, has been pre-programmed, multiple bits of data can be read from the first memory cell MC1 based on the recovery read voltage in recovery read mode. The recovery read voltage can be adjusted according to the state of the zeroth memory cell MC0 adjacent to the first memory cell MC1. For example, when the zeroth memory cell MC0 is in the pre-programmed state, the recovery read voltage applied to the first word line WL1 can be increased or decreased. Therefore, by applying the adjusted recovery read voltage to the first word line WL1, multiple bits of data can be read from the first memory cell MC1.

[0147] Reference Figure 17B In programming memory cells MC0 through MCm, programming can be performed sequentially from MC0 to MCm. Memory cells closer to the ground select transistor GST can be programmed earlier, while those farther from GST can be programmed later. For example, after the first memory cell MC1 is pre-programmed, the second memory cell MC2 can be pre-programmed.

[0148] When the first memory cell MC1, connected to the first word line WL1 of NAND string 211, is restored to power from SPO after being pre-programmed, multiple bits of data can be read from the first memory cell MC1 based on the recovery read voltage in recovery read mode. The recovery read voltage can be adjusted according to the state of the second memory cell MC2 adjacent to the first memory cell MC1. For example, when the second memory cell MC2 is in the pre-programmed state, the recovery read voltage applied to the first word line WL1 can be increased or decreased. Therefore, by applying the adjusted recovery read voltage to the first word line WL1, multiple bits of data can be read from the first memory cell MC1.

[0149] As described above, when the first memory cell MC1 is pre-programmed and then the adjacent zeroth memory cell MC0 or the second memory cell MC2 is pre-programmed, the threshold voltage of the first memory cell MC1 can be changed by applying a programming voltage to the zero word line WL0 connected to the zeroth memory cell MC0 adjacent to the first memory cell MC1 or the second word line WL2 connected to the second memory cell MC2 adjacent to the first memory cell MC1. Therefore, the recovery read voltage is adjusted according to the pre-programming state of the adjacent memory cells (e.g., the zeroth memory cell MC0 or the second memory cell MC2) to compensate for the change in the threshold voltage of the first memory cell MC1.

[0150] Figure 18 This is a flowchart of an operation method of a storage system according to an embodiment. (Refer to...) Figure 1 and Figure 18 In operation S510, storage system 10 can pre-program multi-page data into storage cells. In operation S520, storage system 10 can generate status group codes based on the multi-page data.

[0151] In operation S530, storage system 10 can back up the status group code to NVM device 200. In operation S540, storage system 10 can determine whether an SPO has occurred. If an SPO has occurred, in operation S550, after power is restored, storage system 10 can read multi-page data from the pre-programmed storage cells based on the backed-up status group code. For example, storage system 10 can read multi-page data based on the status group code, as described above. Figures 11 to 17B As described.

[0152] In operation S560, storage system 10 can reprogram multi-page data into storage cells based on the read multi-page data. The reprogrammed storage cells can be the same as the pre-programmed storage cells.

[0153] If no SPO occurs after pre-programming, in operation S570, storage system 10 can reprogram the multi-page data to the storage cell. Storage system 10 can reprogram the multi-page data based on the multi-page data stored in the buffer memory 130 of storage controller 100.

[0154] according to Figure 18 In one embodiment, storage system 10 can generate and back up state group codes regardless of whether an SPO occurs. For example, the state group code can be generated and backed up before operation 540, which checks for the occurrence of an SPO. For each pre-programmed multi-page data, the state group code can be backed up to NVM device 200. Because the state group code is not backed up when an SPO occurs, it is different from operation S240, which performs the backup of the state group code after an SPO occurs. Figure 8 Compared to the previous embodiment, the size and capacity of the auxiliary power supply used for backing up state group codes can be further reduced.

[0155] Figure 19 This is a flowchart of an operation method of a storage system according to an embodiment. (Refer to...) Figure 1 and Figure 19 In operation S610, storage system 10 can pre-program multi-page data into the first storage unit. In operation S620, storage system 10 can generate a status group code based on the multi-page data.

[0156] In operation S630, the storage system 10 can determine whether an SPO has occurred. If an SPO has occurred, in operation S640, the storage system 10 can back up the status group code to the NVM device 200. In operation S650, after power is restored, the storage system 10 can read multi-page data from the pre-programmed first storage cell based on the backed-up status group code. For example, the storage system 10 can read multi-page data based on the status group code, as described above. Figures 11 to 17B As described.

[0157] Instead of reprogramming the pre-programmed first storage cell, storage system 10 can pre-program a second storage cell, different from the first storage cell, using the multi-page data read in operation S650. For example, in operation S660, storage system 10 can pre-program multi-page data into the second storage cell based on the read multi-page data. In operation S670, storage system 10 can reprogram multi-page data into the second storage cell based on the read multi-page data. The second storage cell may be included in a different storage block than the first storage cell, but the embodiments are not limited thereto.

[0158] If no SPO occurs after pre-programming, in operation S680, storage system 10 can reprogram the multi-page data to the first storage cell. Storage system 10 can reprogram the multi-page data based on the multi-page data stored in the buffer memory 130 of storage controller 100.

[0159] according to Figure 19 In one embodiment, the storage system 10 can program multi-page data into a second storage cell that is different from the pre-programmed first storage cell after power is restored from the SPO. For example, when programming operations on the first storage cell can no longer be performed, the storage system 10 can perform new programming operations on the second storage cell based on the restored multi-page data.

[0160] Figure 20 This is a flowchart of an operation method of a storage system according to an embodiment. (Refer to...) Figure 1 and Figure 20 In operation S701, the storage system 10 can perform a first pre-programming operation to pre-program multi-page data into the storage cells. In operation S702, the storage system 10 can generate a first state group code based on the multi-page data.

[0161] In operation S703, the storage system 10 can determine whether a SPO has occurred. If an SPO has occurred, in operation S704, the storage system 10 can back up the first state group code to the NVM device 200. In operation S705, after power is restored, the storage system 10 can read multi-page data from the storage cell that has undergone the first pre-programming operation based on the backed-up first state group code. In operation S706, the storage system 10 can perform a second pre-programming operation based on the read multi-page data to pre-program the multi-page data into the storage cell that has undergone the first pre-programming operation. For example, the pre-programming verification voltage of the second pre-programming operation can be higher than the pre-programming verification voltage of the first pre-programming operation.

[0162] If no SPO occurs after the first preprogramming operation, in operation S707, the storage system 10 may perform a second preprogramming operation to preprogram multipage data into the storage cells that have already undergone the first preprogramming operation. The storage system 10 may perform the second preprogramming operation based on the multipage data stored in the buffer memory 130 of the storage controller 100.

[0163] In operation S708, the storage system 10 can generate a second state group code based on multi-page data. For example, the overlap area between threshold voltage distributions generated by the second pre-programming operation can be reduced compared to the overlap area between threshold voltage distributions generated by the first pre-programming operation. Therefore, the number of state groups used to classify threshold voltage distributions generated by the second pre-programming operation can be less than the number of state groups used to classify threshold voltage distributions generated by the first pre-programming operation. Therefore, the number of bits in the second state group code can be less than the number of bits in the first state group code.

[0164] In operation S709, the storage system 10 can determine whether an SPO has occurred. If an SPO has occurred, in operation S710, the storage system 10 can back up the second state group code to the NVM device 200. In operation S711, after power is restored, the storage system 10 can read multi-page data from the storage cell that has undergone the second pre-programming operation based on the backed-up second state group code. In operation S712, the storage system 10 can reprogram the multi-page data to the storage cell that has undergone the second pre-programming operation based on the read multi-page data. For example, the reprogramming verification voltage used for reprogramming can be higher than the pre-programming verification voltage used for the second pre-programming operation.

[0165] If no SPO occurs after the second pre-programming operation, in operation S713, the storage system 10 can reprogram the multi-page data to the storage cell that has already undergone the second pre-programming operation. If an SPO has occurred in operation S703, the storage system 10 can perform reprogramming based on the multi-page data read from the storage cell that has already undergone the first pre-programming operation. If no SPO occurs in operation S703, the storage system 10 can perform reprogramming based on the multi-page data stored in the buffer memory 130 of the storage controller 100.

[0166] As described above, the storage system 10 can perform multiple pre-programmed operations. The storage system 10 can generate a state group code (i.e., state group data) corresponding to each pre-programmed operation. The number of bits in the state group data can vary with the pre-programmed operation, and the number of bits in the state group data corresponding to an earlier pre-programmed operation can be greater than the number of bits in the state group data corresponding to a later pre-programmed operation.

[0167] Figure 21 A memory device having a chip-to-chip structure according to an embodiment is shown.

[0168] Reference Figure 21 The memory device 900 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (i.e., memory cell regions) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then bonding the upper and lower chips together. For example, the bonding method may include electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip to a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal can be formed of copper (Cu), the bonding method may be copper-to-copper (Cu-Cu) bonding. However, the invention is not limited thereto. In an example embodiment, the bonding metal may be formed of aluminum or tungsten.

[0169] The peripheral circuit area PERI and cell area CELL of the storage device 900 can each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0170] The Peripheral Circuit Region (PERI) may include: a first substrate 710, an interlayer insulating layer 715, a plurality of circuit elements 720a, 720b, and 720c formed on the first substrate 710, first metal layers 730a, 730b, and 730c respectively connected to the plurality of circuit elements 720a, 720b, and 720c, and second metal layers 740a, 740b, and 740c respectively formed on the first metal layers 730a, 730b, and 730c. In an example embodiment, the first metal layers 730a, 730b, and 730c may be formed of tungsten, while the second metal layers 740a, 740b, and 740c may be formed of copper. Tungsten has a higher resistivity than copper.

[0171] exist Figure 21 In the example embodiments shown, although first metal layers 730a, 730b, and 730c and second metal layers 740a, 740b, and 740c are shown and described, they are not limited thereto, and one or more metal layers may be further formed on the second metal layers 740a, 740b, and 740c. At least a portion of the one or more metal layers formed on the second metal layers 740a, 740b, and 740c may be formed of a metal such as aluminum. The resistivity of the metal in the one or more metal layers may be lower than the resistivity of the copper forming the second metal layers 740a, 740b, and 740c.

[0172] An interlayer insulating layer 715 may be disposed on a first substrate 710 and cover a plurality of circuit elements 720a, 720b, and 720c, first metal layers 730a, 730b, and 730c, and second metal layers 740a, 740b, and 740c. The interlayer insulating layer 715 may include an insulating material such as silicon oxide or silicon nitride.

[0173] Lower bonding metals 771b and 772b can be formed on the second metal layer 740b in the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals 771b and 772b in the peripheral circuit area (PERI) can be electrically connected to the upper bonding metals 871b and 872b in a bonding manner, and the lower bonding metals 771b and 772b, as well as the upper bonding metals 871b and 872b, can be formed of aluminum, copper, tungsten, or the like. Furthermore, the upper bonding metals 871b and 872b in the cell area (CELL) can be referred to as first metal pads, while the lower bonding metals 771b and 772b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0174] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 810 and a common source line 820. Multiple word lines 831 to 838 (i.e., 830) may be stacked on the second substrate 810 in a direction perpendicular to the upper surface of the second substrate 810 (Z-axis direction). At least one string select line and at least one ground select line may be arranged on and below the multiple word lines 830, respectively; that is, the multiple word lines 830 may be positioned between the at least one string select line and the at least one ground select line.

[0175] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 810 and pass through multiple word lines 830, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c may be a bit line contact, and the second metal layer 860c may be a bit line. In an example embodiment, the bit line 860c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 810.

[0176] exist Figure 21 In the example embodiment shown, the region provided with the channel structure CH, bit line 860c, etc., can be defined as the bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 860c can be electrically connected to circuit element 720c that provides page buffer 893 in the peripheral circuit region PERI. For example, bit line 860c can be connected to upper bonding metals 871c and 872c in the cell region CELL, and upper bonding metals 871c and 872c can be connected to lower bonding metals 771c and 772c that are connected to the circuit element 720c of the page buffer 893.

[0177] In the word line bonding area (WLBA), multiple word lines 830 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 810 and may be connected to multiple cell contact plugs 841 to 847 (i.e., 840). The multiple word lines 830 and the multiple cell contact plugs 840 may be connected to each other in pads provided by at least a portion of the multiple word lines 830 extending at different lengths in the second direction. A first metal layer 850b and a second metal layer 860b may be sequentially connected to the lower portion of the multiple cell contact plugs 840 connected to the multiple word lines 830. The multiple cell contact plugs 840 may be connected to the circuit region PERI in the word line bonding area (WLBA) via upper bonding metals 871b and 872b of the cell region CELL and lower bonding metals 771b and 772b of the peripheral circuit region PERI.

[0178] Multiple cell contact plugs 840 may be electrically connected to circuit element 720b providing a row decoder 894 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit element 720b providing the row decoder 894 may differ from the operating voltage of circuit element 720c providing the page buffer 893. For example, the operating voltage of circuit element 720c providing the page buffer 893 may be greater than the operating voltage of circuit element 720b providing the row decoder 894.

[0179] A common source line contact plug 880 can be disposed in the external pad bonding region PA. The common source line contact plug 880 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 820. A first metal layer 850a and a second metal layer 860a can be sequentially stacked on the lower part of the common source line contact plug 880. For example, the region where the common source line contact plug 880, the first metal layer 850a, and the second metal layer 860a are disposed can be defined as the external pad bonding region PA.

[0180] Input / output pads 705 and 805 can be set in the external pad bonding area PA. (See reference...) Figure 21 A lower insulating film 701 covering the lower surface of the first substrate 710 may be formed below the first substrate 710, and a first input / output pad 705 may be formed on the lower insulating film 701. The first input / output pad 705 can be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI via a first input / output contact plug 703, and can be separated from the first substrate 710 by the lower insulating film 701. In addition, a side insulating film may be disposed between the first input / output contact plug 703 and the first substrate 710 to electrically separate the first input / output contact plug 703 from the first substrate 710.

[0181] Reference Figure 21 An upper insulating film 801 covering the upper surface of the second substrate 810 can be formed on the second substrate 810, and a second input / output pad 805 can be disposed on the upper insulating film 801. The second input / output pad 805 can be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI via a second input / output contact plug 803. For example, the second input / output contact plug 803 can be connected to the circuit element 720a via lower bonding metals 771a and 772a.

[0182] According to the embodiment, the second substrate 810 and the common source line 820 are not disposed in the region where the second input / output contact plug 803 is disposed. Furthermore, the second input / output pad 805 does not overlap with the word line 830 in the third direction (Z-axis direction). (Refer to...) Figure 21 The second input / output contact plug 803 can be separated from the second substrate 810 in a direction parallel to the upper surface of the second substrate 810, and can pass through the interlayer insulating layer 815 of the cell region CELL to connect to the second input / output pad 805.

[0183] According to embodiments, the first input / output pad 705 and the second input / output pad 805 can be selectively formed. For example, the storage device 900 may include only the first input / output pad 705 disposed on the first substrate 710, or it may include only the second input / output pad 805 disposed on the second substrate 810. Alternatively, the storage device 900 may include both the first input / output pad 705 and the second input / output pad 805.

[0184] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell region CELL and the external pad bonding area PA and bit line bonding area BLBA included in the peripheral circuit region PERI, the metal pattern in the uppermost metal layer can be set as a dummy pattern or the uppermost metal layer can be absent.

[0185] In the external pad bonding region PA, the storage device 900 may include a lower metal pattern 773a in the uppermost metal layer of the peripheral circuit region PERI. The lower metal pattern 773a may correspond to the upper metal pattern 872a formed in the uppermost metal layer of the cell region CELL, and may have the same shape as the upper metal pattern 872a of the cell region CELL. In the peripheral circuit region PERI, the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL.

[0186] Lower bonding metals 771b and 772b can be formed on the second metal layer 740b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 771b and 772b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 871b and 872b of the cell region CELL via Cu-Cu bonding.

[0187] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 892, corresponding to the lower metal pattern 752 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern 752 of the peripheral circuit region PERI, can be formed in the uppermost metal layer of the cell region CELL. No contact is formed on the upper metal pattern 892 formed in the uppermost metal layer of the cell region CELL. For example, the lower metal pattern 752 can be connected to the circuit element 720c via a lower bonding metal 751.

[0188] In an example embodiment, a reinforcing metal pattern corresponding to and having the same shape as the metal pattern formed in the uppermost metal layer of one of the cell region CELL and the peripheral circuit region PERI can be formed in the uppermost metal layer of the other of the cell region CELL and the peripheral circuit region PERI, and contacts may not be formed on the reinforcing metal pattern.

[0189] Figure 22 This is a block diagram illustrating an example of applying a storage system to an SSD system according to an embodiment. (Refer to...) Figure 22 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 can exchange signals SIG with the host 1100 via a signal connector and can receive power PWR via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and storage devices (MEMs) 1230, 1240, and 1250. The storage devices 1230, 1240, and 1250 can be connected to the SSD controller 1210 via channels Ch1, Ch2, and Chn, respectively.

[0190] SSD controller 1210 can control storage devices 1230, 1240, and 1250 in response to the SIG signal received from host 1100. SSD controller 1210 can use the above-mentioned reference... Figures 1 to 21 The storage controller 100 implements this. For example, when a State of Point of Existence (SPO) occurs during programming of multi-bit data, the SSD controller 1210 can control storage devices 1230, 1240, and 1250 to back up state group data corresponding to the multi-bit data. The SSD controller 1210 can control storage devices 1230, 1240, and 1250 so that the multi-bit data can be restored based on the backed-up state group data after power is restored. Therefore, even if an SPO occurs during programming of multi-bit data, the programming operation can be completed normally.

[0191] Storage devices 1230, 1240, and 1250 can operate under the control of SSD controller 1210. Storage devices 1230, 1240, and 1250 can all use the above-mentioned reference... Figures 1 to 21The NVM device 200 is used for implementation. For example, when an SPO occurs, storage devices 1230, 1240, and 1250 can all back up state group data under the control of SSD controller 1210. After power is restored, storage devices 1230, 1240, and 1250 can all read pre-programmed multi-bit data based on the backed-up state group data under the control of SSD controller 1210.

[0192] The auxiliary power supply 1220 can be connected to the host 1100 via a power connector. The auxiliary power supply 1220 can receive power PWR from the host 1100 and can be charged. When the power supply from the host 1100 is unstable, the auxiliary power supply 1220 can supply power to the SSD 1200.

[0193] Figure 23 This is a block diagram of a network system using a storage system according to an embodiment. (Refer to...) Figure 23 Network system 2000 is a facility that stores various types of data and provides services, and may be referred to as a data center or data storage center. Network system 2000 may include application servers 2100 to 2100n and storage servers 2200 to 2200m. Application servers 2100 to 2100n and storage servers 2200 to 2200m may be referred to as computing nodes. The number of application servers 2100 to 2100n and the number of storage servers 2200 to 2200m may vary depending on the embodiment and may differ from each other.

[0194] Application servers 2100 to 2100n and storage servers 2200 to 2200m can communicate with each other via network 2300. Network 2300 can be implemented using Fibre Channel (FC) or Ethernet. In this case, FC is the medium for high-speed data transmission and can use optical switches that provide high performance and / or high availability. Depending on the access method of network 2300, storage servers 2200 to 2200m can be configured as file storage, block storage, or object storage.

[0195] In example embodiments, network 2300 may be used solely for storage, such as a storage area network (SAN). For example, the SAN may include an FC-SAN implemented using an FC network and according to the FC protocol (FCP). In example embodiments, the SAN may include an IP-SAN implemented using a Transmission Control Protocol / Internet Protocol (TCP / IP) network and according to the Internet Small Computer System Interface (iSCSI) (or SCSI over TCP / IP) protocol. In example embodiments, network 2300 may include a general network such as a TCP / IP network. For example, network 2300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), or Fabric Fast NVM (NVMe-oF).

[0196] In the following description, the focus will be on application server 2100 and storage server 2200. The description of application server 2100 can also be applied to other application servers 2100n, and the description of storage server 2200 can also be applied to other storage servers 2200m.

[0197] Application server 2100 may include processor 2110 and memory 2120. Processor 2110 can control all operations of application server 2100 and can access memory 2120 and execute instructions and / or data loaded into memory 2120. According to embodiments, the number of processors 2110 and memory 2120 included in application server 2100 may vary. In an example embodiment, processors 2110 and memory 2120 may form a processor-memory pair. In an example embodiment, the number of processors 2110 may differ from the number of memory 2120.

[0198] Application server 2100 may also include storage device 2150. The number of storage devices 2150 included in application server 2100 may vary depending on the embodiment. Processor 2110 may provide commands to storage device 2150, and storage device 2150 may operate in response to commands received from processor 2110. However, embodiments are not limited thereto, and application server 2100 may not include storage device 2150.

[0199] Application server 2100 may further include a switch (i.e., switch logic circuitry) 2130 and a network interface card (NIC) 2140. Switch 2130 can selectively connect processor 2110 or NIC 2140 to storage device 2150 under the control of processor 2110. NIC 2140 may include a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. In an example embodiment, processor 2110 and NIC 2140 may be integrated with each other. In an example embodiment, storage device 2150 and NIC 2140 may be integrated with each other.

[0200] Application server 2100 can store data requested by users or clients in one of storage servers 2200 to 2200m via network 2300. Application server 2100 can also retrieve data requested by users or clients from one of storage servers 2200 to 2200m via network 2300. For example, application server 2100 may include a web server or a database management system (DBMS).

[0201] Application server 2100 can access via network 2300 the memory 2120n or storage device 2150n, the memory 2220 or storage device 2250, all included in application server 2100n, the memory 2220 or storage device 2250, all included in storage server 2200, or the memory 2220m or storage device 2250m, all included in storage server 2200m. Therefore, application server 2100 can perform various operations on data stored in application servers 2100 and 2100n and / or storage servers 2200 and 2200m. For example, application server 2100 can execute instructions for moving or copying data between application servers 2100 and 2100n and / or storage servers 2200 and 2200m. In this case, for security or privacy, data can be moved in an encrypted state via network 2300.

[0202] Storage server 2200 may include processor 2210 and memory 2220. Processor 2210 can control all operations of storage server 2200 and can access memory 2220 and execute instructions and / or data loaded into memory 2220. According to embodiments, the number of processors 2210 and memory 2220 included in storage server 2200 may vary. In an example embodiment, processors 2210 and memory 2220 may form a processor-memory pair. In an example embodiment, the number of processors 2210 may differ from the number of memory 2220.

[0203] Processor 2210 may include a single-core processor or a multi-core processor. For example, processor 2210 may include a general-purpose processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a microcontroller unit (MCU), a microprocessor, a network processor, an embedded processor, a field-programmable gate array (FPGA), a special-purpose instruction set processor (ASIP), a special-purpose integrated circuit (ASIC) processor, etc.

[0204] Storage server 2200 may also include at least one storage device 2250. The number of storage devices 2250 included in storage server 2200 may vary depending on the embodiment. Storage device 2250 may include a controller (CTRL) 2251, NAND flash memory (NAND) 2252, DRAM 2253, and an interface (I / F) 2254. The configuration and operation of storage device 2250 will be described in detail below. The following description of storage device 2250 can also be applied to other storage devices 2150, 2150n, and 2250m.

[0205] Interface 2254 can provide physical connectivity between processor 2210 and controller 2251, as well as physical connectivity between NIC 2240 and controller 2251. For example, interface 2254 can be implemented using a direct-attached storage (DAS) method that directly connects storage device 2250 via a dedicated cable. Interface 2254 can be implemented using various interface methods such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB, SD card, MMC, eMMC, and CF card interfaces.

[0206] Controller 2251 can control all operations of storage device 2250. Controller 2251 can program data into NAND flash memory 2252 in response to programming commands, and can read data from NAND flash memory 2252 in response to read commands. For example, programming commands and / or read commands can be provided via processor 2110 or directly from processor 2210 of storage server 2200, processor 2210m of storage server 2200m, processor 2110 of application server 2100, or processor 2110n of application server 2100n.

[0207] NAND flash memory 2252 may include multiple NAND flash memory cells. However, embodiments are not limited thereto. Storage device 2250 may include NVM such as RRAM, PRAM, or MRAM, magnetic storage media, or optical storage media other than NAND flash memory 2252.

[0208] DRAM 2253 can be used as a buffer memory. For example, DRAM 2253 may include Double Data Rate Synchronous DRAM (DDR SDRAM), Low Power DDR (LPDDR) SDRAM, Graphics DDR (GDDR) SDRAM, Rambus DRAM (RDRAM), or High Bandwidth Memory (HBM). However, embodiments are not limited to these, and storage device 2250 may use other volatile memory besides DRAM or NVM as buffer memory. DRAM 2253 may temporarily store (or cache) data to be programmed into or read from NAND flash memory 2252.

[0209] Storage server 2200 may also include switch 2230 and NIC 2240. Switch 2230 can selectively connect processor 2210 or NIC 2240 to storage device 2250 under the control of processor 2210. In an example embodiment, processor 2210 and NIC 2240 may be integrated with each other. In an example embodiment, storage device 2250 and NIC 2240 may be integrated with each other.

[0210] Storage devices 2150, 2150n, 2250, and 2250m can all correspond to the above reference. Figures 1 to 20 The storage system 10 is described. For example, storage device 2250 can operate according to multi-page data programming commands from one of processors 2110, 2110n, 2210, and 2210m. When storage device 2250 operates according to programming commands from one of processors 2110, 2110n, 2210, and 2210m, storage device 2250 can receive programming commands through processor 2210, or it can receive programming commands directly from a processor connected via switch 2230. Controller 2251 can control NAND flash memory 2252 to store multi-page data in response to programming commands. For example, when a SPO occurs during a programming operation on multi-page data (e.g., when an SPO occurs in storage server 2200), storage device 2250 can back up the state group code corresponding to the multi-page data to NAND flash memory 2252. When power is restored from the SPO, storage device 2250 can restore the pre-programmed multi-page data based on the backed-up state group code. Storage device 2250 can perform programming operations on multi-page data by performing reprogramming operations based on recovered multi-page data.

[0211] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a storage system including a storage controller and non-volatile storage devices, the method comprising: Multipage data in the storage controller is preprogrammed into a plurality of memory cells in the non-volatile storage device connected to a first word line, wherein the multipage data includes a plurality of multi-bit data, wherein each of the plurality of memory cells is preprogrammed to have a threshold voltage according to a corresponding multi-bit data in the plurality of multi-bit data, and wherein the threshold voltage corresponds to one of a plurality of preprogrammed states; A status group code is generated based on the plurality of multi-bit data in the multi-page data, wherein the status group code includes a plurality of status group data, wherein the number of bits in each status group data is less than the number of bits in the corresponding single multi-bit data in the plurality of multi-bit data in the multi-page data, and wherein each status group data is generated based on the number of "1" bits in the corresponding single multi-bit data in the plurality of multi-bit data; When a sudden power failure occurs after the storage unit has been pre-programmed, the state group code is backed up to the non-volatile storage device; After power is restored from the sudden power outage, the multi-page data is recovered by reading the pre-programmed plurality of storage units based on the state group code; The multi-page data recovered from the pre-programmed plurality of storage units is reprogrammed back into the pre-programmed plurality of storage units; and If no sudden power failure occurs after the storage cells have been pre-programmed, the multi-page data in the storage controller is reprogrammed into the pre-programmed storage cells.

2. The operating method according to claim 1, in, The multiple pre-programmed states are grouped into N state groups. Each of the N state groups has M pre-programmed states from the plurality of pre-programmed states, where M is equal to the number of the plurality of pre-programmed states divided by N, and M and N are integers. Each of the multiple state group data represents a corresponding state group among the N state groups.

3. The operating method according to claim 2, in, The reading of the multi-page data from the plurality of storage units includes: Set the read operation of the non-volatile storage device to a recovery read mode; and In the recovery read mode, a first read voltage is applied to the first word line connected to the pre-programmed plurality of memory cells, the first read voltage being determined based on each of the plurality of state group data.

4. The operating method according to claim 3, in, The read voltage level of the first read voltage applied to the first word line to read the multi-page data in the recovery read mode is different from the read voltage level of the second read voltage applied to the first word line to read the multi-page data in the normal read mode.

5. The operating method according to claim 3, in, The first read voltage has a first read voltage level corresponding to a first state group data among the plurality of state group data, and a second read voltage level different from the first read voltage level corresponding to a second state group data among the plurality of state group data.

6. The operating method according to claim 3, in, In the recovery read mode, the number of read voltage levels applied to the first word line according to the read command is greater than the number of read voltage levels applied to the first word line according to the read command in the normal read mode.

7. The operating method according to claim 3, in, The voltage level of the first read voltage applied to the first word line is adjusted according to whether the memory cell connected to the second word line adjacent to the first word line is in a pre-programmed state.

8. The operating method according to claim 1, in, The programming verification voltage used for the reprogramming is higher than the programming verification voltage used for the preprogramming.

9. The operating method according to claim 1, in, The non-volatile storage device generates the state group code based on a state group code generation command from the storage controller.

10. The operating method according to claim 1, in, The backup of the state group code to the non-volatile storage device is performed by programming the state group code into the non-volatile storage device in a single-level cell mode.

11. The operating method according to claim 1, in, The reprogramming of the multi-page data includes: Correcting errors in the multi-page data read from the pre-programmed plurality of storage units; and The corrected multi-page data is reprogrammed into the pre-programmed plurality of storage units.

12. A method of operating a storage system including a storage controller and a non-volatile storage device, the method comprising: Multipage data in the storage controller is preprogrammed into a plurality of memory cells in the non-volatile storage device connected to a word line, wherein the multipage data includes a plurality of multi-bit data, wherein each of the plurality of memory cells is preprogrammed to have a threshold voltage according to a corresponding multi-bit data in the plurality of multi-bit data, and wherein the threshold voltage corresponds to one of a plurality of preprogrammed states; A status group code is generated based on the plurality of multi-bit data in the multi-page data, wherein the status group code includes a plurality of status group data, wherein the number of bits in each status group data is less than the number of bits in the corresponding single multi-bit data in the plurality of multi-bit data in the multi-page data, and wherein each status group data is generated based on the number of "1" bits in the corresponding single multi-bit data in the plurality of multi-bit data; The state group code is backed up to the non-volatile storage device; After power is restored following a sudden power outage that occurred after the state group code was backed up, the multi-page data is recovered by reading the pre-programmed plurality of storage units based on the state group code; The multi-page data recovered from the pre-programmed plurality of storage units is reprogrammed back into the plurality of storage units; and If no sudden power failure occurs after the state group code is backed up, the multi-page data in the storage controller is reprogrammed into the pre-programmed plurality of storage cells.

13. The operating method according to claim 12, in, The multiple pre-programmed states are grouped into N state groups. Each of the N state groups has M non-overlapping pre-programmed states from the plurality of pre-programmed states, where M is equal to the number of the plurality of pre-programmed states divided by N, and M and N are integers. Each of the multiple state group data represents one of the N state groups.

14. The operating method according to claim 13, in, The reading of the multi-page data from the plurality of storage units includes: Change the read operation of the non-volatile storage device from normal read mode to recovery read mode; and In the recovery read mode, a first read voltage is applied to the word line connected to the pre-programmed plurality of memory cells, the first read voltage being determined based on each of the plurality of state group data.

15. The operating method according to claim 14, in, The read voltage level of the first read voltage applied to the word line to read the multi-page data in the recovery read mode is different from the read voltage level of the second read voltage applied to the word line to read the multi-page data in the normal read mode.

16. The operating method according to claim 14, in, The first read voltage has a first read voltage level corresponding to a first state group data among the plurality of state group data, and a second read voltage level different from the first read voltage level corresponding to a second state group data among the plurality of state group data.

17. The operating method according to claim 14, in, In the recovery read mode, the number of read voltage levels applied to the word line according to the read command is greater than the number of read voltage levels applied to the word line according to the read command in the normal read mode.

18. A method of operating a storage system including a storage controller and a non-volatile storage device, the non-volatile storage device including a storage cell region and a peripheral circuit region, the storage cell region including a first metal pad, the peripheral circuit region including a second metal pad and connected to the storage cell region in a vertical direction via the first metal pad and the second metal pad, the method of operating comprising: Multipage data in the storage controller is preprogrammed into a plurality of memory cells in the non-volatile storage device connected to a first word line, wherein the multipage data includes a plurality of multi-bit data, wherein each of the plurality of memory cells is preprogrammed to have a threshold voltage according to a corresponding multi-bit data in the plurality of multi-bit data, and wherein the threshold voltage corresponds to one of a plurality of preprogrammed states; A status group code is generated based on the plurality of multi-bit data in the multi-page data, wherein the status group code includes a plurality of status group data, wherein the number of bits in each status group data is less than the number of bits in the corresponding single multi-bit data in the plurality of multi-bit data in the multi-page data, and wherein each status group data is generated based on the number of "1" bits in the corresponding single multi-bit data in the plurality of multi-bit data; When a sudden power failure occurs after the storage unit has been pre-programmed, the state group code is backed up to the non-volatile storage device; After power is restored from the sudden power outage, the multi-page data is recovered by reading the pre-programmed plurality of storage units based on the state group code; The multi-page data recovered from the pre-programmed plurality of storage units is reprogrammed back into the pre-programmed plurality of storage units; and If no sudden power failure occurs after the storage cells have been pre-programmed, the multi-page data in the storage controller is reprogrammed into the pre-programmed multiple storage cells.

19. The operating method according to claim 18, in, The first metal pad and the second metal pad are formed of copper.

20. The operating method according to claim 18, in, The first metal pad and the second metal pad are connected to each other in an engagement manner.

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