Scalable nand interface based micro-instruction processor and method thereof

Abstract

The application discloses a micro-instruction processor based on an extensible NAND interface and a method thereof; the processor adopts: a longitudinal link which, by configuring an adaptive module, an instruction storage module, an extensible instruction set module and an interface decoding and executing module, completes configuration, instruction and execution, realizes complete programmability of control logic, the adaptive module actively reads configuration information in an initialization stage, and generates a complete running context in combination with metadata provided by external firmware; a transverse link which adopts a host interface, a data memory module, a data preprocessing module, a physical layer interface and a storage medium, and constructs a high-throughput and low-delay data link. The link focuses on efficient flow of I / O data, and ensures that a host request can quickly and reliably reach a NAND flash medium. The technical scheme of the application can be compatible with NAND flash of different brands and different models, and effectively reduces the adaptation cost of a storage controller.

Description

Technical Field

[0001] This invention relates to the field of memory control chip technology, and in particular to a microinstruction processor and method based on a scalable NAND interface control. Background Technology

[0002] NAND flash memory is widely used in consumer electronics, industrial storage, and other fields due to its high capacity and low cost. However, NAND flash memory from different manufacturers (such as Samsung, Micron, and Kioxia) not only follows the JEDEC general standard, but also has a large number of manufacturer-defined commands (such as Yangtze Memory's special erase commands and cache operation commands); in addition, the timing parameters (such as read / write latency and signal setup time) of different models of NAND flash memory from the same manufacturer (such as TLC / QLC, different processes) also differ.

[0003] Traditional NAND interface controllers have fixed hardware logic instruction sets, supporting only preset general instructions and timings. Adapting to new manufacturers or models of NAND flash memory requires redesigning the hardware circuitry, resulting in long development cycles and poor compatibility. While some existing configurable NAND controllers support timing parameter adjustments, they cannot expand to include new instructions, making it difficult to cover vendor-specific command scenarios.

[0004] Therefore, an interface control microinstruction processor that can dynamically expand the instruction set and adapt to diverse NAND flash memory is needed to solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies where configurable NAND controller instruction sets are fixed, cannot be expanded with new instructions, and still cannot cover vendor-specific command scenarios. The invention proposes a scalable NAND interface control microinstruction processor and its method, which integrates a configurable NAND control microinstruction processor into the chip, thereby enabling the expansion of new NAND commands and timing parameters. It is suitable for storage controllers (such as SSD controllers and embedded storage controllers) that need to be compatible with NAND flash memory from multiple vendors and specifications.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A microinstruction processor based on a scalable NAND interface control includes:

[0008] The configuration adaptation module is used to receive external configuration data and perform extended instruction registration, timing parameter configuration, and vendor command mapping for the extensible instruction set module.

[0009] The instruction storage module is used to store microinstruction sequences related to the control of NAND flash memory and to receive instruction data from the scalable instruction set module.

[0010] The extensible instruction set module has a built-in general NAND basic instruction set and instruction templates. It can receive external extended instruction definitions through the configuration adapter module and dynamically update the instruction library.

[0011] The interface decoding and execution module connects the instruction storage module and the expandable instruction set module, and is used to parse instructions and generate control signals for the NAND interface.

[0012] Furthermore, it also includes a data memory module and a data preprocessing module. The data memory module temporarily stores data to be written or read and is coupled to the data preprocessing module. The data preprocessing module receives and processes the raw data from the data memory module, sends the processed raw data to the interface decoding execution module, and receives data returned from the NAND interface.

[0013] Furthermore, it also includes a storage medium, which is connected via a NAND interface, outputs raw data and status information, and receives write requests or erase commands.

[0014] Furthermore, the NAND interface includes a host interface and a physical layer interface. The host interface is a port for connecting to the chip bus and receiving data from the host. The physical layer interface is an electrical interface for directly connecting to the storage medium and connecting to the interface decoding execution module. It receives control signals from the interface decoding execution module and feeds back the status bits returned by the NAND interface to the interface decoding execution module.

[0015] Furthermore, the configuration adaptation module identifies the manufacturer type based on the ID information read from the NAND flash memory, and selects the corresponding instruction template from the instruction library of the extensible instruction set module based on a preset mapping table.

[0016] Furthermore, the scalable instruction set module is in the form of a programmable memory, and loads manufacturer-defined instructions through firmware updates.

[0017] Furthermore, the physical layer interface integrates a configurable timing engine, which receives timing parameters from the interface decoding execution module.

[0018] Furthermore, when performing encoding or decoding, the data preprocessing module sends a synchronization trigger signal to the interface decoding execution module, so that the interface decoding execution module starts verification while sending write commands or receiving read data.

[0019] An application method for controlling a microinstruction processor based on a scalable NAND interface includes the following:

[0020] Power-on initialization includes NAND flash memory access and operation, hardware resource initialization, clock synchronization, register clearing, internal memory initialization, physical layer interface reset, host interface communication link establishment, reading default parameters preset in the chip or external firmware, and starting NAND flash memory ID information recognition.

[0021] Extended configuration: dynamically load the corresponding configuration parameters based on the raw data of the detected NAND flash memory ID and manufacturer information;

[0022] Instruction decoding takes configuration parameters from the extensible instruction set module loaded by the extended configuration as input and outputs a sequence of signals.

[0023] Instruction execution involves the interface decoding and execution module sending a signal sequence to control the physical layer interface to output the correct level sequence, sending addresses, commands, and data to the NAND flash memory, and triggering write, read, or erase operations.

[0024] Wait for NAND status information and check the RDY / BUSY pin status;

[0025] Determine if the NAND is ready. If the NAND is not ready, return to wait for NAND status information and continue polling. If it is ready, proceed to the next step.

[0026] Determine whether to replace the NAND flash memory. If not, end the current operation. If yes, trigger the dynamic adaptation process, return to the extended configuration, re-execute the configuration operation, and load the new NAND flash memory.

[0027] In comparison, the advantages of this invention are as follows: This invention transforms NAND interface control from a hardware-fixed approach to a hardware-software co-operation model with scalable instructions and configurable timing. It is compatible with NAND flash memory of different brands, models, and specifications, effectively reducing the adaptation cost of the storage controller. It can dynamically adapt to custom instructions and timing parameters from multiple manufacturers without hardware modifications. Instructions and timing parameters can be updated simply through configuration adaptation, quickly adapting to new process NAND flash memory, significantly reducing adaptation costs, improving product versatility, extending lifespan, and meeting the needs of different application scenarios. It is suitable for various manufacturers' proprietary command scenarios. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the composition of the microinstruction processor based on the scalable NAND interface control in Embodiment 1 of the present invention;

[0029] Figure 2 This is a schematic diagram of the workflow of the microinstruction processor controlled by the scalable NAND interface in Embodiment 1 of the present invention;

[0030] Figure 3This is a schematic diagram of the composition of the storage medium using Micron MT29F NAND flash memory or Yangtze Memory X3-9070 NAND flash memory in Embodiment 2 of the present invention;

[0031] Figure 4 This is a schematic diagram of the workflow in Embodiment 2 of the present invention, which uses Yangtze Memory X3-9070 NAND flash memory as the storage medium. Detailed Implementation

[0032] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0033] With the development of NAND manufacturers and the diversification of specifications, the instruction set of traditional NAND interface controllers is fixed, which makes it impossible for custom-implemented chips to be compatible with and adapt to the new specifications of NAND flash memory media from multiple manufacturers. If the chips need to support the new specifications of NAND flash memory media from different manufacturers, they need to be redesigned. Considering the customization, the configurable or modifiable parameters of NAND timing parameters are limited, such as the size of tPROG. The timing of tPROG in the hardware is fixed through the instruction set, and the maximum supported range of tPROG cannot be changed.

[0034] Example 1

[0035] This implementation proposes a scalable NAND interface control microinstruction processor, including an instruction storage module, a scalable instruction set module, an interface decoding and execution module, a configuration adaptation module, and a physical layer interface. It decouples the originally fixed hardware instruction logic into a three-layer architecture of programmable microinstructions, configurable timing, and flexible interface execution, thereby achieving compatibility support for NAND flash memory (including proprietary commands) from different manufacturers and models.

[0036] Figure 1 This demonstrates the basic architecture of a microinstruction processor based on a scalable NAND interface. Vertically, the control path consists of a configuration adapter module, a scalable instruction set module, and an instruction storage module. Horizontally, the data transmission path comprises a host interface, a data memory module, a data preprocessing module, an interface decoding and execution module, a physical layer interface, and storage media. The vertical and horizontal paths are connected via the interface decoding and execution module, forming a complete read / write control and data transmission structure.

[0037] The functions of each module are described below:

[0038] The host interface is a port on the high-speed bus that connects to the chip. It receives data from the host, as well as I / O requests including read, write, and erase operations, retrieves response data from the data memory module, and sends it back to the host.

[0039] The data memory module is coupled to the host interface, temporarily stores data to be written or read, caches data received from the host, alleviates the speed difference between the controller and NAND, supplies data to the data preprocessing module, and receives processed data returned by the data preprocessing module for writing back to the host. DDR memory is typically used.

[0040] The data preprocessing module, coupled to the data memory module, receives raw data from the data memory module and sends the processed raw data to the interface decoding execution module. It also receives data returned from the NAND interface (physical layer interface) for reading. It should be noted that data from the host needs to be encoded using ldpc or bch algorithms, and data from the storage medium needs to be decoded using ldpc or bch algorithms. During encoding or decoding, a synchronization trigger signal is sent to the interface decoding execution module, causing the interface decoding execution module to initiate the corresponding ECC check while sending write commands or receiving read data, thus achieving tight coupling and coordination between instruction and data processing.

[0041] The configuration adaptation module is used to receive external configuration data and realize the registration of extended instructions, timing parameter configuration and vendor command mapping for the extensible instruction set module. It identifies the vendor type based on the ID information read from the NAND flash memory and selects the corresponding instruction template from the instruction library of the extensible instruction set module based on the preset mapping table.

[0042] The instruction storage module stores microinstruction sequences and preset mapping tables related to NAND flash memory control. It supports page-by-page writing and random reading of microinstructions and online updating of preset mapping tables. It receives instruction data from the extensible instruction set module and provides the microinstruction stream to be executed to the interface decoding and execution module. In multi-task scenarios, it supports context switching, such as managing different instruction queues of multiple NAND chips simultaneously.

[0043] The extensible instruction set module, as a loadable and updatable instruction library, adopts the form of programmable memory and loads manufacturer-defined instructions through firmware updates. It has a built-in general NAND basic instruction set and instruction templates, including read, write, erase, and status query instructions. It also receives external extended instruction definitions through a configuration adaptation module and dynamically updates the instruction library. The instruction library includes JEDEC standard instructions, manufacturer-specific instructions, cache management instructions, etc.

[0044] The interface decoding and execution module connects the instruction storage module and the expandable instruction set module. It is used to parse instructions and generate control signals for the NAND interface, drive the physical layer interface, and the control signals for the NAND interface include chip select signal, read / write enable signal, address or command latch signal, and timing parameters. It also sends the control signals of the NAND interface to the physical layer interface and processes status feedback.

[0045] The physical layer interface is an electrical interface connecting the interface decoding execution module and the storage medium (NAND flash memory). It is used to convert the control signals of the NAND interface into physical layer signals (such as LVCMOS level signals) that conform to the electrical characteristics of NAND flash memory, realize high-low level conversion, generate precise clock synchronization signals, receive control signals from the interface decoding execution module, and feed back the status bits returned by NAND to the interface decoding execution module. It supports NAND flash memory adaptation with different voltage specifications and integrates a configurable timing engine. The configurable timing engine receives timing parameters from the interface decoding execution module and dynamically generates clock and control waveforms that conform to any mode of the ONFI 4.0, Toggle Mode 3.0, or Xtend protocol.

[0046] The storage medium, the NAND medium where the final data is stored, is the actual NAND flash memory. It is connected through the NAND interface (physical layer interface), outputs raw data and status information, and receives write requests or erase commands, etc.

[0047] The NAND interface control processor based on scalable microinstructions proposed in this embodiment constructs a highly collaborative, dynamically adaptable, and self-sensing intelligent control structure through a vertical control chain, a horizontal data chain, and a multi-dimensional cross-coupling mechanism.

[0048] For the vertical link, the control logic achieves full programmability through configuration, instructions, and execution. During system initialization or hot-plug detection, the configuration adaptation module actively reads the ID information or parameter table configuration information of the NAND flash memory and combines it with metadata provided by the external firmware to generate a complete runtime context. This context is passed to the extensible instruction set module, which dynamically selects and loads applicable instruction subsets from a large instruction library. The loaded instruction subsets are temporarily stored in the instruction storage module in the form of structured microinstruction sequences, and then parsed line by line by the interface decoding and execution module. Each microinstruction not only defines the command bytes and address period to be sent, but also embeds precise timing constraints.

[0049] Traditional controllers embed this logic in a state machine, while the architecture proposed in this invention software-izes it into loadable, composable, and version-manageable microinstructions, achieving full programmability of the control logic and enabling a single hardware platform to seamlessly adapt to heterogeneous NAND products such as Samsung V-NAND, Kioxia BiCS, and Yangtze Memory Xtacking.

[0050] For the horizontal link, a high-throughput, low-latency data link is constructed using a host interface, data memory, data preprocessing, physical layer interface, and storage media. This link focuses on the efficient flow of I / O data, ensuring that host requests can reach the NAND flash memory medium quickly and reliably.

[0051] The host initiates read / write requests through the host interface. Data first enters the data memory module, which can use on-chip SRAM or LPDDR cache to buffer the speed difference between the host and NAND flash memory. In the write path, data flows from the data memory module to the data preprocessing module. The preprocessed data is temporarily stored in the data preprocessing module and waits for the interface decoding execution module to send a data latch signal. Then, it is written to the NAND flash memory through the physical layer interface with a waveform conforming to the relevant electrical specifications of ONFI / Toggle (open NAND flash memory interface and switching mode). In the read path, the raw data returned from the NAND flash memory is sampled by the physical layer interface and sent to the data preprocessing module for ECC decoding verification and error correction. The corrected valid data is then filled back into the data memory module and finally returned to the host through the host interface.

[0052] This horizontal link adopts a pipelined and parallel processing design, and data preprocessing and command execution can be performed concurrently. For example, the ECC engine can be prepared while receiving the address, which can significantly improve throughput efficiency. At the same time, the data memory module serves as an intermediate hub, supporting multi-channel concurrent access.

[0053] Based on the above operational logic, the working method of the NAND interface control processor based on extensible microinstructions proposed in this embodiment will be further explained. Its workflow is as follows: Figure 2 .

[0054] Power-on initialization: Upon power-on or reset, the processor enters its initial state, preparing for NAND flash memory access and operation. This includes hardware resource initialization, clock synchronization to eliminate clock phase deviation, and register clearing (including the instruction address register and data buffer register). Internal memory initialization: This involves initializing the NAND instruction storage module, initializing the instruction read pointer, and setting storage medium read / write timing parameters (such as read latency and write cycle) to ensure subsequent microinstruction sequences can be loaded and read correctly. Simultaneously, it initializes the basic instruction units of the extensible instruction set module, loading pre-set general NAND instructions from the JEDEC standard (such as read ID, reset, page read, page write, and block erase instructions). Physical layer interface reset: The host interface communication link is established, pre-set default parameters in the chip or external firmware are read, and NAND flash memory ID information identification is initiated, reading information such as the NAND flash memory manufacturer ID, device ID, and storage specification (TLC / QLC) to prepare for subsequent expansion configurations.

[0055] The extended configuration module, based on the detected NAND flash memory ID information and vendor information, matches the corresponding extended configuration parameter package from the parameter template library stored in the external firmware. This parameter package includes vendor-defined instruction sets, private timing parameters, physical layer interface configuration parameters, and instruction mapping table update data. It dynamically loads the corresponding configuration parameters, including vendor-specific command sets, timing parameters, data transmission modes, and ECC algorithm types. The matched configuration parameters are then dynamically loaded into the extensible instruction set module, interface decoding execution module, and physical layer interface, completing parameter updates for each module. For the extensible instruction set module, extended instruction units are written, and the opcode mapping relationship between the instruction and interface signals is updated. For the interface decoding execution module, timing constraint parameters generated by timing (such as tCAS, tWP, tWPRE, etc.) are updated. For the physical layer interface, the voltage specifications for level conversion, the termination resistance value for impedance matching, and the data buffer transmission mode (synchronous or asynchronous) are adjusted.

[0056] Instruction decoding takes configuration parameters from the extensible instruction set module loaded by the extended configuration as input, decomposes high-level instructions into a series of low-level control signal sequences, and outputs the signal sequences. Instruction decoding also involves reading the micro-instruction sequence to be executed (such as page write, block erase, data read, etc.) from the instruction storage module, extracting the opcode (32 bits, used to identify the instruction type), operands (such as address offset, data length, command cycle count, etc.), and function identifier from each micro-instruction. Based on the extracted opcode of the micro-instruction, the instruction library in the extensible instruction set module is queried to match the corresponding instruction function description, command sequence (such as single-cycle commands, multi-cycle command combinations), address field length (0 / 3 / 4 bytes), and timing constraints to complete the instruction decoding. If it is a basic general instruction (such as the reset instruction 0xFF), the parsing logic of the basic instruction unit is directly called; if it is a vendor-defined extended instruction, the private association logic of the extended instruction unit is called to ensure parsing accuracy. Based on the instruction decoding results and the timing parameters configured in the extensible instruction set module, the timing generation unit of the interface decoding execution module decomposes the signal sequence into a series of low-level control signals, including chip select signal (CE#), write enable signal (WE#), read enable signal (RE#), address / command latch signal, etc., clarifying the timing relationship of each signal (such as signal trigger time, duration, phase difference), and ensuring that the signal sequence conforms to the electrical characteristics and timing requirements of the current NAND flash memory.

[0057] Instruction execution involves the interface decoding and execution module issuing a sequence of signals to control the NAND interface. This drives the physical layer interface to output the correct level sequence, strictly adhering to the currently configured timing parameters. Addresses, commands, and data are sent to the NAND flash memory, triggering write, read, or erase operations. Specifically:

[0058] For the signal sequence sent by the physical layer interface receiving interface decoding execution module, the signal is converted into a physical layer signal conforming to the current NAND flash voltage specification (3.3V / 1.8V, the interface level corresponding to the Vcc core power supply) through level conversion. Impedance matching is used to optimize signal integrity and avoid signal reflection during high-speed transmission. Subsequently, the converted control signals, address, command sequence (such as page read command 0x00+0x30), and data are sent to the NAND flash through the physical layer interface pins, triggering the NAND flash to enter the corresponding operation mode. If it is a write operation or a read or erase operation with an address, the processor sends the corresponding address information (such as page address, block address) to the NAND flash in the format required by the NAND flash through the data bus of the physical layer interface. After the address is sent, the data to be written (write operation) or the data to be read from the NAND flash is sent (read operation). In high-speed transmission scenarios, the data strobe signal (DQS) is enabled to achieve synchronous sampling of data and control signals, improving transmission efficiency and accuracy. After receiving control signals, command sequences, and addresses (if any), the NAND flash memory executes the corresponding operations: During a write operation, the received data is written to the specified storage medium, and data verification is performed; during a read operation, data is read from the specified storage medium and fed back to the processor via the data bus; during an erase operation, an erase operation is performed on the specified storage medium, clearing all data within the storage medium. Throughout the entire operation, the processor monitors the operation progress in real time through the interface decoding execution module.

[0059] After the instruction execution phase begins, the interface decoding and execution module automatically triggers the NAND status query process, stops sending new control signals, and enters the status polling mode. It waits for NAND status information, queries the RDY / BUSY pin status, and ensures that the NAND flash memory has completed the current operation before proceeding to the next step. This step is crucial for ensuring reliability. To avoid frequent polling consuming excessive processor resources, a reasonable polling interval is set (which can be adjusted through extended configuration parameters, such as 50ns / time), until a ready signal is detected or a timeout exception is triggered.

[0060] To determine whether the NAND is ready, the interface decoding and execution module judges the NAND status information collected above and executes different process branches according to the judgment result; if the NAND is not ready, it returns to wait for the NAND status information to continue polling; if it is ready, it proceeds to the next judgment.

[0061] Determine whether to replace the NAND flash memory. If the host requests to replace the NAND flash memory, or if a NAND flash memory failure or performance degradation is detected, switch the target chip in a multi-chip management scenario. If not, end the operation directly. If yes, trigger the dynamic adaptation process, return to the extended configuration step, re-execute the configuration operation, and load the new NAND flash memory.

[0062] Traditional NAND interface controller processor instruction sets are hardware-fixed designs, only compatible with NAND flash memory from preset manufacturers and models. Changing manufacturers or models, or adapting to new manufacturing processes, requires redesigning the hardware and modifying the tape-out, resulting in high R&D costs, long cycles, and short product lifecycles. This processor application method, through the coordinated operation of the above steps, achieves efficient adaptation and stable operation between the NAND interface controller microinstruction processor and NAND flash memory, balancing compatibility, scalability, and reliability. It can be widely used in various scenarios such as SSD controllers, embedded storage controllers, and industrial storage, adapting to NAND flash memory from multiple manufacturers, with different specifications and new manufacturing processes.

[0063] Example 2

[0064] This embodiment uses an SSD hard drive with PCIe Gen4 as the high-speed data transmission interface and Micron MT29F NAND flash memory or Yangtze Memory X3-9070 NAND flash memory as the storage medium to briefly explain the working mode of the microinstruction processor controlled by the scalable NAND interface.

[0065] Using Micron MT29F flash memory or Yangtze Memory X3-9070 NAND flash memory as the storage medium, its overall structure is as follows: Figure 3 As shown, taking PCIe Gen4 SSD as an application scenario, the following key components are used:

[0066] The host interface is a PCIe Gen4×4 interface, providing up to 8GB / s of bidirectional bandwidth. The PCIe Gen4×4 interface is coupled to the data memory DDR used for caching host read and write data. ECC encoding, compression, and bad block management are implemented through the data preprocessing module.

[0067] The storage medium uses Micron MT29F NAND flash memory or Yangtze Memory X3-9070 NAND flash memory, which is connected to Micron MT29F NAND flash memory or Yangtze Memory X3-9070 NAND flash memory via NAND interface.

[0068] The interface decoding and execution module parses instructions and drives the physical layer, establishing connections with the data preprocessing module and the instruction storage module (total capacity 2048×32). The instruction storage module stores micro-instruction sequences and connects to the expandable instruction set module. The expandable instruction set module has built-in general and private instruction libraries and connects to the configuration adaptation module. The configuration adaptation module loads corresponding parameters according to the NAND flash memory type. The expandable instruction set module adopts the form of programmable memory and loads manufacturer-defined instructions through firmware updates. Manufacturer-defined instructions include, but are not limited to, at least one of Yangtze Memory's special erase instructions, Micron's cache management instructions, or Kioxia's multi-plane operation instructions.

[0069] As a mainstream domestically produced NAND flash memory, Yangtze Memory's X3-9070 NAND flash memory has proprietary instructions that cannot be recognized by traditional controllers. This embodiment uses Yangtze Memory's X3-9070 NAND flash memory as an example to introduce the configuration adaptation and instruction execution process, referring to... Figure 4 As shown, the explanation is as follows:

[0070] The data that needs to be written to NAND flash memory mainly comes from the host (such as PC, server) which initiates write requests through the file system or RAID layer. User data (such as text, video, database records, etc.) written to NAND flash memory is raw, unprocessed data that needs to be processed before it can be written to NAND flash memory.

[0071] Writing data to DDR memory via the PCIe Gen4×4 interface decouples host speed from the slow characteristics of NAND, providing sufficient buffer space to handle multi-task concurrency.

[0072] The data is encoded using ldpc or bch algorithms, with added redundant bits and check codes to resist bit flipping errors caused by wear in NAND flash memory, thus improving reliability, especially for QLC / TLC NAND.

[0073] The microinstruction processor is initialized. The initialization is triggered when the system powers on or receives the first write request. All control registers are initialized, default configuration parameters are loaded, the instruction storage module (2048×32) is started, preparations are made to enter the extensible instruction mode, the clock frequency is set, the interrupt flag is cleared, and the DMA channel is enabled.

[0074] The configuration adapter module reads the vendor ID, extends the page program instruction (opcode 0x81, standard JEDEC instruction 0x80), and the Yangtze Memory X3-9070 NAND flash memory supports the enhanced page programming instruction 0x81, which allows for longer write time windows, higher reliability, or lower power consumption. It identifies the current NAND flash memory as Yangtze Memory X3-9070 NAND flash memory, loads the corresponding configuration table from the firmware library, replaces the standard JEDEC instruction 0x80 with the private instruction 0x81, registers this new instruction in the instruction library of the extensible instruction set module, and updates the instruction library storage content.

[0075] Instruction decoding yields the instruction sequence 0x80+0x10, with an address of 6 bytes and tADL=120ns.

[0076] After instruction execution and the mapping between logical and physical addresses, the microinstruction processor sends the microinstruction sequence, address bytes, and host data to the NAND flash memory. The host requests the logical block address, which is converted to a physical page address via FTL. The interface decoding and execution module constructs a complete write packet: the microinstruction sequence is [0x80, 0x10], the address is 6 bytes (e.g., 0xAB, 0xCD, 0xEF, 0x00, 0x00, 0x00), the data is 512 bytes and an ECC checksum, and the control is via the CE#, WE#, ALE, and CLE pins. When sending the write packet, the command must be sent first, then the address, and finally the data.

[0077] Send a command to check the NAND status, query whether the NAND has been programmed, and obtain status register information. This is automatically triggered by the interface decoding execution module without host intervention.

[0078] Check the RDY / BUSY pin status to determine if it is high, i.e., check if the NAND pin is set to a high level. If the RDY / BUSY pin is still low, return to the previous step and continue polling; if it becomes high, it means that the NAND has been programmed and proceed to the next step.

[0079] The criteria for determining whether to replace the Yangtze Memory X3-9070 NAND flash memory are: whether the host actively replaces the SSD, whether a NAND fault is detected, or whether it is switched to another Yangtze Memory X3-9070 NAND flash memory.

[0080] If not, the data will be written to the Yangtze Memory X3-9070 NAND flash memory, ending the current process; if yes, dynamic adaptation will be triggered, and the new device will be reconfigured.

[0081] This embodiment uses an enterprise-level storage controller SSD main controller scenario as an example to illustrate that this solution can be compatible with NAND flash memory from manufacturers such as Micron MT29F8T08EULCHD5T (TLC, 3.3V), Yangtze Memory YMNOAQF1B5MF6D (QLC, 2.5V), and Kioxia TH58LKT0DA5BA8C (SLC, 3.3V). It only requires loading the proprietary instructions of each manufacturer (such as Micron Address Cycle Read Retry (ACRR) and Yangtze Memory AMPI mode cmd sequence) and timing parameters by configuring the adaptation module. Actual operation verification shows that full adaptation can be completed in only 1-2 days. There is no need to design multiple sets of hardware, and the adaptation cost is estimated to be reduced by 80%. Moreover, it has long-term operational stability, can continuously support new devices through OTA upgrades, supports hot-swappable maintenance, and automatically identifies different batches of NAND flash memory without manual intervention.

[0082] When adapting to the next-generation process, YMNOBQF1E5MFBE Yangtze Memory Technologies Co., Ltd. (YMTC) storage with Single Level Read functionality, only the addition of Single Level Read instructions and adjustment of timing parameters are required. Actual verification can be completed in just one day, without any tape-out modifications. Existing SSD products can support the new generation of NAND via firmware upgrades, extending their lifespan by an estimated 2-3 years. Adapting traditional processors to multiple manufacturers requires multiple hardware designs, incurring greater time and cost for adapting to the new process.

[0083] It should be noted that any parts not covered in this invention are the same as or can be implemented using existing technology. The above description is merely a preferred embodiment of this invention, but the scope of protection of this invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in this invention, based on the technical solution and inventive concept of this invention, should be covered within the scope of protection of this invention.

Claims

1. A microinstruction processor based on a scalable NAND interface, characterized in that: include: The configuration adaptation module is used to receive external configuration data and perform extended instruction registration, timing parameter configuration and vendor command mapping for the extensible instruction set module. It identifies the vendor type based on the ID information read from the NAND flash memory and selects the corresponding instruction template from the instruction library of the extensible instruction set module based on the preset mapping table. The instruction storage module is used to store the micro-instruction sequence related to NAND flash memory control, receive instruction data from the expandable instruction set module, and provide the micro-instruction sequence to be executed to the interface decoding and execution module. The extensible instruction set module has a built-in general NAND basic instruction set and instruction template. It receives external extended instruction definitions through the configuration adaptation module and dynamically updates the instruction library. The instruction library includes JEDEC standard instructions, vendor-specific instructions, and cache management instructions. It adopts the form of programmable memory and loads vendor-customized instructions through firmware updates. The interface decoding and execution module connects the instruction storage module and the extensible instruction set module. It is used to parse instructions and generate control signals for the NAND interface, decompose high-level instructions into signal sequences and output the signal sequences, read the micro-instruction sequence to be executed from the instruction storage module, extract the opcode, operands and function identifiers from each micro-instruction, query the instruction library in the extensible instruction set module based on the extracted opcode of the micro-instruction, match the corresponding instruction function description, command sequence, address field length and timing constraints, and complete the instruction decoding. The scalable NAND interface controls the instruction execution process of the microprocessor as follows: The interface decoding and execution module sends a signal sequence to control the physical layer interface to output the correct level sequence, send addresses, commands and data to the NAND flash memory, and trigger write, read or erase operations; Wait for NAND status information and check the RDY / BUSY pin status; Determine if the NAND is ready. If the NAND is not ready, return to wait for NAND status information and continue polling. If it is ready, proceed to the next step. Determine whether to replace the NAND flash memory. If not, end the current operation. If yes, trigger the dynamic adaptation process, return to the extended configuration, re-execute the configuration operation, and load the new NAND flash memory.

2. The microinstruction processor based on a scalable NAND interface according to claim 1, characterized in that, It also includes a data memory module and a data preprocessing module. The data memory module temporarily stores data to be written or read and is coupled to the data preprocessing module. The data preprocessing module receives and processes the raw data from the data memory module, sends the processed raw data to the interface decoding execution module, and receives data returned from the NAND interface.

3. The microinstruction processor based on a scalable NAND interface according to claim 1, characterized in that, It also includes a storage medium, which is connected through the NAND interface, outputs raw data and status information, and receives write requests or erase commands.

4. The scalable NAND interface-based control microinstruction processor according to any one of claims 1-3, characterized in that, The NAND interface includes a host interface and a physical layer interface. The host interface is a port for connecting to the chip bus and receiving data from the host. The physical layer interface is an electrical interface for directly connecting to the storage medium and is connected to the interface decoding execution module. It receives control signals from the interface decoding execution module and feeds back the status bits returned by the NAND interface to the interface decoding execution module.

5. The scalable NAND interface-based microinstruction processor according to claim 4, characterized in that, The physical layer interface integrates a configurable timing engine, which receives timing parameters from the interface decoding execution module.

6. The microinstruction processor based on a scalable NAND interface according to claim 2, characterized in that, When performing encoding or decoding, the data preprocessing module sends a synchronization trigger signal to the interface decoding execution module, so that the interface decoding execution module starts verification at the same time as sending write commands or receiving read data.

7. The application method for controlling a microinstruction processor based on a scalable NAND interface according to any one of claims 1-6, characterized in that, include: Power-on initialization involves NAND flash memory access and operation, hardware resource initialization, clock synchronization, register clearing, internal memory initialization, physical layer interface reset, host interface communication link establishment, reading default parameters preset in the chip or external firmware, and initiating NAND flash memory ID information identification. Extended configuration: dynamically load the corresponding configuration parameters based on the raw data of the detected NAND flash memory ID and manufacturer information; Instruction decoding takes configuration parameters from the extensible instruction set module loaded by the extended configuration as input and outputs a sequence of signals. Instruction execution involves the interface decoding and execution module sending a signal sequence to control the physical layer interface to output the correct level sequence, sending addresses, commands, and data to the NAND flash memory, and triggering write, read, or erase operations. Wait for NAND status information and check the RDY / BUSY pin status; Determine if the NAND is ready. If the NAND is not ready, return to wait for NAND status information and continue polling. If it is ready, proceed to the next step. Determine whether to replace the NAND flash memory. If not, end the current operation. If yes, trigger the dynamic adaptation process, return to the extended configuration, re-execute the configuration operation, and load the new NAND flash memory.

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