Wideband power transistor devices and amplifiers with output T-type matching and harmonic termination circuits, and methods for their manufacture.

Abstract

Embodiments of the RF amplifier and the packaged RF amplifier device each include an amplification path with a transistor die and an output-side impedance matching circuit with a T-type matching circuit topology. The output-side impedance matching circuit includes a first inductor (e.g., a first bond wire) connected between the transistor output and a quasi-RF cold spot node, a second inductor (e.g., a second bond wire) connected between the quasi-RF cold spot node and the output of the amplification path, and a first capacitor connected between the quasi-RF cold spot node and a ground reference node. The RF amplifier and device also include a baseband termination circuit connected to the quasi-RF cold spot node, the baseband termination circuit including an envelope resistor, an envelope inductor, and an envelope capacitor series coupled between the quasi-RF cold spot node and the ground reference node.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to radio frequency (RF) amplifiers, and more specifically, to broadband power transistor devices and amplifiers, as well as methods of manufacturing such devices and amplifiers. Background Technology

[0002] Wireless communication systems employ power amplifiers to amplify the power of radio frequency (RF) signals. For example, in a cellular base station, a Doherty power amplifier can form part of the final amplification stage in the transmission chain before the amplified signal is supplied to the antenna for radiation over the air interface. In such wireless communication systems, the desired characteristics of the power amplifier are high gain, high linearity, stability, and a high level of power addition efficiency.

[0003] In the field of power amplifier device design, there is a growing desire for concurrent multi-band, broadband amplification. For example, to successfully design a broadband power amplifier device for concurrent multi-band, broadband operation in a Dougherty power amplifier circuit, it is desirable to achieve good broadband base-matching (e.g., a fractional bandwidth exceeding 20%) to properly handle harmonic frequency interactions and to achieve a wide baseband termination. However, power amplifier device designers continue to face challenges in achieving these goals. Summary of the Invention

[0004] According to one aspect of the present invention, a radio frequency (RF) amplifier having a first amplification path is provided, comprising:

[0005] A transistor die, the transistor die having a transistor and a transistor output terminal;

[0006] An output-side impedance matching circuit, wherein the output-side impedance matching circuit has a T-type matching circuit topology coupled between the transistor output terminal and the output of the first amplification path, wherein the output-side impedance matching circuit includes:

[0007] A first inductor element is connected between the transistor output terminal and the quasi-RF cold spot node.

[0008] A second inductor element is connected between the quasi-RF cold spot node and the output of the first amplification path.

[0009] A first capacitor, the first capacitor being connected between the quasi-RF cold spot node and the ground reference node; and

[0010] A baseband termination circuit connected to the quasi-RF cold spot node, wherein the baseband termination circuit includes multiple components, wherein the multiple components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi-RF cold spot node and the ground reference node.

[0011] According to one or more embodiments, the first inductor element includes a first plurality of bonding wires; and the second inductor element includes a second plurality of bonding wires.

[0012] According to one or more embodiments, the RF amplifier further includes an output-side harmonic termination circuit, the output-side harmonic termination circuit including a third inductor and a second capacitor connected in series between the transistor output and the ground reference node, and the output-side harmonic termination circuit resonates at the second harmonic frequency of the fundamental operating frequency of the RF amplifier.

[0013] According to one or more embodiments, the transistor is a gallium nitride transistor with a drain-source capacitance of less than 0.2 picofarads per watt.

[0014] According to one or more embodiments, the RF amplifier is a Dougherty power amplifier, the RF amplifier further comprising: a second amplification path; a power divider having a power divider input configured to receive an RF signal, a first power divider output coupled to an input of the first amplification path, and a second power divider output coupled to an input of the second amplification path, wherein the power divider is configured to split the RF signal into a first RF signal provided to the first amplification path via the first power divider output and a second RF signal provided to the second amplification path via the second power divider output; and a combining node configured to receive and combine the amplified RF signals generated by the first amplification path and the second amplification path.

[0015] According to a second aspect of the present invention, a packaged radio frequency (RF) amplifier device is provided, comprising:

[0016] device substrate;

[0017] A first input lead is coupled to the device substrate;

[0018] A first output lead is coupled to the device substrate;

[0019] A first transistor die coupled to the device substrate, wherein the first transistor die includes a first transistor, a transistor input coupled to the first input lead, and a transistor output coupled to the first output lead, and wherein the drain-source capacitance of the first transistor is less than 0.2 picofarads per watt.

[0020] A first output-side impedance matching circuit, the first output-side impedance matching circuit having a T-type matching circuit topology coupled between the output terminal of the first transistor and the first output lead, wherein the first output-side impedance matching circuit includes:

[0021] A first inductor element is connected between the transistor output terminal and a first quasi-RF cold spot node, wherein the first inductor element includes a first plurality of bonding wires.

[0022] A second inductor element is connected between the first quasi-RF cold spot node and the first output lead, wherein the second inductor element includes a second plurality of bonding wires.

[0023] A first capacitor, the first capacitor being connected between the first quasi-RF cold spot node and the ground reference node; and

[0024] A first baseband termination circuit is connected to the first quasi-RF cold spot node, wherein the first baseband termination circuit includes a first plurality of components, wherein the first plurality of components include a first envelope resistor, a first envelope inductor, and a first envelope capacitor coupled in series between the first quasi-RF cold spot node and the ground reference node.

[0025] According to one or more embodiments, the transistor is a gallium nitride transistor.

[0026] According to one or more embodiments, the packaged RF amplifier device further includes: an integrated passive device coupled to the device substrate and located between the first transistor die and the first output lead, wherein the integrated passive device includes a first quasi-RF cold spot node, a first capacitor, an envelope resistor, an envelope inductor, and an envelope capacitor.

[0027] According to one or more embodiments, the packaged RF amplifier device further includes: an output-side harmonic termination circuit, the output-side harmonic termination circuit including a third inductor and a second capacitor connected in series between the transistor output terminal and the ground reference node, wherein the third inductor includes a third plurality of bond wires, and the output-side harmonic termination circuit resonates at the second harmonic frequency of the fundamental operating frequency of the RF amplifier.

[0028] According to one or more embodiments, the second capacitor is integrally formed with the integrated passive device.

[0029] According to one or more embodiments, the packaged RF amplifier device further includes: a second baseband termination circuit connected to the first quasi-RF cold spot node, wherein the second baseband termination circuit includes a second plurality of components, wherein the second plurality of components includes a second envelope inductor and a second envelope capacitor series coupled between the first quasi-RF cold spot node and the ground reference node.

[0030] According to one or more embodiments, a packaged RF amplifier device is provided, wherein the second envelope inductor includes an additional lead having a proximal end electrically coupled to the first quasi-RF cold spot node and a distal end outside the packaged RF amplifier device; and the second envelope capacitor includes a discrete capacitor having a first end coupled to the distal end of the additional lead and a second end coupled to ground.

[0031] According to one or more embodiments, the packaged RF amplifier device further includes: a second input lead coupled to the device substrate; a second output lead coupled to the device substrate; a second transistor die coupled to the device substrate, wherein the second transistor die includes a second transistor coupled between the second input lead and the second output lead; a second output-side impedance matching circuit having a T-type matching circuit topology coupled between the second transistor and the second output lead, and further having a second quasi-RF cold spot node; and a second baseband termination circuit connected to the second quasi-RF cold spot node.

[0032] According to another aspect of the present invention, a method for manufacturing an RF amplifier device is provided, the method comprising the following steps:

[0033] Couple the input leads to the device substrate;

[0034] Couple the output lead to the device substrate;

[0035] A transistor die is coupled to the device substrate between the input lead and the output lead, wherein the transistor die includes a transistor and a transistor output terminal, and wherein the drain-source capacitance of the transistor is less than 0.2 picofarads per watt.

[0036] An integrated passive device is coupled to the device substrate between the transistor die and the input lead, wherein the integrated passive device includes a quasi-RF cold spot node, a ground reference node, a first capacitor coupled between the quasi-RF cold spot node and the ground node, and a baseband termination circuit, wherein the baseband termination circuit includes an envelope resistor, an envelope capacitor, and an envelope inductor coupled in series between the quasi-RF cold spot node and the ground reference node; and

[0037] An output-side impedance matching circuit with a T-type matching circuit topology is created between the transistor output terminal and the output lead, wherein the T-type matching circuit topology includes the first capacitor, and the output-side impedance matching circuit is created by coupling a first inductor element between the transistor output terminal and the quasi-RF cold spot node and coupling a second inductor element between the quasi-RF cold spot node and the output lead, wherein the first inductor element includes a first plurality of bond wires, and wherein the second inductor element includes a second plurality of bond wires.

[0038] According to one or more embodiments, the integrated passive device further includes: an additional node, and a second capacitor coupled between the additional node and the ground reference node; and the method further includes: creating an output-side harmonic termination circuit by coupling a third inductor element between the transistor output and the additional node, wherein the third inductor element includes a third plurality of bond wires, and the output-side harmonic termination circuit resonates at the second harmonic frequency of the fundamental operating frequency of the RF amplifier device. Attached Figure Description

[0039] A more complete understanding of the subject matter can be obtained by considering the following figures, and by referring to the specific embodiments and claims. Similar reference numerals are used throughout the figures to refer to similar elements.

[0040] Figure 1 This is a schematic circuit diagram of a power amplifier circuit according to an example embodiment;

[0041] Figures 2A-2F Various example embodiments of the baseband termination circuit are shown;

[0042] Figure 3 This is a simplified schematic diagram of a Dougherty power amplifier according to an example embodiment;

[0043] Figure 4 This is a top view of a packaged RF power amplifier device including two parallel amplification paths according to an example embodiment;

[0044] Figure 5This is a top view of a portion of a packaged RF power amplifier device according to an example embodiment, including portions of the power transistor and the output impedance matching circuit.

[0045] Figure 6 According to the example embodiment Figure 5 A cross-sectional side view of the portion of the RF power amplifier device along line 6-6; and

[0046] Figure 7 This is a flowchart of a method for manufacturing a packaged RF power amplifier device including an output impedance matching circuit, according to an example embodiment. Detailed Implementation

[0047] An embodiment of a radio frequency (RF) amplifier having a first amplification path includes a transistor die having a transistor and a transistor output, and an output-side impedance matching circuit having a T-type matching circuit topology coupled between the transistor output and the output of the first amplification path. The output-side impedance matching circuit includes a first inductor connected between the transistor output and a quasi-RF cold spot node, a second inductor connected between the quasi-RF cold spot node and the output of the first amplification path, and a first capacitor connected between the quasi-RF cold spot node and a ground reference node. The RF amplifier also includes a baseband termination circuit connected to the quasi-RF cold spot node. The baseband termination circuit includes multiple components, including an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi-RF cold spot node and the ground reference node.

[0048] In another embodiment, the first inductor element includes a first plurality of bond wires, and the second inductor element includes a second plurality of bond wires. In yet another embodiment, the baseband termination circuit further includes a bypass capacitor coupled in parallel across one or more of the plurality of components of the first baseband termination circuit. In yet another embodiment, the bypass capacitor is coupled in parallel across an envelope inductor, and the envelope inductor and the bypass capacitor form a parallel resonant circuit at a frequency close to the operating center frequency of the RF amplifier. In yet another embodiment, the RF amplifier further includes an output-side harmonic termination circuit, which includes a third inductor element and a second capacitor connected in series between the transistor output and a ground reference node, and the output-side harmonic termination circuit resonates at the second harmonic frequency of the RF amplifier's fundamental operating frequency. In yet another embodiment, the inductance value of the first inductor element is in the range of 20 picohenons to 3 nanohenons, the inductance value of the second inductor element is in the range of 20 picohenons to 3 nanohenons, and the capacitance value of the first capacitor is in the range of 10 picofarads to 140 picofarads. In another embodiment, the inductance of the third inductor is in the range of 20 picohens to 3 nanohens, and the capacitance of the second capacitor is in the range of 1 picofarad to 100 picofarads. In another embodiment, the resistance of the envelope resistor is in the range of 0.1 ohms to 5.0 ohms, the inductance of the envelope inductor is in the range of 5 picohens to 3000 picohens, and the capacitance of the envelope capacitor is in the range of 1 nanofarad to 1 microfarad. In another embodiment, the transistor is a gallium nitride transistor with a drain-source capacitance of less than 0.2 picofarads per watt. In another embodiment, the RF amplifier is a Dougherty power amplifier that further includes a second amplification path, a power divider, and a combination node. The power divider has a power divider input configured to receive an RF signal, a first power divider output coupled to an input of the first amplification path, and a second power divider output coupled to an input of the second amplification path. The power divider is configured to split the RF signal into a first RF signal provided to the first amplification path via the first power divider output and a second RF signal provided to the second amplification path via the second power divider output. The combining node is configured to receive and combine the amplified RF signals generated by the first amplification path and the second amplification path.

[0049] An embodiment of a packaged RF amplifier device includes a device substrate, a first input lead coupled to the device substrate, a first output lead coupled to the device substrate, and a first transistor die coupled to the device substrate. The first transistor die includes a first transistor, a transistor input coupled to the first input lead, and a transistor output coupled to the first output lead, and the drain-source capacitance of the first transistor is less than 0.2 picofarads per watt. The packaged RF amplifier device further includes a first output-side impedance matching circuit having a T-type matching circuit topology coupled between the first transistor output and the first output lead. The first output-side impedance matching circuit includes a first inductor connected between the transistor output and a first quasi-RF cold spot node, a second inductor connected between the first quasi-RF cold spot node and the first output lead, and a first capacitor connected between the first quasi-RF cold spot node and a ground reference node. The first inductor includes a first plurality of bond wires, and the second inductor includes a second plurality of bond wires. The packaged RF amplifier device further includes a first baseband termination circuit connected to the first quasi-RF cold spot node. The first baseband termination circuit includes a first plurality of components, the components including a first envelope resistor, a first envelope inductor, and a first envelope capacitor, which are coupled in series between a first quasi-RF cold spot node and a ground reference node.

[0050] In another embodiment, the transistor is a gallium nitride transistor. In yet another embodiment, the packaged RF amplifier device further includes an integrated passive device coupled to the device substrate between the first transistor die and the first output lead, and the integrated passive device includes a first quasi-RF cold spot node, a first capacitor, an envelope resistor, an envelope inductor, and an envelope capacitor. In yet another embodiment, the packaged RF amplifier device further includes an output-side harmonic termination circuit having a third inductor element and a second capacitor connected in series between the transistor output and a ground reference node, wherein the third inductor element includes a third plurality of bond wires, and the output-side harmonic termination circuit resonates at the second harmonic frequency of the operating fundamental frequency of the RF amplifier. In yet another embodiment, the second capacitor is integrally formed with the integrated passive device. In yet another embodiment, the packaged RF amplifier device further includes a second baseband termination circuit connected to the first quasi-RF cold spot node, and the second baseband termination circuit includes a second plurality of components, the components including a second envelope inductor and a second envelope capacitor connected in series between the first quasi-RF cold spot node and the ground reference node. In another embodiment, the second envelope inductor includes an additional lead having a proximal end electrically coupled to a first quasi-RF cold spot node and a distal end outside the packaged RF amplifier device, and the second envelope capacitor includes a discrete capacitor having a first end coupled to the distal end of the additional lead and a second end coupled to ground. In yet another embodiment, the packaged RF amplifier device further includes: a second input lead coupled to a device substrate; a second output lead coupled to a device substrate; a second transistor die coupled to a device substrate, wherein the second transistor die includes a second transistor die coupled between the second input lead and the second output lead; a second output-side impedance matching circuit having a T-type matching circuit topology coupled between the second transistor and the second output lead, and additionally having a second quasi-RF cold spot node; and a second baseband termination circuit connected to the second quasi-RF cold spot node.

[0051] An embodiment of a method for manufacturing an RF amplifier device includes: coupling an input lead to a device substrate; coupling an output lead to the device substrate; coupling a transistor die to the device substrate between the input lead and the output lead; and coupling an integrated passive device to the device substrate between the transistor die and the input lead. The transistor die includes a transistor and a transistor output terminal, and the drain-source capacitance of the transistor is less than 0.2 picofarads per watt. The integrated passive device includes a quasi-RF cold spot node, a ground reference node, a first capacitor coupled between the quasi-RF cold spot node and the ground node, and a baseband termination circuit, wherein the baseband termination circuit includes an envelope resistor, an envelope capacitor, and an envelope inductor coupled in series between the quasi-RF cold spot node and the ground reference node. The method further includes creating an output-side impedance matching circuit with a T-type matching circuit topology between the transistor output and the output lead, wherein the T-type matching circuit topology includes a first capacitor, and the output-side impedance matching circuit is created by coupling a first inductor element between the transistor output and the quasi-RF cold spot node and coupling a second inductor element between the quasi-RF cold spot node and the output lead. The first inductor element includes a first plurality of bond wires, and the second inductor element includes a second plurality of bond wires.

[0052] According to yet another embodiment, the integrated passive device further includes an additional node and a second capacitor coupled between the additional node and a ground reference node, and the method further includes creating an output-side harmonic termination circuit by coupling a third inductor element between the transistor output and the additional node, wherein the third inductor element includes a third plurality of bond wires, and the output-side harmonic termination circuit resonates at the second harmonic frequency of the fundamental operating frequency of the RF amplifier device.

[0053] In the field of high-power radio frequency (RF) power amplification for cellular base stations and other applications, broadband power amplification using silicon-based devices (e.g., laterally diffused metal-oxide-semiconductor (LDMOS) power transistors with output matching networks) has been successfully achieved. However, these silicon-based devices exhibit relatively low efficiency and power density compared to gallium nitride (GaN)-based power amplifier devices. Therefore, GaN-based power amplifier devices are increasingly being considered for high-power broadband applications. However, achieving broadband power amplification (e.g., fractional bandwidth exceeding 20%) using GaN technology presents challenges.

[0054] For example, it is known that the nonlinear input capacitance of RF power devices including GaN transistors can generate harmonics and intermodulation distortion that can impair efficiency and linearity. Furthermore, the drain-source capacitance Cds of GaN-based transistors is relatively low per RF output peak power compared to silicon-based LDMOS transistors. For instance, while the drain-source capacitance of LDMOS transistors can be greater than about 0.4 picofarads per watt (0.4 pF / W), the drain-source capacitance of GaN-based transistors can be less than about 0.2 pF / W in some embodiments and less than about 0.1 pF / W in others.

[0055] Second harmonic termination also plays a significant role in the overall performance of power amplifier designs using GaN-based transistors. Without knowledge of the second harmonic impedance at the current source plane, it is extremely difficult to tune a power amplifier to achieve a relatively high fractional bandwidth with good performance. Furthermore, for broadband applications, the second harmonic termination can vary significantly over a large bandwidth, further complicating circuit tuning.

[0056] To overcome these and other challenges in designing broadband power amplifiers using GaN-based devices, the embodiments disclosed herein can achieve broadband output impedance matching at the fundamental frequency using an output impedance matching circuit system with a T-type matching circuit topology (hereinafter referred to as a "T-type matching" circuit). The parallel capacitor in the output-side T-type matching circuit can also have a sufficiently high capacitance value (e.g., greater than 10 picofarads (pF) but less than 140 pF) to provide an acceptable RF low impedance point (i.e., a "quasi-RF cold spot" indicating a low impedance point in the circuit for RF signals). In various embodiments, one or more baseband termination circuits with good RF isolation are connected to the quasi-RF cold spot.

[0057] Additionally, in some embodiments where a harmonic termination circuit is included at the output of the device, the inductance provided between the transistor output and the parallel capacitor within the output impedance matching circuit can be significantly reduced. These harmonic termination circuit system embodiments can be used to control the second harmonic impedance over a wide (e.g., more than 20%) fractional bandwidth with relatively low impedance (e.g., near short circuit). This can be useful for achieving relatively high efficiency in broadband applications. Some specific embodiments of the subject matter of this invention include an output harmonic termination circuit system comprising an integrated capacitor (e.g., a metal-insulator-metal (MIM) capacitor) and an inductor (e.g., in the form of a bonded wire array) series coupled between the transistor output and a ground reference.

[0058] During operation of an embodiment of the device, at the device's fundamental operating frequency, the output-side harmonic termination circuit essentially functions as a capacitor, with the capacitance value roughly equivalent to the series-coupled inductance and capacitance of the harmonic termination circuit (e.g., Figure 1 The effective capacitance of the inductor 172 and capacitor 174. Because this equivalent parallel capacitance from the series-coupled combination of inductance and capacitance is coupled in parallel with the drain-source capacitance between the transistor output and ground reference, the equivalent parallel capacitance in the harmonic termination circuit effectively increases the drain-source capacitance of the transistor. In some embodiments, the equivalent parallel capacitance from the series-coupled combination of inductance and capacitance in the harmonic termination circuit has a capacitance value that effectively increases the drain-source capacitance of the transistor connected thereto by at least 10% (e.g., between 10% and about 50% or more).

[0059] Figure 1 This is a schematic diagram of an RF power amplifier circuit 100. In an embodiment, circuit 100 includes an input 102 (e.g., a first conductive package lead), an input impedance matching circuit 110 (which includes a harmonic termination circuit 130), a transistor 140, an output impedance matching circuit 150 (which includes a harmonic termination circuit 170), baseband termination (BBT) circuits 160, 161, and 162, and an output lead 104 (e.g., a second conductive package lead). Each of the inputs 102 and the output 104 may be more generally referred to as an "RF input / output (I / O)".

[0060] The input impedance matching circuit 110 (including harmonic termination circuit 130) and the baseband termination circuit 160 can be collectively referred to as the "input circuit". Similarly, the output impedance matching circuit 150 (including harmonic termination circuit 170) and the baseband termination circuits 161, 162 can be collectively referred to as the "output circuit". According to an embodiment, in the output circuit, the baseband termination circuit includes an "in-package" baseband termination circuit 161 (IN-PKG BBT CKT) and an "out-of-package" baseband termination circuit 162 (OUT-PKG BBTCKT). As will be discussed below, although components of the in-package baseband termination circuit 161 may be included in a power amplifier device (e.g., Figure 4 The device 400 is inside the package, but the outer baseband termination circuit 162 may include additional leads 195 (e.g., a third conductive package lead) and one or more components outside the power amplifier device.

[0061] Although transistor 140 and various elements of input impedance matching circuits 110 and 150, baseband termination circuits 160-162, and harmonic termination circuits 130, 170 are shown as single components, this depiction is for illustrative purposes only. Based on the description herein, those skilled in the art will understand that certain elements of transistor 140 and / or input impedance matching circuit 110 (including harmonic termination circuit 130), output impedance matching circuit 150 (including harmonic termination circuit 170), and baseband termination circuits 160-162 may each be implemented as multiple components (e.g., connected in parallel or series with each other). Furthermore, embodiments may include single-path devices (e.g., including a single input lead, output lead, transistor, etc.), dual-path devices (e.g., including two input leads, output leads, transistors, etc.), and / or multi-path devices (e.g., including two or more input leads, output leads, transistors, etc.). Additionally, the number of input / output leads may differ from the number of transistors (e.g., for a given set of input / output leads, multiple transistors operating in parallel may exist). The following description of the transistor 140 and the various components of the input impedance matching circuit 110 (including the harmonic termination circuit 130), the output impedance matching circuit 150 (including the harmonic termination circuit 170), and the baseband termination circuits 160-162 is therefore not intended to limit the scope of the invention to the embodiments shown.

[0062] Input 102, output 104, and lead 195 may each include a conductor configured to electrically couple circuit 100 to an external circuitry (not shown). More specifically, input 102, output 104, and lead 195 are physically positioned across the exterior and interior of the device package. Input impedance matching circuitry 110 (including harmonic termination circuitry 130) and baseband termination circuitry 160 are electrically coupled between input 102 and a first terminal 142 of transistor 140 (e.g., the gate terminal of transistor 140), which is also located inside the device. Similarly, output impedance matching circuitry 150 (including harmonic termination circuitry 170) and in-package baseband termination circuitry 161 are electrically coupled between a second terminal 144 of transistor 140 (e.g., the drain terminal of transistor 140) and output 104. The outer baseband termination circuit 162 is electrically coupled to the second terminal 144 of the transistor 140 via a lead 195, which also forms the inductor portion of the outer baseband termination circuit 162.

[0063] According to an embodiment, transistor 140 is the primary active component of circuit 100. Transistor 140 includes a control terminal 142 and two conductive terminals 144, 145, wherein the conductive terminals 144, 145 are spatially and electrically separated by a variable conductivity channel. For example, transistor 140 may be a field-effect transistor (FET) including a gate (control terminal 142), a drain (first conductive terminal 144), and a source (second conductive terminal 145). According to an embodiment, and using nomenclature generally applied to FETs in a non-limiting manner, the gate 142 of transistor 140 is coupled to an input impedance matching circuit 110 (including a harmonic termination circuit 130) and a baseband termination circuit 160, the drain 144 of transistor 140 is coupled to an output impedance matching circuit 150 (including a harmonic termination circuit 170) and baseband termination circuits 161, 162, and the source 145 of transistor 140 is coupled to ground (or another voltage reference). The current between the conductive terminals of transistor 140 can be modulated by changing the control signal supplied to the gate of transistor 140.

[0064] According to various embodiments, transistor 140 is a III-V field-effect transistor (e.g., a high electron mobility transistor (HEMT)) that has a relatively low drain-source capacitance Cds compared to silicon-based FETs (e.g., LDMOS FETs). In Figure 1, the drain-source capacitance of transistor 140 is defined by the drain of transistor 140 and the transistor output terminal 144 (e.g., corresponding to...). Figure 7 The capacitor 146 between the transistor output terminal 744 is represented. More specifically, the capacitor 146 is not a physical component, but rather a model of the drain-source capacitance of the transistor 140. According to embodiments, the drain-source capacitance of the transistor 140 can be less than about 0.2 pF / W. Additionally, in some embodiments, the transistor 140 can be a GaN FET, but in other embodiments, the transistor 140 can be another type of III-V transistor (e.g., gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), or indium antimonide (InSb)), or another type of transistor with a relatively low drain-source capacitance. In other embodiments, the transistor 140 can be implemented as a silicon-based FET (e.g., an LDMOS FET).

[0065] Input impedance matching circuit 110 is coupled between input 102 and control terminal 142 (e.g., gate) of transistor 140. Input impedance matching circuit 110 is configured to raise the impedance of circuit 100 to a higher (e.g., intermediate or higher) impedance level (e.g., in the range of about 2 ohms to about 10 ohms or higher). This is advantageous because it allows the printed circuit board level (PCB level) matching interface from the drive stage to have an impedance that can be achieved in high-volume manufacturing with minimal loss and variation (e.g., a “user-friendly” matching interface).

[0066] According to an embodiment, the input impedance matching circuit 110 has a T-matching configuration comprising two inductor elements 112 and 116 (e.g., two sets of bond wires) and a parallel capacitor 114. A first inductor element 112 (e.g., a first set of bond wires) is coupled between the input 102 and node 118, which in turn is coupled to a first end of the capacitor 114. A second inductor element 116 (e.g., a second set of bond wires) is coupled between node 118 (or the first end of the capacitor 114) and a control terminal 142 of the transistor 140. A second end of the capacitor 114 is coupled to ground (or another voltage reference). The combination of inductor elements 112 and 116 and the parallel capacitor 114 acts as a low-pass filter. According to an embodiment, the inductance value of the series combination of inductor elements 112 and 116 can be in the range of about 20 picohens (pH) to about 3 nanohenries (nH), and the capacitance value of the parallel capacitor 114 can be in the range of about 5 pF to about 120 pF. In some embodiments, the capacitance of the parallel capacitor 114 can be relatively large (e.g., greater than 10 pF but less than 140 pF) to provide an acceptable low RF impedance point at node 118.

[0067] Additionally, harmonic termination circuit 130 is coupled between the control terminal 142 (e.g., gate) of transistor 140 and ground (or another voltage reference). Harmonic termination circuit 130 includes an inductor 132 (e.g., a third set of bond wires) and a capacitor 134, series coupled between the control terminal 142 of transistor 140 and ground (or another voltage reference), and this series combination of elements acts as a low-impedance path for signal energy to ground at harmonic frequencies (e.g., the second harmonic of the operating fundamental frequency of circuit 100). According to embodiments, the inductance value of inductor 132 can be in the range of about 20 pH to about 3 nH, and the capacitance value of capacitor 134 can be in the range of about 1 pF to about 100 pF, but the values ​​of these components can also be outside these ranges. For example, at an operating fundamental frequency of 2.0 GHz (whose second harmonic is 4.0 GHz), the inductance value of inductor 132 can be about 120-140 pH, and the capacitance value of capacitor 134 can be about 11-12 pF. The desired inductance and / or capacitance values ​​used to achieve a low-impedance path for signal energy to ground at the second harmonic frequency may be affected by the mutual coupling between the bond wires used to implement inductors 116 and 132.

[0068] According to an embodiment, an RF low-impedance point may be present at or coupled to node 118 between inductor elements 112 and 116, wherein the RF low-impedance point represents a low-impedance point in the circuit used for RF signals. According to an embodiment, a baseband termination (BBT) circuit 160 is coupled between node 118 (e.g., at or coupled to node 118) and a ground reference node. The baseband termination circuit 160 can be used to improve the low-frequency resonance (LFR) of circuit 100 caused by the interaction between the input matching circuit 110 and the bias feed (not shown) by presenting low impedance at the envelope frequency and / or high impedance at the RF frequency. From an RF matching perspective, the baseband termination circuit 160 can be essentially considered "invisible" because it primarily affects impedance at the envelope frequency (i.e., the baseband termination circuit 160 provides termination for the envelope frequency of circuit 100). Only one baseband termination circuit 160 is shown coupled to node 118, and when a single baseband termination circuit 160 is implemented in the input circuitry, the baseband termination circuit can be an "in-package" or "out-of-package" baseband termination circuit, as previously defined. In alternative embodiments, both in-package and out-of-package baseband termination circuits can be coupled to node 118, and these in-package and out-of-package, input-side baseband circuits can be implemented similarly to the baseband termination circuits 161 and 162 discussed below. As will be discussed later... Figures 2A-2F In more detail, in various embodiments, the baseband termination circuit 160 can have any of a variety of different circuit configurations.

[0069] On the output side of circuit 100, output impedance matching circuit 150 is coupled between the first conductive terminal 144 (e.g., drain) of transistor 140 and output 104. Output impedance matching circuit 150 is configured to match the output impedance of circuit 100 with the input impedance of external circuitry or components (not shown) that may be coupled to output 104.

[0070] According to an embodiment, the output impedance matching circuit 150 has a T-type matching configuration, which includes two inductor elements 152 and 154 (e.g., two sets of bond wires) and a parallel capacitor 156. A first inductor element 152 (e.g., a fourth set of bond wires) is coupled between terminal 144 of transistor 140 and node 158, which in turn is coupled to a first terminal of capacitor 156. A second inductor element 154 (e.g., a fifth set of bond wires) is coupled between node 158 (or the first terminal of capacitor 156) and output 104. A second terminal of capacitor 156 is coupled to ground (or another voltage reference). The combination of inductor elements 152 and 154 and parallel capacitor 156 acts as a low-pass filter. According to an embodiment, the inductance value of the series combination of inductor elements 152 and 154 can be in the range of about 20 pF to about 3 nH, and the capacitance value of parallel capacitor 156 can be in the range of about 10 pF to about 140 pF. In any case, choose the value of parallel capacitor 156 to provide an acceptable low RF impedance point at node 158.

[0071] Additionally, a harmonic termination circuit 170 is coupled between the first conductive terminal 144 (e.g., drain) of transistor 140 and ground (or another voltage reference). The harmonic termination circuit 170 includes an inductor 172 (sixth set of bond wires) and a capacitor 174 coupled in series between the first conductive terminal 144 of transistor 140 and ground (or another voltage reference), and this series combination of elements serves as another low-impedance path for signal energy at harmonic frequencies (e.g., the second harmonic of the operating fundamental frequency of circuit 100) to ground. According to embodiments, the inductance value of inductor 172 can range from about 20 pH to about 3 nH, and the capacitance value of capacitor 174 can range from about 1 pF to about 100 pF, but the values ​​of these components can also be outside these ranges. For example, at an operating fundamental frequency of 2.0 GHz (whose second harmonic is 4.0 GHz), the inductance value of inductor 172 can be about 120-140 pH, and the capacitance value of capacitor 174 can be about 11-12 pF. As will be explained below, the desired inductance and / or capacitance values ​​used to achieve a low-impedance path from the signal energy at the second harmonic frequency to ground may be affected by the mutual coupling between the bond wires used to implement inductors 152 and 172.

[0072] An RF low-impedance point (also known as a "quasi-RF cold spot node") exists at node 158 between inductor elements 152 and 154. Similarly, RF low-impedance point 158 ​​represents a low-impedance point in the circuit used for RF signals. According to various embodiments, one or more additional baseband termination circuits 161, 162 are coupled between RF low-impedance point 158 ​​and the ground reference node. (The last sentence appears to be incomplete and possibly refers to a different context.) Figure 4-6 In more detail, the first output-side baseband termination circuit 161 is considered an in-package baseband termination circuit, and the second output-side baseband termination circuit 162 is considered an out-of-package baseband termination circuit. Similarly, baseband termination circuits 161 and 162 can be used to further improve the LFR of circuit 100 caused by the interaction between the output impedance matching circuit 150 and the bias feed (not shown) by presenting low impedance at the envelope frequency and / or high impedance at the RF frequency. From an RF matching perspective, baseband termination circuits 161 and 162 can also be considered "invisible".

[0073] If combined Figures 2A-2F As described, in various embodiments, each of the baseband termination circuits 160-162 may have any of a variety of different circuit configurations. For example, Figures 2A-2F The baseband termination circuit is shown (e.g., Figure 1 Six example embodiments of the baseband termination circuits 160-162. Figures 2A-2F In each of the diagrams, baseband termination circuits 200, 201, 202, 203, 204, and 205 are coupled to connection node 218 (e.g., Figure 1 Between nodes 118 and / or 158 and ground (or another voltage reference). Additionally, each baseband termination circuit 200-205 includes an envelope inductor L series coupled between node 218 and ground. env 262. Envelope resistor R env 264 and envelope capacitor C env 266. In Figures 2A-2E In each of the diagrams, the first end of the envelope inductor 262 is coupled to node 218, and the second end of the envelope inductor 262 is coupled to node 280. The first end of the envelope resistor 264 is coupled to node 280, and the second end of the envelope resistor 264 is coupled to node 282. The first end of the envelope capacitor 266 is coupled to node 282, and the second end of the envelope capacitor 266 is coupled to ground (or another voltage reference). Although in Figures 2A-2E In this embodiment, the series connection order of the components between node 218 and the ground reference node is envelope inductor 262, envelope resistor 264, and envelope capacitor 266. However, in other embodiments, the order of components in the series circuit may be different. For example, in... Figure 2FIn the diagram, envelope resistor 264 is coupled between node 218 and node 284, envelope inductor 262 is coupled between node 284 and node 286, and envelope capacitor 266 is coupled between node 286 and ground (or another voltage reference).

[0074] refer to Figures 2A-2F Furthermore, according to an embodiment, the envelope inductor 262 can be implemented as an integrated inductor (e.g., Figure 5 The inductor 562), implemented as a discrete inductor, and / or implemented as one or more conductors coupling connection node 218 to envelope resistor 264 (e.g., via node 280). Figure 4 and, for example Figure 5 One of the bonding wires 590 and the lead 492-495 connected in series (e.g., bonding wire 590). For example, and as will be described in detail below, when the baseband termination circuits 201-205 form an in-package baseband termination circuit (e.g., Figure 1 When the BBT circuit 160, 161) is used as part of the circuit, the envelope inductor 262 can be integrally formed as part of the integrated passive device (IPD), for example... Figure 4-6 IPD 480-483. Alternatively, when the baseband termination circuits 201-205 form an external baseband termination circuit (e.g., Figure 1 When the BBT circuit 162 is part of the package, the envelope inductor 262 may include one or more series-connected inductors configured to provide a signal path between the inside of the package and the outside of the package (e.g., Figure 4 and, for example Figure 5 One of the bond wires 492-495 connected in series, such as bond wire 590. For example, the inductance value of envelope inductor 262 can be in the range of about 5 pH to about 3000 pH. For in-package baseband termination circuits (e.g., Figure 1 For the BBT circuits 160, 161, it is desirable that the inductance value of the envelope inductor 262 is less than about 500 pH (e.g., as low as 50-150 pH, or possibly even lower, in the embodiments). For the packaged external baseband termination circuit (e.g., Figure 1 In the BBT circuit 162, the envelope inductance 262 may be significantly higher (e.g., between 1000 pH and 3000 pH). In other embodiments, the value of the envelope inductance 262 may be lower or higher than the range given above.

[0075] In an embodiment, the envelope resistor 264 may be implemented as an integrated resistor (e.g., Figure 5 Resistor 564), or in another embodiment implemented as a discrete resistor. For example, when baseband termination circuits 201-205 form an in-package baseband termination circuit (e.g., Figure 1When the BBT circuit 160, 161) is used as part of the circuit, the envelope resistor 264 can be integrally formed as part of the IPD, for example. Figure 4-6 IPD 480-483. Alternatively, when the baseband termination circuits 201-205 form an external baseband termination circuit (e.g., Figure 1 When the BBT circuit 162 is part of the baseband termination circuit, the envelope resistor may not be included in the baseband termination circuit, or the envelope resistor 264 may include package leads (e.g., Figure 1 , 4 The inherent resistance of the leads 195, 495, or the envelope resistor may be provided in other ways. In an embodiment, the resistance value of the envelope resistor 264 may be in the range of about 0.1 ohms to about 5.0 ohms, but the resistance value of the envelope resistor 264 may also exceed this range.

[0076] In an embodiment, the envelope capacitor 266 may be implemented as an integrated capacitor (e.g., Figure 5 The capacitor 566), or in another embodiment, implemented as a discrete capacitor (e.g., as a ...). Figure 4 One of the discrete capacitors 498 and 499). For example, when baseband termination circuits 201-205 form an in-package baseband termination circuit (e.g., Figure 1 When the BBT circuit 160, 161) is used as a part, the envelope capacitor 266 can be integrally formed as part of the IPD, for example. Figure 4-6 IPD 480-483. Alternatively, when the baseband termination circuits 201-205 form an external baseband termination circuit (e.g., Figure 1 When the BBT circuit 162 is part of the circuit, the envelope capacitor 266 can be implemented as a discrete capacitor (e.g., as a...). Figure 4 One of discrete capacitors 498 and 499), said discrete capacitor having a coupling to a package lead (e.g., Figure 4 The first end of the distal end of one of leads 494 and 495, and the second end coupled to the ground reference point of the PCB to which the amplifier device is coupled. In an embodiment, for the in-package baseband termination circuit (e.g., Figure 1 In the BBT circuits 160 and 161, the capacitance value of the envelope capacitor 266 can be in the range of about 1 nanofarad (nF) to about 1 microfarad (μF), while for the packaged external baseband termination circuit (e.g., Figure 1 In the BBT circuit 162, the value of the envelope capacitor 266 can be significantly higher (e.g., the capacitance value is in the range of approximately 1 μF to 20 μF). In other embodiments, the capacitance value of the envelope capacitor 266 may also exceed these ranges.

[0077] Figure 2AThe first embodiment of the baseband termination circuit 200 shown includes a simple series combination of an envelope inductor 262, an envelope resistor 264, and an envelope capacitor 266. Conversely, in Figure 2B-2F In embodiments, the baseband termination circuits 201-205 may include one or more “bypass” or “parallel” capacitors C coupled in parallel with the envelope inductor 262 and / or the envelope resistor 264. para 268, 270, 272, 274, 276, 278. In some embodiments, each of the bypass capacitors 268, 270, 272, 274, 276, 278 can be implemented as a discrete capacitor (e.g., Figure 5 The bypass capacitor 578, or in other embodiments, is implemented as an integrated capacitor. In each of these embodiments, the capacitance value of the bypass capacitors 268, 270, 272, 274, 276, and 278 can be in the range of about 3.0 pF to about 1400 pF. In other embodiments, the value of any one of the bypass capacitors 268, 270, 272, 274, 276, and 278 can be lower or higher than the range given above.

[0078] exist Figure 2B In the baseband termination circuit 201, the bypass capacitor C para 268 is coupled in parallel with envelope inductor 262. More specifically, the first ends of envelope inductor 262 and bypass capacitor 268 are coupled to node 218, and the second ends of envelope inductor 262 and bypass capacitor 268 are coupled to node 280.

[0079] exist Figure 2C In the baseband termination circuit 202, the bypass capacitor C para 270 is coupled in parallel with the envelope resistor 364. More specifically, the first end of the envelope resistor 264 and the bypass capacitor 270 is coupled to node 280, and the second end of the envelope resistor 264 and the bypass capacitor 270 is coupled to node 282.

[0080] exist Figure 2D In the baseband termination circuit 203, the bypass capacitor C para 272 is coupled in parallel with envelope inductor 262 and envelope resistor 264. More specifically, bypass capacitor 272 is coupled between node 218 and node 282.

[0081] exist Figure 2E In the baseband termination circuit 204, the first bypass capacitor C para1 274 is coupled in parallel with envelope inductor 262, and the second bypass capacitor C para2Envelope inductor 276 is coupled in parallel with envelope resistor 264. More specifically, the first terminals of envelope inductor 262 and first bypass capacitor 274 are coupled to node 218, and the second terminals of envelope inductor 262 and first bypass capacitor 274 are coupled to node 280. Additionally, the first terminals of envelope resistor 264 and second bypass capacitor 276 are coupled to node 280, and the second terminals of envelope resistor 264 and second bypass capacitor 276 are coupled to node 282.

[0082] refer to Figure 2B , 2E The baseband termination circuits 201, 204, and 205 of 2F, along with the parallel-coupled inductor 262 and capacitors 268, 274, or 278, form a parallel resonant circuit at a frequency close to the operating center frequency of the device or circuit including circuits 201, 204, or 205 (e.g., circuit 100). As used herein and according to embodiments, the term "close to the operating center frequency" means "within 20% of the operating center frequency." Thus, for example, when the operating center frequency of the device is 2.0 gigahertz (GHz), the frequency "close to the operating center frequency" corresponds to a frequency falling within the range of 1.8 GHz to 2.2 GHz. Although 2.0 GHz is given as an example operating center frequency, the operating center frequency of the device may also be different from 2.0 GHz. In alternative embodiments, the term "close to the operating center frequency" may refer to "within 10% of the operating center frequency" or "within 5% of the operating center frequency."

[0083] Because L env / / C para A parallel resonant circuit is formed at a frequency close to the operating center frequency of the device, therefore the parallel resonant circuit L env / / C para For such frequencies, it essentially presents as an open circuit. Therefore, the RF energy near the operating center frequency that may exist at node 218 coupled to circuits 201, 204, or 205 will be neutralized by the parallel resonant circuit L. env / / C para Deflection. This deflection may be provided even using the relatively low inductance value of inductor 262. For these reasons, circuits 201, 204, and 205 can significantly improve the LFR of a device or circuit (e.g., circuit 100) including said circuits 201, 204, and 205 by presenting low impedance at the envelope frequency and high impedance at the RF frequency.

[0084] exist Figure 2C , 2DIn each embodiment of the baseband termination circuits 202, 203, and 204 of circuit 2E, bypass capacitors 270, 272, or 276 are coupled in parallel with envelope resistor 264. Because capacitors 270, 272, or 276 can be used to channel RF current around envelope resistor 264, circuits 202, 203, and 204 can reduce the RF current dissipated by envelope resistor 264. This feature of circuits 202, 203, and 204 can also be used to better protect envelope resistor 264 from potential damage caused by excessive current that might otherwise flow through envelope resistor 264 without bypass capacitors 270, 272, or 276. Each of circuits 201-205 can improve device efficiency compared to circuit 200 because circuits 201-205 allow less RF current to flow through envelope resistor 264 (and be dissipated).

[0085] Refer again Figure 1 And will be combined with the following text Figure 4-6 In more detail, various embodiments of the RF amplifier device may include at least one input-side integrated passive device (IPD) component (e.g., Figure 4 IPD components 480, 481) and at least one output-side IPD component (e.g., Figure 4-6 The IPD components 482 and 483 are examples of input-side IPD components (e.g., IPD components 480 and 481). Input-side IPD components (e.g., IPD components 480 and 481) include portions of input circuitry 110 (including harmonic termination circuitry 130) and baseband termination circuitry 160. Similarly, output-side IPD components (e.g., IPD components 482 and 483) include portions of output circuitry 150 (including harmonic termination circuitry 170) and in-package baseband termination circuitry 161. More specifically, each IPD component may include a semiconductor substrate having one or more integrated passive components. In a specific embodiment, each input-side IPD component may include parallel capacitors 114 and 134, and portions of the baseband termination circuitry 160 (e.g., ...). Figures 2A-2F Components 262, 264, 266, 268, 270, 272, 274, 276, 278). In other specific embodiments, each output-side IPD component may include parallel capacitors 156 and 174, and components of the in-package baseband termination circuit 161 (e.g., Figures 2A-2F Components 262, 264, 266, 268, 270, 272, 274, 276, 278.

[0086] In other embodiments, portions of the input impedance matching circuit 110, the output impedance matching circuit 150, and the baseband termination circuits 160-162 may be implemented as different / discrete components or as portions of other types of assemblies (e.g., low-temperature co-fired ceramic (LTCC) devices, small PCB assemblies, etc.). In other embodiments, portions of the input impedance matching circuit 110 and / or the output impedance matching circuit 150 may be coupled to and / or integrated within a semiconductor die including the transistor 140. The following detailed description of embodiments including IPD components should not be construed as limiting the subject matter of the invention, and the terms "passive device substrate" or "IPD substrate" refer to any type of structure including passive devices, including IPDs, LTCC devices, transistor dies, PCB assemblies, etc.

[0087] In various embodiments, amplifier circuit 100 may further include a bias circuit system (not shown in the original text). Figure 1 (as shown in the diagram). In order to provide a bias voltage to the gate terminal 142 and / or drain terminal 144 of transistor 140, an external bias circuit (not shown) can be connected to the gate terminal 142 and / or drain terminal 144 of transistor 140 via input 102, output 104 and / or via additional package leads, and can provide a bias voltage via input 102, output 104 and / or additional leads.

[0088] Figure 1 The RF amplifier circuit 100 can be used as a single-path amplifier that receives an RF signal at input 102, amplifies the signal through transistor 140, and generates an amplified RF signal at output 104. Alternatively, multiple instances of the RF amplifier circuit 100 can be used to provide a multipath amplifier, such as a Dougherty power amplifier or another type of multipath amplifier circuit.

[0089] For example, Figure 3 This is a simplified schematic diagram of a Dougherty power amplifier 300, one embodiment of which can implement the RF power amplifier circuit 100. Amplifier 300 includes an input node 302, an output node 304, a power divider 306 (or splitter), a main amplifier path 320, a peaking amplifier path 321, and a combination node 380. A load 390 can be coupled to combination node 380 (e.g., via an impedance transformer, not shown) to receive amplified RF signals from amplifier 300.

[0090] Power divider 306 is configured to split the power of the input RF signal received at input node 302 into a main portion and a peaked portion of the input signal. The main input signal is provided to the main amplifier path 320 at power divider output 308, and the peaked input signal is provided to the peaked amplifier path 321 at power divider output 309. During full-power mode operation, when both the main amplifier 340 and the peaked amplifier 341 supply current to the load 390, power divider 306 distributes the input signal power between amplifier paths 320 and 321. For example, power divider 306 may distribute the power equally, such that approximately half of the input signal power is provided to each path 320 and 321 (e.g., for a symmetrical Dougherty amplifier configuration). Alternatively, power divider 306 may distribute the power unequally (e.g., for an asymmetrical Dougherty amplifier configuration).

[0091] Essentially, the power divider 306 distributes the input RF signal supplied at input node 302, and the distributed signal is amplified separately along the main amplifier path 320 and the peaking amplifier path 321. The amplified signals are then combined in phase at the combining node 380. Importantly, maintaining phase coherence between the main amplifier path 320 and the peaking amplifier path 321 throughout the entire band of interest ensures that the amplified main signal and the peaked signal arrive at the combining node 380 in phase, and thus ensures proper Dougherty amplifier operation.

[0092] Each of the main amplifier 340 and the peaking amplifier 341 includes one or more single-stage or multi-stage power transistor integrated circuits (ICs) (or power transistor dies) for amplifying RF signals transmitted through amplifiers 340, 341. According to various embodiments, all amplifier stages or the final amplifier stage of either or both of the main amplifier 340 and / or the peaking amplifier 341 may be implemented, for example, using III-V field-effect transistors (e.g., HEMTs), such as GaN FETs (or another type of III-V transistor, including GaAs FETs, GaP FETs, InP FETs, or InSb FETs). In some embodiments, where only one of the main amplifier 340 or the peaking amplifier 341 is implemented as a III-V FET, the other amplifiers may be implemented as silicon-based FETs (e.g., LDMOS FETs). In other embodiments, both the main amplifier 340 and / or the peaking amplifier 341 may be implemented as silicon-based FETs.

[0093] While the main power transistor IC and the peaking power transistor IC can have the same size (e.g., in a symmetrical Dougherty configuration), they can also have different sizes (e.g., in various asymmetrical Dougherty configurations). In asymmetrical Dougherty configurations, the peaking power transistor IC is typically a factor larger than the main power transistor IC. For example, the size of the peaking power transistor IC can be twice the size of the main power transistor IC to ensure that the current carrying capacity of the peaking power transistor IC is twice that of the main power transistor IC. Ratios of peaking amplifier IC size to main amplifier IC size other than 2:1 can also be implemented.

[0094] During operation of the Dougherty amplifier 300, the main amplifier 340 is biased to operate in Class AB mode, and the peaking amplifier 341 is biased to operate in Class C mode. At low power levels, where the power of the input signal at node 302 is lower than the turn-on threshold level of the peaking amplifier 341, amplifier 300 operates in low-power (or back-off) mode, where the main amplifier 340 is the only amplifier supplying current to the load 390. When the power of the input signal exceeds the threshold level of the peaking amplifier 341, amplifier 300 operates in high-power mode, where both the main amplifier 340 and the peaking amplifier 341 supply current to the load 390. In this mode, the peaking amplifier 341 provides active load modulation at the combined node 380, thereby allowing the current of the main amplifier 340 to increase linearly and continuously.

[0095] Input impedance matching networks and output impedance matching networks 310, 350 (input MNm, output MNm) can be implemented at the input and / or output of the main amplifier 340. Similarly, input impedance matching networks and output impedance matching networks 311, 351 (input MNp, output MNp) can be implemented at the input and / or output of the peaking amplifier 341. In each case, matching networks 310, 311, 350, 351 can be used to incrementally increase the circuit impedance to the load impedance and source impedance. As previously discussed, in specific embodiments, the input impedance matching networks and output impedance matching networks 310, 311, 350, 351 may each have quasi-cold point nodes (e.g., Figure 1 The T-type matching circuit topology (nodes 118, 158). Baseband termination circuits 360, 361, 362, 363 (e.g., Figure 1 The BBT circuits 160-162 can be coupled between these quasi-cold point nodes and the ground reference. All or part of the input impedance matching network and output impedance matching network 310, 311, 350, 351 and the baseband termination circuits 360-363 can be implemented within a power transistor package including a main amplifier 340 and / or a peaking amplifier 341.

[0096] Additionally, embodiments of the subject matter of this invention include harmonic frequency termination circuits 330, 331 coupled between the inputs of amplifiers 340, 341 and a ground reference. Other embodiments of the subject matter of this invention include harmonic frequency termination circuits 370, 371 coupled between the outputs of amplifiers 340, 341 and a ground reference. The harmonic frequency termination circuits 330, 331, 370, 371 are configured to control harmonic impedance over a relatively wide fractional bandwidth. For example, the harmonic frequency termination circuits 330, 331, 370, 371 can provide a low-impedance path from the second harmonic of the operating center frequency (also referred to herein as the operating "fundamental frequency") fo of amplifier 300 to ground.

[0097] The Dougherty amplifier 300 has a “non-inverted” load network configuration. In the non-inverted configuration, the input circuitry is configured such that the input signal supplied to the peaking amplifier 341 at the operating center frequency fo of the amplifier 300 is delayed by 90 degrees relative to the input signal supplied to the main amplifier 340. As is important for proper Dougherty amplifier operation, to ensure that the main input RF signal and the peaked input RF signal arrive at the main amplifier 340 and the peaking amplifier 341 with a phase difference of approximately 90 degrees, the phase delay element 382 applies a phase delay of approximately 90 degrees to the peaked input signal. For example, the phase delay element 382 may comprise a quarter-wavelength transmission line, or another suitable type of delay element having an electrical length of approximately 90 degrees.

[0098] To compensate for the resulting 90-degree phase delay difference between the main amplifier path 320 and the peaking amplifier path 321 at the inputs of amplifiers 340 and 341 (i.e., to ensure that the amplified signal arrives in phase at the combination node 380), the output circuitry is configured to apply an approximately 90-degree phase delay to the signal between the outputs of the main amplifier 340 and the combination node 380. This is achieved by an additional delay element 384. Alternative embodiments of the Dougherty amplifier may have an “inverted” load network configuration. In such a configuration, the input circuitry is configured such that the input signal supplied to the main amplifier 340 at the operating center frequency fo of amplifier 300 is delayed by approximately 90 degrees relative to the input signal supplied to the peaking amplifier 341, and the output circuitry is configured to apply an approximately 90-degree phase delay to the signal between the outputs of the peaking amplifier 341 and the combination node 380.

[0099] Amplifiers 340 and 341, along with harmonic frequency termination circuits 330, 331, 370, 371, matching networks 310, 311, 350, 351, and baseband termination circuits 360-363, may be implemented in discrete, packaged power amplifier devices. In such devices, input and output leads are coupled to a substrate, and each amplifier 340, 341 may include single-stage or multi-stage power transistors also coupled to the substrate. A portion of the harmonic frequency termination circuits 330, 331, 370, 371, and the input and output matching networks 310, 311, 350, 351 may be implemented as additional components within the packaged device. Furthermore, as described in detail below, a portion of the baseband termination circuits 360-363 (e.g., Figures 2A-2F shown Figure 1 The baseband termination circuits 160-162 in the embodiments can also be implemented as additional components within the package device.

[0100] For example, Figure 4 It is a manifestation Figure 1 A top view of an embodiment of a packaged RF amplifier device 400, comprising two parallel instances of circuit 100, and said packaged RF amplifier device 400 can be used in a Dougherty amplifier (e.g., Figure 3 The Doherty Amplifier 300 provides amplifiers (e.g., Figure 3 Amplifiers 340, 341), and parts of the matching network (e.g., Figure 3 (Parts of the matching networks 310, 311, 350, 351). Additionally, as will be described in more detail below, the device 400 includes two input-side IPD components 480, 481, each of which includes input impedance matching circuits 410, 411 (e.g., ...). Figure 1 , 3 Circuits 110, 310, 311), baseband termination circuits 460, 461 (e.g., Figure 1 , 3 Circuits 160, 360, 361) and harmonic termination circuits 430, 431 (for example, Figure 1 , 3 The circuits 130, 330, and 331 are included. Additionally, device 400 includes two output-side IPD components 482 and 483, each of which includes output impedance matching circuits 450 and 451 (e.g., Figure 1 , 3 Circuits 150, 350, 351), baseband termination circuits 462, 463 within the package (e.g., Figure 1 , 3 Circuits 161, 362, 363) and harmonic termination circuits 470, 471 (for example, Figure 1 , 3The circuits 170, 370, and 371). For each amplification path 420 and 431, an external baseband termination circuit 464 and 465 (e.g., ...) can also be provided on the output side of the device 400. Figure 1 , 3 Circuits 162, 362, and 363.

[0101] In an embodiment, device 400 includes a flange 406 (or "device substrate") comprising a rigid conductive substrate of sufficient thickness to provide structural support for various electrical components and elements of device 400. Additionally, flange 406 can serve as a heat sink for transistor dies 440, 441 and other devices mounted on flange 406. Flange 406 has a top surface and a bottom surface (…). Figure 4 Only the central portion of the top surface is visible in the image, along with a generally rectangular perimeter corresponding to the perimeter of the device 400.

[0102] Flange 406 is formed of a conductive material and can be used to provide a ground reference node for device 400. For example, various components and elements may have ends electrically coupled to flange 406, and flange 406 may be electrically coupled to system ground when device 400 is integrated into a larger power system. At least the top surface of flange 406 is formed of a layer of conductive material, and it is possible that all of flange 406 is formed of bulk conductive material.

[0103] In one embodiment, the isolation structure 408 is attached to the top surface of the flange 406. The isolation structure 408, formed of a rigid electrically insulating material, provides electrical isolation between conductive features of the device (e.g., between leads 402-405 and flange 406). In one embodiment, the isolation structure 408 has a frame shape, comprising a generally closed quadrilateral structure with a central opening. The isolation structure 408 may have a generally rectangular shape, such as… Figure 4 As shown, the isolation structure 408 may have another shape (e.g., a ring, an ellipse, etc.).

[0104] The portion of the top surface of the flange 406 exposed through the opening in the isolation structure 408 is referred to herein as the “active region” of the device 400. Transistor dies 440, 441 and IPD assemblies 480, 481, 482, 483 are located together within the active device region of the device 400, which will be described in more detail below. For example, transistor dies 440, 441 and IPD assemblies 480-483 may be coupled to the top surface of the flange 406 using conductive epoxy, solder, solder bumps, sintering, and / or eutectic coupling.

[0105] Device 400 accommodates two amplification paths (indicated by arrows 420, 421), where each amplification path 420, 421 represents circuit 100. Figure 1 The physical implementation scheme of ). When incorporated into a Dougherty amplifier (e.g., Figure 3 In the Doherty amplifier 300, the amplification path 420 can be connected to the main amplifier path (e.g., Figure 3 The main amplifier path 320 corresponds to the amplification path 421, and the amplification path 421 can correspond to the peaking amplifier path (e.g., Figure 3 The peaking amplifier path 321 corresponds to this.

[0106] Each path 420, 421 includes input leads 402, 403 (e.g., Figure 1 Input 102), output leads 404, 405 (e.g., Figure 1 Output 104), one or more transistor dies 440, 441 (e.g., Figure 1 transistor 140 or Figure 3 Amplifiers 340 and 341), input impedance matching circuits 410 and 411 (e.g., Figure 1 Input impedance matching circuit 110 or Figure 3 The input matching networks 310 and 311 (parts of the input impedance matching networks), and the output impedance matching circuits 450 and 451 (e.g., Figure 1 Output impedance matching circuit 150 or Figure 3 The output matching networks 350 and 351 (parts of the output matching networks), and the input-side baseband termination circuits 460 and 461 (e.g., Figure 1 , 3 Baseband termination circuits 160, 360, 361), and output-side baseband termination circuits 462, 463, 464, 465 (e.g., Figure 1 , 3 The baseband termination circuits 161, 162, 362, 363), and the input-side harmonic termination circuits 430, 431 (for example, Figure 1 , 3 Harmonic termination circuits 130, 330, 331), and output-side harmonic termination circuits 470, 471 (e.g., Figure 1 , 3 Harmonic termination circuits 170, 370, and 371.

[0107] Input and output leads 402-405 are mounted on the top surface of the isolation structure 408, on the opposite side of the central opening, and thus rise above and are electrically isolated from the top surface of the flange 406. Typically, the input and output leads 402-405 are oriented to allow bonding wires to be attached between the input and output leads 402-405 and components and elements within the central opening of the isolation structure 408.

[0108] Each transistor die 440, 441 includes an integrated power FET, wherein each FET has a control terminal (e.g., a gate) and two conductive terminals (e.g., a drain and a source). The control terminal of the FET within each transistor die 440, 441 is coupled to input leads 402, 403 via input impedance matching circuits 410, 411. Additionally, one conductive terminal (e.g., a drain) of the FET within each transistor die 440, 441 is coupled to output leads 404, 405 via output impedance matching circuits 450, 451. In an embodiment, the other conductive terminals (e.g., sources) of the FET within each transistor die 440, 441 are electrically coupled to a flange 406 (e.g., to ground) via dies 440, 441.

[0109] This document does not discuss in detail the embodiments of the input impedance matching circuits 410, 411, the baseband termination circuits 460, 461, and the harmonic termination circuits 430, 431. Rather, some components of these circuits can be implemented within the IPD components 480, 481. In simple terms, each input impedance matching circuit 410, 411 is coupled between the input leads 402, 403 and the control terminal of the FET within the transistor die 440, 441. Each input-side baseband termination circuit 460, 461 is coupled to nodes 418, 419 within the IPD components 480, 481 (e.g., with...). Figure 1 The conductive bonding pad corresponding to node 118 is between a ground reference (e.g., flange 406). Each harmonic termination circuit 430, 431 is coupled between the control terminal (e.g., gate) of the FET within transistor dies 440, 441 and the ground reference (e.g., flange 406).

[0110] Combining Figure 5 and Figure 6 The embodiments of the output impedance matching circuits 450 and 451, the baseband termination circuits 462 and 463, and the harmonic termination circuits 470 and 471 are described in more detail. Figure 5 and Figure 6 The components of these circuits 450, 451, 462, 463, 470, and 471 are shown in more detail. (As will be combined...) Figure 5 and Figure 6 As can be seen, some components of these circuits can be implemented within IPD components 482, 483. In simple terms, each output impedance matching circuit 450, 451 is coupled between the conductive terminal (e.g., drain) of the FET within transistor dies 440, 441 and the output leads 404, 405. Each baseband termination circuit 462, 463 is coupled between nodes 458, 459 within IPD components 482, 483 (e.g., using...). Figure 1Node 158 is located between a conductive bonding pad (in the form of an RF low-impedance point or quasi-RF cold spot node) and a ground reference (e.g., flange 406). Each harmonic termination circuit 470, 471 is coupled between a conductive terminal (e.g., drain) of the FET within transistor dies 440, 441 and a ground reference (e.g., flange 406).

[0111] exist Figure 4 In this example, device 400 includes two transistor dies 440 and 441 that operate substantially in parallel, but another semiconductor device may also include a single transistor die or more than two transistor dies. Additionally, device 400 includes two input-side IPD components 480 and 481 and two output-side IPD components 482 and 483 that also operate substantially in parallel. It should be understood that more or fewer IPD components 480-483 may also be implemented.

[0112] According to an embodiment, device 400 is incorporated into an air-cavity package, wherein transistor dies 440, 441, IPD assemblies 480-483, and various other components are located within a closed air-cavity. Essentially, the air-cavity is bounded by flange 406, isolation structure 408, and a cover (not shown) that covers and contacts isolation structure 408 and leads 402-405. Figure 4 In the diagram, the example perimeter of the cover is indicated by dashed box 409. In other embodiments, components of device 400 may be incorporated into an overmolded package (i.e., a package in which electrical components within the active device region are encapsulated by a non-conductive molding compound and portions of leads 402-405 are also surrounded by a molding compound). In an overmolded package, the isolation structure 408 may not be included.

[0113] Now for reference Figure 5 and Figure 6 It includes an enlarged view of portion 500 of device 400, which includes an output T-type matched impedance matching circuit 451 (e.g., Figure 1 Circuit 150), baseband termination circuit 463 (e.g., Figure 1 Baseband termination circuit 161) and harmonic termination circuit 471 (e.g., Figure 1 An embodiment of the harmonic termination circuit 170). More specifically, Figure 5 It is along amplifier path 421 Figure 4 A top view of the upper right output side portion 500 of the packaged RF power amplifier device 400. (See attached image.) Figure 5 The most clearly shown portion 500 includes a portion of the power transistor die 441, a portion of the output lead 405, and an output-side IPD assembly 483. For enhanced understanding, Figure 6 Including along line 6-6 according to the example embodiment Figure 5A cross-sectional side view of part 500 of the RF power amplifier device. It should be understood that although part 500 of device 400 is... Figure 5 and Figure 6 The details of the output circuit system of amplifier path 421 are described in detail, but the output circuit system of amplifier path 420 can be substantially the same as the output circuit system along amplifier path 421. More specifically, it can be as follows: Figure 5 and Figure 6 The output circuitry system for the carrier path and the peaking amplifier path is shown and implemented as described in detail below.

[0114] like Figure 6 As most clearly shown, the power transistor die 441 and IPD assembly 483 are coupled to the top surface of the conductive flange 406, and the output lead 405 is electrically isolated from the conductive flange 406 (e.g., using an isolation structure 408). The power transistor die 441 includes a transistor output terminal 544 (e.g., a conductive bonding pad) that is electrically connected within the power transistor die 441 to a first conductive terminal (e.g., a drain terminal) of a single-stage or final-stage FET 630 integrated within the die 441. As previously discussed, each FET 630 may include a III-V field-effect transistor (e.g., a HEMT), such as a GaN FET (or another type of III-V transistor, including GaAs FET, GaP FET, InP FET, or InSb FET). More specifically, each FET 630 may be integrally formed in and on a substrate semiconductor substrate 632 (e.g., a GaN substrate, a GaN-on-silicon substrate, a GaN-on-silicon substrate, etc.). A conductive connection between the first conductive terminal (e.g., the drain terminal) of the FET 630 and the output terminal 544 of the die 441 can be achieved through a multilayer structure 634. A conductive layer 636 on the bottom surface of the die 441 can provide a ground node (e.g., for the source terminal), which can be connected to the conductive layer 636 (and thus to the conductive flange 406) using a substrate via or a doped heat dissipation region.

[0115] IPD assembly 483 may also include a substrate semiconductor substrate 682 (e.g., a silicon substrate, silicon carbide substrate, GaN substrate, or another type of semiconductor substrate which may be referred to herein as an "IPD substrate") and a multilayer structure 684 having alternating dielectric and patterned conductive layers, wherein portions of the patterned conductive layers are electrically connected using conductive vias. Various electrical components, including output impedance matching circuit 451, in-package baseband termination circuit 461, and harmonic termination circuit 471, are integrally formed within and / or connected to IPD assembly 483, as will be discussed in more detail below. These electrical components may be electrically connected to conductive bonding pads (e.g., bonding pads 459, 573) on the top surface of IPD assembly 483, and may also be electrically connected to conductive flange 406 (e.g., to ground) using substrate vias to a conductive layer 686 on the bottom surface of IPD assembly 483.

[0116] In some embodiments, the output-side IPD component 483 more specifically includes an output impedance matching circuit (e.g., Figure 1 Circuit 150, Figure 3 Circuits 350, 351 or Figure 4 The first parallel capacitor 556 (e.g., in circuits 450, 451) is connected in parallel. Figure 1 Parallel capacitor 156), harmonic termination circuit (e.g., Figure 1 Circuit 170, Figure 3 Circuits 370, 371 or Figure 4 The second parallel capacitor 574 (e.g., in circuits 470, 471) is connected in parallel. Figure 1 The parallel capacitor 174), and the baseband termination circuit within the package (e.g., Figure 1 Circuit 161, Figures 2A-2F One of the circuits 200-205, Figure 3 Circuits 362, 363 or Figure 4 Components of circuits 462 and 463. In Figure 5 , 6 In embodiments, components including the baseband termination circuit in the IPD component 483 more specifically include the envelope resistor 564 (e.g., Figures 2A-2F Resistor 264), envelope inductor 562 (e.g., Figures 2A-2F Inductor 262), envelope capacitor 566 (e.g., Figures 2A-2F Capacitor 266) and bypass capacitor 578 (e.g., Figure 2F (Bypass capacitor 278). Each of these components will be discussed in more detail below.

[0117] First, the connection between the transistor die 441 and the output lead 405 via the output impedance matching circuit 451 will be described in more detail. More specifically, through an example of the output impedance matching circuit 451, the first conductive terminal (e.g., drain) of the FET 630 within the transistor die 441 is electrically coupled to the output lead 405 via the output terminal 544. For example, in an embodiment, the output impedance matching circuit 451 has a T-matching configuration, the output impedance matching circuit 451 including two inductor elements 552, 554 (e.g., ...) coupled in series. Figure 1 The inductor elements 152, 154), and the parallel capacitor 556 (e.g., Figure 1 Parallel capacitor 156). First inductor element 552 (e.g., Figure 1 The inductor element 152 can be implemented as a first set of bonding wires coupled between the output terminal 544 of the die 441 and the conductive bonding pad 459 on the top surface of the IPD assembly 483. The second inductor element 554 (e.g., Figure 1 The inductor element 154 can be implemented as a second set of bond wires coupled between the conductive bonding pad 459 and the output lead 405. To prevent... Figure 5 The diagram appears cluttered; only one bond wire from a set of bond wires including inductor element 552 is circled and labeled with reference numeral 552. It should be understood that inductor element 552 includes all bond wires coupled between output terminal 544 and bonding pad 459. According to embodiments, the inductance values ​​of the bond wire arrays 552 and 554 can each be in the range of approximately 20 pH to approximately 3 nH, but their inductance values ​​can also be lower or higher.

[0118] According to an embodiment, the parallel capacitor 556 of the output impedance matching circuit 451 can be implemented as a capacitor (or a group of parallel-coupled capacitors) integrally formed with the IPD substrate of the IPD component 483. For example, the parallel capacitor 556 can be implemented as one or more integrated MIM capacitors, which include a first conductive electrode and a second conductive electrode (formed by a patterned portion of the conductive layer of the multilayer structure 684) aligned with each other and electrically separated by the dielectric material of the multilayer structure 684. In an embodiment, the first electrode (or end) of each parallel capacitor 556 is electrically coupled to a conductive bonding pad 459 (and thus electrically coupled to bonding lines 552 and 554), and the second electrode (or end) of each parallel capacitor 556 is electrically coupled to a conductive flange (e.g., using a conductive substrate via extending through the semiconductor substrate 682). In a more specific embodiment, the first electrode of the parallel capacitor 556 is “directly connected” to the bonding pad 459, where “directly connected” means an electrical connection, possibly through one or more conductive traces and / or conductive vias, but without the intervention of any circuit elements (i.e., circuit elements with an inductance greater than the trace inductance, where “trace inductance” is an inductance less than about 100 pH). Because the parallel capacitor 556 and the bonding pad 459 are “directly connected,” and the bonding pad 459 also only has trace inductance, in this embodiment, the bonding lines 552, 554 and the parallel capacitor 556 can also be considered “directly connected.” In an alternative embodiment, the parallel capacitor 556 can be implemented using a discrete capacitor coupled to the top surface of the IPD assembly 483 or using another type of capacitor. According to embodiments, the capacitance value of the parallel capacitor 556 can be in the range of about 10 pF to about 140 pF, but the capacitance value can also be lower or higher.

[0119] Enter previous combination Figure 1 The T-type matching configuration formed by inductors 552, 554 and parallel capacitor 556, as discussed, can serve as a low-pass matching stage. Additionally, in embodiments, the conductive bonding pad 459 to which bonding wires 552 and 554 are coupled can be connected to an RF low-impedance point node or a "quasi-RF cold point node" (e.g., Figure 1 Corresponding to node 158). According to the embodiment, both the inner baseband termination circuit 463 and the outer baseband termination circuit 465 are electrically coupled to the conductive bonding pad 459 (i.e., coupled to the quasi-RF cold spot node).

[0120] In one embodiment, the in-package baseband termination circuit 463 is included in the IPD component 483. In various embodiments, the baseband termination circuit 463 may have any of a variety of configurations, such as, but not limited to, those described above. Figures 2A-2F One of the configurations shown. In Figure 4-6 In the illustrated embodiment, with Figure 2FCorresponding to the baseband termination circuit 205, the baseband termination circuit 463 includes an envelope resistor 564 (e.g., Figure 2F Resistor 264), envelope inductor 562 (e.g., Figure 2F The inductor 262), and electrically connected at node 459 (e.g., possibly corresponding to a low impedance point of the RF). Figure 1 , 2F Envelope capacitor 566 (e.g., between nodes 158, 218) and ground reference (e.g., flange 406) Figure 2F The capacitor 266) is connected in series. Additionally, the baseband termination circuit 463 includes a bypass capacitor 578 (e.g., capacitor 266) connected in parallel with the envelope inductor 562. Figure 2F Bypass capacitor 278). In Figure 4-6 In the embodiments, two instances of the parallel combination of envelope inductor 562 and bypass capacitor 578 are implemented on the other side of IPD component 483. More specifically, in the illustrated embodiment, the parallel combination of envelope inductor 562 and capacitor 578 is connected in parallel between envelope resistor 564 and envelope capacitor 566. In alternative embodiments, baseband termination circuit 463 may include only one instance of the combination of envelope inductor 562 and capacitor 578, or more than two instances of the combination of envelope inductor 562 and capacitor 578.

[0121] exist Figure 4-6 In one embodiment, the envelope resistor 564 is integrally formed as part of the IPD assembly 483. For example, each envelope resistor 564 may be a polysilicon resistor formed from a polysilicon layer on or within the multilayer structure 684, and electrically coupled between node 459 and the parallel combination of envelope inductor 562 and bypass capacitor 578. In other alternative embodiments, the envelope resistor 564 may be formed of tungsten silicide or another material, may be a thick-film resistor or a thin-film resistor, or may be a discrete component coupled to the top surface of the IPD assembly 483.

[0122] like Figure 5 , 6 As shown in the embodiments, the envelope inductor 562 can also be integrally formed as part of the IPD assembly 483. For example, each envelope inductor 562 can be provided by a patterned conductor formed from portions of one or more conductive layers of the multilayer structure 684, wherein a first end of the conductor is electrically coupled to an envelope resistor 564 and a second end of the conductor is electrically coupled to a first end of an envelope capacitor 566. In alternative embodiments, each envelope inductor 562 can be implemented as a plurality of bond wires, or as a spiral inductor (e.g., on or near the top surface of the IPD assembly 483), or as a discrete inductor coupled to the top surface of the IPD assembly 483.

[0123] In this embodiment, bypass capacitors 578 are coupled in parallel with each envelope inductor 562. Each of the bypass capacitors 578 may be a discrete capacitor, for example, connected (e.g., using solder, conductive epoxy, or other components) to the top surface of the IPD assembly 483. More specifically, a first terminal of each bypass capacitor 578 may be electrically coupled to an envelope resistor 564 and to a first terminal of an envelope inductor 562, and a second terminal of each bypass capacitor 578 may be connected to a second terminal of an envelope inductor 562 and to a first terminal of an envelope capacitor 566.

[0124] For example, each bypass capacitor 578 may be a multilayer capacitor (e.g., a multilayer ceramic capacitor) with parallel interleaved electrodes and wrap-around terminations. Alternatively, each bypass capacitor 578 may be part of a separate IPD (e.g., a MIM capacitor formed on a semiconductor substrate), or may be a capacitor integrally formed with the semiconductor substrate of the IPD assembly 483. Alternatively, each bypass capacitor 578 may be implemented as some other type of capacitor capable of providing the desired capacitance to the baseband termination circuit 463.

[0125] Envelope capacitor 566 is electrically coupled between a ground reference node (e.g., a conductive layer 686 at the bottom surface of each IPD component 483) and a parallel combination of envelope inductor 562 and bypass capacitor 578. For example, capacitor 566 may be a MIM capacitor integrally formed with the IPD substrate of IPD component 483. In some embodiments, capacitor 566 may be formed in a multilayer structure 684 integrally over semiconductor substrate 682, or capacitor 566 may have portions extending into or otherwise coupled to or in contact with semiconductor substrate 682. According to embodiments, capacitor 566 may be formed of a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The dielectric material of capacitor 566 may include one or more layers of polysilicon, various oxides, nitrides, or other suitable materials. In various embodiments, the first and second electrodes of capacitor 566 may include horizontal portions of a conductive layer (e.g., portions parallel to the top and bottom surfaces of IPD component 483) and / or vertical portions of interconnecting conductive layers (e.g., portions parallel to the sides of IPD component 483). Additionally, the first and second electrodes of capacitor 566 may be formed of a metal layer and / or a conductive semiconductor material (e.g., polysilicon). Alternatively, each enveloping capacitor 566 may be, for example, a discrete capacitor connected (e.g., using solder, conductive epoxy, or other components) to the top surface of IPD component 483. Although in Figure 6The document illustrates specific two-plate capacitor structures for capacitors 556, 574, and 566, but various other alternative capacitor structures can be utilized, as those skilled in the art will understand based on the description herein.

[0126] The outer baseband termination circuit 465 includes a combination of envelope inductance and envelope capacitance series coupled between the conductive bonding pad 458 (i.e., the quasi-RF cold spot node) and ground. The envelope inductance is formed by bonding wire 590 ( Figure 5 ) and additional lead 495 ( Figure 4 The series combination of ) provides the envelope capacitance, and the envelope capacitance is provided by discrete capacitor 499 ( Figure 4 Provided. More specifically, a first end of the bonding wire 590 may be connected to a conductive bonding pad 459, and a second end of the bonding wire 590 may be connected to a proximal end of an additional lead 495. A first end of an envelope capacitor 499 is coupled to a distal end of the additional lead 495, and a second end of the capacitor 499 is coupled to a ground reference point of the PCB, to which the amplifier device 400 is coupled.

[0127] As previously discussed, the harmonic termination circuit 471 is also connected between the first conductive terminal (e.g., drain) of the FET 630 within the transistor die 441 and a ground reference (e.g., to the conductive layer 686 on the bottom surface of the IPD assembly 483). Figure 5 and Figure 6 In the embodiments, the harmonic termination circuit 471 includes a parallel inductor element 572 (e.g., Figure 1 Parallel inductor 172) and parallel capacitor 574 (e.g., Figure 1 The parallel capacitor 174) is connected in series. The parallel inductor element 572 can be implemented as a set of bonding wires, wherein the first end of the bonding wire is connected to the output terminal 544 of the die 441 (and thus to the first conductive terminal of the FET 630), and the second end of the bonding wire is connected to the conductive bonding pad 573 exposed on the top surface of the IPD assembly 483. In order to prevent Figure 5 The diagram appears cluttered; only two bond wires from a set of bond wires including inductor element 572 are circled and labeled with reference numeral 572. It should be understood that inductor element 572 includes all bond wires coupled between output terminal 544 and bond pad 573. Within IPD assembly 483, bond pad 573 is electrically connected to a first terminal of parallel capacitor 574, and a second terminal of parallel capacitor 574 is electrically connected (e.g., using a substrate via) to a ground reference (e.g., to a conductive layer 686 on the bottom surface of IPD assembly 483).

[0128] According to an embodiment, the parallel capacitor 574 of the harmonic termination circuit 471 can be implemented as a capacitor integrally formed with the IPD substrate of the IPD assembly 483. For example, the parallel capacitor 574 can be implemented as an integrated MIM capacitor, which includes a first conductive electrode and a second conductive electrode (formed by a patterned portion of the conductive layer of the multilayer structure 684) aligned with each other and electrically separated by the dielectric material of the multilayer structure 684. In an embodiment, the first electrode (or end) of the parallel capacitor 574 is electrically coupled to a conductive bonding pad 573, and the second electrode (or end) of the parallel capacitor 574 is electrically coupled to a conductive flange (e.g., using a substrate via). In a more specific embodiment, the first electrode of the parallel capacitor 574 is "directly connected" (as previously defined) to the bonding pad 573. Because the parallel capacitor 574 and the bonding pad 573 are "directly connected," and the bonding pad 573 only has trace inductance, in an embodiment, the bonding line 572 and the parallel capacitor 574 can also be considered as "directly connected." In an alternative embodiment, the parallel capacitor 574 can be implemented using a discrete capacitor coupled to the top surface of the IPD component 483 or using another type of capacitor.

[0129] According to an embodiment, the harmonic termination circuit 471 acts as a low-impedance path for signal energy to ground at harmonic frequencies (e.g., the second harmonic of the fundamental operating frequency of device 400). More specifically, the component values ​​for the parallel inductor 572 and the parallel capacitor 574 are selected so that the series combination of the parallel inductor 572 and the parallel capacitor 574 resonates at or near the second harmonic frequency. For example, the fundamental operating frequency of device 400 can be in the range of about 800 MHz to about 6.0 GHz, and therefore the second harmonic frequency (and the resonant frequency of circuit 471) can be in the range of about 1.6 GHz to about 12.0 GHz. According to an embodiment, the inductance value of inductor 572 can be in the range of about 20 pF to about 3 nH, and the capacitance value of capacitor 574 can be in the range of about 1 pF to about 100 pF, but the values ​​of these components can also be outside these ranges. Figure 1 As discussed, for example, at an operating fundamental frequency of 2.0 GHz (with a second harmonic of 4.0 GHz), the inductance of inductor 572 can be approximately 120-140 pF, and the capacitance of capacitor 574 can be approximately 11-12 pF. However, the designed inductance and / or capacitance values ​​may be affected by the mutual coupling between the bond wires used to implement inductors 552 and 572.

[0130] More specifically, and according to embodiments, the bond wires corresponding to inductor elements 552 and 572 are physically configured and arranged relative to each other to exhibit predictable mutual coupling between these adjacent bond wire groups during operation. More specifically, the bond wire profiles (e.g., the height and shape of each group of bond wires 552 and 572) and their proximity to other bond wires produce predictable mutual coupling during operation, such that the effective inductance value of inductor elements 552 and 572 during operation differs from the self-inductance value of inductor elements 552 and 572 when each inductance is acquired in an isolated manner (i.e., the inductance is not affected by mutual inductance from other inductors). For example, at an operating center frequency of 2.0 GHz, the mutual coupling between inductor elements 552 and 572 can range from about 1 pH to about 150 pH (e.g., about 69 pH).

[0131] According to an embodiment, when compared to a conventional device, the inductance provided between the parallel capacitors within the transistor output and the output impedance matching circuit may be significantly reduced in the embodiment including the harmonic termination circuit 471. More specifically, during operation of device 400, at the fundamental operating frequency of device 400, the harmonic termination circuit 471 essentially functions as a capacitor, with a capacitance value roughly equivalent to the effective capacitance of the series-coupled inductors / capacitors 572 / 574. Because this parallel capacitance is coupled in parallel with the drain-source capacitance between the transistor output and the ground reference, the equivalent parallel capacitance from the combination of inductors / capacitors 572 / 574 effectively increases the drain-source capacitance of the FET 630 within transistor die 441. In some embodiments, the capacitance value of the parallel capacitor 574 effectively increases the drain-source capacitance of the FET 630 to which it is connected by at least 10%. Due to this effective increase in drain-source capacitance, the inductance between the transistor output and the parallel capacitor in the output impedance matching circuit (e.g., capacitor 556 in circuit 451) may decrease compared to conventional circuitry. Therefore, while conventional circuitry might require an additional inductor to provide a greater inductance than that provided by the bond wire connecting the transistor die to the parallel capacitor in the output impedance matching circuitry, this additional inductor is not included in circuit 451. Instead, in circuit 451, the bond wire 552 can be directly connected (as previously defined) to the parallel capacitor 556.

[0132] Figure 4-6An embodiment of an RF amplifier device is illustrated, comprising input and output leads coupled to a substrate (i.e., with intervening electrical isolation), and a transistor die also coupled to the substrate between the input and output leads. Such RF amplifier devices may be particularly suitable for high-power amplification. Based on the description herein, those skilled in the art will understand that various embodiments can also be implemented using different forms of packaging or construction. For example, one or more amplification paths including embodiments of the subject matter of this invention may be coupled to a substrate such as a PCB, a leadless type package (e.g., a square flat no-lead (QFN) package), or another type of package. In such embodiments, conductive pads or other input / output (I / O) structures may be used to implement the input and output of the amplification path. Such implementations may be particularly suitable for smaller power amplification systems, such as those including relatively low-power Dougherty amplifiers, where the main amplification path and peaking amplification path (including bare transistor dies, IPDs, bias circuits, etc.), power dividers, delay and impedance inversion elements, combiners, and other components may be coupled to the substrate. It should be understood that embodiments of the subject matter of this invention are not limited to the embodiments shown.

[0133] Figure 7 This is according to various example embodiments for manufacturing packaged RF power amplifier devices (e.g., Figure 4 A flowchart of a method for a packaged RF power amplifier device (400) is provided, wherein the packaged RF power amplifier device includes an input impedance matching circuit and an output impedance matching circuit, a baseband termination circuit and a harmonic termination circuit (e.g., Figures 2A-2F Embodiments of circuits 200-205, 410, 411, 430, 431, 450, 451, 460-463, 470, 471 (4). In blocks 702-704, the method can begin by forming one or more IPD components. More specifically, in block 702, one or more input IPDs and output IPDs (e.g., Figure 4-6 According to embodiments, each input IPD (e.g., IPD 480, 481) may include components of an impedance matching circuit, a baseband termination circuit, and a harmonic termination circuit. According to embodiments, each output IPD (e.g., IPD 482, 483) may also include components of an impedance matching circuit, a baseband termination circuit, and a harmonic termination circuit. For example, each output IPD may include one or more integrated parallel capacitors (e.g., Figure 5 , 6 Capacitors 556, 566, 574), and one or more envelope inductor elements (e.g., Figure 5 , 6 The inductor element 562), and one or more envelope resistors (e.g., Figure 5 , 6(Resistor 564). In addition to the passive components forming each IPD, forming each IPD also includes forming various conductive features (e.g., conductive layers and vias) that facilitate electrical connections between various components of each circuit. For example, forming an IPD may also include forming various accessible connection nodes (e.g., ...) on the surface of each IPD substrate. Figure 4-6 Nodes 459 and 573). As previously discussed, connection nodes may include conductive bonding pads that can receive inductive elements (e.g., Figure 5 , 6 The bonding lines 552, 554, and 572 are attached. Additionally, in block 704, various circuit elements (e.g., Figure 5 , 6 The discrete components corresponding to the bypass capacitor 578 can be coupled to conductors exposed on the surface of each IPD to form one or more IPD assemblies.

[0134] In box 706, for the air cavity embodiment, the isolation structure (e.g., Figure 4 An isolation structure 408 is coupled to a device substrate (e.g., flange 406). Additionally, one or more active devices (e.g., transistors 440, 441) and IPD components (e.g., IPD components 480-483) are coupled to portions of the top surface of the substrate exposed through openings in the isolation structure. Leads (e.g., input and output leads 402-405, and additional leads 492-495, if included) are coupled to the top surface of the isolation structure. For overmolded (e.g., encapsulated) device embodiments, the isolation structure may not be included, and the substrate and leads may form a portion of a lead frame.

[0135] In box 708, the input lead, transistor, IPD assembly, and output lead are electrically coupled together. For example, various device components and elements can be electrically connected using bonding wires, as previously discussed. For instance, some bonding wires are connected to inductive components of the input matching circuit or output matching circuit (e.g., Figure 4-6 Bonding wires 552, 554) and inductor components of harmonic termination circuits (e.g., Figure 4-6 The bonding line 572 corresponds to this. Finally, in block 710, the device is covered (e.g., for air cavity encapsulation) or encapsulated (e.g., using a molding compound for overmolding). The device can then be incorporated into a larger electrical system (e.g., a Dougherty amplifier or other type of electrical system).

[0136] Embodiments of the RF amplifier and the packaged RF amplifier device each include an amplification path with a transistor die and an output-side impedance matching circuit with a T-type matching circuit topology. The output-side impedance matching circuit includes a first inductor (e.g., a first bond wire) connected between the transistor output and a quasi-RF cold spot node, a second inductor (e.g., a second bond wire) connected between the quasi-RF cold spot node and the output of the amplification path, and a first capacitor connected between the quasi-RF cold spot node and a ground reference node. The RF amplifier and device also include a baseband termination circuit connected to the quasi-RF cold spot node, the baseband termination circuit including an envelope resistor, an envelope inductor, and an envelope capacitor series coupled between the quasi-RF cold spot node and the ground reference node.

[0137] The foregoing specific embodiments are merely illustrative in nature and are not intended to limit the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, one should not be bound by any expressed or implied theory presented in prior art, background art, or specific embodiments.

[0138] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in the embodiments of the subject matter. Furthermore, certain terms may be used herein for reference only, and therefore these terms are not intended to be limiting, and unless the context explicitly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply order or sequence.

[0139] As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes can be implemented with a single physical element (and although received or output at a common node, two or more signals can still be multiplexed, modulated, or otherwise distinguished).

[0140] The above description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly engaged to (or directly communicates with) another element, and not necessarily mechanically. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly communicates with) another element electrically or otherwise, and not necessarily mechanically. Therefore, while the schematic diagrams shown depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0141] While at least one exemplary embodiment has been presented in the preceding details, it should be understood that numerous variations exist. It should also be understood that the exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the preceding details will provide a convenient guide for those skilled in the art to implement the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing this patent application.

Claims

1. A radio frequency (RF) amplifier having a first amplification path, characterized in that, include: A transistor die, the transistor die having a transistor and a transistor output terminal; An output-side impedance matching circuit, wherein the output-side impedance matching circuit has a T-type matching circuit topology coupled between the transistor output terminal and the output of the first amplification path, wherein the output-side impedance matching circuit includes: A first inductor element is connected between the transistor output terminal and the RF low-impedance point node. A second inductor element is connected between the RF low-impedance point node and the output of the first amplification path. A first capacitor is connected between the RF low-impedance point node and the ground reference node. as well as A baseband termination circuit connected to the RF low-impedance point node, wherein the baseband termination circuit includes multiple components, wherein the multiple components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the RF low-impedance point node and the ground reference node.

2. The RF amplifier according to claim 1, characterized in that: The first inductor element includes a first plurality of bonding wires; and The second inductor element includes a second plurality of bonding wires.

3. The RF amplifier according to claim 1 or 2, characterized in that, In addition, including: The output-side harmonic termination circuit includes a third inductor and a second capacitor connected in series between the transistor output terminal and the ground reference node, and the output-side harmonic termination circuit resonates at the second harmonic frequency of the fundamental operating frequency of the RF amplifier.

4. The RF amplifier according to claim 1, characterized in that, The transistor is a gallium nitride transistor with a drain-source capacitance of less than 0.2 picofarads per watt.

5. The RF amplifier according to claim 1, characterized in that, The RF amplifier is a Dougherty power amplifier, and the RF amplifier further includes: Second amplification path; A power divider having a power divider input configured to receive an RF signal, a first power divider output coupled to an input of a first amplification path, and a second power divider output coupled to an input of a second amplification path, wherein the power divider is configured to split the RF signal into a first RF signal provided to the first amplification path via the first power divider output and a second RF signal provided to the second amplification path via the second power divider output; and A combining node configured to receive and combine amplified RF signals generated by the first amplification path and the second amplification path.

6. A packaged radio frequency (RF) amplifier device, characterized in that, include: device substrate; A first input lead is coupled to the device substrate; A first output lead is coupled to the device substrate; A first transistor die coupled to the device substrate, wherein the first transistor die includes a first transistor, a transistor input coupled to the first input lead, and a transistor output coupled to the first output lead, and wherein the drain-source capacitance of the first transistor is less than 0.2 picofarads per watt. A first output-side impedance matching circuit, the first output-side impedance matching circuit having a T-type matching circuit topology coupled between the output terminal of the first transistor and the first output lead, wherein the first output-side impedance matching circuit includes: A first inductor element is connected between the transistor output terminal and the first RF low-impedance point node, wherein the first inductor element includes a first plurality of bonding wires. A second inductor element is connected between the first RF low-impedance node and the first output lead, wherein the second inductor element includes a second plurality of bonding wires. The first capacitor is connected between the first RF low impedance point node and the ground reference node; as well as A first baseband termination circuit is connected to the first RF low-impedance point node, wherein the first baseband termination circuit includes a first plurality of components, wherein the first plurality of components include a first envelope resistor, a first envelope inductor, and a first envelope capacitor coupled in series between the first RF low-impedance point node and the ground reference node.

7. The packaged RF amplifier device according to claim 6, characterized in that, The transistor is a gallium nitride transistor.

8. The packaged RF amplifier device according to claim 6 or 7, characterized in that, In addition, including: An integrated passive device is coupled to the device substrate and located between the first transistor die and the first output lead, wherein the integrated passive device includes the first RF low impedance node, the first capacitor, the envelope resistor, the envelope inductor, and the envelope capacitor.

9. The packaged RF amplifier device according to claim 8, characterized in that, In addition, including: An output-side harmonic termination circuit includes a third inductor and a second capacitor connected in series between the transistor output terminal and the ground reference node, wherein the third inductor includes a third plurality of bond wires, and the output-side harmonic termination circuit resonates at the second harmonic frequency of the fundamental operating frequency of the RF amplifier.

10. A method for manufacturing an RF amplifier device, characterized in that, The method includes the following steps: Couple the input leads to the device substrate; Couple the output lead to the device substrate; A transistor die is coupled to the device substrate between the input lead and the output lead, wherein the transistor die includes a transistor and a transistor output terminal, and wherein the drain-source capacitance of the transistor is less than 0.2 picofarads per watt. An integrated passive device is coupled to the device substrate between the transistor die and the input lead, wherein the integrated passive device includes an RF low-impedance node, a ground reference node, a first capacitor coupled between the RF low-impedance node and the ground node, and a baseband termination circuit, wherein the baseband termination circuit includes an envelope resistor, an envelope capacitor, and an envelope inductor coupled in series between the RF low-impedance node and the ground reference node; and An output-side impedance matching circuit with a T-type matching circuit topology is created between the transistor output terminal and the output lead, wherein the T-type matching circuit topology includes the first capacitor, and the output-side impedance matching circuit is created by coupling a first inductor element between the transistor output terminal and the RF low-impedance point node and coupling a second inductor element between the RF low-impedance point node and the output lead, wherein the first inductor element includes a first plurality of bond wires, and wherein the second inductor element includes a second plurality of bond wires.

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