Electronic circuit for generating high impedance load and related method

Abstract

An electronic circuit for presenting a high-impedance load between a load point and a reference point includes a capacitive element disposed between a first node and a reference point, a first element connected in parallel with the capacitive element, a first switching element disposed in series between the first node and a voltage source point, a second switching element disposed between the first node and a second node, a second element connected between the second switching element, the load point, and the reference point, and timing control logic for implementing three phases. During a charging phase, the first switching element is closed, and the second switching element charges a node voltage at the first node. During a discharging phase, the first switching element is opened, and the second switching element is also opened, allowing the capacitive element to discharge through the first element. During a transfer phase, the second switching element is closed to connect the first node and the second node, after which the second switching element is opened and the second element is biased to present a high-impedance load.

Description

Technical Field

[0001] The present invention relates to an electronic circuit which creates a high impedance load, for example for interfacing with a sensor circuit, and to a method of operating such an electronic circuit, in particular an integrated semiconductor circuit, to create a high impedance load. Background Art

[0002] As part of a semiconductor integrated circuit, it may be necessary to create an on-chip impedance of very high resistance while trying to minimize the surface area of the silicon (e.g., to maintain cost-effectiveness). Such high-resistance elements can be used in analog filtering, biasing, and grounding circuits, and as termination elements in high-impedance input stages.

[0003] An example of this is in sensor applications, where the sensor element that converts a physical parameter into an electrical signal typically has a very high output impedance. To preserve the typically small signal as best as possible, the input stage of the circuit connected to such a sensor must present a very high, yet finite, input impedance to prevent charge accumulation while also not causing unnecessary loading effects on the sensor. These charge accumulations and loading effects can be detrimental to correct sensor operation. A practical example is the thermoceramic element used in passive infrared (PIR) sensors. The same is generally true for thermopiles, biosensors, gas detectors, and various other sensors.

[0004] Important requirements for high-impedance termination components that form part of the sensor input stage may include:

[0005] A predictable, well-established operating point—its current and voltage—and a method for establishing and controlling that operating point;

[0006] Predictable temperature stability within the generally applicable temperature range;

[0007] Repeatability (die-to-die and wafer-to-wafer);

[0008] Relatively insensitive to process variations;

[0009] Will not negatively impact the analog inputs of sensors and sensing circuits;

[0010] The equipment and its operation should be sufficiently robust to be implemented within standard manufacturing processes; and

[0011] Should be implemented using a reasonable amount of silicon area to remain cost-effective.

[0012] For electronic circuits, especially integrated circuits, there are several solutions to consider. On-chip options include:

[0013] Use low-doped thin-layer resistors, such as high-resistance polysilicon resistors, but these present the following challenges:

[0014] oThey are closely related to process parameters and temperature;

[0015] o Larger areas result in larger parasitic capacitances, which degrade the already small signals typically produced by components such as sensors; and

[0016] oThe large area required for implementation is very expensive;

[0017] Use a continuous current mirror that relies on a bias resistor as the reference current, but these are not suitable for presenting the very high impedances required to draw the picoamps of current; or

[0018] Use a switched-capacitor circuit to limit the current drawn from the sensor while preventing charge buildup.

[0019] A more suitable approach might be to use the subthreshold characteristics of MOSFET (metal oxide semiconductor field effect transistor) devices, or exploit the exponential current-voltage relationship of diodes or BJTs (bipolar junction transistors), thereby enabling circuit elements to act as very high impedance devices without sacrificing the silicon space typically required to implement large resistances using passive components. However, this is complex, so accurately and repeatably biasing these components is not common.

[0020] Applicants desire a high impedance electronic circuit that addresses or ameliorates at least some of these problems.

[0021] In the prior art work of Hellen [1], it is shown that Figure 1 The circuit shown, including the capacitor and the diode, has a time-varying voltage behavior as shown in equation (1),

[0022]

[0023] In t and v D (t) is independent of the initial condition voltage of C and is an exponential function mainly determined by the capacitance C, where m is a correction factor related to the diode characteristics of the pn junction, I0 is the diode reverse saturation current, and V T = kT / q is the thermal voltage. This is shown in the discharge of the capacitor through the diode. Figure 1 Shown in. Summary of the Invention

[0024] Therefore, the present invention provides an electronic circuit for presenting a high impedance load between a load point and a reference point (further referred to as a high impedance electronic circuit), the high impedance electronic circuit comprising:

[0025] a capacitive element (C) disposed between the first node (node A) and a reference point;

[0026] a first element having a nonlinear voltage-current relationship (D1) connected in parallel with the capacitive element (C) between the first node (A) and a reference point;

[0027] a first switching element (S1) arranged in series between the first node (A) and a voltage source point;

[0028] a second switching element (S2) provided between the first node (A) and a second node (node B); and

[0029] connecting a second element having a nonlinear voltage-current relationship (D2) between the second switching element (S2), the load point, and the reference point; and

[0030] Timing control logic for controlling a first switching element (S1) and a second switching element (S2) to bias the second element (D2) and operate in at least three phases including: a charging phase in which the first switching element (S1) is closed and the second switching element (S2) is open for a charging duration (T CH ) so that the capacitor element (C) can charge the node voltage v at the first node (A) D (t) to a sufficient or predetermined initial voltage threshold V i ;

[0031] Discharge phase, wherein the first switching element (S1) is turned off and the second switching element (S2) is turned off for a discharge duration (T DCH ) so that the capacitor element (C) discharges through the first element (D1), thereby causing the current through the first element (D1) to reach a sufficient or predetermined bias current (I BIAS ) and / or node voltage v D (t=T CH +T DCH ) is equal to a sufficient or predetermined bias voltage (V BIAS );and

[0032] Transfer phase, in which the second switching element (S2) is closed for a transfer duration (T XFR ) to connect the first node (A) and the second node (B), thereby increasing the bias voltage (V BIAS ) is applied or transferred to a contact of a second element (D2) connected to a second node (B) to adjust the current according to a bias voltage (V BIAS ) biasing the second element (D2);

[0033] The timing control logic is used to turn off the second switching element (S2) after the transfer phase, and the second element (D2) is biased to present a high impedance load between the load point and the reference point.

[0034] These phases can be repeated, reordered, or extended as needed.

[0035] Strictly speaking, "transfer of voltage" may include transfer of charge to establish a specific voltage, but for simplicity of explanation, this is referred to as "transfer of voltage."

[0036] The capacitive element (C) may be a capacitor. The capacitor may be a transistor-implemented capacitor. The capacitive element (C) may be a parasitic capacitor present in another component of the electronic circuit. The capacitive element may be a non-transistor current-carrying element.

[0037] The first and second elements (D1, D2) may be diodes or transistors. If the first element (D1) is a transistor, it may be a diode-connected transistor. If the first and second elements (D1, D2) are transistors, they may be MOSFETs or BJTs.

[0038] The first and second elements (D1, D2) may have the same voltage-current relationship, or may have related (eg, proportional or ratiometric) voltage-current relationships.

[0039] The numerical definition of "high impedance" varies depending on the application. Therefore, it can be difficult to define an exact range of values. An important application of the present invention may be in processing signals generated by sensors (referred to as sensor signals). In this case, one definition of "high impedance" may be in terms of the effect of not degrading the sensor signal to an unusable level.

[0040] Another way to define "high impedance" can be to look at conventional impedance elements that can be replaced by electronic circuits according to the present invention. Such conventional impedance elements can be on-chip resistors, such as polysilicon resistors, which are currently typically in the range of 10-100 kΩ and can be as high as 100-1000 kΩ. Therefore, for the purposes of this specification, a high impedance can be at least 1 MΩ, can be at least 10 MΩ, can be at least 100 MΩ, and can be at least 1 GΩ.

[0041] A high impedance load may present only a resistive load, or may present a combination of resistive and reactive loads.

[0042] Transfer stage duration T XFRIt can be calculated to be long enough to allow for efficient voltage transfer between the first node (A) and the second node (B), but not so long as to unreasonably affect the discharge of the capacitive element (C) or the bias point of the second element (D2), which is typically a transistor. The transfer duration T can be calculated as XFR , to transfer the voltage v between the first node (A) and the second node (B) using the second switching element (S2) D (t), and keeps the capacitive element (C) charged to ensure that the bias voltage on the second node (B) of the second element (D2) remains above the ground potential (0V).

[0043] For the sake of brevity, the switching elements may be referred to as switches only.During the transfer phase, the first switch (S1) may remain open.

[0044] The timing control logic can be used to, depending on the exact implementation of the timing signal, start the next charging phase at T IDLE The idle phase can be optional and T IDLE Can be zero. The timing control logic can be used to periodically or intermittently repeat the charging phase, the discharging phase and the transfer phase. The timing control logic can be used to determine the timing of the charge phase, the discharge phase and the transfer phase in a manner that depends on the load voltage v L The charging phase, discharging phase and transfer phase are repeated at a frequency of 100 Hz. The timing control logic can be used to maintain the ratio v L / i L constant to establish a constant real impedance.

[0045] The voltage source point can be a power supply point or a power rail.

[0046] There may be a resistive element connected in series with the first switching element (S1). The resistive element may limit the current inrush into the capacitive element (C).

[0047] The electronic circuit may be an integrated circuit, or may be implemented by an integrated circuit, or may form part of an integrated circuit.

[0048] The present invention extends to a method of generating a high impedance load (further referred to as a high impedance electronic circuit) between a load point and a reference point, the method comprising:

[0049] A high-impedance electronic circuit is provided, the high-impedance electronic circuit comprising:

[0050] Disposing a capacitive element (C) between the first node (node A) and a reference point;

[0051] a first element having a nonlinear voltage-current relationship (D1) connected in parallel with the capacitive element (C) between the first node (A) and a reference point;

[0052] a first switching element (S1) arranged in series between the first node (A) and a voltage source point;

[0053] a second switching element (S2) provided between the first node (A) and a second node (node B); and

[0054] a second element having a nonlinear voltage-current relationship (D2) connected between the second switching element (S2), the load point, and the reference point; and

[0055] Timing control logic for activating the first switch (S1) and the second switch (S2) to bias the second element (D2) and operate in at least three stages,

[0056] The method further includes:

[0057] When the first switch (S1) is closed and the second switch (S2) is open for a charging duration (T CH ) charging phase, the capacitor element (C) is charged to the node voltage v at the first node (A) D (t) Charge to a sufficient or predefined initial voltage threshold V i ; When the first switch (S1) is disconnected and the second switch (S2) is disconnected for a discharge duration (T DCH ) discharge phase, the capacitor element (C) is discharged through the first element (D1), so that the current through the first element (D1) reaches a sufficient or predetermined bias current (I BIAS ) and / or node voltage v D (t=T CH +T DCH ) is equal to a sufficient or predetermined bias voltage (V BIAS );

[0058] After the second switch (S2) is closed for a transfer duration (T XFR ) to connect the first node (A) and the second node (B) during the transfer phase, the bias voltage (V BIAS ) is transmitted to the contact of the second element (D2) connected to the second node (B) to adjust the current according to the bias voltage (V BIAS ) biasing the second element (D2); and

[0059] After the transfer phase, the second switch (S2) is opened and the second element (D2) is biased to present a high impedance load between the load point and the reference point.

[0060] The method defined above may be implemented by an electronic circuit defined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The invention will now be further described, by way of example, with reference to the accompanying illustrated drawings.

[0062] In the attached figure:

[0063] Figure 1 A schematic circuit diagram of the prior art circuit of reference [1] is shown, illustrating the discharge of a capacitor through a diode;

[0064] Figure 2 Shows the Figure 1 The diode in the circuit is replaced by a transistor.

[0065] Figure 3 shows a schematic circuit diagram of an electronic circuit for generating a high impedance load according to the present invention;

[0066] Figure 4 Shown Figure 3 Diagrams of the various operating stages of electronic circuits and the timing signals on switches;

[0067] Figure 5 a schematic circuit diagram showing another embodiment of an electronic circuit configured to generate a high impedance load according to the present invention; and

[0068] Figure 6 A schematic circuit diagram of another embodiment of an electronic circuit configured to generate a high impedance load according to the present invention is shown. DETAILED DESCRIPTION

[0069] The invention will first be described with reference to some enabling theory and then will be described with reference to practical implementations of that theory.

[0070] The present invention proposes that the aforementioned properties of nonlinear elements (e.g., MOS transistors, diodes, and BJTs) can be used to create high-impedance termination elements. One aspect of the invention relates to a method by which such high-impedance elements can be biased in an appropriate operating region to produce desired results.

[0071] The present invention is based on equation (1) and Figure 1 Based on the phenomena explained in the previous section, it is noted that if the diode current i D (t) Rewrite the calculation as follows

[0072]

[0073] The current is much larger than I0. This is important because it turns out that for a capacitor discharging through a forward-biased diode, the diode current depends only on the total node capacitance C and the time t.

[0074] Through analysis Figure 2 The circuit in Figure 2 can be extended to MOS transistors, where Figure 1The diode is replaced by a diode-connected NMOS (n-type MOS) transistor.

[0075] It can be seen that when the term t / C and the node voltage V D When (t) (from equation (1)) is appropriately constrained, the current through the MOS transistor follows the expression

[0076]

[0077] Where n is the technical constant, V T is the thermal voltage, V t is the threshold voltage of the MOS transistor, and C represents the node capacitance.

[0078] To generalize these two cases, equations (2) and (3) can be rewritten and interpreted as

[0079]

[0080] Where k is a technology constant, C is the capacitance being discharged, and t is time. The resulting equation (4) yields an unexpected insight: simply by choosing C and an appropriate t, the discharge current, and thus the operating point of the device or circuit, can be set.

[0081] The present invention discloses that the above characteristic resulting from equation (4) can be used in a unique way to establish a well-controlled bias point for the device to act as a high impedance element.

[0082] This can be illustrated using a typical field-effect transistor (e.g., an NMOS transistor), which is commonly used by circuit designers implementing designs using CMOS manufacturing processes. The device has four terminals, including a gate (G), a drain (D), a source (S), and a bulk (B). In strong inversion operation, the gate-source voltage V GS >V t , while in subthreshold operation, V GS <V t It is known that in the subthreshold region, the output impedance of the device between the drain-source terminals is significantly higher than that in strong inversion.

[0083] Reference again Figure 2 In the circuit, the capacitor can be used with an initial voltage V at t = 0. i At the beginning, the initial voltage V i Much higher than the device threshold voltage V t Since V GS =V DS >V t , so the device will start a strong reversal in a very short time; after the device is discharged, V GS Down to Vt In a typical 0.35μm CMOS process, given a reasonable value of C, this happens in a few hundred nanoseconds or less. Once V GS Lower than V t , the transistor will enter its subthreshold operating region and the discharge rate will be significantly slower. From equation (3), summarized in equation (4), the magnitude of the current depends only on time t, node capacitance C and technology or device constant k.

[0084] By using equation (4) and selecting the target MOS element bias current I BIAS (It can be considered as i D (t=T CH +T DCH )), the required discharge time T can be determined DCH , therefore, i D (t=T CH +T DCH )=I BIAS , and conversely, it is possible to determine the predefined T DCH The C value is assumed to be the initial voltage on the node, so that v D (t=T CH )=V i .

[0085] Since the discharge device is used to establish I BIAS , so the same device itself cannot be used as a high impedance circuit element. However, with the current i D (t=T CH +T DCH ) The gate-source voltage V GS The bias point of the transistor can now be replicated by "copying" the gate voltage to another second MOS transistor. If the second transistor is of the same size and operates with the same conditions at its terminals, the second transistor can be used as the intended high-impedance circuit element by considering the behavior between its drain and source terminals. Since subthreshold operation is known from Gray [2],

[0086]

[0087] This shows that for V DS >>V T , for a given V GS , the output current remains largely constant, and the small-signal output impedance is shown, excluding drain-induced barrier lowering and body effects.

[0088]

[0089] For a constant VGS , although it is nonlinear, it can achieve very large impedance (for small signals). Alternatively, this approach can be used where the termination elements are used to produce a small but predictable and well-controlled current.

[0090] Similar behavior can be expected from a bipolar junction transistor (BJT). C =βi B The forward current gain term β and note that the total current is i D =(β+1)i B , Equation (2) can be made applicable to BJT, and the small signal output impedance of BJT can be approximated as

[0091]

[0092] Among them, V A is the early voltage associated with a particular device. For the desired I using equation (2) and appropriate choices of C and t C When the value is very low, r CE It could get really big.

[0093] Turning now to the practical or technical implementation of the above theory. Figure 3 An exemplary electronic circuit 100 according to the present invention is shown for generating a high impedance load. The electronic circuit 100 can be configured according to the conclusions drawn from equation (4) to implement a high impedance element or load. In the figures, the reference point is shown as a ground point.

[0094] This example shows an electronic circuit 100 using an active element (D1) with a nonlinear voltage-current relationship in the form of an NMOS transistor, but other implementations are possible (see below). The electronic circuit 100 may comprise three conceptual parts, each serving a specific purpose during a respective phase of operation.

[0095] 1. The first part (part 1) of the electronic circuit 100 generates a voltage signal which can be used to adjust the load impedance Δv according to the desired load impedance Δv. L / Δi L Or load current bias point i L Biasing the transistor in the subthreshold or low current region.

[0096] 2. The second portion (portion 2) of the electronic circuit 100 transfers the bias point voltage signal on node A of the first portion of the circuit to node B of the third portion.

[0097] 3. The third part (part 3) of the electronic circuit 100 includes a component that uses the transferred voltage signal to bias the transistor to establish a voltage from v L (i.e. the voltage at the load point) and iL Section 3, after the transfer phase, presents a high impedance load, such as R in circuit 110. EFF Indicated.

[0098] Sections 1 and 2 may be considered to be bias sections of circuit 100 , while the third section is a load presentation section.

[0099] During the design process, the circuit designer must use equations (4) and / or (6) to select the target current set point I for transistor D1. BIAS or the required small signal impedance, and then derive the capacitance C and the discharge duration T DCH The value of .

[0100] The first part of the electronic circuit 100 comprises three main elements:

[0101] · Elements that can be active elements, e.g. Figure 3 The transistor or diode D1 in the circuit is n-type or p-type depending on the specific circuit implementation;

[0102] Capacitor (C), usually Figure 3 The capacitor and parasitic capacitance at node A, and

[0103] Switching elements, Figure 3 S1 in the circuit connects and disconnects the capacitor element from the power supply, thereby setting or establishing the initial voltage at the node.

[0104] Figure 4 As shown above, Figure 3 Figure 200 shows different stages of circuit operation where D2 acts as a high impedance element as described above. The timing signals for closing S1 and S2 are also indicated.

[0105] Figure 4 The four stages of circuit operation can be explained as:

[0106] 1. Phase 1 (Charging): During Phase 1, switch S1 connects the charge storage node to a charging source, typically a power rail, possibly through a resistive element to limit the inrush current to the storage element, while switch S2 is open. The duration of the charging phase is T CH should be long enough to ensure that the node voltage v D (t) reaches a sufficiently high level to make equation (2) valid for a diode or bipolar transistor, or equation (3) valid for a diode-connected MOS device. Although a small current will flow through the discharge element, Figure 3 The NMOS transistor D1 in the circuit is switched off, but it should be negligible compared to the charging current flowing through S1. Once a sufficient initial voltage v D(t=T CH )=V i , switch S1 is open, where T CH The duration of the charging phase is marked and the next phase begins.

[0107] 2. Phase 2 (discharge) During phase 2, both S1 and S2 are disconnected, v D (t=T CH )=V ii is the initial voltage on node A at the beginning of the discharge phase. The first part of the circuit now follows the general behavior of equation (4), and the charge stored on node A passes through the element ( Figure 3 The diode connected to NMOSD1 in the middle is discharged. According to the parameters selected by the designer, the duration of this phase should be T DCH During this period, the current through D1 will reach I BIAS The target value of the node voltage v D (t=T CH +T DCH )=V BIAS .

[0108] 3. Phase 3 (Transfer): At the end of the discharge phase, switch S2 is closed to transfer node AV BIAS The voltage on S2 is transferred to node B. Ideally, the voltage on node B is now equal to the voltage on node A and will continue to be so after S2 opens, although this may require several repetitions. Figure 3 In the example above, there is now V on the gate of D2. BIAS , thereby biasing the device according to equations (5) and (6) to act as the intended high impedance circuit element, for example, between its drain and source. With S2 closed, T XFR The duration should be long enough to achieve an effective voltage transfer between nodes A and B, but not so long as to unduly affect the discharge circuit and bias points. The conversion phase ends when switch S2 opens. The total node capacitance at node B should be high enough to maintain this voltage and suppress discharge (and voltage drop / change) during the time when S2 is open.

[0109] 4. Phase 4 (idle phase): After the bias point is transferred to the load device D2, the system can enter the optional idle phase 4 before starting the next charging phase, which lasts for T IDLE , depends on the specific implementation of the timing signal. In most cases, T IDLE May be zero. This phase may be optional.

[0110] 5. Repeat the process of establishing and maintaining bias: In order to establish and maintain the bias point, the above three stages need to be repeated regularly or intermittently to maintain accurate VBIAS , especially when using bipolar devices with non-negligible base currents that affect the set point on node B. In addition, due to the capacitance ratio of node A to node B, when first establishing the bias point, it may take a long time before settling at the target bias voltage V BIAS Before reaching or near the node B, node B may need to transfer charge from node A for multiple cycles, with the initial condition of each repeated cycle being v D (t=T CH )=V i , so v is allowed D (t=T CH +T DCH )=V BIAS After a number of cycles it settles down so that a stable high impedance operating point can be applied to D2. Timing control logic can be used to repeat the charge phase, discharge phase and transfer.

[0111] like Figure 5-6 As shown, other variations of the electronic device 100 are possible. Figure 3 A first variant of the circuit shown is, according to the invention, Figure 5 The electronic device 300 shown in FIG, may implement two NMOS transistors using bipolar junction devices (BJTs) and adapting the circuit to necessary changes in behavior such as the persistence of base current. Such adaptation may require adding capacitance to node B in addition to any existing parasitic capacitance to sustain these currents while maintaining the node voltage.

[0112] and Figure 3 A second variation of the circuit shown is that the transistors, MOS or BJT devices or a combination thereof can be implemented as n-type or p-type devices by adjusting the circuit and associated polarity accordingly.

[0113] Although the circuit operation method described in the previous section focuses on using the discharge time T in explaining equation (4) DCH As the determining factor, it should be noted that equation (4) can also be modified to express I BIAS , that is, in terms of frequency, at t = T CH +T DCH The bias current through D1 is

[0114] I BIAS (f) = kCf#(8)

[0115] In each cycle, the voltage at node A starts at a repeatable initial voltage V i , and when the idle stage is omitted, f = 1 / (T CH +T DCH +T XFR ). The frequency f can be varied by varying the respective duration of each phase accordingly.

[0116] Figure 3 The circuit of and similar circuits in general can be adjusted so that device D1 is geometrically different from device D2 so that the resulting current through D2 is a scaled version of the current through D1. For example, assuming that Figure 3 In the example, the (W / L) ratio of D2 to D1 is 2, so for a given V BIAS , D2 conducts about twice the current of D1 - that is, i L =2I BIAS In this way, the device geometry can be adapted to compensate or fine-tune the current of the high-impedance terminal element D2 for different applications. For BJTs, the emitter area can be scaled to the same effect.

[0117] Although D2 presents a very high small signal impedance for a given operating bias point, this impedance is nonlinear because the voltage v on the drain (field effect transistor) or collector (bipolar transistor) of D2 L In another variation, as Figure 6 The diagram 400 shown in FIG. 4 can be adapted in an absolute manner to T DCH To dynamically compensate for this. For a fixed repetition period T TOTAL =T CH +T DCH +T XFR +T IDLE =1 / f, the switching signals of S1 and S2 can be adjusted appropriately to adapt to the isolation T DCH The frequency f can also be adjusted dynamically, implicitly changing T DCH To adapt to v L changes, thereby adapting to Figure 3 R shown EFF , in order to maintain R EFF The value is relatively constant.

[0118] Applicants believe that the exemplary present invention is advantageous because circuits 100, 300, 400 can be manufactured using cost-effective, industry-standard manufacturing processes, such as silicon-based CMOS (complementary metal oxide semiconductor). Circuits 100, 300, 400 can be used in readout circuits for passive infrared (PIR) sensors and other sensors.

[0119] The invention described provides a new way to create a high impedance termination element that meets the requirements of such circuits 100, 300, 400 as part of a sensor circuit front end. As an additional advantage, the described circuits 100, 300, 400 and methods enable a highly dynamic and adaptable solution that can form part of a modern high performance integrated circuit in a cost-effective manner.

[0120] References

[0121] [1] Hellen, E.H., “Verifying the diode-capacitor circuit voltage delay,” American Journal of Physics, Vol. 71, No. 8, July 10, 2003.

[0122] [2] Grey, P.R. et al., “Analysis and design of analog integrated circuits”, 4th edition, John Wiley and Sons, Inc., 2001.

Claims

1. An electronic circuit for presenting a high impedance load between a load point and a reference point, further referred to as a high impedance electronic circuit, the high impedance electronic circuit comprising: a capacitive element (C) disposed between the first node (node A) and a reference point; a first element (D1) having a nonlinear voltage-current relationship connected in parallel with the capacitive element (C) between the first node (A) and a reference point; a first switching element (S1) arranged in series between the first node (A) and a voltage source point; a second switching element (S2) disposed between the first node (A) and a second node (node B); and connecting a second element (D2) having a nonlinear voltage-current relationship between the second switching element (S2), the load point and the reference point; and Timing control logic for controlling a first switching element (S1) and a second switching element (S2) to bias the second element (D2) to operate in at least three phases including: A charging phase in which the first switching element (S1) is closed and the second switching element (S2) is open for a charging duration T CH , so that the capacitor element (C) can charge the node voltage v at the first node (A) D (t) to the predetermined initial voltage threshold V i ; A discharge phase in which the first switching element (S1) is switched off and the second switching element (S2) is switched off for a discharge duration T DCH , so that the capacitive element (C) discharges through the first element (D1), thereby causing the current through the first element (D1) to reach a sufficient or predetermined bias current (I BIAS ) and / or node voltage v D (t) is equal to a sufficient or predetermined bias voltage (V BIAS ), where t=T CH +T DCH ;and Transfer phase, in which the second switching element (S2) is closed for a transfer duration (T XFR ) to connect the first node (A) and the second node (B), thereby increasing the bias voltage (V BIAS ) is applied or transferred to the contact of the second element (D2) connected to the second node (B) to adjust the current according to the bias voltage (V BIAS ) bias the second element (D2); The timing control logic is used to turn off the second switching element (S2) after the transfer phase, and the second element (D2) is biased to present a high impedance load between the load point and the reference point.

2. The electronic circuit according to claim 1, wherein The first and second elements (D1, D2) are diodes or transistors.

3. The electronic circuit according to claim 2, wherein The first element (D1) is a diode-connected transistor, and the second element (D2) is a transistor.

4. The electronic circuit according to claim 3, wherein: The first and second elements (D1, D2) are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors); or The first and second elements (D1, D2) are BJTs (bipolar junction transistors); or The first element (D1) is a BJT, and the second element (D2) is a MOSFET; or The first element (D1) is a diode, and the second element (D2) is a BJT.

5. The electronic circuit according to claim 1, wherein The first and second components (D1, D2) have an associated voltage-current relationship.

6. The electronic circuit according to claim 1, wherein Calculate the transfer duration (T XFR ), to transfer the voltage v between the first node (A) and the second node (B) using the second switching element (S2) D (t), and to keep the capacitive element (C) charged to ensure that the bias point voltage on the second node (B) of the second element (D2) remains above the ground potential (0V).

7. The electronic circuit according to claim 1, wherein The timing control logic is used to periodically or intermittently repeat the charging phase, the discharging phase and the transfer phase.

8. The electronic circuit according to claim 7, wherein The timing control logic is used to depend on the load voltage v L The charging phase, the discharging phase and the transfer phase are repeated at a frequency of 9. The electronic circuit according to claim 8, wherein The timing control logic is used to maintain the ratio v L / i L Constant to establish a constant real impedance.

10. The electronic circuit of claim 1, which is part of, or forms part of, an integrated circuit (IC).

11. A method for generating a high impedance load between a load point and a reference point, the method comprising: A high-impedance electronic circuit is provided, the high-impedance electronic circuit comprising: a capacitive element (C) disposed between the first node (node A) and a reference point; a first element (D1) having a nonlinear voltage-current relationship connected in parallel with the capacitive element (C) between the first node (A) and a reference point; a first switching element (S1) arranged in series between the first node (A) and a voltage source point; a second switching element (S2) provided between the first node (A) and a second node (node B); and a second element (D2) having a nonlinear voltage-current relationship connected between the second switching element (S2), the load point, and the reference point; and timing control logic for activating the first switching element (S1) and the second switching element (S2) to bias the second element (D2) in at least three stages, The method further includes: When the first switching element (S1) is closed and the second switching element (S2) is open for a charging duration T CH During the charging phase, the capacitor element (C) is charged to the node voltage v at the first node (A). D (t) Charge to a sufficient or predefined initial voltage threshold V i ; After the first switching element (S1) is turned off and the second switching element (S2) is turned off for a discharge duration T DCH In the discharge phase, the capacitor element (C) is discharged through the first element (D1), so that the current through the first element (D1) reaches a sufficient or predetermined bias current (I BIAS ) and / or node voltage v D (t) is equal to a sufficient or predetermined bias voltage (V BIAS ), where t=T CH +T DCH ; After the second switching element (S2) is closed for a transfer duration (T XFR ) to connect the first node (A) and the second node (B) during the transfer phase, the bias voltage (V BIAS ) is transferred to the contact of the second element (D2) connected to the second node (B) to adjust the current according to the bias voltage (V BIAS ) biasing the second element (D2); and After the transfer phase the second switching element (S2) is opened, said second element (D2) being biased to present a high impedance load between the load point and the reference point.

12. The method according to claim 11, wherein The charging phase, the discharging phase, and the transferring phase are repeated periodically or intermittently.

13. The method according to claim 12, wherein: Depends on the load voltage v L The charging phase, the discharging phase and the transfer phase are repeated at a frequency of 14. The method according to claim 13, comprising maintaining the ratio v L / i L Constant to establish a constant real impedance.

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