Film stack simplification for high aspect ratio patterning and vertical scaling

Abstract

Provided herein is a method for forming a patterned multilayer stack including a metal-containing layer. The method involves using a non-metallic material containing silicon in a multilayer stack including a sacrificial layer to be removed later and replaced with a metal, while maintaining an etch contrast to pattern the multilayer stack and selectively removing the sacrificial layer before depositing the metal. The method involves using silicon oxycarbide instead of silicon nitride, and using a sacrificial non-metallic material instead of a metal-containing layer to manufacture a multilayer stack, patterning the multilayer stack, selectively removing the sacrificial non-metallic material to leave a space in the stack, and depositing a metal-containing material into the space. The sacrificial non-metallic material includes silicon nitride and doped polysilicon, such as boron-doped silicon.

Description

[0001] Incorporated by Reference

[0002] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] Semiconductor device manufacturing involves the manufacture of a variety of devices such as flash memory. As devices shrink, structures for manufacturing complex, efficient, and multiple memory cells are used to maximize the density of memory cells in memory devices. 3D NAND technology addresses the challenges associated with two-dimensional NAND technology by stacking memory cells vertically in multiple layers. In addition, manufacturing involves increasingly complex multi-layer stacks that include combinations of conductive and dielectric materials.

[0004] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed. Summary of the invention

[0005] Methods and devices for manufacturing semiconductor devices are provided herein. One aspect relates to a method, comprising: providing a semiconductor substrate; depositing a metal-free multilayer stack having at least three different materials, at least one of the three different materials being a sacrificial layer; etching a groove or a via in the metal-free multilayer stack having the at least three different materials; after etching the groove or the via, selectively etching the sacrificial layer relative to other materials of the metal-free multilayer stack to form at least one space between multiple layers of the metal-free multilayer stack; and depositing metal in the at least one space to form a metal-containing multilayer stack having a groove or a via etched therein.

[0006] In various embodiments, the metal-free multilayer stack includes three different materials.

[0007] In various embodiments, the metal-free multilayer stack includes four different materials.

[0008] The method may further include recessing a dielectric material in a sidewall of the trench or via in the metal-free multilayer stack after etching the trench or via and before selectively etching the sacrificial layer.

[0009] In various embodiments, the sacrificial layer is polysilicon or silicon nitride.

[0010] In various embodiments, the at least three different materials include one or more of silicon oxide, undoped polysilicon, doped polysilicon, silicon nitride, oxygen-doped silicon carbide, and nitrogen-doped silicon carbide.

[0011] In various embodiments, the metal is tungsten or molybdenum.

[0012] The method may also include depositing a metal-containing liner in the at least one space before depositing the metal, thereby depositing the metal on the metal-containing liner in the at least one space. In some embodiments, the metal-containing liner is selected from the group consisting of titanium nitride, aluminum oxide, and tungsten carbonitride.

[0013] In various embodiments, the metal-free multilayer stack includes alternating layers of silicon oxycarbide, nitrogen-doped silicon carbide, and silicon oxide.

[0014] In various embodiments, a metal-free multilayer stack includes a sacrificial dielectric and alternating layers of silicon oxycarbide and silicon oxide.

[0015] In various embodiments, the at least three different materials include silicon nitride, silicon oxide, nitrogen-doped silicon carbide, and oxygen-doped silicon carbide.

[0016] In various embodiments, the at least three different materials include polysilicon, silicon oxide, nitrogen-doped silicon carbide, and oxygen-doped silicon carbide.

[0017] In various embodiments, the at least three different materials include polysilicon, silicon nitride, silicon oxide, and oxygen-doped silicon carbide.

[0018] In some embodiments, the sacrificial layer is silicon nitride. In some embodiments, the sacrificial layer can be polysilicon, or doped polysilicon.

[0019] In various embodiments, the layers of the metal-free multilayer stack are deposited by atomic layer deposition.

[0020] In some embodiments, layers of the metal-free multilayer stack are deposited in different chambers of a single tool.

[0021] In various embodiments, the layers of the metal-free multilayer stack are deposited without breaking vacuum.

[0022] In some embodiments, the layers of the metal-free multilayer stack are deposited in four different tools.

[0023] In various embodiments, at least two layers of the metal-free multilayer stack are deposited in a first tool, and at least two other layers of the metal-free multilayer stack are deposited in a second tool.

[0024] In some embodiments, the layers of the metal-free multilayer stack are deposited by chemical vapor deposition.

[0025] In various embodiments, the layers of the metal-free multilayer stack are deposited by plasma enhanced chemical vapor deposition.

[0026] In some embodiments, the layers of the metal-free multilayer stack are deposited by physical vapor deposition.

[0027] In various embodiments, the method further includes: recessing one of the at least three different materials after etching the trench or through-hole to form a recessed area of ​​the through-hole; depositing a dielectric material or a semiconductor material into the trench or through-hole; etching back the dielectric material or semiconductor material in the trench or through-hole to form a smooth sidewall, thereby leaving the dielectric material or semiconductor material in the recessed area; and depositing a gate material into the trench or through-hole before selectively etching the sacrificial silicon nitride.

[0028] Another aspect relates to a method comprising: providing a semiconductor substrate; depositing a multilayer stack of alternating sacrificial silicon nitride layers and non-oxide layers; etching trenches or vias in the multilayer stack of alternating sacrificial silicon nitride and non-oxide layers; after etching the trenches, selectively etching the sacrificial silicon nitride to form spaces between the non-oxide layers; and depositing metal in the spaces to form a substrate including trenches etched in the alternating metal and non-oxide layers and at least one dielectric barrier layer.

[0029] In various embodiments, the at least one dielectric barrier layer includes oxygen-doped silicon carbide. For example, the oxygen concentration in the oxygen-doped silicon carbide can be between about 1% and about 65% atomic.

[0030] In various embodiments, the non-oxide layer includes one or more of a second silicon nitride, silicon oxycarbide, and polysilicon having a wet etch contrast relative to the sacrificial silicon nitride.

[0031] In some embodiments, the polysilicon is doped. For example, the polysilicon can be doped with a dopant selected from the group consisting of boron, phosphorus, and arsenic.

[0032] In various embodiments, the metal includes tungsten.

[0033] In various embodiments, the metal includes molybdenum.

[0034] In various embodiments, the sacrificial silicon nitride has a wet etch contrast of at least about 10:1 in 100:1 dilute hydrofluoric or phosphoric acid relative to the non-oxide layer and the at least one dielectric barrier layer.

[0035] In various embodiments, the method further includes: recessing a layer in the multilayer stack after etching the groove or through-hole to form a recessed region of the through-hole; depositing a dielectric material or a semiconductor material into the groove or through-hole after recessing the layer; etching back the dielectric material or semiconductor material in the groove or through-hole to form a smooth sidewall, thereby leaving the dielectric material or semiconductor material in the recessed region; and depositing a gate material into the groove or through-hole before selectively etching the sacrificial silicon nitride.

[0036] These and other aspects are further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a process flow diagram of operations performed according to a method of forming a 3D NAND structure.

[0038] Figure 2 , 3 , 4A, 4B, 5A, 5B, and 6-8 are schematic diagrams of exemplary cross-sections of multilayer stacks during operation of various processes.

[0039] Figures 9A-9D Schematic diagrams showing exemplary cross-sections of a multilayer stack during various processing operations.

[0040] Fig.10 is a process flow diagram of operations performed in accordance with certain disclosed embodiments.

[0041] Fig.11A is a process flow diagram of operations performed in accordance with certain disclosed embodiments.

[0042] Fig. 11B is a process flow diagram of exemplary operations performed in accordance with certain disclosed embodiments.

[0043] Figures 12A-12M Schematic diagrams showing exemplary cross-sections of a multilayer stack during various operations performed in accordance with certain disclosed embodiments.

[0044] Fig.13 Block diagrams showing various reactor components configured for implementing the techniques are depicted in accordance with certain disclosed embodiments.

[0045] Fig.14 Embodiments of a multi-site cluster tool are depicted in accordance with disclosed embodiments.

[0046] Fig.15 Another example of a multi-station processing tool is schematically shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be implemented without some or all of these specific details. In other instances, well-known processing operations are not described in detail to avoid unnecessarily obscuring the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

[0048] Semiconductor device processing involves the formation of multilayer stacks that can be used to manufacture a variety of three-dimensional devices (e.g., 3D NAND structures). Some stacks include multiple alternating layers of dielectric materials and conductive materials, each of which can be about 10 nm or thicker. One way to form such a stack involves depositing multiple alternating layers of oxide materials and nitride materials (ONON multilayer deposition), then selectively removing the nitride material and backfilling the metal into the space previously occupied by the nitride material. This method can be used to manufacture 3D NAND structures.

[0049] Another approach is to directly pattern a stack of multiple alternating oxide layers and polysilicon (or "polycrystalline" as used elsewhere in this article) layers, where the polysilicon is retained as a conductive layer. In some cases, the stack may include a metal, such as a tungsten material. However, it may be challenging to use some techniques to form a stack including a dielectric, polysilicon, and a metal. In particular, it may be difficult to etch trenches and to recess the sidewalls of the oxide material to form, for example, a floating gate. Etching of the metal inside the stack itself may also result in a high risk of metal residues on the resulting device, and may also undesirably change the profile of the etched pattern. In some cases, the manufacture of 3-terminal devices includes a variety of different materials, but cannot be manufactured using existing technologies. In some cases, manufacturing 2-terminal capacitors in 3D NAND structures is challenging because separate source / drain regions are to be manufactured on each device.

[0050] Figure 1 A process flow diagram of operations performed according to a method of forming a 3D NAND structure is shown. In operation 182, a substrate is provided. In various embodiments, the substrate is a semiconductor substrate. The substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, which includes a wafer having one or more layers of material, such as a wafer having a dielectric material, a conductive material, or a semiconductive material deposited thereon. An exemplary substrate 100 is provided as Figure 2 Schematic diagram in. Return Figure 1 In operation 184, a film stack of alternating oxide films and nitride films is deposited on the substrate. In various embodiments, the deposited oxide layers are silicon oxide layers. In various embodiments, the deposited nitride layers are silicon nitride layers. Each oxide and nitride layer is deposited to about the same thickness, such as a thickness between about 10 nm and about 100 nm in some embodiments, or about The oxide layer may be deposited at a deposition temperature between about room temperature and about 600° C. It should be understood that “deposition temperature” (or “substrate temperature”) as used herein means the temperature set for a susceptor holding a substrate during deposition.

[0051] The oxide and nitride layers used to form the alternating oxide and nitride film stack may be deposited using any suitable technique, such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or sputtering. In various embodiments, the oxide and nitride layers are deposited by PECVD.

[0052] The film stack may include alternating oxide and nitride layers between 48 and 512 layers, whereby each oxide layer or nitride layer constitutes one layer. In some embodiments, depending on the application, the film stack may include alternating oxide and nitride layers of less than 48 layers or greater than 512 layers. The film stack including alternating oxide and nitride layers may be referred to as an ONON stack. Although the film stack described relates to alternating oxide layers and nitride layers, it should be understood that additional layers may also be included in the stack, and in addition, other materials may be used for alternating layers that are not oxide layers and are not nitride layers. For example, in some cases, a silicon germanium layer may be used instead of a nitride layer or a silicon nitride layer. Other additional layers that may be located on the stack include silicon-containing layers, germanium-containing layers, or both. Exemplary silicon-containing layers include doped and undoped silicon carbide layers, doped and undoped polysilicon layers, amorphous silicon layers, doped and undoped silicon oxide layers, and doped and undoped silicon nitride layers. Dopants may include non-metallic dopants. For example, an exemplary doped silicon carbide layer is oxygen-doped silicon carbide. In another example, an exemplary doped silicon carbide layer is nitrogen-doped silicon carbide.

[0053] Figure 3 An example schematic diagram of a substrate 100 is shown, wherein alternating oxide (101) and nitride (102) films are deposited on the substrate 100. Note that although Figure 3The illustrated structure shows oxide deposited first, then nitride, oxide, nitride, etc., but nitride may be deposited first, then oxide, nitride, oxide, etc.

[0054] After depositing the ONON stack, a channel can be etched in the substrate ( Figure 3 ). Subsequently, refer to Figure 1 , in operation 186, a stair-like pattern is formed on the substrate. The "stair-like pattern" referred to herein includes two or more steps, each step including an oxide and a nitride layer. It should be understood that the top layer of each set of oxide and nitride layers can be either an oxide or a nitride used to form the stair-like steps. In various embodiments, the stair-like pattern includes 24 to 256 steps. A variety of patterning techniques can be used to form the stair-like pattern. For example, one technique can include depositing a sacrificial layer above the substrate and covering various areas of the substrate to etch each set of oxide and nitride layers to form the steps.

[0055] Figure 4A An example of a substrate 100 is provided that includes a stepped pattern of oxide (111) and nitride (112) layers with a hard mask 110 over the topmost nitride layer. Figure 4A Four steps of the staircase pattern are shown, but it should be understood that the staircase pattern can have 24 to 256 steps. Each step includes a nitride and an oxide layer, and as shown in FIG. Figure 4A The distance d shown in can be between about 150 nm and about 1000 nm, such as about 500 nm.The area of ​​each step that extends outward from the edge of the step above it can be referred to as a "pad" having a particular distance d.

[0056] For purposes of discussion, the following discussion of substrates and subsequent schematic diagrams will include Figure 4B Half side view 199 shown.

[0057] exist Figure 1 In operation 188, an oxide is deposited over the substrate. In various embodiments, the oxide can have the same composition as the oxide deposited in the layer of the ONON stack. In various embodiments, the oxide deposited on the substrate is deposited at a deposition temperature different from the deposition temperature used for the oxide layer deposited in the ONON stack. The deposition temperature can be between room temperature and about 600° C. After depositing the oxide, a vertical slit 135 can then be etched in the substrate. Figure 5A An exemplary substrate 100 is shown including an ONON step, a hard mask 110, and an oxide 122 deposited over the substrate. Figure 5B A side view of the substrate 100 after etching the vertical slits 130 is shown.

[0058] return Figure 1 In operation 190, the nitride is selectively etched relative to the oxide on the substrate. The etching can be performed using a selective dry etching process, such as by exposing the substrate to any one or more of the following gases: chlorine (Cl2), oxygen (O2), nitrous oxide (N2O), tetrafluoromethane (CF4), sulfur tetrafluoride (SF4), carbon dioxide (CO2), fluoromethane (CH3F), nitrogen trifluoride (NF3), nitrogen (N2), hydrogen (H2), ammonia (NH3), methane (CH4), sulfur hexafluoride (SF6), argon (Ar), carbonyl sulfide (COS), carbon disulfide (CS2), hydrogen sulfide (H2S), and nitric oxide (NO). This operation removes the nitride layer from the ONON stack, causing the etching species to flow into the vertical slits and selectively etch the nitride. It should be understood that selective etching involves etching the first material at a faster rate than etching the second material. For example, selectively etching the nitride relative to the oxide means etching the nitride at a faster rate than etching the oxide. A wet etching process is used to selectively etch the nitride, for example by exposing the substrate to phosphoric acid (H3PO4) and / or dilute hydrofluoric acid ("DHF") or a mixture of these solutions. Figure 6 A side view of a cross section of the substrate is shown, wherein gaps 132 are formed by selectively etching the nitride.

[0059] return Figure 1 In operation 192, tungsten is deposited into the gap of the substrate to form a tungsten wordline. Tungsten can be deposited by any suitable technique such as ALD, CVD, PEALD, and / or PECVD. In some embodiments, a barrier layer and / or a tungsten nucleation layer is deposited prior to depositing the bulk tungsten. Exemplary barrier layers include titanium nitride, aluminum oxide, and tungsten carbonitride. Figure 7 A schematic diagram of a cross section of a substrate is shown from a side view, with tungsten 140 deposited in the gap where nitride previously existed. As shown, metal deposition results in deposition on the sidewalls of oxide 111. Although tungsten is described herein, other metals may be used, such as molybdenum.

[0060] return Figure 1 In operation 194, vias are formed by vertically etching the substrate, which may include both etching oxide deposited above the steps and etching metal to remove metal from the sidewalls of the oxide in the alternating layers. The oxide may be etched by dry etching using exposure to one or more of the following gases: O2, Ar, C4F6, C4F8, SF6, CHF3, and CF4. Figure 8 An exemplary substrate 100 is shown comprising an ONON stack in a stair-like pattern with vias 135 etched into the stack.

[0061] exist Figure 1 In operation 196, tungsten may be deposited in the vias to form interconnects to the tungsten word lines. The depth of the vias varies and may have a depth between about 1 micron and about 12 microns. Shallow vias may be defined as having a depth less than 3.0 microns, such as a depth between about 1.5 microns and 3.0 microns. Deep vias may have a depth greater than 3.0 microns. The critical dimension of the vias formed in the oxide may be between about 50 nm and about 500 nm. The vias may be etched using a dry etching process, which may involve a masking operation to pattern the oxide. In various embodiments, the patterning process may include Figure 1 For example, after depositing oxide over the substrate in operation 188, the trench may be etched to form a channel. The channel may be filled with a charge trapping layer and a large trench or slit may be etched before selectively etching the nitride in operation 190. Tungsten may be removed from the sidewalls before etching the oxide vertically and after depositing the tungsten wordline.

[0062] Figure 1 An example is provided where tungsten backfill is deposited by CVD for ONON gate replacement. This technique can be used to form an ONON or OPOP integration scheme of a memory cell stack, for example in some embodiments where polysilicon is retained as the gate of an OPOP scheme, both ONON and OPOP schemes can be etched in this way without much risk. However, applying this type of technique to complex multi-layer stacks presents challenges.

[0063] For example, the layers may include silicon oxide, tungsten, polysilicon, and another dielectric in the final structure. This may involve recessing the sidewalls of the dielectric, similar to the floating gate formation in the OPOP scheme. Although one approach is to etch a film stack containing silicon oxide, silicon nitride, polysilicon, tungsten, and titanium nitride, and then recess the silicon oxide or silicon nitride (e.g., relative to the wet etch contrast between silicon oxide, silicon nitride, polysilicon, and tungsten) using the wet etch contrast between silicon oxide, silicon nitride, polysilicon, and tungsten, the dielectric may be recessed. Figures 9A-9D However, such processes present some challenges.

[0064] Figures 9A-9D Another set of schematics for processing different multilayer stacks is shown. Fig.9A The silicon nitride layer 902 includes a tungsten layer 940 (with an optional titanium nitride liner (not shown) between the tungsten layer 940 and the silicon nitride layer 902), a polysilicon layer 900 (with an optional titanium nitride layer (also not shown) between the tungsten layer 940 and the polysilicon layer 900), a silicon oxide layer 901, and a silicon nitride layer 902. Fig. 9BIn the etching of the via or trench 950, it involves etching all the above-mentioned materials in the stack, including the metal, which may result in unwanted metal residues on the substrate. The silicon oxide 901 may be further recessed to form a structure for the substrate. Fig. 9C In the embodiment, polysilicon 900 is filled to fill the concave region adjacent to silicon oxide 901. Fig.9D In the embodiment, the polysilicon 900 is further etched to form a through hole again, thus including the following steps: Fig.9D The structure shown in .

[0065] However, this process involves etching tungsten and / or metals and other silicon-containing materials, which can be challenging. First, etching a multilayer stack of dielectrics and metals while maintaining a vertical profile is very difficult, in part due to varying etch rates and etching chemistries for different materials. This can lead to feature collapse and degradation of feature profiles. Second, metal residues left in high aspect ratio structures are difficult to clean, and metal residues can affect the integrity of the device. Third, the deposition of tungsten films can result in the formation of a rough surface and can cause device performance control issues.

[0066] Methods and apparatus are presented herein for forming and etching multilayer film stacks to perform high aspect ratio patterning and vertical and three-dimensional scaling. The multilayer film stack may include repeated sets of layers in which one layer is deposited on top of another layer. Each set of layers may include at least three different materials. In some embodiments, each set includes four different materials. For the same set of layers, one may be stacked on top of another multiple times, such as about 5 times, or such as about 10 times, or such as about 20 times, or more.

[0067] A high aspect ratio via or trench patterned using certain disclosed embodiments can have an aspect ratio greater than about 5:1, or between about 5:1 and about 20:1, or between about 25:1 and about 35:1, or greater. Some embodiments involve replacing the metal in a film stack with another dielectric that has a dry etching behavior similar to that of the other material, but exhibits a strong wet etching contrast relative to the other material. For example, in 100:1 dilute hydrofluoric acid or phosphoric acid, the wet etching contrast of the dielectric replacing the metal relative to the other material can be about 10:1. The disclosed embodiments can be performed to form a structure having both metal and dielectric materials without the risk of causing metal residues on the substrate. In various embodiments, etching of the substrate having both metal and dielectric materials is avoided because the metal is deposited after the patterned structure. That is, in various embodiments, a metal-free film stack is etched and processed in the absence of metal so that a dielectric material is deposited and positioned in an area where metal will later be deposited, and after the desired structure is formed, the dielectric material is removed, and metal is subsequently deposited in its place to form the desired pattern or device. Certain disclosed embodiments relate to process integration, which is: forming a structure including a dielectric material and a sacrificial layer in an area (where metal will later be deposited in the area), etching the sacrificial layer after patterning to leave a space in the structure, and depositing metal into the space. The disclosed embodiments may be advantageous for performing sidewall recesses to form specific devices such as floating gates. Certain disclosed embodiments also enable better profile control.

[0068] Certain disclosed embodiments can be used to abandon etching tungsten of a multilayer stack by using a silicon nitride sacrificial material to etch a pattern, then selectively removing the silicon nitride to create a space using the etching contrast between the silicon nitride and other dielectric materials, and then depositing the metal into the space. In the case where the multilayer stack also includes other non-sacrificial silicon nitride layers, these materials can be replaced with oxygen-doped silicon carbide, which can have an etching contrast when selectively removing silicon nitride and can provide properties similar to silicon nitride to perform the function of the specific layer. The dielectric layer (e.g., SiOC) described herein will have a wet etching contrast during the removal of SiN and the recessing of SiO2, but will have similar dry etching behavior during high aspect ratio patterning. The dielectric can also be other materials that provide similar performance. Such materials can be polysilicon with different dopants, or SiN deposited under different process conditions that are very different from the wet etching rate of sacrificial SiN, or nitrogen-doped SiC (SiNC).

[0069] The disclosed embodiments may be used in a variety of applications, including for the fabrication of 3D-NAND devices, floating gates, etc. An example of a specific stack that may be formed using certain disclosed embodiments is described herein; it should be understood that other materials and other patterning schemes and stacks may be formed using certain disclosed embodiments, and the disclosed embodiments are not limited to this example.

[0070] In certain disclosed embodiments, a stack is deposited using silicon nitride as a sacrificial layer, and a metal may be deposited later at the sacrificial layer so that the sacrificial layer may be removed after an etching operation to form a space for the metal material, and the metal may be backfilled into the space. Although tungsten is described herein as an exemplary metal, it is understood that other metals, such as molybdenum, may be used. In another embodiment, polysilicon material or doped polysilicon may be used in place of silicon nitride as a sacrificial layer. In the case where other silicon nitride films (top and bottom films in the provided stack) are present in the stack to be manufactured, such layers are replaced with oxygen-doped silicon carbide to avoid etching these layers when the sacrificial silicon nitride layer is removed. An advantage of oxygen-doped silicon carbide is that it may provide an etching contrast relative to other materials on the substrate (including silicon nitride and polysilicon) when removal or recessing of SiN, polysilicon, or SiO2 is performed.

[0071] Thus, an alternating stack of oxygen-doped silicon carbide and silicon oxide can be formed, silicon nitride can be used as a sacrificial layer (where tungsten will be deposited later), and the silicon oxide can be recessed before depositing polysilicon because the silicon oxide can be etched with an etching contrast relative to oxygen-doped silicon carbide and silicon nitride. In some embodiments, the silicon oxide can be recessed with an etching contrast relative to nitrogen-doped silicon carbide and silicon nitride. In some embodiments, the silicon oxide can be etched with an etching contrast relative to oxygen-doped silicon carbide and silicon germanium. In some embodiments, the silicon oxide can be recessed with an etching contrast relative to any other non-silicon oxide material on the substrate, including but not limited to nitrogen-doped silicon carbide, doped silicon, silicon nitride, and silicon germanium. After depositing polysilicon and any other patterning processes, a wet etching process can be used to selectively remove the silicon nitride sacrificial layer. A titanium nitride liner can be optionally deposited, and tungsten is deposited in the area previously occupied by the silicon nitride sacrificial layer. Such processes avoid patterning of tungsten on the stack, thereby reducing redeposition of tungsten on the substrate. In addition, the tungsten material in the stack is not affected by various process conditions that may warp and / or modify the grain structure of the tungsten material because the tungsten is deposited after all other processes have been performed. Etching of the stack is simplified because the etching chemistry is not limited to chemistries that can etch tungsten; instead, the materials on the stack are all silicon-containing materials and can be accurately etched using a variety of existing etching processes.

[0072] Certain disclosed embodiments relate to depositing a metal-free multilayer stack having at least three different materials, at least one of which is a sacrificial layer. The term "metal-free" as used herein includes silicon-containing materials; that is, metal-free primarily means such materials that do not include transition metals or metalloids, but include semiconducting materials. Exemplary metal-free materials include, but are not limited to, silicon nitride, silicon carbide, doped silicon carbide, silicon oxide, amorphous silicon, doped silicon, and polycrystalline silicon. In various embodiments, the metal-free stack does not include tungsten. In various embodiments, the metal-free stack is tungsten-free. Sacrificial layers are used during etching and patterning of the multilayer stack; sacrificial layers can be used to avoid etching metal. After patterning, the sacrificial layer can then be etched, and the sacrificial layer is replaced with a metallic material for the final structure. For example, in some embodiments, a metal-free multilayer stack having at least three different materials is deposited, a trench or via is etched in the metal-free multilayer stack, and after etching, the sacrificial layer is selectively etched relative to the other materials of the stack to form a space, and the metal is deposited in the space. In various embodiments, the metal-free multilayer stack has four different silicon-containing materials. In some embodiments, the metal-free multilayer stack has four different metal-free materials. In some embodiments, "different" materials means materials with different molecular or atomic compositions, or different grain structures, or different lattice structures. When exposed to multiple etchants including liquid etchants, selective etching of the sacrificial layer can be achieved by using the etching contrast between the materials.

[0073] In various embodiments, the sacrificial layer can be polysilicon or a silicon nitride material. Etch contrast for the silicon nitride sacrificial layer can be achieved by using other materials in the multilayer stack, including but not limited to silicon oxides, oxygen-doped silicon carbides, or silicon oxycarbides, and polysilicon. Etch contrast for the polysilicon sacrificial layer can be achieved by using an etchant whereby the polysilicon is etched substantially faster than the other materials on the substrate. Even if the other material on the stack includes polysilicon, the etch contrast can be achieved using differences in dopant concentrations in the polysilicon. The dopant concentration in the polysilicon can be about 1E19 atoms / cm 3 to about 1E20 atoms / cm 3 For example, in some embodiments, the multilayer stack may include boron-doped polysilicon, while the sacrificial layer includes undoped polysilicon, so that the undoped polysilicon can be etched with an etching contrast relative to the boron-doped polysilicon to leave space for later metal deposition. It should be understood that the metal deposition can be performed by first depositing a liner layer such as, but not limited to, titanium nitride, followed by metal deposition.

[0074] Different variations of multilayer stacks may be used. For example, in some embodiments, the multilayer stack includes silicon nitride, silicon oxide, and oxygen-doped silicon carbide. In some embodiments, the terms silicon oxycarbide and oxygen-doped silicon carbide may be used interchangeably. In some embodiments, the multilayer stack includes polycrystalline silicon, silicon oxide, and oxygen-doped silicon carbide. In some embodiments, the multilayer stack includes polycrystalline silicon, silicon nitride, silicon oxide, and oxygen-doped silicon carbide.

[0075] In some embodiments, the multilayer stack includes alternating layers of silicon nitride and non-oxide layers, and trenches or through holes are etched in the multilayer stack, followed by selective etching of silicon nitride to form spaces between non-oxide layers. Metal can then be deposited into the space. The non-oxide layer can be silicon carbide oxide, polysilicon, or a silicon nitride material with a wet etching contrast relative to another silicon nitride material. In some embodiments, the multilayer stack including alternating layers also includes another layer with a material different from silicon nitride or non-oxide layers. The layer can be a dielectric barrier layer. In some embodiments, the layer is not a dielectric barrier layer. In some embodiments, the layer is not a dielectric material. In some embodiments, the other layer with a material different from silicon nitride and non-oxide layers is an oxygen-doped silicon carbide layer. In some embodiments, the other layer is used to achieve etching contrast when etching silicon nitride. In some embodiments, the multilayer stack can be used to form a 3D NAND structure.

[0076] As described herein, the oxygen-doped silicon carbide or silicon oxycarbide has an oxygen concentration between about 1% and about 65% atomic.

[0077] Fig.10 1080 is a process flow diagram depicting operations performed according to certain disclosed embodiments. In operation 1082, a substrate is provided. The substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a wafer having one or more layers of material, such as a dielectric, conductive, or semiconductive material deposited on the wafer. In operation 1084, a film stack comprising an oxide, and an oxygen-doped carbide, and one or more layers of a sacrificial silicon nitride is deposited, wherein the sacrificial silicon nitride is deposited in spaces where metal is desired in the final structure. Although silicon oxide, silicon nitride, and oxygen-doped silicon carbide are described herein, it should be understood that in some embodiments, other oxides, nitrides, and oxygen-doped carbides may be used.

[0078] The silicon-oxygen doped carbide may be deposited by plasma enhanced chemical vapor deposition by introducing a silicon-containing precursor, an oxygen-containing reactant, and a carbon-containing reactant while igniting a plasma.

[0079] Precursor molecules for depositing silicon carbide may include silicon-containing molecules having silicon-hydrogen (Si-H) and / or silicon-silicon (Si-Si) bonds, and silicon-carbon (Si-C) bonds. In some embodiments, the precursor molecules for depositing the silicon carbide layer may be silicon-containing and carbon-containing precursors. Precursor molecules for depositing silicon carbide oxides include silicon-containing molecules having silicon-hydrogen (Si-H) bonds and / or silicon-silicon (Si-Si) bonds, and silicon-oxygen (Si-O) bonds and / or silicon-carbon (Si-C) bonds. Precursor molecules for depositing silicon carbon nitrides include silicon-containing molecules having silicon-hydrogen (Si-H) bonds and / or silicon-silicon (Si-Si) bonds, and silicon-nitrogen (Si-N) bonds and / or silicon-carbon (Si-C) bonds. Precursor molecules for depositing silicon nitride carbon oxide include silicon-containing molecules with silicon-hydrogen (Si-H) bonds and / or silicon-silicon (Si-Si) bonds, and silicon-nitrogen (Si-N) bonds, silicon-oxygen (Si-O) bonds, and / or silicon-carbon (Si-C) bonds. In some embodiments, the silicon-containing precursor may include a reactant with a Si-O bond and a reactant with a Si-C bond. It should be understood that any number of suitable reactants may be used within the scope of the present disclosure. The silicon-containing precursor includes one or more Si-H bonds and / or one or more Si-Si bonds. During the deposition process, the Si-H bonds and / or Si-Si bonds are broken and act as reaction sites for forming bonds between the silicon-containing precursors in the deposited silicon carbide film. The broken bonds may also be used as sites for crosslinking during the heat treatment performed during or after deposition. The bonding and crosslinking at the reaction sites can form a main chain or matrix together in the resulting silicon carbide film. In some embodiments, silicon carbide, nitrogen-doped silicon carbide, boron- and nitrogen-doped silicon carbide, and combinations thereof, including combinations with oxygen-doped silicon carbide, may be used in place of oxygen-doped silicon carbide.

[0080] As discussed, the precursors used in forming the silicon carbide film may include silicon-containing precursors, so that at least some of the silicon-containing precursors have at least one Si-H and / or at least one Si-Si bond. In certain embodiments, the silicon-containing precursor has at most one hydrogen atom on each silicon atom. Thus, for example, a precursor having one silicon atom has at most one hydrogen atom bonded to the silicon atom; a precursor having two silicon atoms has one hydrogen atom bonded to one silicon atom and optionally another hydrogen atom bonded to the second silicon atom; a precursor having three silicon atoms has at least one hydrogen atom bonded to one silicon atom, and optionally one or more hydrogen atoms bonded to one or both of the remaining silicon atoms, and so on. In addition, the silicon-containing precursor may include at least one Si-O bond, at least one Si-N bond, and / or at least one Si-C bond. Although any number of suitable precursors may be used to form the silicon carbide film, at least some of the precursors will include silicon-containing precursors having at least one Si-H bond or Si-Si bond, and optionally at least one Si-O bond, Si-N bond, and / or Si-C bond.

[0081] In certain embodiments, at least some of the carbon provided to the silicon carbide film is provided by one or more hydrocarbon groups on the silicon-containing precursor. Such groups may be from alkyl, alkenyl, alkynyl, aryl, etc. In certain embodiments, the hydrocarbon group has a single carbon atom to minimize steric hindrance of Si-H and / or Si-Si bond breaking reactions during deposition. However, the precursor is not limited to a single carbon group; instead, a higher number of carbon atoms, such as 2, 3, 4, 5 or 6 carbon atoms, may be used. In certain embodiments, the hydrocarbon group is linear. In certain embodiments, the hydrocarbon group is cyclic.

[0082] In some embodiments, the silicon-containing precursor belongs to the chemical class. It should be understood that other chemical classes of silicon-containing precursors can be employed, and the silicon-containing precursors are not limited to the chemical classes discussed below.

[0083] In some embodiments, the silicon-containing precursor can be a siloxane. In some embodiments, the siloxane can be cyclic. Cyclic siloxanes can include cyclotetrasiloxanes, such as 2,4,6,8-tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), and heptamethylcyclotetrasiloxane (HMCTS). Other cyclic siloxanes can also include, but are not limited to, cyclotrisiloxane and cyclopentasiloxane. An embodiment using cyclic siloxanes is to introduce pores into the annular structure of the oxygen-doped silicon carbide film, the size of the pores corresponding to the radius of the ring. For example, the cyclotetrasiloxane ring can have a radius of about 10000. The radius of .

[0084] In some embodiments, siloxanes may have a three-dimensional or cage-like structure. Cage-like siloxanes have silicon atoms bridged to each other via oxygen atoms to form a polyhedron or any 3-D structure. An example of a cage-like siloxane precursor molecule is silsesquioxane. Cage-like siloxane structures are described in more detail in U.S. Patent No. 6,576,345 co-owned by Cleemput et al., which is incorporated herein by reference in its entirety for all purposes. Like cyclic siloxanes, cage-like siloxanes can introduce pores into oxygen-doped silicon carbide films. In some embodiments, the porosity level is mesoporous.

[0085] In some embodiments, the siloxane may be linear. Examples of suitable linear siloxanes include, but are not limited to, disiloxanes, such as pentamethyldisiloxane (PMDSO) and tetramethyldisiloxane (TMDSO), and trisiloxanes, such as hexamethyltrisiloxane, heptamethyltrisiloxane.

[0086] In some embodiments, the silicon-containing precursor can be an alkylsilane or other hydrocarbon-substituted silane. The alkylsilane includes a central silicon atom, wherein one or more alkyl groups are bonded thereto and one or more hydrogen atoms are bonded thereto. In certain embodiments, any one or more of the alkyl groups contain 1-5 carbon atoms. The hydrocarbon group can be saturated or unsaturated (e.g., olefins (e.g., vinyl), alkynyl, and aromatic groups). Examples include, but are not limited to, trimethylsilane (3MS), triethylsilane, pentamethyldisilane ((CH3)2Si-CH2-Si(CH3)3) and dimethylsilane (2MS).

[0087] In some embodiments, the silicon-containing precursor may be an alkoxysilane. Alkoxysilanes include a central silicon atom having one or more alkoxy groups bonded thereto and one or more hydrogen atoms bonded thereto. Examples include, but are not limited to, trimethoxysilane (TMOS), dimethoxysilane (DMOS), methoxysilane (MOS), methyldimethoxysilane (MDMOS), diethoxymethylsilane (DEMS), dimethylethoxysilane (DMES), and dimethylmethoxysilane (DMMOS).

[0088] In addition, disilane, trisilane or other higher silanes can be used instead of monosilane. An example of disilane from the alkylsilane class is hexamethyldisilane (HMDS). Another example of disilane from the alkylsilane class can include pentamethyldisilane (PMDS). Other types of alkylsilanes can include alkylcarbosilanes, which can have a branched polymer structure with carbon bonded to the silicon atom and an alkyl bonded to the silicon atom. Examples include dimethyltrimethylsilylmethane (DTMSM) and bisdimethylsilylethane (BDMSE). In some embodiments, one of the silicon atoms can have a carbon-containing or hydrocarbon-containing group attached thereto, and one of the silicon atoms can have a hydrogen atom attached thereto.

[0089] In some embodiments, two or more different chemical sources may be used. For example, one chemical source may include silicon, while a second chemical source includes carbon. In some embodiments, the chemical source including silicon may be TEOS or any silane as described above. In some embodiments, the chemical source including carbon may include methane, alkanes (e.g., ethane (C2H6)), alkenes (e.g., ethylene (C2H4)), and alkynes (e.g., C2H3).

[0090] In depositing silicon carbide, a variety of silicon-containing precursors may be present in the process gas. For example, siloxane and alkylsilane may be used together, or siloxane and alkoxysilane may be used together. The relative proportions of the various precursors may be selected based on the chemical structure of the selected precursor and the application of the resulting silicon carbide film.

[0091] Some silicon carbide films in multilayer stacks may have high breakdown voltage and low leakage current. An example of breakdown voltage achieved by certain disclosed embodiments is about 4 MV / cm. An example of low leakage current achieved by certain disclosed embodiments is about 1E-8 at 2 MV / cm.

[0092] In some embodiments, the process conditions can substantially preserve Si-C bonds, and Si-O bonds and Si-N bonds (if present) in the just-deposited layer of the silicon carbide film. Therefore, the reaction conditions adjacent to the substrate provide selective breaking of Si-H and / or Si-Si bonds, such as extracting hydrogen from the broken Si-H bonds, but the reaction conditions do not provide extracting oxygen from the Si-O bonds, extracting nitrogen from the Si-N bonds, or extracting carbon from the Si-C bonds. However, as described below, the introduction of a co-reactant (e.g., oxygen) can extract carbon from the Si-C bonds. Typically, the reaction conditions described are present on the exposed surface of the substrate (the surface where the silicon carbide film is deposited). They may further be present at a certain distance above the substrate, for example, about 0.5 microns to about 150 millimeters above the substrate. In fact, the activation of the precursor can occur in the gas phase at a considerable distance above the substrate. Typically, although some applications may allow some variations, the relevant reaction conditions will be uniform or substantially uniform over the entire exposed surface of the substrate.

[0093] Silicon-containing precursors are usually transported to an environment adjacent to the substrate together with other substances (especially carrier gases). In some embodiments, silicon-containing precursors exist together with free radical substances and other substances (including other reactive substances and / or carrier gases). In some embodiments, silicon-containing precursors can be introduced as a mixture. Upstream of the deposition reaction surface, silicon-containing precursors can be mixed with inert carrier gases. Exemplary inert carrier gases include but are not limited to nitrogen (N2), argon (Ar), and helium (He). In addition, silicon-containing precursors can be introduced into a mixture with primary and secondary substances, so that the secondary substances contain some elements or structural features (e.g., ring structures, cage structures, unsaturated bonds, etc.), which are present in the silicon carbide film at a relatively low concentration. If appropriate, multiple precursors can exist in equimolar or quite similar ratios to form the main chain or matrix in the resulting silicon carbide film. In other embodiments, the relative amounts of different precursors substantially deviate from equimolar amounts.

[0094] To deposit silicon oxide, one or more silicon-containing precursors may be used. Silicon-containing precursors suitable for use according to the disclosed embodiments include polysilane (H3Si-(SiH2) n -SiH3), where n >0. Examples of silanes are silane (SiH4), disilane (Si2H6), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane (thexylsilane), isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, and the like.

[0095] Halosilanes include at least one halogen group, and may or may not include hydrogen and / or carbon groups.The example of halosilanes is iodosilane, bromosilane, chlorosilane and fluorosilane.Although halosilanes (especially fluorosilanes) can form reactive halide species, which can etch silicon materials when plasma ignites, in some embodiments, when plasma ignites, halogenated silanes may not be introduced into the chamber, and therefore reactive halide species formed by halosilanes can be alleviated.Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallyl silane, chloromethyl silane, dichloromethyl silane, chlorodimethyl silane, chloroethyl silane, tert-butyl chlorosilane, di-tert-butyl chlorosilane, chloroisopropyl silane, chloro-sec-butyl silane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane etc.

[0096] Aminosilanes include at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilanes (H3Si(NH2), H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively) and substituted mono-, di-, tri-, and tetra-aminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilylamine, bis(tert-butylamino)silane, (SiH2(NHC(CH3)3)2(BTBAS), tert-butylsilylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, and the like. Another example of an aminosilane is trimethylsilylamine (N(SiH3)). In various embodiments, plasma may not be used during the deposition of any layer of the multilayer stack. In some embodiments, plasma may be used during the deposition of any layer of the multilayer stack.

[0097] Exemplary techniques for depositing some of the layers described herein are provided in U.S. Patent No. 8,741,394, U.S. Patent No. 9,028,924, and U.S. Patent Publication No. 2011 / 0236594, which are incorporated herein by reference in their entirety.

[0098] Oxygen doping can be adjusted using certain techniques, such as adjusting temperature, pressure, plasma power, and frequency, as well as the oxygen-containing reactive gas flow relative to other gas flows. The amount of oxygen doping affects the relative etching contrast. For example, silicon nitride may have a specific etching contrast of about 0% to about 65% relative to oxygen-doped silicon carbide, whereas the same material may have a lower etching contrast relative to silicon carbide doped with 66% oxygen under the same process conditions. In hot phosphoric acid (H3PO4), silicon nitride has an etching contrast relative to silicon oxide. Silicon carbide oxide can be used to provide wet etching contrast both relative to silicon nitride in H3PO4 wet etching and relative to silicon oxide in hydrofluoric acid (HF) wet etching.

[0099] return Fig.10 , in operation 1086, any pattern may be etched on the substrate. For example, in some embodiments, a groove or a through hole is etched through the multilayer stack, which can be performed using existing dielectric etching techniques without any risk of metal residue or degradation of the etching profile. For example, the operation may involve recessing the silicon oxide material, which may be performed because oxygen-doped silicon carbide, silicon nitride, and polysilicon may provide sufficient etching contrast relative to the etching of silicon oxide. In various embodiments, the etching chemicals used to pattern the stack include one or more of tetrafluoromethane (CF4), fluoromethane (CFH3), difluoromethane (CH2F2), octafluorocyclobutane (C4F8), and nitrogen trifluoride (NF3). Patterning may be performed to etch a groove or a through hole. In some embodiments, the operation may not include a silicon oxide recessing operation.

[0100] During the patterning in operation 1086, the etching contrast can vary depending on the materials in the stack. In some embodiments, the silicon oxide is recessed after the trench is etched so that the silicon oxide is selectively removed from the sidewalls in the trench, thereby causing the trench to have a varying width at a specific depth in the stack. For example, the trench can be etched into a stack including silicon nitride, silicon oxide, and polysilicon (wherein the silicon oxide is between the silicon nitride and the polysilicon), and then the silicon oxide can be etched in the trench so that the sidewalls of the trench with silicon oxide are recessed. The recessing of silicon oxide can be performed using a specific etching chemistry with an etching contrast relative to other materials on the substrate. In various embodiments, the etching of silicon oxide is between about 5 and about 1000 times faster than silicon nitride, polysilicon, and oxygen-doped silicon carbide.

[0101] Silicon oxide is provided as an example. In some embodiments, the dielectric material is recessed so that the dielectric material is selectively removed from the sidewalls of the trench. Exemplary dielectric materials include, but are not limited to, silicon oxide and doped silicon oxide.

[0102] In operation 1090, a sacrificial silicon nitride material is selectively etched from the substrate relative to other materials (polysilicon, oxides, oxygen-doped silicon carbide) on the substrate. This operation can be performed using the etching contrast of the sacrificial silicon nitride relative to these materials in a wet etching process. For example, in some embodiments, the sacrificial silicon nitride can be etched by immersing the substrate in hot H3PO4. Etching in this manner will result in the formation of spaces in the positions previously occupied by silicon nitride on the substrate. The etching selectivity of silicon nitride relative to other materials on the substrate can be between about 10 and about 1000, where the other materials are silicon oxide, oxygen-doped silicon carbide, and polysilicon.

[0103] In operation 1092, tungsten is deposited on the substrate in the spaces previously occupied by the sacrificial silicon nitride material. For example, tungsten can be deposited into the horizontal spaces between the oxide layers. In some embodiments, a metal-containing liner is deposited prior to depositing the metal. In various embodiments, the metal-containing liner can be titanium nitride, aluminum oxide, or tungsten carbonitride. The metal deposited in operation 1092 can be deposited directly on or above the metal-containing liner. For example, tungsten can be deposited on a titanium nitride liner.

[0104] Fig.11A An exemplary process flow diagram depicting operations performed according to certain disclosed embodiments is shown. In this example, a substrate is provided in operation 1282. In operation 1284, a metal-free film stack is deposited, such as with reference to Fig.9A and the following Fig. 12A As described. In operation 1285, a trench is etched in the metal-free stack. In various embodiments, the etched trench has a high aspect ratio, such as a high aspect ratio between about 5:1 and about 20:1. In various embodiments, the width of the trench is between about 30nm and about 200nm. In operation 1286, the silicon oxide can be recessed. In various embodiments, the silicon oxide recessing is performed so that the etching rate of the silicon oxide is at least about 50 times faster than the etching rate of other materials in the metal-free stack. The silicon oxide recessing can be performed using any suitable etching chemistry, including but not limited to halogen-based chemistry, such as hydrofluoric acid. In operation 1290, the sacrificial silicon nitride layer is selectively removed. In various embodiments, the sacrificial silicon nitride layer is etched using a phosphorus-based chemistry of a wet etch (e.g., by using diluted H3PO4). In operation 1292, tungsten is deposited at the location where the sacrificial silicon nitride is removed.

[0105] Fig. 11BYet another exemplary process flow diagram depicting operations performed according to certain disclosed embodiments is shown. In this example, a substrate is provided in operation 1182. In operation 1184, a film stack is deposited so that multiple groups of the following film stacks (from top to bottom) are deposited on top of one another: oxygen-doped silicon carbide, silicon nitride, doped polysilicon, silicon oxide, doped polysilicon, and silicon nitride. In operation 1186a, the silicon oxide can be recessed. In operation 1186b, polysilicon is filled into the substrate. In some embodiments, the material used to fill the substrate can be a dielectric material or a semiconductor material. In operation 1190, a sacrificial silicon nitride layer is selectively removed. In operation 1192, tungsten is deposited at the location where the sacrificial silicon nitride was removed.

[0106] Figures 12A-12E Exemplary schematic diagrams of various substrates subjected to certain disclosed process embodiments are shown.

[0107] exist Fig. 12A In, with Fig.9A In contrast, a substrate having oxygen-doped silicon carbide 400, a sacrificial silicon nitride layer 402, polysilicon 100, silicon oxide 101, and oxygen-doped silicon carbide 400 is provided. Fig. 12B In the embodiment, a trench is formed and the silicon oxide 101 is recessed. Fig. 12C In some embodiments, polysilicon 100 is deposited to fill the recessed space of silicon oxide 101. Fig. 12C and 12D The polysilicon 100 is etched back in the operation between Fig.12D In the embodiment, the sacrificial silicon nitride layer 402 is selectively removed, for example, by wet etching. Fig.12E In the embodiment of the present invention, tungsten 440 is deposited into the space previously occupied by the silicon nitride layer. Since polysilicon 100 is present in the structure, tungsten is not deposited on the sidewalls of previously patterned trenches or vias, so this avoids etching tungsten during via formation and during silicon oxide recessing.

[0108] In various embodiments, oxygen-doped silicon carbide deposited by PECVD can replace silicon nitride, and silicon nitride replaces tungsten and titanium nitride. Because the materials used can be etched using techniques developed for OPOP and ONON etch processes, high aspect ratio etching of the film stack has a lower risk and no risk of metal residues. Because oxygen-doped silicon carbide, silicon nitride, and polysilicon will provide sufficient etching contrast, silicon oxide can be recessed in a similar manner. Finally, silicon nitride can be removed and backfilled with titanium nitride and tungsten, and tungsten roughness will not be a concern because the surface will be limited by the dielectric sidewalls.

[0109] Another approach is to replace tungsten and titanium nitride with doped polysilicon. In some cases, this will simplify the etching process by changing the number of materials to be etched with a high aspect ratio from 5 to 3. However, because doped polysilicon and undoped polysilicon have very different wet etch rates, the doped polysilicon can be removed by wet etching and then backfilled with titanium nitride and tungsten. Exemplary dopants include boron, phosphorus, and arsenic.

[0110] A variety of dopant precursors may be used during deposition of the doped polysilicon to form the doped polysilicon. In some embodiments, a suitable dopant source may be elemental arsenic, or arsenic hydrogen (ASH3), or arsenic-doped silicate glass (ASG), or arsenic trioxide (As2O3) and / or arsenic pentoxide (AS2O3). 5+ ). In other embodiments, a suitable dopant source may be elemental boron or a boron compound, such as diborane (B2H6), and a suitable dopant precursor may be a boron compound, such as an alkyl borate. For example, trimethyl borate (TMB) (shown below) is a particular alkyl borate that works well as a dopant precursor to form the dopant source boron trioxide (B2O3); however, other dopant precursors may also be suitable for forming a variety of boron-based dopant sources. In addition, dopant sources based on elements other than boron and arsenic (e.g., gallium or phosphorus-based dopant sources) may also be suitable.

[0111]

[0112] Trimethyl borate is a suitable dopant precursor. However, according to embodiments, other compounds can also be used as suitable dopant precursors. For example, other suitable boron-based dopant precursors can include: other alkyl borates, such as triethyl borate, triisopropyl borate, and tributyl borate, as well as trimethyl boron, triethyl boron, triphenyl boron, triisopropyl borate, tri-n-pentyl borate, B-trichloroborazine, tris(pentafluorophenyl)borane, and other similar boron-containing compounds. Additionally, dopant sources based on elements other than boron would also be suitable. Examples include dopant sources based on gallium, phosphorus, arsenic, or other elements suitable for doping semiconductor substrates, such as other group III and V elements. Arsenic-based dopant precursors can include, but are not limited to, alkylarsines, alkoxyarsines, and aminoarsine chemical families, and include, but are not limited to, the following specific compounds: arsine, triethyl arsenate, trimethylarsine, triethylarsine, triphenylarsine, triphenylarsine oxide, ethylenebis(diphenylarsine), tris(dimethylamino)arsine, and AS(OR)3, where R is -CH3 or -C2H5 or other alkyl groups (including saturated and unsaturated alkyl groups), and other similar arsenic-containing compounds. Phosphorus-based dopant precursors can include, but are not limited to, phosphine (PH3), triethoxyphosphine oxide, trimethyl phosphate, trimethyl phosphite, and other similar phosphorus-containing compounds. The choice of dopant precursor is generally determined by the ease of integration into existing delivery systems, the purity of the film, and the total cost.

[0113] Heavily boron-doped polysilicon can have a relatively high wet etch rate, thus providing an etch contrast relative to other materials on the substrate during patterning. The wet etch rate increases with increasing boron concentration, thereby providing an etch contrast that can be adjusted according to the dopant concentration.

[0114] "Silicon oxide", as referred to herein, is meant to include any and all stoichiometric possibilities including Si x O y wherein x and y can be integer or non-integer values, and some of the H can be bonded to Si or O. For example, "silicon oxide" includes compounds having the chemical formula SiO n where 1 < n < 2, where n can be an integer or a non-integer value. "Silicon oxide" can include sub-stoichiometric compounds, such as SiO 1.8 . "Silicon oxide" also includes silicon dioxide (SiO2) and silicon monoxide (SiO). "Silicon oxide" also includes natural and synthetic variants, and also includes any and all crystalline and molecular structures, including the tetrahedral coordination of oxygen atoms around the central silicon atom. "Silicon oxide" also includes amorphous silicon oxide and silicates.

[0115] "Silicon nitride", as referred to herein, is meant to include Si x N yAny and all stoichiometric possibilities, including integral values of x and y and non-integral values of x and y, such as x = 3 and y = 4. For example, "silicon nitride" includes compounds having the chemical formula SiN n where 1 < n < 2, where n can be an integer or a non-integral value. "Silicon nitride" can include sub-stoichiometric compounds, such as SiN 1.8 . "Silicon nitride" also includes Si3N4 and silicon nitrides with some and / or interstitial hydrogen (SiNH), and silicon nitrides with trace and / or interstitial oxygen (SiON). "Silicon nitride" also includes natural and synthetic variants, and also includes any and all lattice, crystal, and molecular structures, including triangular α-silicon nitride, hexagonal β-silicon nitride, and cubic γ-silicon nitride. "Silicon nitride" also includes amorphous silicon nitride, and can include silicon nitride with trace impurities. Hydrogen will also be present in SiN and can be bonded to Si or N, or both. The hydrogen concentration in silicon nitride can range from about 1% to about 30%.

[0116] Figures 12F-12M Shows yet another exemplary patterning scheme, which is a schematic diagram of a plurality of substrates that have undergone certain disclosed process embodiments.

[0117] In Fig.12F , a substrate is provided that has: silicon oxide 1201, doped polysilicon 1210 above and below the silicon oxide 1201; and silicon carbide doped with oxygen 1200; and a sacrificial silicon nitride layer 1202, with an etch stop layer 1230 below the sacrificial silicon nitride layer 1202 below. In Fig.12F , a trench 1250 is formed. In Fig.12H , the silicon oxide 1201 is recessed at 1240. In Fig.12I , polysilicon 1260 is deposited to fill the space created by the trench 1250 and the recessing of the silicon oxide 1201. In Fig.12J , the doped polysilicon 1260 can be re-etched as shown. In some embodiments, the polysilicon 1260 can become a thin film transistor. In Figure 12K , a gate 1270 is deposited into the trench. In Figure 12L , the sacrificial silicon nitride layer 1202 is selectively removed, for example by wet etching, to create a feature 1225. In Figure 12M , tungsten 1240 is deposited into the feature 1225 at the location previously occupied by the silicon nitride layer. Due to the presence of the polysilicon 1210 in the structure, since tungsten is not deposited on the sidewalls of the previously patterned trenches or vias, this avoids etching tungsten during via formation and during the recessing of the silicon oxide. Although specific materials are described with respect to Figures 12F-12M , it should be understood that Fig.12F The multilayer stack in the embodiment may include other dielectric materials having an etch contrast different from that shown and described herein. Certain disclosed embodiments may be used to form devices other than transistors, such as capacitors or, for example, in Fig.12J Other memory cells inside the recessed area of ​​the scheme depicted.

[0118] Device

[0119] Fig.13 A schematic diagram of an embodiment of an atomic layer deposition (ALD) and / or chemical vapor deposition (CVD) process station 1300 having a process chamber body 1302 for maintaining a low pressure environment is depicted. Multiple process stations 1300 may be included in a common low pressure process tool environment. For example, Fig.14 and 15 An exemplary embodiment of a multi-station processing tool is depicted.In some embodiments, one or more hardware parameters of the ALD processing station 1300 can be programmatically adjusted by one or more computer controllers 1350, including those discussed in detail below.

[0120] The processing station 1300 is in fluid communication with a reactant delivery system 1301a to deliver process gases to a distribution showerhead 1306. The reactant delivery system 1301a includes a mixing vessel 1304 for mixing and / or conditioning process gases, such as silicon precursor gases, or second reactant gases (e.g., oxygen-containing reactants, carbon-containing reactants, etc.), for delivery to the showerhead 1306. One or more mixing vessel inlet valves 1320 can control the introduction of process gases to the mixing vessel 1304. Plasma can also be delivered to the showerhead 1306 or can be generated in the processing station 1300. The reactant delivery system 1301a can be configured to deliver process gases to a substrate provided in the processing station 1300.

[0121] As an example, Fig.13Embodiments include a vaporization point 1303 for vaporizing liquid reactants to be supplied to a mixing container 1304. In some embodiments, the vaporization point 1303 may be a heated vaporizer. The saturated reactant vapor produced by such a vaporizer may condense in a downstream delivery pipeline. Incompatible gases exposed to condensed reactants may produce small particles. These small particles may clog pipelines, hinder valve operation, contaminate substrates, etc. Some methods to solve these problems involve cleaning and / or emptying the delivery pipeline to remove residual reactants. However, cleaning the delivery pipeline may increase the processing station cycle time and reduce the throughput of the processing station. Therefore, in some embodiments, the delivery pipeline downstream of the vaporization point 1303 can be heated and tracked. In some examples, the mixing container 1304 can also be heated and tracked. In a non-limiting example, the pipeline downstream of the vaporization point 1303 has an increased temperature distribution extending from about 100°C to about 150°C at the mixing container 1304.

[0122] In some embodiments, liquid precursors or liquid reactants can be vaporized at the liquid injector. For example, the liquid injector can inject a pulse of liquid reactants into the carrier gas flow upstream of the mixing container 1304. In one embodiment, the liquid injector can evaporate the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector can atomize the liquid into dispersed droplets, which are then evaporated in a heated delivery pipe. Smaller droplets may evaporate faster than larger droplets, thereby reducing the delay between liquid injection and complete vaporization. Faster evaporation can reduce the length of the pipeline downstream of the vaporization point 1303. In one case, the liquid injector can be directly mounted to the mixing container 1304. In another case, the liquid injector can be directly mounted to the spray head 1306.

[0123] In some embodiments, a liquid flow controller (LFC) upstream of the vaporization point 1303 may be provided to control the mass flow of the liquid to vaporize and be delivered to the processing station 1300. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-differential (PID) controller in electrical communication with the MFM. However, it may take one second or longer to stabilize the liquid flow using feedback control. This may extend the dosing time of the liquid reactant. Therefore, in some embodiments, the LFC can be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, this can be performed by disabling the sensing tubes of the LFC and PID controller.

[0124] The showerhead 1306 distributes the process gas toward the substrate 1319. Fig.13In the illustrated embodiment, substrate 1319 is positioned below showerhead 1306 and is shown resting on pedestal 1308. Showerhead 1306 can have any suitable shape and can have any suitable number and arrangement of ports for distributing process gases to substrate 1319.

[0125] In some embodiments, the pedestal 1308 may be raised or lowered to expose the substrate 1319 to the volume between the substrate 1319 and the showerhead 1306. It will be appreciated that in some embodiments, the pedestal height may be programmatically adjusted by a suitable computer controller 1350.

[0126] In another case, in an embodiment where a plasma is ignited, adjusting the height of the pedestal 1308 can enable changing the plasma density during a plasma activation cycle in a process. At the end of a process phase, the pedestal 1308 can be lowered in another substrate transfer phase to enable removal of the substrate 1319 from the pedestal 1308.

[0127] In some embodiments, the temperature of the susceptor 1308 can be controlled via the heater 1310. In some embodiments, the susceptor 1308 can be heated to a temperature of at least about 250° C., or in some embodiments, less than about 300° C., such as about 250° C., during deposition of the silicon nitride film as described in the disclosed embodiments. In some embodiments, the susceptor is set to a temperature between about 50° C. and about 300° C., such as between about 200° C. and about 275° C. In some embodiments, the susceptor is set to a temperature between about 50° C. and about 300° C. In some embodiments, the susceptor is set to a temperature between about 200° C. and about 275° C.

[0128] Additionally, in some embodiments, pressure control of the processing station 1300 may be provided by a butterfly valve 1312. Fig.13 In the embodiment shown in FIG. 1 , butterfly valve 1312 regulates the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of process station 1300 can also be adjusted by varying the flow rate of one or more gases introduced into process station 1300.

[0129] In some embodiments, the position of the showerhead 1306 can be adjusted relative to the pedestal 1308 to change the volume between the substrate 1319 and the showerhead 1306. In addition, it should be understood that the vertical position of the pedestal 1308 and / or the showerhead 1306 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 1308 can include a rotation axis for rotating the orientation of the substrate 1319. It should be understood that in some embodiments, one or more of these example adjustments can be performed programmatically by one or more suitable computer controllers 1350.

[0130] In some embodiments where plasma can be used as described above, the showerhead 1306 and the base 1308 are electrically connected to a radio frequency (RF) power supply 1314 and a matching network 1316 for powering the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the processing station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 1314 and the matching network 1316 can be operated at any suitable power to form a plasma of free radical substances with a specific composition. Examples of suitable power are included above. Similarly, the RF power supply 1314 can provide RF power of any suitable frequency. In some embodiments, the RF power supply 1314 can be configured to control high-frequency and low-frequency RF power sources independently of each other. Exemplary low-frequency RF frequencies can include, but are not limited to, frequencies between 0kHz and 500kHz. Exemplary high-frequency RF frequencies can include, but are not limited to, frequencies between 1.8MHz and 2.45GHz, or frequencies greater than about 13.56MHz, or frequencies greater than 27MHz, or frequencies greater than 180MHz, or frequencies greater than 60MHz. It will be appreciated that any suitable parameter may be modulated discretely or continuously to provide plasma energy for surface reactions.

[0131] In some embodiments, plasma can be monitored in situ by one or more plasma monitors. In one case, plasma power can be monitored by one or more voltage, current sensors (e.g., VI probes). In another case, plasma density and / or process gas concentration can be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters can be programmed to adjust based on the measurement results from such in situ plasma monitors. For example, an OES sensor can be used in a feedback loop to provide programmed control of plasma power. It should be understood that in some embodiments, other monitors can be used to monitor plasma and other processing characteristics. Such monitors can include but are not limited to infrared (IR) monitors, sound monitors, and pressure sensors.

[0132] In some embodiments, instructions for controller 1350 can be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting the conditions of the processing stage can be included in the corresponding recipe stage of the process recipe. In some cases, the process recipe stage may be arranged in order so that all instructions of the processing stage are executed simultaneously with the processing stage. In some embodiments, instructions for setting one or more reactor parameters can be included in the recipe stage. For example, the first recipe stage may include instructions for setting the flow rate of an inert gas and / or a reactant gas (e.g., a first precursor such as a silicon precursor), instructions for setting the flow rate of a carrier gas (e.g., argon), and time delay instructions for the first recipe stage. The subsequent second recipe stage may include instructions for adjusting or stopping the flow rate of an inert gas and / or a reactant gas, instructions for adjusting the flow rate of a carrier gas or a purge gas, and time delay instructions for the second recipe stage. The third recipe stage may include instructions for adjusting the flow rate of a second reactant gas, instructions for adjusting the flow rate of a carrier gas or a purge gas, and time delay instructions for the third recipe stage. A subsequent fourth recipe stage may include instructions for adjusting or stopping the flow rates of the inert gas and / or the reactant gas, as well as instructions for adjusting the flow rates of the carrier gas or the purge gas, and time delay instructions for the fourth recipe stage. It should be understood that these recipe stages may be further subdivided and / or repeated in any suitable manner within the scope of the embodiments of the present disclosure.

[0133] As described above, one or more processing stations may be included in a multi-station processing tool. Fig.14 A schematic diagram of an embodiment of a multi-station processing tool 1400 having an inbound load lock 1402 and an outbound load lock 1404 is shown, either or both of which may include a remote plasma source. A robot 1406 at atmospheric pressure is configured to move a wafer from a cassette loaded by a wafer boat 1408 into the inbound load lock 1402 via an atmospheric port 1410. The wafer is placed on a pedestal 1412 in the inbound load lock 1402 by the robot 1406, the atmospheric port 1410 is closed, and the load lock 1402 is evacuated. In the case where the inbound load lock 1402 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment in the inbound load lock 1402 before being introduced into the processing chamber 1414. In addition, the wafer may also be heated in the inbound load lock 1402, for example, to remove moisture and adsorbed gases. Next, the chamber transfer port 1416 of the process chamber 1414 is opened and another robot (not shown) places the wafer into the reactor on a susceptor at the first station shown in the reactor for processing. Fig.14The embodiment depicted in FIG. 1 includes a load lock, but it should be understood that in some embodiments, the wafer may be allowed to enter the processing station directly.

[0134] The depicted processing chamber 1414 includes four processing stations, Fig.14 The illustrated embodiment is numbered from 1 to 4. Each station has a heated base (shown as 1418 for station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station can have different or multiple purposes. For example, in some embodiments, the processing station can switch between ALD and plasma enhanced ALD process modes. Additionally or alternatively, in some embodiments, the processing chamber 1414 can include one or more matched pairs of ALD processing stations and plasma enhanced ALD processing stations. Although the depicted processing chamber 1414 includes four stations, it should be understood that a processing chamber according to the present disclosure can have any suitable number of stations. For example, in some embodiments, the processing chamber can have five or more stations, while in other embodiments, the processing chamber can have three or fewer stations.

[0135] Fig.14 One embodiment of a wafer handling system 1490 for transferring wafers within the processing chamber 1414 is depicted. In some embodiments, the wafer handling system 1490 can transfer wafers between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable wafer handling system can be used. Non-limiting examples include wafer conveyors and wafer handling robots.

[0136] It should be understood that in some embodiments, a low pressure transfer chamber may be included in a multi-station processing tool to facilitate transfer between multiple processing chambers. Fig.14 Another embodiment of a multi-station processing tool 1500 is schematically shown. Fig.14 In the illustrated embodiment, the multi-station processing tool 1400 includes a plurality of processing chambers 1414 including a plurality of processing stations (numbered 1 to 4). The processing chambers 1414 interface with a low pressure transport chamber 1404 including a robot 1406 configured to transport substrates between the processing chambers 1414 and a load lock 1419. An atmospheric substrate transfer module 1410 including an atmospheric robot 1412 is configured to facilitate the transfer of substrates between the load lock 1419 and the wafer box 1408.

[0137] Fig.14Also depicted is an embodiment of a system controller 1450 for controlling processing conditions and hardware states of the processing tool 1400. The system controller 1450 may include one or more memory devices 1456, one or more mass storage devices 1454, and one or more processors 1452. The processor 1452 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor control board, and the like.

[0138] In some embodiments, the system controller 1450 controls all activities of the processing tool 1400. The system controller 1450 executes system control software 1458, which is stored in the mass storage device 1454, loaded into the memory device 1456, and executed on the processor 1452. Alternatively, the control logic can be hard-coded in the controller 1450. Application-specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays or FPGAs), etc. can be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally equivalent hard-coded logic can be used. The system control software 1458 can include instructions for controlling timing, gas mixtures, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperatures, target power levels, RF power levels, substrate pedestals, chuck and / or susceptor positions, and other parameters of a particular process performed by the processing tool 1400. The system control software 1458 can be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components for performing various process tool processes.The system control software 1458 may be coded in any suitable computer readable programming language.

[0139] In some embodiments, the system control software 1458 may include input / output control (IOC) sequenced instructions for controlling the various parameters described above. Other computer software and / or programs stored on the mass storage device 1454 and / or the memory device 1456 associated with the system controller 1450 may be employed in some embodiments. Examples of programs or program segments used for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0140] The substrate positioning program may include program code for processing tool components to load a substrate onto the pedestal 1418 and control the spacing between the substrate and other parts of the processing tool 1400 .

[0141] The process gas control program may include code for controlling gas composition (e.g., silicon precursor gas, carbon-containing gas, carrier gas, and sweep gas as described herein) and flow rate, and optionally for flowing gas into one or more process stations to stabilize the pressure of the process station prior to deposition. The pressure control program may include code for controlling the pressure in a process station by adjusting, for example, a throttle valve in an exhaust system of the process station, gas flow into the process station, etc.

[0142] The heater control program may include code for controlling the flow of current to a heating unit for heating the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (eg, helium) to the substrate.

[0143] According to embodiments herein, a plasma control program may include code for setting RF power levels applied to process electrodes in one or more process stations.

[0144] According to embodiments herein, the pressure control program may include code for maintaining the pressure in the reaction chamber.

[0145] In some embodiments, there may be a user interface associated with the system controller 1450. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and a user input device such as a pointing device, a keyboard, a touch screen, a microphone, etc.

[0146] In some embodiments, the parameters adjusted by the system controller 1450 may relate to process conditions. Non-limiting examples include process gas composition and flow, temperature, pressure, plasma conditions (such as RF bias power level), etc. These parameters may be provided to the user in the form of a recipe that may be entered using a user interface.

[0147] Signals for monitoring the process may be provided through analog and / or digital input connections from various process tool sensors of the system controller 1450. Signals for controlling the process may be output on analog and digital output connections of the process tool 1400. Non-limiting examples of process tool sensors that may be monitored include: mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with the data from these sensors to maintain process conditions.

[0148] System controller 1450 may provide program instructions for implementing the above-described deposition process. The program instructions may control various process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. In accordance with various embodiments described herein, the instructions may control the parameters to operate the in-situ deposition of the film stack.

[0149] The system controller 1450 will typically include one or more memory devices and one or more processors configured to execute instructions so that the device will perform methods according to the disclosed embodiments. A machine-readable medium containing instructions for controlling processing operations according to the disclosed embodiments may be coupled to the system controller 1450.

[0150] In some implementations, the system controller 1450 is part of a system, which can be part of the above examples. Such a system can include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller", which can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 1450 can be programmed to control any process disclosed herein, any process including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer delivery in and out of tools and other delivery tools and / or load locks connected to a specific system or interfaced with a specific system.

[0151] Broadly speaking, the system controller 1450 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software to receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions delivered to the system controller 1450 or system in the form of various individual settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0152] In some embodiments, the system controller 1450 can be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 1450 can be in the "cloud" or in all or part of a wafer factory (fab) host system, which can allow remote access to wafer processing. The computer can implement remote access to the system to monitor the current progress of manufacturing operations, check the history of past manufacturing operations, study trends or performance metrics from multiple manufacturing operations, change the parameters of the current processing, set the processing steps to follow the current processing, or start a new processing. In some examples, a remote computer (such as a server) can provide a process recipe to the system through a network (which can include a local network or the Internet). The remote computer can include a user interface that enables input or programming of parameters and / or settings, and then the parameters and / or settings are delivered to the system from the remote computer. In some examples, the system controller 1450 receives instructions in the form of data that specify the parameters of each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool, and the system controller 1450 is configured to interface with or control the tool. Thus, as described above, the system controller 1450 may be distributed, for example, by including one or more discrete system controllers 1450 networked together and working toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such a purpose would be one or more integrated circuits on a chamber communicating with one or more integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0153] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0154] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in material transport to transport wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0155] Fig.15 A schematic diagram of an embodiment of a multi-station processing tool 1500 is shown with an inbound load lock 1502 and an outbound load lock 1504, either or both of which may include a remote plasma source. An example of a commercial embodiment of a suitable tool is the Strata tool available from Lam Research Corp. (Fremont, CA).

[0156] The depicted processing tool 1500 includes four processing chambers 1510a, 1510b, 1510c, and 1510d. Each processing chamber includes four processing stations, which are labeled 1, 2, 3, and 4 in the processing chamber 1510a. Each station has a heated susceptor (shown as processing station 1 in the processing chamber 1510a), and a gas pipeline inlet. It should be understood that in some embodiments, each processing station may have different or multiple uses. For example, in some embodiments, the processing station can be switched between PECVD, ALD, and plasma-enhanced ALD process modes. Additionally or alternatively, in some embodiments, the processing chamber 1510a may include one or more pairs of matched PECVD, ALD, and plasma-enhanced ALD processing stations. Although the depicted processing chamber 1510b includes four stations 1, 2, 3, and 4, it should be understood that the processing chamber according to the present disclosure may have any suitable number of stations. Each station in each processing chamber can be used to process four different materials, so that one material is deposited in each station. In some embodiments, each station can be used to deposit four different materials. In some embodiments, a single station processing chamber can be used. In some embodiments, a four-station processing chamber can be used.

[0157] Additionally, processing tool 1500 shows four processing chambers, but it should be understood that the processing tool may include more than four or fewer than four processing chambers, each processing chamber having one or more processing stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments, a processing chamber may have three or fewer stations.

[0158] Fig.15 A wafer handling system 1590 is included for transferring wafers between the processing chambers 1510a, 1510b, 1510c, and 1510d and within the processing tool 1500.

[0159] In some embodiments, the wafer handling system 1590 can transfer wafers between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable wafer handling system can be used. Non-limiting examples include wafer conveyors and wafer handling robots.

[0160] Fig.15Also depicted is an embodiment of a system controller 1550 for controlling processing conditions and hardware states of the processing tool 1500. The system controller 1550 may include one or more memory devices 1556, one or more mass storage devices 1554, and one or more processors 1552. The processor 1552 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor control board, and the like.

[0161] In some embodiments, the system controller 1550 controls all activities of the processing tool 1500. The system controller 1550 executes system control software 1558, which is stored in the mass storage device 1554, loaded into the memory device 1556, and executed on the processor 1552. Alternatively, the control logic can be hard-coded in the controller 1550. Application-specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays or FPGAs), etc. can be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally equivalent hard-coded logic can be used. The system control software 1558 can include instructions for controlling timing, gas mixtures, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperatures, target power levels, RF power levels, substrate pedestals, chuck and / or susceptor positions, and other parameters of a particular process performed by the processing tool 1500. The system control software 1558 can be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components for performing various process tool processes.The system control software 1558 may be coded in any suitable computer readable programming language.

[0162] Controller 1550 may have any of the features described above with reference to controller 1450 .

[0163] Suitable apparatus for performing the methods disclosed herein are further discussed and described in U.S. patent application Ser. No. 13 / 084,399, filed on April 11, 2011, entitled “PLASMA ACTIVATED CONFORMAL FILMDEPOSITION” (now U.S. Patent No. 8,728,956), and U.S. patent application Ser. No. 13 / 084,305, filed on April 11, 2011, entitled “SILICON NITRIDE FILMS AND METHODS,” the entire contents of each of which are incorporated herein.

[0164] The apparatus / processes described above may be used in conjunction with photolithographic patterning tools or processes, for example, for preparing or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, although not necessarily, such tools / processes will be performed or used in a common manufacturing facility. Photolithographic patterning of films generally includes some or all of the following operations, each of which is performed using a number of possible tools: (1) applying photoresist to a workpiece (i.e., substrate) using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible light or UV light or X-ray light using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist, thereby patterning it using a tool such as a wet bench; (5) transferring the resist pattern to an underlying film or workpiece by using a dry etching tool or a plasma assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0165] Experimental

[0166] Experiments were conducted to etch high aspect ratio trenches in a multilayer stack having sets of metal-free layers between two silicon oxide layers with an ashable hard mask layer over the top silicon oxide layer. The sets of metal-free layers included silicon-containing layers. The metal-free layers did not include any tungsten. There were 4-12 sets of metal-free layers in the substrate. High aspect ratio features were etched and the resulting features did not exhibit line collapse and exhibited smooth profiles.

[0167] A second experiment was conducted to concave the sidewalls of the silicon oxide material in a patterned multilayer stack having multiple groups of metal-free layers. Each group of metal-free layers includes at least one layer of silicon oxide. Because the multilayer stack is patterned, the pillars of the multilayer stack are etched simultaneously so that the sidewalls of the silicon oxide layers of all multilayer pillars are etched simultaneously. The space between the pillars is a negative feature with a depth-to-width ratio between about 25:1 and about 35:1. An etching selectivity of at least 50:1 is achieved for silicon oxide relative to other silicon-containing metal-free layers on the substrate. Etching is performed using 100:1 dilute HF. High isotropic etching selectivity is achieved for silicon oxide materials relative to silicon nitride, polysilicon, and silicon carbide materials.

[0168] in conclusion

[0169] The ranges described herein include their endpoints. Although the foregoing embodiments have been described in considerable detail for the purpose of clear understanding, it is apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternatives to the processes, systems, and devices of the present embodiments. Therefore, the present embodiments are considered to be illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; depositing a metal-free multilayer stack having at least three different materials, at least one of the three different materials being a sacrificial layer; etching trenches or vias in the metal-free multilayer stack having the at least three different materials; recessing a dielectric material in a sidewall of the trench or via in the metal-free multilayer stack; selectively etching the sacrificial layer relative to other materials of the metal-free multilayer stack to form at least one space between multiple layers of the metal-free multilayer stack; and Metal is deposited in the at least one space to form a metal-containing multilayer stack having trenches or vias etched therein. 2 . The method of claim 1 , wherein the metal-free multilayer stack comprises three different materials. The method of claim 1 , wherein the metal-free multilayer stack comprises four different materials.

4. The method of claim 1, wherein the sacrificial layer is selected from the group consisting of polysilicon and silicon nitride.

5. The method of claim 1, wherein the at least three different materials comprise a material selected from the group consisting of silicon oxide, undoped polysilicon, doped polysilicon, silicon nitride, oxygen-doped silicon carbide, and nitrogen-doped silicon carbide.

6. The method of claim 1, wherein the layers of the metal-free multilayer stack are deposited by a technique selected from the group consisting of atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, and physical vapor deposition.

7. The method of claim 1, wherein the layers of the metal-free multilayer stack are deposited in different chambers of a single tool. The method of claim 1 , wherein the layers of the metal-free multilayer stack are deposited without breaking vacuum.

9. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; depositing a metal-free multilayer stack having at least three different materials, at least one of the three different materials being a sacrificial layer; etching trenches or vias in the metal-free multilayer stack having the at least three different materials; Recessing one of the at least three different materials after etching the trench or via to form a recessed region of the via; Depositing a dielectric material or a semiconductor material into the trench or via: etching back the dielectric material or semiconductor material in the trench or via to form smooth sidewalls, thereby leaving the dielectric material in the recessed area; Before selectively etching the sacrificial layer, depositing a gate material into the trench or via; selectively etching the sacrificial layer relative to other materials of the metal-free multilayer stack to form at least one space between multiple layers of the metal-free multilayer stack; and Metal is deposited in the at least one space to form a metal-containing multilayer stack having trenches or vias etched therein.

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