Dynamic Program Erase Targeting with Bit Error Rate

Abstract

The present application relates to dynamic program erase target setting with bit error rate. A system includes a memory array having memory cells and a processing device coupled thereto. The processing device performs a programming target setting operation, the programming target setting operation including: determining a set of difference error counts corresponding to a programming distribution of the memory array; identifying a valley margin corresponding to the programming distribution based on a comparison of the set of difference error counts; selecting a programming target setting rule from a rule set based on the value of the valley margin; performing a programming target setting operation based on the programming target setting rule to adjust a voltage level associated with an erase distribution of the memory array; determining a bit error rate BER of the memory array; in response to the BER satisfying a BER control value, reducing the voltage level by a certain voltage step; and in response to the BER not satisfying the BER control value, increasing the voltage level by the voltage step.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to dynamic program erase target setting with bit error rate. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present application provides a system comprising: a memory array comprising a plurality of memory cells; and a processing device coupled to the memory array and performing a programming target setting operation on the memory array, wherein in order to perform the programming target setting operation, the processing device: determines a set of difference error counts corresponding to a plurality of programming distributions of the memory array; identifies a plurality of valley margins corresponding to the plurality of programming distributions based on a comparison of the set of difference error counts; selects a programming target setting rule from a rule set based on the values ​​of the plurality of valley margins; performs a program erase target setting operation based on the programming target setting rule to adjust a voltage level associated with an erase distribution of the memory array; determines a bit error rate BER of the memory array; in response to the BER satisfying a BER control value, reduces the voltage level by a certain voltage step; and in response to the BER not satisfying the BER control value, increases the voltage level by the voltage step.

[0004] On the other hand, the present application further provides a method, which includes: presetting the voltage level of the erase distribution of a memory array to be higher than a default value by a processing device, the memory array including a plurality of memory cells of a first logical page type and a second logical page type; and performing a programming target setting operation by the processing device, the programming target setting operation including: determining a set of difference error counts corresponding to a plurality of programming distributions of the first logical page type; identifying a plurality of valley margins corresponding to the plurality of programming distributions based on a comparison of the set of difference error counts; adjusting the values ​​of at least some of the plurality of valley margins multiple times to balance the relative valley margins of the first logical page type so that the read window budget RWB of the valleys of the first logical page type is approximately the same RWB; determining a bit error rate BER of the memory array; and increasing the voltage level by a certain voltage step in response to the BER not satisfying a BER control value.

[0005] In yet another aspect, the present application provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform a programming target setting operation, the programming target setting operation comprising: determining a set of difference error counts corresponding to a plurality of programming distributions of a memory array, the memory array comprising a plurality of memory cells; identifying a plurality of valley margins corresponding to the plurality of programming distributions based on a comparison of the set of difference error counts; selecting a programming target setting rule from a rule set based on values ​​of the plurality of valley margins; performing a program erase target setting operation based on the programming target setting rule to adjust a voltage level associated with an erase distribution of the memory array; determining a bit error rate BER of the memory array; reducing the voltage level by a certain voltage step in response to the BER satisfying a BER control value; and increasing the voltage level by the voltage step in response to the BER not satisfying the BER control value. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1A An example computing system including a memory subsystem in accordance with some embodiments is described.

[0008] Figure 1B is a block diagram of a memory subsystem having a dynamically programmed calibration mechanism configured in accordance with various embodiments.

[0009] Figure 2 is a set of graphs illustrating erase distributions of program verify voltage level targets and first and second programming passes according to an embodiment.

[0010] Figure 3A-3B is a set of graphs illustrating difference error counts for two read level thresholds between two adjacent programming distributions according to some embodiments.

[0011] Figure 4 is a graph illustrating eight programming distributions according to some embodiments, including two programming distributions after adjusting at least two of the program verify targets according to a program target set (PT) operation.

[0012] Figure 5A An example set of rules corresponding to adjusting the voltage of an erase program distribution and locking the program verify target of a last programmed distribution according to various embodiments is described.

[0013] Figure 5B An example set of rules corresponding to adjusting the voltage of a last programmed distribution of an erased programmed distribution according to various embodiments is described.

[0014] Figure 5C Example rule sets corresponding to adjusting voltages for erased program distributions, adjusting program verify targets for last program distributions, and locking program verify targets for program distributions adjacent to initial program distributions according to various embodiments are described.

[0015] Figure 6 is a flow chart of an example method for performing dynamic program erase targeting at bit error rate (BER) according to various embodiments.

[0016] Figure 7 is a flow chart of an example method for performing memory quality testing using one or more read voltage levels according to additional embodiments.

[0017] Figure 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0018] Various aspects of the present disclosure are directed to read voltage assisted manufacturing testing in a memory subsystem. The memory subsystem may be a memory device, a memory module, or a mixture of a memory device and a memory module. Figure 1A-1B Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components (e.g., a memory device that stores data). The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0019] The memory subsystem may include multiple memory devices, which in turn include a memory array of memory cells that can store data from a host system according to multiple programming distributions. A continuous read level calibration (cRLC) operation continuously samples the margin between programming distributions, also referred to as a read threshold valley, or more simply a valley. This valley margin may refer to the relative width between a pair of adjacent programming distributions. The valley margin may be related to a read window budget (RWB). The read window budget of a valley may refer to an absolute measurement between two adjacent programming distributions, in units of volts, such as millivolts (mV).

[0020] Conventional memory subsystems experience wear and tear, which can result in an imbalance in the bit error rate (BER) between logical page types. The BER can be calculated from the number of bit errors detected in an error correction code (ECC) codeword divided by the total number of bits in the codeword. The calculated BER can include the bit error count for a single codeword, an average (mean or median) over many codewords, or can include only codewords for a specific page or page type. An imbalance in BER between page types can result in an increase in the average error correction trigger rate during the life of each die, including end-of-life (EOL) conditions due to dominance of a logical page type. In addition, BER imbalance can result in valleys for each logical page type having different RWBs, resulting in reduced endurance (e.g., fewer total program / erase cycles) for each die in the memory subsystem.

[0021] Aspects of the present disclosure address the above and other deficiencies by performing cRLC measurements used in conjunction with various types of programming target setting operations, also referred to herein as dynamic programming target setting (DPT) operations. The programming target setting (PT) operations control the placement of a program verification (PV) target (e.g., a threshold voltage (Vt)) so that the programming distribution is placed in a favorable arrangement. The PV target may refer to a voltage value or trim value used to program a memory cell at a given voltage level. The PV target may set the threshold voltage (Vt) of a memory cell, e.g., the minimum voltage at which the memory cell turns on or conducts. The position of the erased programming distribution (i.e., L0) may be controlled (e.g., moved to the right or left) by adjusting the erased voltage (also referred to as "Vera") to adjust the valley margin between the erased distribution and the first programming distribution (i.e., L1 distribution). The erased programming distribution is also more simply referred to as the erased distribution.

[0022] In various embodiments, the erase distribution is controlled by a quality feedback metric, which in one example may be a bit error rate (BER) of a memory subsystem that may be tested at a memory array level, for example. In the disclosed embodiment, a dynamic program erase target setting (DPET) based on BER (or DPET_BER) is configured to reduce the erase allocation voltage level in response to a higher BER signal and increase the erase allocation voltage level in response to a lower BER signal. This feedback control may be driven by comparing a particular BER control value to the current BER of the memory array to adjust the voltage step (higher or lower) at a time. After adjusting the voltage level of the erase distribution to equilibrium, the control system may jitter the voltage level by adding or subtracting one voltage step in a subsequent DPET_BER adjustment cycle. In one embodiment, the BER control value is set as a percentage above a baseline BER of the memory subsystem, where the baseline BER is based on a factory default trim value.

[0023] Advantages of the present disclosure include, but are not limited to, controlling the PV target placement and voltage of the erase program distribution to improve the measured BER, toggle rate, toggle rate margin, and read window budget (RWB) associated with the memory subsystem. According to an embodiment, the lowest program distribution and the highest distribution are moved along with the erase distribution to enable the full available RWB to be utilized (e.g., across all valleys). Furthermore, allowing all program distributions to move in a controlled manner results in adjusting the total RWB from the erase distribution to the highest program distribution to utilize die-to-die variations to obtain optimal placement, rather than the fixed window placement of conventional memory subsystems.

[0024] Further advantageously, moving the erase distribution to a higher voltage can improve endurance. Also, moving the erase distribution to a lower voltage can improve margins to read errors, temperature, program disturb, read disturb, and defects. Additionally, programmable control points (e.g., BER control values) allow different dies in the same product to be set to have different characteristics, for example, some dies can be set to improve endurance while other dies can be set to improve margin. Programmable control points in system product manufacturing can allow the same product to be manufactured with different endurance and margin characteristics, for example, where customer A requires a high endurance product and customer B requires a high margin product.

[0025] Figure 1A An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, secure digital (SD) cards, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1A An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components or devices, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components or devices), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0029] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0030] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting a Double Data Rate (DDR)), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0031] The memory devices may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. Cross-point arrays of non-volatile memory can be combined with stackable cross-grid data access arrays to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells.

[0033] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] Although non-volatile memory components such as 3D crosspoint and NAND are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), "NOR" flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0037] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1A The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 through a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0040] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] In some embodiments, controller 115 includes an error correction code (ECC) encoder / decoder 111 and a programming target setting component 113. ECC encoder / decoder 111 may perform ECC encoding on data written to memory device 130 and ECC decoding on data read from memory device 130. ECC decoding may be performed to decode ECC codewords to correct errors in the original read data, and in many cases also report the number of bit errors in the original read data.

[0042] In various embodiments, the memory subsystem 110 includes a programming goal setting component 113 that performs as described herein (including including reference to Figure 1B ). In some embodiments, programming target setting component 113 may be part of host system 120, controller 115, memory device 130 or 140, operating system, or application. Programming target setting component 113 may program the PV target of one or more programming distributions (e.g., the second program distribution, the last program distribution, or both). For example, controller 115 may include processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0043] In some embodiments, the controller 115 includes at least a portion of the programming target setting component 113. In addition, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 to perform the operations described herein. In some embodiments, the programming target setting component 113 is part of the host system 120, application program, or operating system.

[0044] Figure 1B is a memory subsystem 110 ( Figure 1A). As shown, the memory subsystem 110 may include a memory array 104 (e.g., NAND flash or other memory type memory devices 130 and / or 140) and a controller 115. The memory subsystem 110 may operably couple the memory array 104 to a host system 120 (e.g., an upstream central processing unit (CPU)). The memory array 104 may include circuitry configured to store data in the memory array 104 and provide access to the data in the memory array 104.

[0045] In various embodiments, the memory array 104 may be provided as a semiconductor, an integrated circuit, and / or an external removable device in a computer or other electronic device. The memory array 104 includes a plurality of memory regions or memory cells 118. The memory cells 118 may be individual memory dies, memory planes in a single memory die, stacks of memory dies vertically connected to through silicon vias (TSVs), and the like. In one embodiment, each of the memory cells 118 may be formed by a semiconductor die and arranged in a single device package (not shown) with other memory cell dies. In other embodiments, one or more of the memory cells 118 may be co-located on a single die and / or distributed in multiple device packages. The memory subsystem 110 and / or individual memory cells 118 may also include other circuit components (not shown) for accessing and / or programming (e.g., writing) data and other functionality, such as for processing information and / or communicating with the controller 115, such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / data input registers, and the like.

[0046] Each of the memory cells 118 includes an array of memory cells 122 that each stores data in a charge storage structure. The memory cells 122 may include, for example, floating gate, charge trapping, phase change, capacitive, ferroelectric, magnetoresistive, and / or other suitable storage elements configured to store data persistently or semi-persistently. The memory cells 122 may be single transistor memory cells that are programmable to a target state to represent information. For example, charge may be placed on or removed from a charge storage structure (e.g., a charge well or floating gate) of the memory cell 122 to program the cell to a particular data state. The charge stored on the charge storage structure of the memory cell 122 may indicate a threshold voltage (Vt) of the cell. For example, a single level cell (SLC) may be programmed to one of two different data states that may be represented by a binary unit of 1 or 0.

[0047] Some memory cells can be programmed to one target state in more than two data states. For example, a memory cell that can be programmed to any of four states (e.g., represented by binary 00, 01, 10, 11) can be used to store two bits of data and can be referred to as a multi-level cell (MLC). Other flash memory cells can also be programmed to any of eight data states (e.g., 000, 001, 010, 011, 100, 101, 110, 111), permitting storage of three bits of data in a single cell. Such cells can be referred to as triple-level cells (TLC). Even higher numbers of data states are possible, such as those found in quad level cells (QLCs), which can be programmed to any of 16 data states (e.g., 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111) to store four bits of data. Memory cells 122 capable of storing a higher number of data states can provide higher density memory without increasing the number of memory cells because each cell can represent more than one digit (e.g., more than one bit).

[0048] The memory cells 122 may be arranged in rows (e.g., each row corresponds to a word line 143) and columns (e.g., each column corresponds to a bit line). Each word line 143 may include one or more memory pages 124 depending on the number of data states that the memory cells 122 of the word line 143 are configured to store. For example, a single word line of memory cells 122 each configured to store one of two data states (e.g., SLC memory cells configured to each store one bit) may include a single memory page 124. Alternatively, a single word line 143 of memory cells 122 each configured to store one of four data states (e.g., MLC memory cells configured to each store two bits) may include two memory pages 124. Furthermore, within a word line 143, pages 124 may be interleaved so that a word line 143 of memory cells 122 each configured to store one of two data states (e.g., SLC memory cells) may include two pages in an "even-odd bit line architecture" (e.g., where all memory cells 122 in odd-numbered columns of a single word line 143 are grouped as a first page, and all memory cells 122 in even-numbered columns of the same word line 143 are grouped as a second page). When an even-odd bit line architecture is used in word lines 143 of memory cells 122 each configured to store a larger number of data states (e.g., memory cells configured as MLC, TLC, QLC, etc.), the number of pages per word line 143 may be even higher (e.g., 4, 6, 8, etc.). Each column may include a string of serially connected memory cells 122 coupled to a common source. Each string of memory cells 122 can be connected in series between a source select transistor (eg, a field effect transistor) and a drain select transistor (eg, a field effect transistor). The source select transistors can be commonly coupled to a source select line, and the drain select transistors can be commonly coupled to a drain select line.

[0049] The memory subsystem 110 may process data using different groupings of memory cells 122. For example, memory pages 124 of memory cells 122 may be grouped into memory blocks 126. In operation, data may be written or otherwise programmed (e.g., erased) with respect to various memory regions of the memory subsystem 110, such as by writing to groups of pages 124 and / or memory blocks 126. In NAND-based memory, a write operation typically includes programming the memory cells 122 in a selected memory page 124 with a particular data value (e.g., a string of data bits having a value of logic 0 or logic 1). An erase operation is similar to a write operation, except that an erase operation reprograms an entire memory block 126 or multiple memory blocks 126 to the same data state (e.g., logic 0).

[0050] In other embodiments, the memory cells 122 may be arranged in different types of groups and / or hierarchies than shown in the illustrated embodiment. Additionally, although a certain number of memory cells, rows, columns, blocks, and memory cells are shown in the illustrated embodiment for purposes of illustration, in other embodiments, the number of memory cells, rows, columns, blocks, and memory cells may vary and may be larger or smaller in proportion than shown in the illustrated example for purposes of illustration. For example, in some embodiments, the memory subsystem 110 may include only one memory cell 118. Alternatively, the memory subsystem 110 may include two, three, four, eight, ten, or more (e.g., 16, 32, 64, or more) memory cells 118. Although the memory cells 118 are shown in Figure 1B 126, but in other embodiments, each memory cell 118 may include one, three, four, eight, or more (e.g., 16, 32, 64, 100, 128, 256, or more memory blocks). In some embodiments, each memory block 123 may include, for example, 215 memory pages, and each memory page within the block may include, for example, 212 memory cells 122 (e.g., a "4k" page).

[0051] In the illustrated example, further organization or detail of the memory array 104 is represented with a page map 142. The page map 142 may represent the grouping, address, type, or combination thereof of memory pages 124 for each of the memory blocks 126. For example, each of the memory blocks 126 may include memory pages 124 corresponding to word line groups 144. Also, the memory pages 124 may further correspond to logical page types 146, such as lower pages (LP) 148, upper pages (UP) 150, or additional pages (EP) 152, for example.

[0052] Word line groups 144 may include groupings of memory pages 124 corresponding to one or more word lines 143 used to implement a processing function, such as reading or writing data. Word line groups 144 may be groupings of memory pages 124 used for or connected to word lines 143. Word lines 143 may correspond to the physical layout or architecture of memory cells 122.

[0053] The page type 146, such as the page type for the upper page 150, the lower page 148, and the additional page 152, can represent the bit grouping of the memory page 124 in a specific order. The type of the page can correspond to the logical layout, architecture, or value of the memory cell 122. For example, the lower page 148 can represent a first information bit stored in the memory page 124 or the memory cell 122 therein. The lower page 148 can be used for an SLC type cell, an MLC type cell, a TLC type cell, or a combination thereof. Also, for example, the upper page 150 can correspond to or represent a second information bit stored in the memory page 124 or the memory cell 122 therein. The upper page 150 can be used for a TLC or MLC type memory cell 122. Also, for example, the additional page 152 can represent a third information bit stored in the memory page 124 or the memory cell 122 therein, such as for the most significant bit or the least significant bit. The additional page 152 can be used for a TLC type memory cell 122.

[0054] The memory subsystem 110 may use processing levels 154 to store or access data. The processing levels 154 may include threshold or operating levels of voltage or current. The processing levels 154 may include a threshold voltage 156, a read level voltage 158, a programming level voltage 160, a programming voltage step 162 (also referred to as a voltage step for ease of reference), or a combination thereof. The voltage step may also be referred to as a voltage trimming level. The threshold voltage 156 may be a voltage applied to a control gate on which the circuitry for the memory cell 122 conducts and can measure current. The threshold voltage 156 may be affected and controlled by controlling the amount of charge held in the floating gate or charge well of the memory cell 122. The memory subsystem 110 may store a certain amount of charge in the memory cell 122 based on the programming level voltage 160 to represent a corresponding data value. The memory subsystem 110 applies the programming level voltage 160 to the control gate or word line to charge the floating gate or charge well. The floating gate or charge well may be electrically isolated, which may enable the memory cell to store and retain charge.

[0055] The memory subsystem 110 may use the stored charge to represent data. For example, storing charge on a floating gate or charge well may be used to store a bit value of 0 for an SLC type cell. A bit value of 1 may correspond to a floating gate or charge well having no stored charge for an SLC. In other types of cells, such as for MLC, TLC, or QLC, the memory subsystem 110 may store a specific amount of charge on a floating gate or charge well to represent different bit values. An MLC type cell may have four different charge states, a TLC may have eight different charge states, and a QLC may have 16 different charge states. As described above, each of the charge states may correspond to a unique binary value.

[0056] The memory subsystem 110 can read or determine the data value stored in the memory cell 122 using a read level voltage 158 corresponding to the data value. The memory subsystem 110 can apply the read level voltage 158 to the control gate and measure the current or voltage across the memory cell to read the data stored in the cell. The charge stored in the floating gate or charge well can shield or offset the amount of charge placed on the control gate to read or access the stored data. Thus, with the read level voltage 158 applied, the measured current or voltage across the memory cell will correspond to the amount of charge stored in the floating gate or charge well.

[0057] During operation of the memory subsystem 110, the electrical characteristics of the device (i.e., charge retention capability) may change due to repeated data writing, erasing, and / or reading. Repeated data operations may cause damage or wear to the structure of the electrically isolated floating gate or charge trap (e.g., oxide layer). The memory subsystem 110 may shift or calibrate the read level voltage 158 to account for the changing electrical characteristics of the memory cell 122.

[0058] Program level voltage 160 is associated with read level voltage 158 and threshold voltage 156. Program level voltage 160, read level voltage 158, threshold voltage 156, or a combination thereof may correspond to the number of bits stored in memory cell 122, a specific content value of the data stored in memory cell 122, or a combination thereof.

[0059] For example, a memory cell 122 configured to store charge in one of two possible states (e.g., an SLC memory cell) may have different associated programming levels, read levels, and threshold voltages than a memory cell 122 configured to store charge in one of four possible states (e.g., an MLC memory cell) or a memory cell 122 configured to store charge in one of eight possible states (e.g., a TLC memory cell). For each type of memory cell (e.g., SLC, MLC, TLC, QLC, etc.), a specific value of programming level voltage 160, read level voltage 158, threshold voltage 156, or a combination thereof may be associated with each of the possible data values.

[0060] The memory subsystem 110 can iteratively store charge in the memory cell 122 for a write or programming operation, such as for incremental step pulse programming (ISPP). The programming step 162 (e.g., a voltage step) can include an increment or voltage value for increasing the stored charge in each iteration. The memory subsystem 110 can reach the programming level voltage 160 by incrementally storing or increasing the amount of charge corresponding to the programming step 162.

[0061] Figure 22 is a set of graphs illustrating an erase distribution 202, a first pass programming distribution 204, and a second pass programming distribution 206 of a program verify (PV) voltage level target according to an embodiment. In an embodiment, the memory subsystem 110 receives a request from the host system 120 to perform a programming operation to store data at a QLC memory (or other memory device having memory cells storing two or more bits). The memory subsystem 110 may first erase the target memory cells of the memory array 104 while retaining the erase distribution 202 (or vera) in the voltage cell.

[0062] In one embodiment, the memory subsystem 110 may perform a single-pass programming after an erase operation, for example, by programming (or storing data) in multiple (e.g., 16) levels at one time. In another embodiment, after an erase operation, the memory subsystem 110 may store data by performing multiple-pass programming (e.g., two or more programming passes) to program or store data at the memory cell. The multiple-pass programming may program two, eight, or 16 levels in each pass of programming. The first programming pass may program data at the memory cell at a specific time. At a later time, a second programming pass may be performed on the memory cell to store additional data at the memory cell. The second programming pass uses the information stored in the first programming pass. On the same memory cell, a specific amount of time may pass between the memory subsystem performing the first programming pass and the second programming pass. During the first programming pass of the two-pass programming operation, one or more voltage levels may be applied to the memory cell to program a first group of bits (e.g., 3 bits in 3 logical pages). During the second programming pass of the two-pass programming operation, one or more voltage levels may be applied to the memory cell to program additional bits to the first set of bits (e.g., 4 bits in 4 logical pages). The level to which the memory cell is programmed in the second programming pass may be based on the last logical page of the memory cell and the previous logical page programmed at the memory cell in the first programming pass.

[0063] The continuous read level calibration (cRLC) operation continuously samples valley margins between programmed distributions. Valley margins may refer to the relative widths between adjacent programmed distribution pairs (also referred to herein as "margins"). For example, a valley margin associated with a particular logical page type may indicate the relative widths between programmed distribution pairs associated with the particular logical page type. For example, a valley margin for an upper logical page (e.g., valley 2 between the second distribution (L1) and the third distribution (L2)) greater than a valley margin for an upper logical page (e.g., valley 6 between the sixth distribution (L5) and the seventh distribution (L6)) may indicate that valley 2 is greater than valley 3, but does not explicitly state the absolute widths or sizes of the two valleys.

[0064] The valley margin may be related to a read window budget (RWB). The RWB of a valley may refer to an absolute measurement between two adjacent programming distributions in volts, such as millivolts (mV). For example, the RWB for a first valley may be 270 mV, and the RWB for a second valley may be 250 mV. For example, if the first valley margin is greater than the second valley margin, then a correlation may be derived that the RWB of the first valley margin is greater than the RWB of the second valley margin.

[0065] In some cases, the value of RWB is not easily measured. The difference error count (Diff-EC) can be easily measured (e.g., by cRLC operation) and can be related to the valley margin and relative RWB of the valleys for a particular logical page type. Diff-EC is a metric derived from measurements taken at valleys between two adjacent programming distributions and is referenced to Figure 3A-3B Discussed in more detail. In some embodiments, Diff-EC is inversely proportional to valley margin. For example, two valleys of a particular logical page type having the same Diff-EC value have approximately the same valley margin. Since the two valleys have the same valley margin, it can be inferred that the two valleys have approximately the same RWB even if the absolute RWB is not measured. If a first valley of a first logical page type has a higher Diff-EC than a second valley of the first logical page type, it can be inferred that the first valley has a smaller valley margin than the second valley, and the first valley has a smaller RWB than the second valley.

[0066] The cRLC operation is a read level calibration, which can be performed on each of the multiple read level threshold registers used during all read operations. The read level threshold register can store a value indicating the read level threshold voltage of a particular valley. The cRLC operation can be performed to center each read level threshold so that the memory device can achieve the best possible overall bit error rate (BER). The cRLC operation is called a continuous operation because the operation continuously and dynamically samples at discrete intervals. For example, depending on the requirements, sampling can be performed once every 1 to 30 seconds with approximately 1 sampling operation, which can be a set of three readings. Each sample initiated by the cRLC operation returns data for a specific die and a specific logical page type so that information is summarized and fed back into the closed-loop system in many such operations so that each die or read level threshold remains calibrated (e.g., the read level threshold is centered). In one embodiment, the sample is three readings from the same read threshold valley (e.g., also referred to herein as a "valley" or "Vt distribution valley").

[0067] In various embodiments, the read level threshold of the memory device may start with a manufacturing default read level threshold. The cRLC operation may be run during a test mode to calibrate all read level offset trims (also referred to herein as "convergence") for all word line groups (WLGs) of all dies in the memory system. The center value of the memory cell (or WLG or memory device, etc.) calibrated or converged by the cRLC corresponds to a read level threshold (or read level trim) centered in or at the lowest point in the read threshold valley. The center value of the memory cell (or WLG or memory device, etc.) calibrated or converged by the cRLC results in the lowest bit error rate (BER). The BER may refer to the number of bit errors of a data vector divided by the total number of bits of a given data vector. The BER may correspond to a specific logical page type. For example, a specific logical page type has a specific BER, while another logical page type has another BER. Trimming may refer to a digital value for a circuit (e.g., a register) that is converted to an analog voltage value. For example, a read level threshold trim can be programmed into a trim register that generates a read level threshold voltage for reading data from a memory cell.

[0068] The cRLC operation measures and collects information about valley margins, such as center bit error count (CenterEC) and Diff-EC measurements. CenterEC is a metric that indicates the average error count of the center sample for each trim (e.g., each read level threshold). Average CenterEC may refer to the average error count of all read level thresholds for a particular logical page type. The average CenterEC for a particular page logical type may indicate the relative BER of that logical page type relative to other logical page types. For example, a first logical page type is associated with an average CenterEC that is greater than the average CenterEC of a second logical page type. Since the first logical page type has a larger average CenterEC than the second logical page type, it can be inferred that the BER of the first logical page type is higher than the BER of the second logical page type. The cRLC measurements may also be used for various types of programming target setting operations (also referred to herein as "dynamic programming target setting (DPT) operations").

[0069] A programming target setting (PT) operation controls the placement of a program verification (PV) target so that a programming distribution is placed in a favorable manner. A PV target may refer to a voltage value or trim value used to program a memory cell at a given level. A PV target may set a threshold voltage (Vt) of a memory cell (e.g., a minimum voltage at which a memory cell is turned on or conducts). A PV target is associated with a specific programming distribution. For example, a plurality of memory cells programmed at a specific PV target may have threshold voltages within a corresponding programming distribution. A programming distribution may describe a range of threshold voltages for memory cells programmed at a specific PV target (e.g., a normal distribution of threshold voltages). A PT operation is a PV target setting calibration that may be performed for each PV target. A PT operation may be considered a collection of one or more operations that adjust or calibrate the placement of a PV target. A PT operation calibrates a plurality of logical page types so that the BER of each logical page type is approximately the same (e.g., minimizing the BER) over the lifetime of the memory system and in all operating environments. Additionally, a PT operation calibrates each specific logical page type to equalize the width of the valleys of each specific logical page type so that the RWB of the valleys of each specific logical page type is approximately the same. For example, the PT operation may adjust three TLC logical page types, namely, the lower logical page (LP), the upper logical page (UP), and the extra logical page (XP), so that the BER of each of the three logical page types is approximately the same (i.e., balanced). In a closed-loop feedback system, the PT operation uses cRLC as a feedback metric. In addition to balancing the logical page type BER, the PT operation also keeps the BER of each logical page type balanced by dynamically performing the PT operation during block programming (e.g., between the first programming pass and the second programming pass of a multi-pass programming operation on the block). Balancing the BER can reduce the average error correction trigger rate in each die life, including end-of-life (EOL) conditions. By adjusting the PV target, the PT effectively moves the programming distribution in the direction of the adjusted PV target. PT calibration (e.g., adjusting the PV target) can result in equalization of valley margins for a particular logical page type, such that the valley margins converge at a particular convergence value, and the valley margins of the particular page types are approximately equal. PT calibration can also include balancing the BER of each logical page type so that each valley associated with a particular logical page has a substantially similar RWB.

[0070] PT operations can increase the endurance of each die in the memory system (i.e., increase the total program / erase cycles). In one embodiment, the use of PT operations avoids one logical page type dominating the end-of-life criteria. PT operations can be performed independently for each word line group. The PV target of the memory device can start from a manufacturing default PV target. PT operations can be run during test mode so that all PV targets for all word line groups (WLGs) of all dies in the memory system are balanced (i.e., when the BER of the logical page type is approximately the same). In test mode, cRLC and PT operations can be run at an accelerated rate for a short period of time during the manufacturing process so that each WLG will optimize and converge the cRLC read level threshold before deployment. cRLC and PT operations can be performed in an interleaved or simultaneous method so that the memory subsystem is continuously maintained at its optimal and controlled valley margin throughout the life of the memory subsystem.

[0071] In an operational mode (e.g., during field operation), cRLC and PT operations may be run dynamically to extend the useful life of the memory devices of the memory subsystem. As used herein, the term "dynamic" may refer to a process, function, operation, or implementation that occurs during operation, use, or deployment of a corresponding device, system, memory subsystem, or embodiment, and after or concurrently with the operation of firmware of a manufacturer or a third party. The dynamically occurring process, function, operation, or implementation may occur after or subsequently (e.g., after a test mode) during design, manufacturing, and initial testing, setup, or configuration. In some conventional memory subsystems, a manufacturing default PV target is used to set the PV target of the memory device, and the default PV target is not changed at any time during the life of the memory device. In other conventional memory subsystems, some PV targets of the memory devices are dynamically changed in the field. However, the PV targets of the programming distributions adjacent to the initial programming distribution and the final programming distribution (also referred to herein as "second programming distributions") are not part of the PV target group that is allowed to be changed or adjusted.

[0072] The initial programming distribution (L0) (i.e., the erase distribution) is sensitive to disturb effects, such as program disturb and read disturb. For example, read disturb is where the reading of a row of memory cells affects the threshold voltage of unread memory cells in a different row of the same block. Program disturb errors occur when one or more memory cells that are not intended to be programmed are changed (e.g., the bit representation is changed) during a programming operation on other memory cells near one or more memory cells. The disturb effect may cause the initial programming distribution (L0) to move upward toward an adjacent programming distribution (e.g., the second programming distribution (L1)), causing the initial programming distribution (L0) to overlap with the second programming distribution (L1), which can cause bit errors and reduce the reliability of the memory device.

[0073] Additional available margin or RWB used to calibrate the memory cells can have a positive impact on the endurance of the memory cells and, therefore, improve the endurance of the memory device. In theory, the available margin or RWB can be used to adjust the programming distribution in one direction or the other and make the margin between programming distributions wider (or narrower). Having additional available margin improves the ability of the memory subsystem to adjust the PV target of the programming distribution (e.g., move the programming distribution) so that the margin between programming distributions can be maintained throughout the life of the memory cell even taking into account the wear effects of shifting or extending the programming distribution. Endurance can refer to the number of programming and erase cycles that a memory cell can perform over the useful life of the memory cell.

[0074] For example, by allowing the voltages of the initial and final programming distributions to be adjusted, the default margin between the initial and second programming distributions may be initially set to be less than the distance where the initial and second programming distributions are guard bands. As the memory cells begin to wear out over time, the initial programming distribution (L0) may drift higher. The PT operation to calibrate the memory cells may compensate for the wear by moving one or more PV targets of the programming distribution from L1 to the same magnitude as the final programming distribution (e.g., in an "accordion-like" manner). The PT operation may continue to calibrate over the life of the memory device. Over time, the accordion-like calibration operation may be performed until the PV target of the final programming distribution reaches an upper limit (e.g., before exceeding a maximum voltage level limit) that the PV target of the final programming distribution is not allowed to exceed. The PT operation may continue to calibrate the memory cells by taking margin from the valleys of another logical page type and providing the margin to the valley margin (V1) between the initial and second programming distributions. By allowing the positions of the initial and final programmed distributions to be adjusted over the life of the memory device to be adjusted when the valley between the initial and second programmed distributions is identified as being most needed (e.g., having the lowest relative width among the valleys between the plurality of programmed distributions), the memory device is thus better able to compensate for the wear of its memory cells, which improves the endurance of the memory device.

[0075] Various aspects of the present disclosure address the above challenges by performing a programming target setting operation to calibrate one or more PV targets associated with a programming distribution of a memory cell. In some embodiments, a PT operation determines one or more Diff-ECs that indicate the relative width of valleys between programming distributions of memory cells of a memory device. The Diff-ECs may be received from a cRLC operation. A processing device performs a programming target setting operation on the memory cells to calibrate one or more program verification (PV) targets associated with the programming distribution. To perform the programming target setting operation, the processing device selects a rule from a rule set based on the one or more Diff-ECs. The rule set corresponds to an adjustment to a voltage of an erase distribution (i.e., a Vera), a PV target of a last programmed distribution, or both.

[0076] In some embodiments, the PT operation implements a rule set to balance the logical page types so that the BERs of different logical page types are approximately the same. When a rule is selected from the rule set, the PT operation identifies two logical page types. Each of the logical page types may have a BER, and the BER may be inferred for each of the logical page types by averaging CenterEC. If the BER of the first logical page type is less than the BER of the second logical page type, a first subset of rules is identified from the rule set. The rules included in the first subset of rules each give a margin to the second logical page type, and the margin is obtained from the first logical page type. If the BER of the first logical page type is greater than the BER of the second logical page type, a second subset of rules is identified from the rule set. The rules included in the second subset of rules each give a margin to the first logical page type, and the margin is obtained from the second logical page type. Using the PT operation, the margin of the logical page type with a higher BER can be obtained from the logical page type with a lower BER, so that over time, the PT operation can balance the BER between the logical page types.

[0077] To select a particular rule from the first subset of rules, the PT operation identifies the valley value of the second logical page type with the smallest margin. The valley value of the second logical page type with the smallest margin is the valley value of the second logical page type with the highest Diff-EC (also referred to as the "most needed" valley value margin). The PT operation further identifies the valley value of the first logical page type with the largest margin. The valley value of the first logical page type with the largest margin is the valley value of the first logical page type with the lowest Diff-EC (also referred to as the "least needed" valley value margin). The PT operation may identify a rule from the first subset of rules that assigns margin to the valley value of the second logical page type with the smallest margin of any valley value of the second logical page type, and obtains margin from the valley value of the first logical page type with the largest margin of any valley value of the first logical page type. The selected rule may identify the PV target to be adjusted and the magnitude and direction of the PV target to be adjusted to perform the above operation. Thus, over time, the PT operation balances the BER between the logical page types and equalizes the relative widths of the valley values ​​of the particular logical page types.

[0078] To select a particular rule from the second subset of rules, the PT operation identifies the valley value of the first logical page type with the smallest margin. The valley value of the first logical page type with the smallest margin is the valley value of the first logical page type with the highest Diff-EC. The PT operation further identifies the valley value of the second logical page type with the largest margin. The valley value of the second logical page type with the largest margin is the valley value of the second logical page type with the lowest Diff-EC. The PT operation may identify a rule from the second subset of rules that assigns a margin to the valley value of the first logical page type with the smallest margin of any valley value of the first logical page type and obtains a margin from the valley value of the second logical page type with the largest margin of any valley value of the second logical page type. The selected rule may identify the PV target to be adjusted and the magnitude and direction of the PV target to be adjusted to perform the above-mentioned PT operation. As noted above, over time, the PT operation balances the BER between logical page types and equalizes the relative widths of the valley values ​​of specific logical page types.

[0079] Being able to adjust the PV targets of the second programming distribution and the last programming distribution from a default PV target allows the PT operation to increase the amount of available margin or RWB for calibrating the memory cells over the lifetime of the memory cells. By increasing the amount of margin or RWB available for the PT operation, the PT operation can perform additional PV target adjustments (e.g., as described in the rule sets described herein). The additional PV target adjustments, including adjustments to the PV targets of the second programming distribution, the last programming distribution, or both, allow the memory device to better compensate for wear of its memory cells over the lifetime of the memory device, thereby increasing the endurance of the memory device.

[0080] In an embodiment, for the purpose of illustration and not limitation, as described above, the PT operation is described as balancing logical page types and equalizing valleys of a particular logical page type. It may be noted that in other embodiments, the PT operation may be used to control the BER of each logical page type to be different using a scaling factor. The PT operation may also be used to control the valley margin of a particular logical page type to be different using a scaling factor. Although the PT operation is described herein as balancing logical page types and equalizing valleys of a particular logical page type, aspects of the present disclosure may be used in the case where the PT operation uses a scaling factor to control the valley margin of a particular logical page type or the BER between logical page types. In addition, for the purpose of illustration and not limitation, aspects of the present disclosure are described with respect to QLC memory. It may be noted that aspects of the present disclosure may be applied to any multi-bit memory, such as TLC or other multi-bit memory.

[0081] Figure 3A-3B Graph 300 shows a valley 310A between a pair of adjacent programming distributions 308A and 308B. Graph 309 shows a valley 310B between a pair of adjacent programming distributions 308C and 308D. Valleys 310A-B may refer to a region between two adjacent distributions. Valley margins 306A-B may refer to a relative width or relative margin between adjacent programming distribution pairs. One or more of programming distributions 308A-308D are generally referred to herein as "programming distributions 308". One or more of valley margins 306A-306B are generally referred to herein as "valley margins 306". One or more of valleys 310A-310B are generally referred to herein as "valley 310".

[0082] The cRLC operation samples each logical page type in each WLG. Each sample may include three readings: a low sample 301 (also referred to herein as a "negative offset value"), a center sample 302 (also referred to herein as a "center value"), and a high sample 303 (also referred to herein as a "positive offset value"). As noted above, the cRLC operation calibrates or converges by obtaining the center value that results in the lowest bit error rate (BER) for a particular logical page type. Convergence refers to the value of the read level trimming that returns the least number of page or codeword errors. This is known as the calibration value or the centering value, and produces the best BER. In addition to finding the center of the valley 310, the cRLC operation also balances the side sampling (low sample 301 and high sample 303) so that the low sample 301 and the high sample 303 are equal in magnitude for a particular valley and other valleys associated with a particular logical page type. In some embodiments, the low sample 301 and the high sample 303 are equal in magnitude for all valleys of all logical page types (or for multiple logical page types). In some embodiments, for at least some valleys of a particular logical page type, the low sample 301 is equal in magnitude to the high sample 303. Graphs 300 and 309 show examples of calibrated valleys where the center sample 302 is balanced between the side samples (e.g., the amplitudes of the 4 side samples in both graphs 300 and 309 are approximately equal). Graph 309 exhibits wide valley behavior, while graph 309 exhibits narrow valley behavior. During cRLC sampling and updating, when the read level trim (e.g., adjustment register) is centered, the adjustment value will begin to "jitter." Any time a cRLC read level trim changes direction (increases the adjustment value, then decreases the adjustment value, or vice versa) it is considered jittering. This action of jittering indicates that the trim is centered. When the trim is jittering, the center value will be set.

[0083] The center sample 302 is used as a feedback metric by the PT to equalize the LP / UP / XP error rates by slightly moving the PV target. For example, the cRLC operation also obtains the center bit error count (CenterEC) by averaging the error counts of each trimmed center sample (e.g., read level threshold). However, the center sample 302 is sufficient to equalize the BER between logical page types (LP / UP / XP). The valley margins for each logical page type may also have a reasonable match. The default PV target may determine the depth of the valleys 310 between the programming distributions 308, which is related to the valley margin 306 for each valley 310.

[0084] In various embodiments, to determine the valley margin 306 of the programming distribution 308, the cRLC operation determines a value of a metric that indicates the width (or depth) between pairs of adjacent programming distributions 308. In some embodiments, the metric is a difference error, and the value of the metric is a Diff-EC (also referred to herein as a "Diff-EC measurement"). The difference error may be inversely proportional to the valley margin. For example, as illustrated, the Diff-EC of the graph 300 is less than the Diff-EC of the graph 309, and the valley margin 306A of the graph 300 is greater than the valley margin 306B of the graph 309. The cRLC operation may determine a Diff-EC measurement 304. The Diff-EC measurement 304 may be used to identify a relative valley margin. The Diff-EC measurement 304 may be the mean of the two side samples 301, 303 minus the center value 302. The PT operation can perform BER equalization by moving the PV target to match not only the error counts between logical page types (e.g., balance), but also the valley margins within each logical page type (or all logical page types) (e.g., equalization). It should also be noted that the valley margin can be related to the valley depth, e.g., from peak to valley between programming distributions. For example, a deep valley can be associated with a narrower valley margin than a shallow valley (e.g., a deeper valley) associated with a wider valley margin.

[0085] In some embodiments, when multiple valleys associated with a logical page are measured (UP and XP), the EC of the center sample 302 matches. In various embodiments, the center sample bit EC (also referred to as "center bit error count" or "CenterEC") can be the error count of the center sample 302 (e.g., the vertical axis of the graphs 300 and 309). Although the center sample EC matches, the valley margin (or depth) can be very different even within valleys of different logical page types (UP and XP). In order to determine which valley has the largest valley margin or the smallest valley margin, the measure of Diff-EC can be reliably used. The higher the Diff-EC measurement 304, the narrower the valley margin (or the smaller the RWB). For comparison purposes, the offsets between the low sample 301, the center sample 302, and the high sample 303 are equal for different Diff-EC measurement values ​​304. In some embodiments, the cRLC operation can maintain multiple samples (e.g., 16 samples) for each cRLC trim per die. Once all cRLC adjustments are centered, the center sample 302 (and corresponding CenterEC) and Diff-EC measurement 304 may be stored for subsequent execution of PT operations.

[0086] As explained, Figure 3A The example has a Diff-EC measurement value of 304. Figure 3BIn some embodiments, the programming distribution has a larger valley margin and is less desirable. The terms "more desirable" and "less desirable" refer to the relative valley margins applicable to valleys of the same logical page type within a WLG. In other words, the most desirable valley for a logical page type will be the valley that dominates the error count or causes more BER loss than any other valley. The Diff-EC measurement can be used to determine the more desirable and less desirable valleys, including the order of desirable (most desirable to least desirable). For example, for a particular logical page type, the valley with the largest Diff-EC is the most desirable valley (with the smallest valley margin) among the valleys for the particular logical page type. In another example, for a particular logical page type, the valley with the smallest Diff-EC is the least desirable valley (with the largest valley margin) among the valleys for the particular logical page type. When the TLC page stack page BER is balanced, LP (L3 / L4) will have the lowest RWB, UP (L1 / L2 and L5 / L6) will be higher and should be approximately equal, and XP (L2 / L3, L4 / L5, and L6 / L7) ​​will be the highest RWB. Thus, the valleys of LP will have the lowest valley margin, the valleys of UP will have higher valley margins, and the valleys of XP will have the highest valley margins. In various embodiments, a balanced BER causes the RWB to tend toward (e.g., equalize) approximately the same value as the RWB of the valleys of a particular logical page type, which occurs as a natural byproduct of the PT operation.

[0087] Figure 4 Eight distributions according to some embodiments of the present disclosure are described, including erase distributions after adjusting voltage according to PT operation. Figure 4 As illustrated, most of the data in each block is stored as TLC information, with each cell containing three bits. This is accomplished using an erase distribution 420 and seven program distributions 422-434. A lower logical page (LP) is defined by one read level threshold 436 (e.g., approximately centered between program distributions 426 and 428). An upper logical page (UP) is defined by two read level thresholds 438A and 438B (generally referred to herein as "read level thresholds 438"). An additional logical page (XP) is defined by a fourth read level threshold 440A-440D (generally referred to herein as "read level thresholds 440"). The erase distribution and program distributions 420-434 each correspond to levels (L0:L7), each level corresponding to one code (000:111).

[0088] In various embodiments, there is one valley between each pair of eight programming distributions 420-434, for a total of seven valleys (v1:v7). The center or peak of each programming distribution 420-434 corresponds to the PV target of the corresponding programming distribution 420-432. For a 3-bit representation, there may be a total of eight PV targets. In some embodiments, the erase distribution 420 corresponding to level L0 has an adjustable voltage to increase the valley margin of valley v1 when valley v1 is identified as the most desired valley. In some embodiments, the last programming distribution 434 corresponding to level L7 may have a fixed PV target and the erase distribution 420 may have an adjustable PV target, such as Figure 5A In some embodiments, both the erase distribution 420 and the final program distribution 434 corresponding to level L7 have adjustable positions, such as Figure 5B In some embodiments, the second programming profile 422 corresponding to the second level L1 has a fixed PV target, and the final programming profile 434 corresponding to the level L7 has an adjustable PV target, such as Figure 5C as shown in .

[0089] When a valley between a program distribution adjacent to an erase distribution (e.g., program distribution 422) is identified as the most desirable valley (e.g., valley V1 having the smallest valley width, highest DiffEC, and highest BER), aspects of the present disclosure allow the voltage of erase distribution 420 to be adjusted. Using PT operations, the voltage of the erase distribution can be adjusted, and in some cases, the PV targets of additional program distributions corresponding to levels L1-L7 can be adjusted. Figure 4 , programming distribution 420 has the lowest voltage level and is associated with the lowest PV target, and programming distribution 422 has the second lowest voltage level and the second lowest PV target. Programming distribution 434 has the highest voltage level and the highest PV target.

[0090] In the depicted embodiment, PT operation begins with each PV target in a default state defined by factory settings. In some cases, the voltage associated with the erase profile may be adjusted to produce an adjusted erase profile 420A (defined by Figure 4 . In some embodiments, the second PV target of the second programming distribution (L1) and the last PV target of the last programming distribution (L7) may be fixed, allowing for adjustment of intermediate PV targets. For example, using eight PV targets (of L0-L7), the L7 PV target may be fixed, while the other PV targets L1-L6 may receive characterized starting values, allowing for faster cRLC and PT operation transitions. Alternatively, the L1 PV target may be fixed, while the other PV targets L2-L7 may be adjusted. These factory settings of the PV targets and read level thresholds may produce undesirable BER results prior to cRLC and PT operations.

[0091] In some embodiments, a PT operation is defined as a net zero PV target adjustment mechanism. Net zero adjustment maintains a constant RWB for a memory cell. The total RWB of a memory cell of a multi-bit memory cell is constant, but the RWB between programming distributions can be adjusted by changing the PV target. Net zero adjustment manages PV target adjustment to achieve optimal BER and logical page type BER matching. The PT operation performs PV target adjustment to continuously balance the logical page type BER throughout the life of the memory device or memory system to improve the BER sum value. As described herein, the PT operation can be performed between programming passes of a multi-pass programming operation, such as after a first programming pass or a second programming pass. A cRLC calibration is performed in order to perform subsequent PT operations. The cRLC measures and collects the center bit error count (CenterEC) and Diff-EC information on the page stack, and passes the information to subsequent PT operations. Both cRLC and PT can be performed when a block is programmed, rather than after the block is fully programmed.

[0092] In an embodiment, during programming of a selected block for PT, the programming sequence is interrupted to perform cRLC. A programming interruption occurs on each logical page stack (selected as one of the cRLC logical page stacks). A logical page stack may refer to all logical page types for a particular multi-bit memory cell. A programming interruption occurs just before a second pass of programming when the first pass distribution has completely violated the floating gate coupled from its neighbors. During block programming, each of the cRLC page stacks in each of the word line groups is interrupted and cRLC is performed until all read level thresholds of the page stack are centered. The cRLC information from each valley, CenterEC, and Diff-EC is passed to the PT operation for determining the PV target adjustment according to the PT rules. The PV target adjustment will be applied to the next block programmed, and this process will be interrupted, and the cRLC / PT will continue and eventually jitter as the PT converges, and then track the NAND behavior. As described above, by adjusting the PV target, the PT effectively moves the programming distribution in the direction of the adjusted PV target. PT calibration (e.g., adjusting the PV target) may cause the valley margins of a particular logical page type to converge at a particular convergence value so that the valley margins of the particular logical page type are approximately the same. PT calibration may include balancing the BER of each logical page type so that each logical page type has a substantially similar BER. During PT PV target adjustment, when the value of the PV trim begins to "jitter" (any time the PV trim changes direction (increasing the trim value, then decreasing the trim value, or vice versa) is considered to be jittering), the PT operation of the corresponding programming distribution has converged.

[0093] The programming target offset is defined as the difference in position of the PV distribution relative to the default starting value. For example, the PV targets for L2 and L3 first tilt to the right by a certain amount (e.g., about 130mv), and then stop tilting and start shaking, which is stabilized (or calibrated). The valley after L3 is the L3 / L4 valley (v4), whose center value is the read level threshold 436 (corresponding to the LP read level). This movement is caused by balancing the BER of the LP page relative to the other logical pages. After many P / E cycles (e.g., about 40P / E cycles), all PV targets can stabilize. Since the operation alternates between LP / UP and LP / XP adjustments, with a maximum movement of 1 click (e.g., 10mv), it may take some time for the PV targets to stabilize. It is possible to characterize these offsets in many dies, resulting in a set of starting offsets that provide BER equalization at time zero.

[0094] As described herein, BER balancing can be performed as a net-zero adjustment. Figure 4 As illustrated in , a voltage step (e.g., 10 mv or some other voltage step) is given to one level (e.g., labeled +1), and a voltage step (10 mv) is taken from another level (e.g., labeled -1). Figure 4 In the example shown, one voltage step is taken from the erase distribution level (L0), and one voltage step is imparted to the second programming level (L1) 422A to increase the margin between L0 and L1 by two voltage steps (e.g., 20 mv or some other multiple of another voltage step). According to an embodiment, the shifting need not be integer based, such that if the desired result of the PT operation is to maintain a margin of 1 between L0 and L1, L0 may be shifted by -0.5 and L1 may be shifted by +0.5. The PT operation may adjust UP and XP (and TP in QLC memory) relative to LP, resulting in BER balance and RWB equalization for all three TLC logical page types (or all four logical page types in QLC memory). In various embodiments, more RWB may be allocated to higher distributions if required by undesirable NAND behavior (e.g., retention).

[0095] Figure 5AAn example rule set is illustrated according to an embodiment of the present disclosure, which corresponds to the adjustment of the voltage of the erase distribution (L0) and the locking of the PV target of the last program distribution (L15). Figure 500 illustrates the erase distribution (L0) and program distributions (L1-L15) of a QLC memory. The data in each block is stored as QLC information, with each cell containing 4 bits. This is achieved using sixteen program distributions 501A to 501P (generally referred to as "program distributions 501"). The lower logical page (LP) is defined by one read level threshold 502 (e.g., approximately centered between program distributions 501H and 501I). The upper logical page (UP) is defined by two read level thresholds 503A and 503B (generally referred to herein as "read level thresholds" 503). The additional logical page (XP) is defined by four read level thresholds 504A-504D (generally referred to herein as "read level thresholds" 504). The top logical page (TP) is defined by eight read level thresholds 505A-505H (generally referred to herein as "read level thresholds 505"). Sixteen programming distributions 501A-501P each correspond to a level (L0:L15), each level corresponding to a code (0001:1111).

[0096] In some embodiments, the code represents a gray code. Gray code refers to a binary number system in which two consecutive valleys differ by only one bit (e.g., a binary digit). It should be noted that in other embodiments, a different gray code may be used. Between each pair of sixteen programming distributions 501A-501P is a valley, for a total of fifteen valleys (V1:V15). Each of the valley values ​​(V0:V15) bits is between two adjacent programming distributions. For example, valley value 1 (V1) is between programming distributions 501A and 501B, and valley value fifteen (V15) is between programming distributions 501O and 501P. Each of the read level thresholds is centered in a corresponding valley value (V1:V15). For example, read level threshold 502 is centered in valley value eight (V8), read level threshold 505A is centered in valley value one (V1), and so on. The center or peak of each programming distribution 501A-501P corresponds to the PV target of the corresponding programming distribution 501A-501P. For a 4-bit representation, there may be a total of sixteen PV targets. In some embodiments, the first programming distribution 501A corresponding to the first level L0 has a fixed PV target. The second programming distribution 501B corresponding to the second level L1 has a fixed PV target, and the last programming distribution 501P corresponding to the sixteenth level L15 has an adjustable PV target. In some embodiments, the last programming distribution 501P corresponding to the sixteenth level L15 may have a fixed PV target, and the second programming distribution 501B corresponding to the second level L1 has an adjustable PV target. In some embodiments, both the second programming distribution 501B corresponding to the second level L1 and the last programming distribution 501P corresponding to the sixteenth level L15 have adjustable PV targets.

[0097] As described herein, aspects of the present disclosure allow the voltage of the erase distribution (L0) to be adjusted using a set of rules. Using PT operations, the PV targets of the intermediate programming distributions corresponding to levels L1-L15 can be adjusted. Diagram 500 illustrates increasing voltage levels from left to right. For example, the programming distribution adjacent to the erase distribution corresponding to the lowest PV target is also referred to herein as the "second programming distribution". The programming distribution corresponding to the highest PV target (e.g., programming distribution 501P) is also referred to herein as the "last programming distribution".

[0098] Rule set 510 illustrates rules that allow the voltage of the erase distribution to be moved, the second program distribution (L1) to be moved, and finally the program distribution (L15) to be locked. It can be appreciated that the movement of the voltage of the erase distribution and the movement of the PV target associated with a particular program distribution effectively causes the erase and program distributions to move in the same direction and by the same magnitude as the movement of the voltage and PV targets. Rule set 510 illustrates rules for performing a program target operation (e.g., PT calibration). Rule set 510 allows a program target setting operation to move the voltage of the erase distribution and identify the PV target to be moved (if any) and the direction and magnitude to move the identified PV target. As noted above, the program target setting operation implements a rule set to balance logical page types so that the bit error rate (BER) is approximately the same BER for different logical page types, and equalize the relative width of valleys for a particular logical page type so that the read window budget (RWB) of valleys for a particular logical page type is approximately the same RWB.

[0099] BER equalization may be performed as a net-zero adjustment. The programming target setting operation may adjust UP, XP, and TP relative to LP, thereby achieving equalization for all four QLC logical page types. For example, the valley margin of LP may be reduced by one voltage step (e.g., -10 mV), while the valley margin of XP may be increased by one voltage step (+10 mV) (or vice versa) such that a net-zero adjustment is performed. Column 511 illustrates a rule set for TP-LP adjustment such that TP is adjusted relative to LP with a net-zero adjustment as described above. Rule set 510 includes sixteen rules illustrated by cases 1-16. Note that rules and cases are used interchangeably herein. In QLC memory, the TP page corresponds to the second and last programming distributions, whose PV target adjustment issues are addressed in cases 1-16 of rule set 510. It may be noted that for TLC memory, XP corresponds to the second and last programming distributions. A set of rules for XP-LP in TLC memory that adjusts the second programming distribution and the last programming distribution corresponding to XP of TLC memory can be implemented according to aspects of the present disclosure. In the disclosed embodiments, QLC memory is described for purposes of illustration and not limitation. Aspects of the present disclosure can also be applied to different multi-bit memory cells, such as TLC memory, etc.

[0100] In some embodiments, to perform a program target setting operation to calibrate one or more PV targets associated with the programming distribution 501 of the memory cells, a rule may be selected from a rule set 510. The rule may determine the PV target to be adjusted and the magnitude and direction of the adjustment (e.g., ±10 mV). Figure 5A The described operation can be performed by Figure 1AIn some embodiments, to select a rule from a set of rules, the programming goal setting component 113 identifies that the valley between L0 and L1 is most desirable (according to column 512), and adjusts the voltage of the erase distribution (L0), as represented by -1 in table 510.

[0101] In the example shown in case number 1 of table 510, the programming target setting component 113 can identify the valley of TP with the highest Diff-EC (e.g., V1) compared to the other valleys. In addition, the programming target setting component 113 can also determine the valley of LP with the lowest Diff-EC (V8) (e.g., note that LP is associated with only one valley, which can be considered that the valley of LP has the highest or lowest Diff-EC). A rule that increases the valley margin of V1 by increasing the voltage of the erase distribution (L0) while locking the PV target of L8 can be identified from the rule set 510. The selected rule can identify the PV target and the magnitude to be adjusted and the direction of the adjustment, and the programming target setting component 113 can adjust the PV target according to the identified rule.

[0102] In some embodiments, to select a rule from the rule set 510, the programming goal setting component 113 identifies a first logical page type and a second logical page type. For example, in a QLC memory, the programming goal setting component 113 may identify TP and LP. In some embodiments, for QLC memory, the programming goal setting component 113 may identify two logical page types as one of the following: TP-LP, XP-LP, and UP-LP. It may be noted that in some embodiments, the selection of the two logical page types may be based on a particular order. For example, the programming goal setting component 113 may adjust TP-LP, then XP-LP, then UP-LP, and so on. It should also be noted that different rule sets may be used for XP-LP and UP-LP.

[0103] In some embodiments, to select a rule from the rule set 510, the programming target setting component 113 determines whether the BER for the first logical page type (e.g., LP) is less than or greater than the BER for the second logical page type (e.g., TP). In some embodiments, to determine whether the BER of the first logical page type is less than or greater than the BER of the second logical page type, the programming target setting component 113 compares the first average center bit error count (CenterEC) of the first logical page with the second average center bit error count (CenterEC) of the second logical page type. The average CenterEC for a particular page type indicates the BER of the particular logical page type. In one example, the average CenterEC of LP can be compared with the average CenterEC of TP. If the first average CenterEC is less than the second average CenterEC, the BER of the first logical page type (e.g., LP) is less than the BER of the second logical page type (TP). If the first center bit error count (e.g., average CenterEC) is greater than the second center bit error, the BER of the first logical page type (e.g., LP) is greater than the BER of the second logical page type (e.g., TP) count (e.g., CenterEC).

[0104] In some embodiments, in response to determining that the BER of the first logical page type (e.g., LP) is less than the BER of the second logical page type (e.g., TP), the programming target setting component 113 identifies a first subset of the rule set 510 (e.g., LP < TP). The selected rule is from the first subset of rules. For example, the column "average CenterEC" illustrates the first subset of rules (e.g., cases 1 - 8) to be applied when the BER of LP (e.g., lower average CenterEC) is less than the BER of TP (e.g., higher average CenterEC).

[0105] In some embodiments, in response to determining that the BER of the first logical page type (e.g., LP) is greater than the BER of the second logical page type (e.g., TP), the programming target setting component 113 identifies a second subset of the rule set 510 (e.g., TP < LP). The selected rule is from the second subset of rules. For example, the column "average CenterEC" illustrates the second subset of rules (e.g., cases 9 - 16) to be applied when the BER of LP (e.g., higher average CenterEC) is greater than the BER of TP (e.g., lower average CenterEC).

[0106] In some embodiments, after identifying the subset of rules, the programming goal setting component 113 can select a rule from the identified subset of rules. In some embodiments, to identify a rule from a first subset of rules (e.g., cases 1-16), the programming goal setting component 113 identifies a rule from the first subset of rules based on a valley value (V8) with a maximum margin for a first logical page type (e.g., LP) and a valley value with a minimum margin for a second logical page type (e.g., TP). In some embodiments, one or more difference error counts are used to determine the valley value with a maximum margin for the first logical page type (e.g., LP) and the valley value with a minimum margin for the second logical page type (e.g., TP).

[0107] In some embodiments, to identify a rule from the second subset of rules (e.g., cases 21-28), programming goal setting component 113 identifies a rule from the second subset of rules based on a valley value having a maximum margin for the second logical page type (e.g., TP) and a valley value having a minimum margin for the first logical page type (e.g., LP). In some embodiments, one or more difference error counts are used to determine the valley value having a maximum margin for the second logical page type (e.g., TP) and the valley value having a minimum margin for the first logical page type (e.g., LP).

[0108] Columns 512 and 513 of rule set 510 illustrate the "necessity" of valleys for a particular logical page type. Necessity is based on the Diff-EC measurement. For a particular valley of a logical page type, a lower Diff-EC measurement means that the particular valley has a larger valley margin and is less desirable than another valley of the same logical page type with a higher Diff-EC measurement. The terms "more desirable" and "less desirable" refer to the relative valley margins of valleys of the same logical page type. In other words, the most desirable valley for a logical page type will be the valley that leads to the dominant error count (CenterEC) or causes more BER loss than any other valley of the same logical page type. The Diff-EC measurement can be used to determine more desirable and less desirable valleys, including an order of desirability (most desirable to least desirable). For example, for a particular logical page type, the valley with the largest Diff-EC is the most desirable valley (e.g., has the smallest valley margin) among the valleys of that particular logical page type. In another example, for a particular logical page type, the valley with the smallest Diff-EC is the least desirable valley (eg, having the largest valley margin) among the valleys for the particular logical page type.

[0109] As noted above, the programming target setting operation calibrates the memory cells by balancing the logical page types such that the BER is approximately the same among the logical page types. To balance the BER, some of the RWBs of the logical page type with a lower BER are given to other logical page types with a higher BER. In Figure 5A In the example of Case 1 shown, the voltage of the erase distribution that has been reduced to increase the margin of the most needed valley of the logical page type with a higher BER (e.g., L1) is increased with a net zero adjustment. It may be noted that since the BER of the LP is less than the BER of the TP, the first subset of the set of rules includes the rule of giving the RWB to the TP with a net zero adjustment and obtaining the RWB from the LP. In the case where the BER of the LP is greater than the BER of the TP, the second subset of the rules includes the rule of giving the RWB to the LP with a net zero adjustment and obtaining the RWB from the TP.

[0110] In one example, the programming target setting component 113 identifies the LP and the TP as the two logical page types for which the programming target setting operation is to be performed. The programming target setting component 113 identifies the set of rules 510 that is applicable to performing the programming target setting operation (e.g., LP-TP update) on the LP and TP logical page types. The programming target setting component 113 determines that the BER for the LP is less than the BER for the TP. To make the above determination, the programming target setting component 113 determines that the average CenterEC of the LP is less than the average CenterEC of the TP. The average CenterEC of the LP being less than the average CenterEC of the LP indicates that the BER of the LP is less than the BER of the TP. By determining that the average CenterEC of the LP is less than the average CenterEC of the TP, the programming target setting component 113 identifies the first subset of the set of rules 510 that is applicable in the case where the BER of the LP is less than the BER of the TP (e.g., LP < TP, which identifies Cases 1-8). To identify a specific rule from Cases 9-20, the programming target setting component 113 identifies the most needed valley of the TP and the least needed valley of the LP. The most needed valley of the TP is the valley among all the valleys of the TP that has the smallest relative width (e.g., the smallest margin) and the highest Diff-EC. The least needed valley of the LP is the valley among all the valleys of the LP that has the largest relative width (e.g., the largest margin) and the lowest Diff-EC. In a specific case, the valley one (V1) of the TP has the highest Diff-EC among all the valleys of the TP and is the most needed valley, while the valley eight (V8) of the LP has the lowest Diff-EC among all the valleys of the LP and is the least needed valley. Under the above conditions, column 513 can be identified as the rule in the first subset of the set of rules 510 to be applied (e.g., see columns 512 and 513 indicating the combination of the most needed valley and the least needed valley).

[0111] In case 1 of rule set 510, a voltage step (e.g., 10 mv) is taken from the erase distribution (labeled as -1) and a voltage step (e.g., 10 mv) is assigned to the PV targets (e.g., labeled as +1) of the program distributions L1:L7. The program distributions L1:L7 are moved in an accordion fashion such that all PV targets of the program distributions (L1:L7) are moved in the same direction and by the same magnitude. It can be noted that in case 1, as the PV target of the program distribution L1 is moved to the right and the erase distribution is moved to the left, a RWB is assigned to the valley 1 (V1) of the TP. The relative width (or RWB) of the valleys V2:V7 is unchanged because all PV targets for the program distributions L1:L7 are shifted to the right by the same magnitude and direction (e.g., by +10 mV). The corresponding valleys V2:V7 are shifted to the right by corresponding amounts, but the relative widths are unchanged. When the PV target of programming profile L7 is moved to the right and the PV target of programming profile L8 is kept fixed, the RWB is taken from valley 8 (V8) of LP. Valley 8 (V8) of LP is squeezed to give margin to valley 1 (V1) of TP with a net zero adjustment.

[0112] In one embodiment, case 9 of rule set 510 is the opposite of case 1. In case 9, the BER of LP is greater than the BER of TP. The most desired valley of LP is valley 8 (V8) of LP, while the least desired valley of TP is valley 1 (V1). In case 9, a voltage step (e.g., 10 mv) is taken from the erase distribution and the PV target (e.g., labeled -1) of the program distribution L1:L7. The program distribution L1:L7 is moved in an accordion-like manner such that the PV targets of the erase distribution (L0) and the program distribution (L1:L7) move in the same direction and by the same magnitude. It can be noted that in case 9, as the PV target of the program distribution L1 moves to the left, the RWB is taken from valley 1 (V1) of TP. The relative widths (or RWBs) of the valleys V2:V7 do not change because the PV targets of the erase distribution and the program distribution L1:L7 move in the same direction and by the same magnitude (e.g., left by -10 mV). The corresponding valleys V2:V7 are simply shifted to the left by corresponding amounts, but the relative widths remain unchanged. When the PV target of programming distribution L7 is shifted to the left (e.g., 10 mV) and the PV target of programming distribution L8 remains fixed, RWB is assigned to valley 8 (V8) of LP. Valley 1 (V1) of TP is reduced, thereby assigning margin to valley 8 (V8) of LP with a net zero adjustment.

[0113] In one embodiment, rule set 510 is a rule in which program distribution L15 is locked so that the PV target of program distribution L15 is not adjusted by a program target setting operation. The blank space placed in the column designated by "L15" is used to illustrate that the PV target of program distribution L15 is not allowed to be adjusted during a program target setting operation according to rule set 510.

[0114] Figure 5B A set of rules corresponding to adjustment of the PV target of a last programmed distribution and locking of the PV target of a programmed distribution adjacent to an initial programmed distribution is described in accordance with an embodiment of the present disclosure. Figure 5A Figure 500 helps illustrate Figure 5B Unless otherwise described, rule set 520 may be implemented similarly to rule set 510. Rule set 520 illustrates a rule set that can move the position of the erase distribution and allow adjustment of the PV targets of the second distribution (L1) and the last distribution (L15). In an embodiment, rule set 520 may be implemented as a replacement for other rule sets of cases 1-16, as described herein. Several rules (i.e., cases) of rule set 520 are described below to help illustrate an implementation using rule set 520.

[0115] In case 1 of rule set 520, the BER of LP is less than the BER of TP. The most desired valley 512 of TP is valley v1, and the most desired valley 513 of LP is valley v8. The voltage of the erase distribution takes a voltage step (e.g., -10mv) to provide additional margin for the most desired valley v1. The program distribution L1:L7 is moved in an accordion-like manner so that all PV targets of the program distribution (L1:L7) move in the same direction and by the same magnitude.

[0116] In one embodiment, in case 8, RWB does not assign any valleys, but assigns additional margin to the programming distribution (L15) away from the top voltage level limit. Shifting the programming distribution L15 to the left (-10 mV) assigns additional margin between the programming distribution L15 and the highest voltage level limit. The relative width (or RWB) of the valleys V9:V15 is unchanged because all PV targets for programming distributions L8:L15 are shifted to the left by the same magnitude and direction (e.g., -10 mV to the left). The corresponding valleys V9:V15 are shifted to the left by corresponding amounts, but the relative widths are unchanged. When the PV target of programming distribution L8 is shifted to the left and the PV target of programming distribution L7 remains fixed, the RWB is taken from valley 8 (V8) of LP. Valley 8 (V8) of LP is reduced, thereby assigning margin between the last programming distribution of TP and the highest voltage level limit with a net zero adjustment.

[0117] exist Figure 5B, it can be noted that case 16 of rule set 520 is the opposite of case 8. In case 16, the BER of LP is greater than the BER of TP. The most desired valley value for LP is 8 (V8), while the least desired valley value for TP is valley value 15 (V15). In case 16, a voltage step (e.g., +10 mv) is given to the PV targets (e.g., labeled +1) of programming distribution L8:L15. Programming distribution L8:L15 moves in an accordion-like manner such that all PV targets of programming distribution L8:L15 move in the same direction and by the same magnitude. It can be noted that in case 16, as the PV target of programming distribution L15 moves to the right, the RWB is taken from the margin between programming distribution L15 and the highest voltage level limit. The relative width (or RWB) of valley values ​​V9:V15 does not change because all PV targets of programming distribution L8:L15 move in the same direction and by the same magnitude (e.g., right by +10 mV). When the PV target of program distribution L8 is moved rightward (e.g., +10 mV) and the PV target of program distribution L7 is kept fixed, RWB is assigned to valley 8 (V8) of LP. The margin between program distribution L15 of TP and the highest voltage level limit is squeezed, thereby assigning margin to valley 8 (V8) of LP with a net zero adjustment.

[0118] exist Figure 5B , it can also be noted that rule set 520 includes rules (e.g., for cases 1 and 9) that do not lock program distributions L1 and L15, but adjust the positions of erase distributions to provide additional margin to the most needed valleys (e.g., valley v1 in case 1 and valley v8 in case 9). The blank space in each column of table 520 is used to illustrate that the PV target of the corresponding program distribution was not adjusted during the program target setting operation.

[0119] Figure 5C A rule set according to an embodiment of the present disclosure is described, which corresponds to the case where the voltage of the erase distribution and the PV target of the last program distribution are adjustable while the PV target of the second program distribution (L1) is locked. Figure 5A Figure 500 helps illustrate Figure 5C Unless otherwise described, rule set 530 may be implemented similarly to rule set 510 or rule set 520. Rule set 530 shows a rule set in which the PV target of the second distribution (L1) is locked and the voltage of the erase distribution and the PV target of the last distribution (L15) are allowed to be adjusted. Several rules (i.e., cases) of rule set 530 are described below to help illustrate an implementation using rule set 530. According to Rule 1, based on determining that valley v1 is the most desired, the voltage of the erase distribution is reduced (as represented by -1 in table 530) to increase the valley margin of valley v1. Similarly, in case 9, based on determining that valley v8 is the most desired valley and valley v1 is the least desired valley, the voltage of the erase distribution is reduced.

[0120] Figure 6 6 is a flow chart of an example method 600 for performing dynamic program erase target setting with a bit error rate (BER) according to various embodiments. The method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1A 110 and other logic of the memory subsystem 110. Although shown in a particular order or sequence, the order of the processing procedures may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processing flows are possible.

[0121] Before method 600 begins, processing logic may perform erase, program, cRLC operations, and reads with factory default trim values, for example, as initial pre-operations. Processing logic may then measure the BER to establish a baseline BER that may be used to determine a BER control value for comparing future BER measurements.

[0122] At operation 610, processing logic determines a set of difference error counts (e.g., Diff-EC) corresponding to a plurality of programming distributions of a memory array (610). In some embodiments, to determine one or more difference error counts for difference errors, processing logic performs a cRLC operation on the memory cells to calibrate the read level thresholds between programming distributions.

[0123] At operation 620, processing logic identifies a valley margin corresponding to a programming distribution based on a comparison of a set of difference error counts. In one embodiment, a programming distribution adjacent to an erased distribution (i.e., Figure 4 In one embodiment, the processing device identifies the valley associated with the lower page (LP) as having the lowest valley margin (i.e., the most desired valley), such as the valley between program distribution L7 and program distribution L8, based on a comparison of the difference error counts corresponding to the respective program distributions. In one embodiment, the processing device determines that the valley between the erase distribution (L0) and the second program distribution (L1), i.e., valley v1, has the highest relative difference error count, and the result indicates the most desired valley.

[0124] At operation 630, processing logic selects a programming target setting rule from a set of rules based on the value of the valley margin. In some embodiments, to select the rule from the set of rules based on the value of the valley margin, processing logic selects a rule from the set of rules that identifies at least two program verification (PV) targets that describe adjustments that reduce a relative width of a valley with a lowest difference error count (Diff-EC) for a first logical page type and increase a relative width of a valley with a highest Diff-EC for a second logical page type relative to the valley with a lowest difference error count (Diff-EC). Figure 7 and FIG. 5A to FIG. 5C Further describes selecting a rule from a rule set.

[0125] At operation 640, processing logic performs a program erase target setting operation based on the program target setting rule to adjust the voltage level associated with the erase distribution of the memory array. In one embodiment, the program erase target setting operation calibrates the memory cells of the memory array by adjusting the voltage level of the erase distribution and the voltage levels of one or more PV targets associated with other program distributions (e.g., L1-L15), as shown in FIG. Figures 3A to 5C In one embodiment, performing a program erase target setting operation includes lowering a voltage level associated with an erase distribution to increase a margin of valleys between the erase distribution and a program distribution adjacent to the erase distribution. In another embodiment, performing a program erase target setting operation includes increasing a voltage level associated with the erase distribution to decrease a margin of valleys between the erase distribution and a program distribution adjacent to the erase distribution. In various embodiments, the adjustment of the erase distribution voltage level may be performed once each time a certain number of adjustments are performed on one or more PV targets of other program distributions (e.g., L1-L15), for example, once when 10, 20, 25 adjustments are performed on such PV targets.

[0126] At operation 650, processing logic determines a bit error rate (BER) for the memory array. The BER may be calculated from the number of bit errors detected in an error correction code (ECC) codeword divided by the total number of bits in the codeword. The calculated BER may include the bit error count for a single codeword, a mean or median for multiple codewords, or may include only codewords for a particular page or page type.

[0127] At operation 660, processing logic determines whether the BER satisfies the BER control value. In one embodiment, before placing the system into operation, processing logic also determines a baseline BER based on a factory default trim value and sets the BER control value to be a certain percentage above the baseline BER. In different embodiments, the BER control value may be set by the customer or the manufacturer and may be reprogrammed at a later time to drive the system according to a different BER control value. Figure 6 acceptable BER in the control loop.

[0128] At operation 665, in response to the BER satisfying the BER control value, processing logic decreases the voltage level of the erase distribution by a certain voltage step. Satisfying the BER control value may include being greater than the BER control value. In contrast, at operation 670, in response to the BER not satisfying the BER control value, processing logic increases the voltage level by the voltage step. In an embodiment, not satisfying the BER includes being less than or equal to the BER control value.

[0129] At operation 675, processing logic determines whether the voltage level of the erase distribution has reached equilibrium. Equilibrium can be detected when the voltage level moves in one direction for a period of time (e.g., increasing), and then begins to move in the opposite direction (e.g., decreasing), or begins to fluctuate around a voltage level within a range of voltage levels. If the voltage level has not reached equilibrium, processing logic can continue to repeat the control loop defined by the program target setting operations 610 to 660. This control loop (returning to the program target setting operations of method 600) can include performing each loop after performing between tens to hundreds of program / erase cycles on the memory cells.

[0130] At operation 680, if the voltage level of the erase distribution has reached equilibrium, the processing logic may dither the voltage level to change between plus or minus one voltage step during each subsequent cycle after equilibrium of the voltage level is reached. For clarity, subsequent cycles (after equilibrium is reached) are illustrated with dashed lines, where operations 610 to 640 are repeated between dithering the voltage level between plus or minus one voltage step. In this way, the balance of the voltage level of the erase distribution is maintained while performing additional program target setting updates to one or more valley margins of the program distribution.

[0131] Figure 7 700 is a flow chart of an example method 700 for performing a memory quality test using one or more read voltage levels according to various embodiments. The method 700 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, specialized logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 700 is performed by a controller 115 (e.g., Figure 1A The programming target setting component 113 of the memory subsystem 110 is executed by other logic of the memory subsystem 110 as appropriate. Although shown in a specific order or sequence, the order of the processing procedures can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processing flows are possible.

[0132] Before method 700 begins, processing logic may perform erase, program, cRLC operations, and reads with factory default trim values, for example, as initial pre-operations. Processing logic may then measure the BER to establish a baseline BER that may be used to determine a BER control value for comparing future BER measurements.

[0133] At operation 710, processing logic presets a voltage level of an erase distribution of a memory array to be higher than a default value. The memory array includes memory cells of, for example, a first logical page type and a second logical page type. In one example, the first logical page type and the second logical page type are different logical page types. For example, in a QLC memory, the first logical page type may be LP and the second logical page type may be TP, or vice versa. Presetting the voltage level of the erase distribution to a higher voltage will cause a first valley (V1) margin between the erase distribution and the level one (L1) distribution to be reduced (see Figure 2 , 4 ). The higher voltage in turn results in a higher BER for the page type that includes this valley, and generally causes method 700 to branch through operation 770 rather than operation 765, as discussed in more detail below.

[0134] At operation 720, processing logic determines a set of difference error counts corresponding to a plurality of programming distributions of the first logical page type. In one embodiment, operation 720 is performed simultaneously with operation 610 ( Figure 6 ) is the same or similar. Operation 720 may also be viewed as the first operation of a plurality of programming target setting operations of a control loop, as will be discussed in more detail.

[0135] At operation 730, processing logic identifies a plurality of valley margins corresponding to a programming distribution based on the comparison of the set of difference error counts. In one embodiment, operation 730 is performed simultaneously with operation 620 ( Figure 6 ) are the same or similar.

[0136] At operation 740, processing logic adjusts the values ​​of at least some of the valley margins a plurality of times to equalize the relative valley margins of the first logical page type so that the read window budget (RWB) of the valleys of the first logical page type is substantially the same RWB. The plurality of times may be a predetermined number of DPT updates, such as three times, five times, six times, etc. Although operation 740 focuses on equalizing the RWB of the valleys of the first logical page type, operation 740 may also or alternatively include equalizing the RWB of the valleys of the second logical page type. Figures 2 to 5CEqualizing the RWB of valleys by adjusting the width of valley margins is discussed in detail. Furthermore, while operation 740 focuses on equalizing the RWB of valleys of a first logical page type, operation 740 may also or alternatively include balancing the BER between the first logical page type and the second logical page type such that the BER of each of these logical page types is approximately the same. Also refer to Figures 2 to 5C Balancing the BER between logical page types is discussed in detail.

[0137] At operation 750, processing logic determines a bit error rate (BER) for the memory array. The BER may be calculated from the number of bit errors detected in an error correction code (ECC) codeword divided by the total number of bits in the codeword. The calculated BER may include the bit error count for a single codeword, a mean or median for multiple codewords, or may include only codewords for a particular page or page type.

[0138] At operation 760, processing logic determines whether the BER satisfies the BER control value. In one embodiment, before placing the system into operation, processing logic also determines a baseline BER based on a factory default trim value and sets the BER control value to a certain percentage above the baseline BER. In different embodiments, the BER control value may be set by the customer or manufacturer and may be reprogrammed at a later time to drive the system according to a different BER control value. Figure 7 acceptable BER in the control loop.

[0139] At operation 765, in response to the BER satisfying the BER control value, the processing logic decreases the voltage level by a certain voltage step. Satisfying the BER control value may include being greater than the BER control value. In contrast, at operation 770, in response to the BER not satisfying the BER control value, the processing logic increases the voltage level by the voltage step. In an embodiment, not satisfying the BER includes being less than or equal to the BER control value.

[0140] At operation 775, processing logic determines whether the voltage level of the erase distribution has reached equilibrium. Equilibrium may be detected when the voltage level moves in one direction for a period of time (e.g., increasing), and then begins to move in the opposite direction (e.g., decreasing), or begins to fluctuate around a voltage level within a range of voltage levels. If the voltage level has not reached equilibrium, processing logic may continue to repeat the control loop defined by program target setting operations 720 to 770 (assuming, in one embodiment, that operation 765 is skipped because the BER in each cycle does not satisfy the BER control value). This control loop (returning to the program target setting operation of method 700) may include performing each cycle after performing between tens to hundreds of program / erase cycles on the memory cells.

[0141] In some embodiments, repetition of this control loop (operations 720-770) may be further performed with reference to the second logical page type, and in some embodiments may further include balancing the BER between the first logical page type and the second logical page type each time through the multiple adjustments to the valley margin.

[0142] At operation 780, if the voltage level of the erase distribution has reached equilibrium, the processing logic may dither the voltage level to change between plus or minus one voltage step during each subsequent cycle after equilibrium of the voltage level is reached. For clarity, subsequent cycles (after equilibrium is reached) are illustrated with dashed lines, where operations 720 to 740 are repeated between dithering the voltage level between plus or minus one voltage step. In this way, the balance of the voltage level of the erase distribution is maintained while performing additional program target setting updates to one or more valley margins of the program distribution.

[0143] Figure 8 An example machine of a computer system 800 is illustrated in which a set of instructions may be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1A-1B 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A-1B 110) or can be used to perform operations of the controller 115 (e.g., execute an operating system to execute operations corresponding to Figure 1A In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0144] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, an automobile, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0145] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0146] The processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 may further include a network interface device 808 to communicate over a network 820.

[0147] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. The instructions 826 may also reside, in whole or in part, within the main memory 804 and / or within the processing device 802 during execution thereof by the computer system 800, the main memory 804 and the processing device 802 also constituting machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or the main memory 804 may correspond to Figure 1A-1B Memory subsystem 110.

[0148] In one embodiment, instructions 826 include implementing a command corresponding to an error determination component (e.g., Figure 1A The functional instructions of the programming target setting component 113 of the present invention are provided. Although the machine-readable storage medium 824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0149] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is an operation that requires physical control of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0150] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0151] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0152] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0153] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0154] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It should be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: a memory array comprising a plurality of memory cells; as well as a processing device coupled to the memory array and performing a program target setting operation on the memory array, wherein to perform the program target setting operation, the processing device: determining a set of difference error counts corresponding to a plurality of programming distributions of the memory array; identifying a plurality of valley margins corresponding to the plurality of programming distributions based on a comparison of the set of difference error counts; selecting a programming target setting rule from a set of rules based on values ​​of the plurality of valley margins; performing a program erase target setting operation to adjust a voltage level associated with an erase distribution of the memory array based on the program target setting rule; determining a bit error rate BER of the memory array; In response to the BER being greater than a BER control value, reducing the voltage level by a certain voltage step; as well as In response to the BER being less than or equal to the BER control value, the voltage level is increased by the voltage step.

2. The system of claim 1 , wherein the processing device further determines a baseline BER based on a factory default trim value before placing the system into operation, wherein the processing device further sets the BER control value to be a certain percentage above the baseline BER.

3. The system of claim 1, wherein the processing device further: Repeating the program target setting operation as a loop until equilibrium of the voltage levels is reached; and After the equilibrium of the voltage levels is reached, the voltage levels are dithered to vary between plus or minus one voltage step during each subsequent cycle.

4. The system of claim 3, wherein the processing device performs each cycle after performing between tens to hundreds of program / erase cycles on the plurality of memory cells.

5. The system of claim 1, wherein the BER is based on one of a mean or a median of a single codeword or multiple codewords. 6 . The system of claim 1 , wherein the programming target setting rules include locking a PV target for a programming distribution corresponding to a highest program verification PV target. 7 . The system of claim 1 , wherein the processing device further adjusts one or more program verify PV targets of one or more of the plurality of programming profiles based on the programming target setting rule.

8. The system of claim 1 , wherein the program erase target setting operation is to implement the program target setting rule to further balance logical page types so that the BER is approximately the same BER for different logical page types, and balance relative valley margins of specific logical page types so that the read window budget (RWB) of valleys of the specific logical page types is approximately the same RWB.

9. A method comprising: Presetting, by a processing device, a voltage level of an erase distribution of a memory array to be higher than a default value, the memory array comprising a plurality of memory cells of a first logical page type and a second logical page type; as well as The processing device performs a programming target setting operation, wherein the programming target setting operation includes: determining a set of differential error counts corresponding to a plurality of programming distributions of the first logical page type; identifying a plurality of valley margins corresponding to the plurality of programming distributions based on a comparison of the set of difference error counts; adjusting values ​​of at least some of the plurality of valley margins multiple times to equalize relative valley margins of the first logical page type so that a read window budget RWB of valleys of the first logical page type is substantially the same RWB; determining a bit error rate BER of the memory array; and In response to the BER being less than or equal to a BER control value, the voltage level is increased by a voltage step.

10. The method according to claim 9, further comprising: Prior to placing a memory device including the memory array into operation, determining a baseline BER based on a factory default trim value; as well as The BER control value is set to be a certain percentage above the baseline BER.

11. The method of claim 9, wherein the plurality of times comprises a preset number of updates, the method further comprising: Repeating the program target setting operation as a loop until a balance of the voltage levels is reached; during any given cycle, in response to the BER being greater than the BER control value, reducing the voltage level by the voltage step; as well as After the equilibrium of the voltage levels is reached, the voltage levels are dithered to vary between plus or minus one voltage step during each subsequent cycle.

12. The method of claim 11, wherein repeating the program target setting operation as a loop comprises performing each loop after performing between tens to hundreds of program / erase cycles on the plurality of memory cells.

13. The method according to claim 9, further comprising: Before executing v) and vi): for each of the plurality of times, repeating the programming target setting operation for the second logical page type; as well as For each of the multiple times, the BER is balanced between the first logical page type and the second logical page type.

14. The method according to claim 13, further comprising: Repeating the program target setting operation as a loop until a balance of the voltage levels is reached; during any given cycle, in response to the BER being greater than the BER control value, reducing the voltage level by the voltage step; as well as After the equilibrium of the voltage levels is reached, the voltage levels are dithered to vary between plus or minus one voltage step during each subsequent cycle.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform a programming target setting operation, the programming target setting operation comprising: determining a set of difference error counts corresponding to a plurality of programming distributions of a memory array, the memory array comprising a plurality of memory cells; identifying a plurality of valley margins corresponding to the plurality of programming distributions based on a comparison of the set of difference error counts; selecting a programming target setting rule from a set of rules based on values ​​of the plurality of valley margins; performing a program erase target setting operation to adjust a voltage level associated with an erase distribution of the memory array based on the program target setting rule; determining a bit error rate BER of the memory array; In response to the BER being greater than a BER control value, reducing the voltage level by a certain voltage step; as well as In response to the BER being less than or equal to the BER control value, the voltage level is increased by the voltage step.

16. The non-transitory computer-readable storage medium of claim 15, wherein the programming target setting operation further comprises: Prior to placing a memory device including the memory array into operation, determining a baseline BER based on a factory default trim value; as well as The BER control value is set to be a certain percentage above the baseline BER.

17. The non-transitory computer-readable storage medium of claim 15, wherein the programming target setting operation further comprises: Repeating the program target setting operation as a loop until a balance of the voltage levels is reached; as well as After the equilibrium of the voltage levels is reached, the voltage levels are dithered to vary between plus or minus one voltage step during each subsequent cycle.

18. The non-transitory computer-readable storage medium of claim 17, wherein repeating the program target setting operation as a loop comprises performing each loop after performing between tens to hundreds of program / erase cycles on the plurality of memory cells.

19. The non-transitory computer-readable storage medium of claim 15, wherein a valley having a lowest valley margin among the plurality of valley margins is located between the erase distribution and a programming distribution adjacent to the erase distribution, and wherein performing the program erase target setting operation comprises reducing the voltage level associated with the erase distribution to increase a margin of the valley between the erase distribution and the programming distribution adjacent to the erase distribution.

20. The non-transitory computer-readable storage medium of claim 15, wherein a valley having a lowest valley margin among the plurality of valley margins is located between the erase distribution and a program distribution adjacent to the erase distribution, and wherein the program target setting operation further comprises determining that the valley having the lowest valley margin is associated with a highest difference error count among the set of difference error counts.

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