Intelligent Memory Device Test Resources

Abstract

The present disclosure relates to intelligent memory device test resources. A memory device test resource includes a dedicated processing device of the memory device test resource, the dedicated processing device being configured to facilitate testing of a memory device of a memory subsystem coupled to the memory device test resource. The memory device test resource further includes: a memory subsystem interface port coupled to the dedicated processing device and configured to couple the memory device test resource to the processing device; a test condition component coupled to the dedicated processing device and configured to generate test conditions at the memory device test resource; and a test resource monitoring component coupled to the dedicated processing device and configured to monitor one or more conditions at the memory device test resource.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to intelligent memory device test resources. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, the present disclosure relates to a memory device test resource, including: a dedicated processing device of the memory device test resource, the dedicated processing device configured to facilitate testing of a memory device of a memory subsystem coupled to the memory device test resource; a memory subsystem interface port, coupled to the dedicated processing device and configured to couple the memory device test resource to the memory subsystem; a test condition component, coupled to the dedicated processing device and configured to generate test conditions at the memory device test resource; and a test resource monitoring component, coupled to the dedicated processing device and configured to monitor one or more conditions at the memory device test resource.

[0004] In another aspect, the present disclosure relates to a system, including: a memory device; and a processing device operatively coupled to the memory device, the processing device performing operations including: receiving, from a requester, a first request to perform a test on a memory device of a memory subsystem at a memory device test rack, where the memory device test rack includes a plurality of memory device test resources, each memory device test resource including a separate processing device; transmitting a second request to each separate processing device to determine which of the plurality of memory device test resources are available to perform the test on the memory device of the memory subsystem; receiving a response from each separate processing device, the response including an indication of whether each of the plurality of memory device test resources is available to perform the test; determining, based on the responses received from each separate processing device, the available memory device test resources of the memory device test rack to perform the test; and transmitting an indication of the available memory device test resources to the requester.

[0005] On the other hand, the present disclosure relates to a test rack, comprising: a first memory device test resource including a first processing device, wherein the first processing device is configured to facilitate the execution of a test of a memory device of a memory subsystem coupled to the first memory device test resource; and a second memory device test resource including a second processing device, wherein the second processing device is configured to facilitate the execution of the test at the memory device of the memory subsystem coupled to the second memory device test resource in response to the first processing device of the first memory device test resource being unavailable to facilitate the execution of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 Illustrates an example computing system including a memory subsystem in accordance with some embodiments of the present disclosure.

[0008] Figure 2 is a test platform for performing tests of memory devices in accordance with some embodiments of the present disclosure.

[0009] Figure 3 is an example memory device test resource of a memory device test rack in accordance with some embodiments of the present disclosure.

[0010] Figure 4 is an example connection of a memory subsystem to a memory device test resource in accordance with some embodiments of the present disclosure.

[0011] Figure 5 is a flowchart of an example method of a smart memory device test resource in accordance with some embodiments of the present disclosure.

[0012] Figure 6 is a flowchart of an example method of a memory subsystem engaged with a smart memory device test resource in accordance with some embodiments of the present disclosure.

[0013] Figure 7 is a flowchart of an example method of a resource allocator for each processing device of a test resource operatively coupled to a test rack in accordance with some embodiments of the present disclosure.

[0014] Figure 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure relate to a smart memory device test resource. A memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following is combined withFigure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more components (e.g., memory devices) for storing data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0016] Memory devices used in a memory subsystem can be tested before being used for the memory subsystem. In a traditional testing process, a memory device can be placed in a chamber (e.g., an oven) that tests the memory device under various temperature conditions. For example, at a specific temperature, multiple memory devices can be tested in a chamber at one time. The testing process can indicate various operations performed on the memory device at a specific temperature. These operations include but are not limited to read operations, write operations, and / or erase operations. When conducting the testing process, the performance and behavior of the memory device can be observed. For example, performance characteristics (e.g., read or write latency) and reliability of the data stored on the memory device can be measured and recorded during and after the testing process. However, since the chamber can only subject the memory device to a single temperature at any given time, testing the memory device at many different temperatures can take a significant amount of time because the testing process needs to be executed for each target test temperature. Additionally, the chamber can only perform a single testing process at a time. Therefore, if the testing process for the memory device to be tested has many different conditions, performing different tests on the memory device under different operating conditions (e.g., different temperatures) can require a large amount of time.

[0017] In some traditional memory device testing systems, a test component that includes a temperature control component can be used to test a memory device. The temperature control component is used to subject the memory device to specific temperature conditions. In some test components, only the temperature control component is included, and during the testing of the memory device, the memory device is not affected by any other conditions. A test rack can include multiple test components, where each test component of the test rack is coupled to a local test module. The local test module can facilitate the testing of each memory subsystem of the test components coupled to the test rack. For example, the local test module enables various operations to be performed on the memory device at one or more temperature conditions at multiple test components. Since the local test module facilitates the testing of each memory subsystem of the test components coupled to the test rack, when maintenance or a failure occurs in a single local test module, the entire test rack cannot be used.

[0018] In some cases, each test rack may include hundreds of test components. The local test module may maintain a record of multiple test components available for memory device testing. Since the record of test components may include hundreds of entries (i.e., one entry for each test component), the local test module may use a relatively large amount of memory resources to maintain the record. The local test module may refer to the record of available test components in response to each request to perform a memory device test at the memory rack. Each reference to the record may increase the latency of the test process at the test rack, thereby increasing the latency of the entire test system.

[0019] Aspects of the present disclosure address the above and other deficiencies by providing intelligent memory device test resources. A distributed test platform may include multiple memory device test racks. Each test rack may include multiple test resources, where each test resource includes processing means dedicated to facilitating memory device testing at the test resource. The processing means may facilitate testing of memory devices included in a memory subsystem coupled to the memory device test resource. Each test resource further includes one or more test condition components, one or more test resource monitoring components, and a memory subsystem interface port. A memory subsystem including a memory device to be tested may be coupled to the test resource by engaging the memory subsystem interface port. In response to detecting that the memory subsystem is coupled to the test resource, the processing means of the test resource may transmit test instructions to the memory subsystem, the test instructions including one or more operations to be performed at the memory device. A memory subsystem controller of the memory subsystem may cause the one or more operations to be performed at the memory device. The memory subsystem controller may generate a set of test results for each operation performed at the memory device. After the operations are performed at the memory subsystem, the memory subsystem controller transmits the set of test results to the processing means of the memory device test resource.

[0020] Each test resource includes test condition components. The test condition components may include at least one of a temperature controller or a voltage controller. The temperature controller is configured to control the temperature of the memory device during testing. The voltage controller is configured to control the voltage of a power signal provided to the memory subsystem during testing. The processing means of the test resource may cause one or more conditions to occur at the test resource. For example, at least one of the temperature controller or the voltage controller may cause a first condition to occur before initiating a test at the memory device. During testing of the memory device, the temperature controller and / or the voltage controller may cause a second condition to occur. In response to detecting that the second condition has occurred, the memory subsystem controller may generate a second set of test results, where the second set of test results is related to the execution of operations performed at the memory device operating under the second condition.

[0021] Advantages of the present disclosure include, but are not limited to, a reduction in the amount of time the test platform uses to perform tests on a memory device. Since many different tests can be performed at the test platform during the execution of many different operation sequences to test many different conditions (e.g., different temperatures, voltages of different power signals, etc.), the testing of the memory device can be considered more stable because the reliability and performance of the memory device can be tested by performing many different and parallel tests. In addition, since the processing device of each test resource facilitates the testing of the memory device, when a particular test resource or a part of a test resource is unavailable (e.g., for maintenance, etc.), one or more other test resources can be used to test the memory device. In addition, there is no need to maintain a record of available test resources for each test resource of the test rack, and thus there is no need to refer to the record in response to each request to test a memory device at the test resources of the test rack. Consequently, each test of each memory device can be performed in less time, thereby reducing the overall system latency. The reliability of the memory device is also increased because any possible defects can be identified and then addressed when designing or manufacturing the memory device for customer use.

[0022] Since each test resource includes a dedicated processing device, the memory device can be tested at a test resource removed from the test board of the test rack. For example, an operator of the test platform can remove the test resource from the test board of the test rack. The operator can provide power and network connections to the test resource (e.g., by connecting the test resource to a computing device). In response to the test resource receiving power and network connections, the memory subsystem can be coupled to the test resource. When the test resource is disconnected from the test board of the test rack, tests of the memory devices included in the coupled memory subsystem can be performed.

[0023] Figure 1 An example computing system 100 including a memory subsystem 110 is shown in accordance with some embodiments of the present disclosure. The memory subsystem 110 can include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0024] The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs), universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or an Internet-connected commercial device), or such a computing device that includes a memory and a processing device.

[0026] The computing system 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including electrical, optical, magnetic, etc. connections.

[0027] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0028] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include but are not limited to Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interface (e.g., DIMM socket interface supporting Double Data Rate (DDR)), and the like. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 can further utilize the Non-Volatile Memory Express (NVMe) interface to access components (e.g., memory devices 130) when the memory subsystem 110 is coupled to the host system 120 via the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. As an example, Figure 1 illustrates the memory subsystem 110. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" (Negative-AND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The non-volatile memory cross-point array can perform bit storage based on the change of bulk resistance in combination with a stackable cross-gridded data access array. Additionally, compared with many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed in a case where they have been previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, as well as an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices 130 may be grouped into pages, and a page may refer to a logical unit of the memory device for storing data. In some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although non-volatile memory devices, such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND), are described, the memory devices 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (or simply referred to as the controller 115) may communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory devices 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-wired) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, the local memory 119 may include memory registers that store memory pointers, fetched data, and the like. The local memory 119 may also include a read-only memory (ROM) for storing microcode. Although Figure 1 the illustrated memory subsystem 110 is shown as including a memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] Generally, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may translate the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear-leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may translate commands received from the host system into command instructions for accessing the memory device 130 and may translate responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive an address from the memory subsystem controller 115 and decode the address to access the memory device 130.

[0038] In some embodiments, the memory device 130 includes a local media controller 135 that, in conjunction with the memory subsystem controller 115, performs operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is an original memory device combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] The memory subsystem 110 includes a test component 113 that performs tests on the memory devices of the subsystem (e.g., the memory device 130). The memory subsystem 110 may be coupled to the memory device test resources of a test rack, such as Figure 3 the memory device test resources 310. Each memory device test resource of the test rack may include processing means dedicated to facilitating testing of the memory device at the memory device test resource. The test component 113 receives from the processing means of the test resource one or more instructions to perform tests at the memory device 130. The test instructions may include one or more operations to be performed at the memory device 130, such as read operations, write operations, and / or erase operations. The test component 113 causes the one or more operations to be performed at the memory device 130. During the execution of the one or more operations, the test component 113 collects data related to the execution of the one or more operations. The test component 113 generates a first set of test results based on the data collected during the execution of the one or more operations. In some embodiments, the test component 113 detects that one or more conditions of the memory subsystem 110 have changed during the execution of the one or more operations at the memory device 130. For example, during the execution of the one or more operations, the temperature of the memory subsystem 110 may increase from a first temperature to a second temperature. In some embodiments, a test condition component of the test resource may change the one or more conditions of the memory subsystem 110. In such embodiments, the test component 113 generates a second set of test results based on the data collected during the execution of the one or more operations performed under the second condition. After the test component 113 generates the first set of test results and / or the second set of test results, the test component 113 transmits each set of test results to the processing means of the test resource.

[0040] Figure 2A test platform 200 for performing tests on a memory device according to some embodiments of the present disclosure is shown. The test platform 200 may include one or more test racks 210A, 210B, and 210N. Each of the test racks 210A, 210B, and 210N (referred to as test rack 210) may include a plurality of test boards 212, where each test board 212 includes one or more test resources 214 (i.e., test sockets). The test platform 200 may include any number of test racks 210, test boards 212, or test resources 214. As shown, the test board 212 may include one or more test resources 214. Although three test resources 214 are shown, the test board 212 may include any number of test resources 214. Each test resource 214 may include a memory subsystem that has been coupled to the corresponding test resource 214.

[0041] One or more tests may be performed on the memory devices of the memory subsystems that have been coupled to the test resources 214. Each test resource 214 may include a separate processing device dedicated to facilitating the testing of the memory devices. For example, each test resource 214 may have a separate processing device instead of sharing a processing device for each test rack 210 or even each test board 212. The processing device may receive instructions to be executed when performing the tests. The instructions may include one or more operations to be performed at the memory devices of the memory subsystem. The instructions may also include one or more conditions to be applied to the memory subsystem during the tests.

[0042] In some embodiments, the test resource 214 may be removed from the test board 212, and the testing of the memory device may be performed at the removed test resource 214 separate from the test rack 210. The test board 212 and the test resource 214 may include a locking mechanism configured to secure the test resource 214 to the test board 212. A first component of the locking mechanism may be disposed on an outer portion of the test resource 214. A second component of the locking mechanism may be included at the test board 212. The test resource 214 may be secured to the test board 212 in response to the first component of the locking mechanism engaging the second component. Similarly, the test resource 214 may be removed from the test board 212 in response to the first component of the locking mechanism separating from the second component.

[0043] Because the test resource 214 includes dedicated processing devices for facilitating testing of memory devices, testing of the memory devices of the memory subsystem can be performed even when the test resource 214 is removed from the test board 212 and the test rack 210. For example, once removed from the test board 212, the test resource 214 can be connected to a power source and a network connection that is separate from the test board 212 and the test rack 210 (e.g., a separate computing device). In response to the test resource 214 being connected to the power source and the network connection, the processing devices of the test resource 214 can facilitate testing of the memory devices of the memory subsystem coupled to the removed test resource 214.

[0044] The resource allocator component 222 can receive (e.g., from a user) instructions that include a series of one or more operations and / or conditions of a test to be performed on the memory devices of the memory subsystem. The resource allocator component 222 can determine a particular test resource 214 on a different test rack 210 that is available for performing the test. For example, the resource allocator component 222 can query each processing device of each test resource 214 of each test rack 210 to determine a particular test resource 214 on a different test rack 210 that is available for performing the test. In some embodiments, the resource allocator component 222 can be provided by a server 220 connected to each processing device of the test resources 214. In some embodiments, the server 220 is a computing device or system that is coupled to each processing device of each test resource 214 via a network.

[0045] In response to the memory subsystem being coupled to a particular test resource 214, the resource allocator component 222 can transmit the received instructions to the processing device of the particular test resource 214. In some embodiments, the resource allocator component 222 can transmit the received instructions to the processing device before the memory subsystem is coupled to the test resource 214. After the testing of the memory devices of the memory subsystem is performed, the processing device of the test resource 214 can transmit data associated with the test results to the resource allocator component 222 for transmission and / or presentation to the requesting user. The data associated with the test results can include data associated with the execution of operations at the memory devices of the memory subsystem. In some embodiments, the data associated with the test results can further include data associated with one or more conditions of the test resource 214 during the test execution.

[0046] In some examples, the processing device of test resource 214 cannot be used to facilitate testing at test resource 214. In some embodiments, the processing device of another test resource 214 can be used to facilitate testing. For example, the processing device of one test resource 214 cannot be used to facilitate testing of a memory device. Another test resource 214 can be identified, where the other test resource 214 includes a processing device that can be used to facilitate testing of the memory device. The memory device of the memory subsystem can be tested at the other test resource 214 until the processing device of one test resource 214 can be used to facilitate testing.

[0047] Figure 3 is a memory device test resource 310 of a memory device test rack according to some embodiments of the present disclosure. For example, the memory device test resource 310 can be Figure 2 an implementation of any of the memory device test resources 214 shown. The test resource 310 can include a dedicated processing device 312 for facilitating testing at the test resource 310, one or more test condition components 314, one or more test resource monitoring components 316, and a memory subsystem interface port 318 (referred to herein as port 318).

[0048] As previously described, the processing device 312 can facilitate testing of the memory device 324 of the memory subsystem 320 coupled to the test resource 310. The processing device 312 can receive one or more test instructions to be executed when testing the memory device 324. The one or more test instructions can include one or more operations to be performed at the memory device 324. In some embodiments, the one or more test instructions can further include one or more conditions to be applied to the memory subsystem 320 during test execution.

[0049] The memory subsystem 320 can be coupled to the test resource 310 by engaging with the port 318. The port 318 can include a first set of one or more serial input / output (IO) pins configured to couple to corresponding serial IO sockets of the memory subsystem 320. The port 318 can further include a second set of one or more IO pins configured to couple to corresponding IO sockets of the memory subsystem 320. Other details regarding the port 318 are described with respect to Figure 4 described further.

[0050] In response to detecting that the memory subsystem 320 has been coupled to the port 318, the processing device 312 can provide a power signal to the memory subsystem 320 via the port 318 under a first voltage condition. In some embodiments, the power signal can include electricity. The processing device 312 can further transmit one or more test instructions to the memory subsystem 320 via the port 318, including one or more operations to be performed at the memory device 324.

[0051] In some embodiments, the processing device 312 may cause the memory subsystem 320 to initiate a restart process before performing a test at the memory device 324. In such embodiments, the processing device may transmit a signal via port 318 to the memory subsystem controller 322, instructing the memory subsystem controller 322 to initiate a restart process. In response to receiving the signal, the memory subsystem controller 322 may initiate a restart process. The memory subsystem controller 322 may initiate a test after initiating the restart process. In other or similar embodiments, instead of transmitting a signal to initiate a restart process to the memory subsystem controller 322, the processing device 312 may transmit a signal via port 318 to the memory subsystem controller 322, instructing the memory subsystem controller 322 to initiate a test at the memory device 324. The memory subsystem controller 322 may initiate a test at the memory device 324 in response to receiving the signal from the processing device 312 via port 318.

[0052] Before initiating a test at the memory device 324, the processing device 312 may apply one or more conditions of the test resources 310 to the memory subsystem 320. In some embodiments, the processing device 312 may apply the one or more test conditions to the memory subsystem 320 according to the one or more test instructions received from a resource allocator (e.g., Figure 2 resource allocator component 222). The test condition component 314 may generate the one or more test conditions. In some other embodiments, the test condition component 314 may include at least one of a temperature controller or a voltage controller. In some embodiments, the temperature controller may include one or more fans configured to cool the ambient air around the memory subsystem embedded in the test resources. In other or similar embodiments, the temperature controller may be a dual Peltier device (e.g., two Peltier devices) that utilizes the Peltier effect to apply a heating or cooling effect on the surface of the dual Peltier device coupled to the memory subsystem. In another example, voltage conditions may be applied to the memory subsystem 320 by a voltage controller. In some embodiments, the voltage controller may include one or more power supplies configured to provide different voltages to the memory subsystem 320 via port 318.

[0053] In some embodiments, the one or more test instructions may include a first condition to be applied to the memory subsystem during test execution. The first condition may be generated by the test condition component 314 before or during test execution at the memory device 324A. In some embodiments, the one or more test instructions may include at least a second condition to be applied to the memory subsystem 320 during test execution at the memory device 324. The test condition component 314 may cause the first condition to become the second condition during testing of the memory device 324.

[0054] The test resource monitoring component 316 may monitor one or more conditions within the test resources 310. In some embodiments, the test resource monitoring component 316 may monitor the conditions generated by the test condition component 314. For example, a temperature monitoring component may measure the temperature of the test resources 310, where the temperature is generated by a temperature controller of the test resources 310. The test resource monitoring component 316 may include at least one of the following: a temperature monitoring component configured to monitor the temperature of the test resources 310, a voltage monitoring component configured to monitor the voltage of a power signal provided to the memory subsystem 320 via the port 318, a current monitoring component configured to monitor the current of a power signal provided to the memory subsystem 320 via the port 318, or a humidity monitoring component configured to monitor the humidity of the test resources 310.

[0055] As previously described, the memory subsystem controller 322 may receive from the processing device 312 one or more test instructions including one or more operations to be performed at the memory device 324. In response to receiving an instruction from the processing device 312 to initiate testing at the memory device 324, the memory subsystem controller 322 may cause the one or more operations of the received test instructions to be performed at the memory device 324. The memory subsystem controller 322 may generate one or more sets of test results associated with the execution of the one or more operations at the memory device 324. According to the previously described embodiments, the memory subsystem controller 322 may generate a first set of test results.

[0056] In some embodiments, the memory subsystem controller 322 may generate at least a second set of test results. When performing the one or more operations at the memory device 324, the memory subsystem controller 322 may detect a change from a first condition to a second condition, where according to the previously described embodiments, the test condition component 314 causes the first condition to become the second condition. In some embodiments, the memory subsystem controller 322 may detect the change in response to receiving a signal from the processing device 312. In other or similar embodiments, the memory subsystem controller 322 may detect the change in response to receiving a signal from a sensor of the memory subsystem 320 that the condition of the memory subsystem 320 has changed from the first condition to the second condition. In response to detecting the change from the first condition to the second condition, the memory subsystem controller 322 may generate a second set of test results. The second set of test results may correspond to the execution of one or more operations of the test instructions under the second condition.

[0057] In response to completing the test at the memory device 324, the memory subsystem controller 322 may transmit one or more sets of test results to the processing device 312. In response to receiving the one or more sets of test results, the processing device 312 may transmit each set of test results to another computing device, such as Figure 2 the server 220, for transmission and / or presentation to a user who requested the test of the memory device 324.

[0058] In some embodiments, the processing device 312 may include a memory component (not shown) configured to store data associated with one or more conditions of the test resources 310 during the execution of the test at the memory device 324. In such embodiments, the processing device 312 may transmit the data associated with the one or more conditions of the test resources 310 during the execution of the test at the memory device 324 as well as each set of test results.

[0059] In some embodiments, the test resource 310 can be removed from the test rack 210. The test resource 310 can include one or more components of a fastening mechanism disposed external to the main test resource, such as the fastening component 330. The fastening component 330 can be a first component of the fastening mechanism and is configured to engage a second component of the fastening mechanism. In some embodiments, the second component of the fastening mechanism can be included in the test board of the test rack 210. When the fastening component 330 engages the second component of the fastening mechanism, the test resource 310 can be fixed to the test board of the test rack 210. Similarly, when the fastening component 330 is separated from the second component of the fastening mechanism, the test resource 310 can be removed from the test board of the test rack 210. The test resource 310 can be connected to a power supply and a network connection that is separate from the test rack 210. For example, an operator of the test rack 210 can separate the fastening component 330 of the test resource 310 from the second component of the fastening mechanism of the test board and connect the test resource 310 to a power supply and a network connection that is separate from the test rack 210 (e.g., a separate computing device). According to previously disclosed embodiments, in response to the test resource 310 being connected to a power supply and a network connection that is separate from the test rack 210, the processing device 312 can facilitate testing of the memory device 324.

[0060] Figure 4 FIG. 4 is an example connection of a memory device test resource 310 to a memory subsystem 320 in accordance with some embodiments of the present disclosure. The port 318 can be configured to transmit a power signal to the memory subsystem 320. The port 318 can be further configured to transmit and / or receive instructions and data to / from the memory subsystem 320.

[0061] The port 318 can include a first set of pins 412 configured to couple to a first set of sockets 416 of the memory subsystem 320. Each of the first set of pins 412 can be configured to transmit a power signal (e.g., power) to the memory subsystem 320. The first set of sockets 416 can be configured to receive the power signal transmitted via the port 318 from the test resource 310. In some embodiments, each of the first set of pins 412 can be a non-serial input / output (IO) pin. In other or similar embodiments, each of the first set of pins 412 can be a pin of a high-speed serial interface. For example, each of the first set of pins 412 can be configured to facilitate a Peripheral Component Interconnect Express (PCIe) protocol and / or a Serial ATA (SATA) protocol.

[0062] In some embodiments, the memory subsystem 320 can be enclosed in a protective cover 420. The protective cover 420 can have an opening 422 for exposing the first set of sockets 416 to the first set of pins 412 of the test resource 310. The first set of pins 412 can be configured to connect to the first set of sockets 416 via the opening 422 of the protective cover 420.

[0063] Port 318 may further include a second set of pins 414. Each of the second set of pins 414 may be configured to transfer instructions and data between the processing device 312 and the memory subsystem 320. In some embodiments, each of the second set of pins 414 may be a serial IO pin. In other or similar embodiments, each of the second set of pins 414 may be a pin of a low-speed serial interface. For example, each of the second set of pins 414 may be configured to facilitate a Universal Asynchronous Receiver / Transmitter (UART) protocol, a System Management Bus (SMB) protocol, or a Serial Wire Debug (SWD) protocol. Some of the memory subsystems 320 may include a second set of sockets 418. In some embodiments, each of the second set of sockets 418 may be a serial IO socket. The second set of sockets 418 may be configured to receive data from and / or transfer data to the processing device 312. In some embodiments, the opening 422 of the protective cover 420 may expose the second set of sockets 418 to the second set of pins 414 of the port 318. The second set of pins 414 may be configured to be coupled to the second set of sockets 418 via the opening 422 of the protective cover 420.

[0064] Figure 5 is a flowchart of an example method 500 of an intelligent memory device test rack according to some embodiments of the present disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, the hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 500 is executed by the processing device of the test resource (e.g., Figure 3 processing device 312). Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0065] At operation 510, the processing device 312 detects that the memory subsystem has been engaged with the memory device test resource. For example, the memory subsystem may be Figure 3 memory subsystem 320. The memory subsystem 320 may be engaged with the test resource 310 via a memory subsystem interface port (e.g., port 318). The port 318 may include one or more non-serial input / output (IO) pins, such as Figure 4A first set of pins 412, the pins configured to couple to corresponding sockets of the memory subsystem 320, such as the first set of sockets 416. Each of the first set of pins 412 can be configured to transfer power from the test resource 310 to the memory subsystem 320 engaged with the test resource 310. The port 318 can further include one or more serial IO pins, such as a second set of pins 414, the pins configured to couple to corresponding serial IO sockets of the memory subsystem 320, such as the second set of sockets 418. The one or more serial IO pins of the second set of pins 414 can be configured to transfer data and instructions between the processing device 312 and the memory subsystem 320 engaged with the test resource 310.

[0066] In some embodiments, the memory subsystem 320 can be enclosed within a protective cover, such as the memory subsystem protective cover 420. The protective cover 420 can include an opening 422 configured to expose the first set of sockets 416 and the second set of sockets 418 of the memory subsystem 320 to the first set of pins 412 and the second set of pins 414. The first set of pins 412 and the second set of pins 414 can be configured to couple to the first set of sockets 416 and the second set of sockets 418 via the opening 422 of the protective cover 420.

[0067] At operation 520, processing device 312 identifies tests to be performed on a memory device (e.g., memory device 324) of memory subsystem 320, where the tests include one or more test instructions to be executed when performing the tests. Memory subsystem 320 may include a memory subsystem controller, such as memory subsystem controller 322. Memory subsystem controller 322 may be responsible for executing the tests on memory device 324. In some embodiments, the one or more test instructions include one or more operations to be performed at memory device 324, such as read operations, write operations, and / or erase operations. The test instructions may further include conditions under which the tests are performed, referred to as test conditions. For example, the test instructions may include one or more temperature conditions and / or one or more voltage conditions to be applied to memory subsystem 320 during test execution. Each test condition may be generated by test condition component 314 of test resource 310. For example, memory subsystem 320 may be subjected to temperature conditions generated by a temperature controller. The test conditions may be monitored by one or more test resource monitoring components of test resource 310, such as test resource monitoring component 316. For example, a temperature monitoring component may monitor the temperature of memory subsystem 320 during the test. In another example, a voltage monitoring component may monitor the voltage provided to memory subsystem 320 via port 318. Test resource monitoring component 316 may also include a current monitoring component configured to monitor the current provided to memory subsystem 320 via port 318. In other or similar embodiments, test resource monitoring component 316 may include a humidity monitoring component configured to monitor the humidity of the ambient air around memory subsystem 320 during the test.

[0068] At operation 530, processing device 312 transmits the one or more test instructions to memory subsystem 320 via port 318, where the tests are performed by executing the one or more test instructions at memory subsystem 320. Memory subsystem controller 322 of memory subsystem 320 may receive the one or more test instructions and cause the one or more operations of the test to be performed at memory device 324. In some embodiments, processing device 312 causes an operation to be performed at memory device 324 by transmitting a signal via port 318 to memory subsystem controller 322 to initiate execution of the operation at memory device 324. In other or similar embodiments, processing device 312 causes an operation to be performed at memory device 324 by transmitting a signal to cause memory subsystem controller 322 to initiate a restart process. The one or more operations may be performed in response to memory subsystem 320 initiating a restart process.

[0069] The processing device 312 can receive, via port 318, one or more sets of test results associated with the execution of the one or more operations at the memory device 324. Each set of test results can include at least one of the performance characteristics or behaviors of the memory device 324 when performing a test procedure. The performance characteristics and / or behaviors of the memory device 324 can be observed by the memory subsystem controller 322 when the one or more operations are being executed. In response to receiving the one or more sets of test results, the processing device 312 can transmit the test results to a server associated with a customer who requested the memory device test, such as Figure 2 server 220. In some embodiments, the processing device 312 can transmit data associated with one or more conditions monitored by the test resource monitoring component 316 of the test resource 310, as well as the test results. For example, the processing device 312 can transmit data associated with at least one of the following: the temperature of the test resource 310 during the test of the memory device 324, the humidity of the test resource 310, the voltage of the power signal provided to the memory subsystem 320, or the current of the power signal provided to the memory subsystem 320.

[0070] Figure 6 is a flowchart of an example method 600 of a memory subsystem that engages with a memory device test resource of an intelligent memory device test rack according to some embodiments of the present disclosure. Method 600 can be executed by processing logic, which can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 600 is performed by Figure 1 test component 113. Although shown in a particular order or sequence, the order of the processes can be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes can be executed in a different order, and some processes can be executed in parallel. Additionally, in various embodiments, one or more processes can be omitted. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0071] At operation 610, the test component 113 detects that a memory subsystem (e.g., Figure 3 memory subsystem 320) has engaged with a memory device test resource (e.g., test resource 310). According to the previously described embodiments, the memory subsystem 320 can engage with the test resource 310 via a memory subsystem interface port (e.g., port 318).

[0072] At operation 620, the test component 113 receives, via port 318, from a processing device (e.g., processing device 312) of the test resource 310, one or more test instructions for a test to be performed on a memory device (e.g., memory device 324) of the memory subsystem 320. According to previously disclosed embodiments, the one or more test instructions may include operations to be performed at the memory device 324. The memory subsystem 320 may cause each operation of the one or more test instructions to be performed at the memory device 324. In some embodiments, the memory subsystem 320 may cause each operation to be performed under various test conditions, temperature conditions, or voltage conditions. According to previously described embodiments, the temperature conditions and / or voltage conditions may be applied to the memory subsystem 320 by a test condition component (e.g., test condition component 314) of the test resource 310.

[0073] At operation 630, the test component 113 performs a test of the memory device 324 by executing the one or more received test instructions. As previously described, a memory subsystem controller (e.g., memory subsystem controller 322) may perform the test by causing the one or more operations of the received test instructions to be executed. In some embodiments, the memory subsystem controller 322 may perform a test at the memory device 324 in response to receiving a signal from the processing device 312 via port 318 to initiate a test of the memory device 324. In other or similar embodiments, the memory subsystem controller 322 may perform a test in response to initiating a restart process. According to previously described embodiments, the memory subsystem controller 322 may initiate a restart process in response to receiving a signal from the processing device 312.

[0074] At operation 640, the test component 113 generates a first set of test results during test execution. As previously described, the one or more test instructions of the test may include the conditions under which the memory subsystem 320 performs a test of the memory device. In some embodiments, the conditions may include at least a first test condition, such as a first temperature condition and / or a first voltage condition. The first set of test results may correspond to the execution of the test under the first test condition. The memory subsystem controller 322 may generate a second set of test results corresponding to the execution of the one or more operations of the test instructions under a second condition.

[0075] At operation 650, the test component 113 transmits the first set of test results to the processing device 312 via port 318. In some embodiments, according to previously described embodiments, the processing device 312 further transmits a second set of test results generated based on the execution of the one or more operations under a second condition. According to previously described embodiments, in response to receiving the first set of test results and / or the second set of test results, the processing device 312 may transmit the received test results to a server, e.g., Figure 2server 220.

[0076] Figure 7 is a flowchart of an example method 700 of a resource allocator for each processing device of a test board operatively coupled to a test rack according to some embodiments of the present disclosure. Method 700 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 700 is executed by Figure 2 resource allocator component 222. Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0077] At operation 710, the processing logic receives a first request to perform a test on a memory device of a memory subsystem at a memory device test rack. In some embodiments, the memory subsystem may be Figure 3 memory subsystem 320, and the memory device may be memory device 324. In some embodiments, the memory device test rack may be Figure 2 any one of test racks 210A, B, or C. Test rack 210 may include two or more memory device test resources, such as Figure 3 test resource 310. Each test resource 310 may include a dedicated processing device, such as processing device 312, where processing device 312 is dedicated to facilitating the testing of a memory device at test resource 310. Each test resource 310 may further include a test condition component, such as test condition component 314. In some embodiments, the first request may include one or more operations corresponding to test conditions to be applied to memory subsystem 320 during the test.

[0078] At operation 720, the processing logic transmits a second request to each individual processing device 312 of each test resource 310 to determine the test resources 310 available for performing the test. At operation 730, the processing logic receives a response from each individual processing device 312, the response including an indication of whether the test resource 310 is available for performing the test. In some embodiments, the response may include an indication of the test condition component 314 included in the test resource 310. For example, the processing logic may receive from the processing device 312 of a test resource 310 a first response indicating that a test resource 310 is available and that a test resource 310 includes a temperature controller and a voltage controller. The processing logic may also receive from the processing device 312 of another test resource 310 a second response indicating that another test resource 310 is available and that another test resource 310 includes a temperature controller.

[0079] At operation 740, based on the responses received from each individual processing device, the processing logic determines the available test resources 310 of the test board 212 to perform the test. In some embodiments, the available test resources 310 may be further determined based on an indication of whether the available test resources 310 include a test condition component 314 configured to generate the test conditions included in the first request. According to the previous example, the first request may include one or more operations corresponding to the voltage of the power signal provided by the available test resources 310 to the memory subsystem 320. The processing logic may select the available test resources 310 for testing based on the indication of the first response that a test resource 310 includes a voltage controller.

[0080] At operation 750, the processing logic transmits an indication of the available test resources 310. In response to receiving the indication of the available test resources 310, the memory subsystem may be coupled to the available test resources 310 for testing. For example, the processing logic may transmit an indication of the available test resources 310 to an operator of the test rack 210. In response to receiving the indication, the operator may couple the memory subsystem 320 to the available test resources 310 for testing.

[0081] In some embodiments, the processing logic may receive one or more operations to be performed during a test of a memory device. The operations may include test conditions generated by a test condition component 314 of the available test resources 310. In some embodiments, the test conditions may include the temperature of the ambient air around the memory subsystem 320 or the voltage of a power signal provided to the memory subsystem 320. The operations may further include one or more of a read operation, a write operation, or an erase operation to be performed at the memory device 324 during the test. In response to receiving the one or more operations, the processing logic may transmit one or more test instructions including the one or more operations to a processing device 312 assigned to the available test resources 310. In some embodiments, the one or more test instructions may be generated by the processing logic. In some embodiments, in response to receiving an indication that the memory subsystem 320 has been coupled to the available test resources 310 by a memory subsystem interface port (e.g., port 318) of the available test resources 310, the one or more test instructions are transmitted to the processing device 312.

[0082] Figure 8 An example machine of a computer system 800 is shown, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1 host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110), or may be used to execute the operations of a controller (e.g., to execute an operating system to perform the operations corresponding to Figure 1 test component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0083] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Additionally, although a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0084] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0085] The processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 802 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 can further include a network interface device 708 that communicates via a network 820.

[0086] The data storage system 818 can include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which a set or multiple sets of instructions 826 or software embodying any one or more of the methods or functions described herein are stored. The instructions 826 can also reside, completely or at least partially, within the main memory 804 and / or within the processing device 802 during execution by the computer system 800, the main memory 804, and the processing device 802, which also constitutes the machine-readable storage medium. The machine-readable storage medium 824, the data storage system 818, and / or the main memory 804 can correspond to Figure 1 the memory subsystem 110.

[0087] In one embodiment, the instructions 826 include instructions implementing the functionality corresponding to a test component (e.g., Figure 1 the test component 113). Although the machine-readable storage medium 824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing a set or multiple sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0088] Some of the foregoing detailed description has been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the data processing arts to convey the substance of their work to others skilled in the art. Herein, and in general, an algorithm is conceived of as a self-consistent sequence of operations that produces the desired result. The operations are those requiring physical manipulation of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and so forth.

[0089] However, it should be borne in mind that all such and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memory or registers of the computer system or other such information storage systems.

[0090] The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, which are respectively coupled to the computer system bus.

[0091] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. Structures for various of these systems will be presented from the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0092] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, and the like.

[0093] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. Memory device test resources of a memory device test rack, the memory device test resources comprising: A dedicated processing device of the memory device test resources, the dedicated processing device configured to: Receive a test from a test platform associated with the memory device test rack, the test to be performed on a memory device of a memory subsystem coupled to the memory device test resources, wherein the test is selected by the test platform from a set of tests associated with a plurality of memory device test resources of the memory device test rack, the plurality of memory device test resources including the memory device test resources; And Facilitate testing of the memory device of the memory subsystem coupled to the memory device test resources according to the test; A memory subsystem interface port, coupled to the dedicated processing device and configured to couple the memory device test resources to the memory subsystem; A dedicated test condition component, coupled to the dedicated processing device and configured to generate test conditions for the test of the memory device at the memory device test resources; And A dedicated test resource monitoring component, coupled to the dedicated processing device and configured to monitor one or more conditions at the memory device test resources.

2. The memory device test resources according to claim 1, wherein the dedicated processing device is configured to perform operations including the following: Detect that the memory subsystem has been coupled to the memory device test resources; and Cause one or more test instructions of the test to be transmitted to the memory subsystem, wherein the test is performed by executing the one or more test instructions at the memory subsystem.

3. The memory device test resources according to claim 2, wherein the dedicated processing device is configured to perform operations further including the following: Receive a first set of test results of the test performed on the memory device from the memory subsystem.

4. The memory device test resource according to claim 1, wherein the memory subsystem interface port includes: A first set of serial input / output IO pins configured to be coupled to corresponding serial IO sockets of the memory subsystem; And a second set of IO pins configured to be coupled to corresponding IO sockets of the memory subsystem, and wherein one or more test instructions of the test to be performed on the memory device are transmitted to the memory subsystem via the first set of serial IO pins of the memory subsystem interface port.

5. The memory device test resources according to claim 1, wherein the dedicated processing device is configured to perform operations including the following: Based on one or more test instructions of the test to be performed on the memory device, cause the dedicated test condition component to generate a first test condition to be applied to the memory subsystem; and Receive data associated with one or more conditions within the memory device test resources from the dedicated test resource monitoring component, wherein the one or more conditions include the first test condition generated by the test condition component.

6. The memory device test resource according to claim 5, wherein the dedicated processing device is configured to perform operations including the following: Cause the dedicated test condition component to generate a second test condition to be applied to the memory subsystem when performing the test at the memory device; and Receive from the memory subsystem a first set of test results of the test performed on the memory device under the first test condition and a second set of test results of the test performed on the memory device under the second test condition.

7. The memory device test resource according to claim 1, wherein the dedicated test condition component includes at least one of a temperature controller or a voltage controller, and the dedicated test resource monitoring component includes at least one of a temperature monitoring component, a voltage monitoring component, a current monitoring component, or a humidity monitoring component.

8. A system, comprising: A memory device; And A processing device operatively coupled to the memory device, the processing device performing operations including the following: Receive from a requester a first request to perform a test on a memory device of a memory subsystem at a memory device test rack, wherein the memory device test rack includes a plurality of memory device test resources, and each memory device test resource includes a separate processing device; Transmit a second request to each separate processing device to determine which of the plurality of memory device test resources are available for performing the test on the memory device of the memory subsystem; Receive a response from each separate processing device, the response including an indication of whether each of the plurality of memory device test resources is available for performing the test; Based on the responses received from each separate processing device, determine the available memory device test resources of the memory device test rack for performing the test; And Transmit an indication of the available memory device test resources to the requester.

9. The system according to claim 8, wherein the processing device will further perform operations including the following: Receive from the requester one or more operations to be performed during the test on the memory device of the memory subsystem; Transmit one or more test instructions including the one or more operations to the separate processing devices assigned to the available memory device test resources.

10. The system according to claim 9, wherein in response to receiving an indication that the memory subsystem has been coupled to the available memory device test resources by the memory subsystem interface ports of the available memory device test resources, the one or more test instructions are transmitted to the separate processing devices.

11. The system according to claim 9, wherein the one or more operations correspond to at least one of the test conditions generated by the test condition component of the available memory device test resources during the test or one or more of a read operation, a write operation, or an erase operation performed on the memory device during the test.

12. The system according to claim 11, wherein the test conditions include at least one of a temperature of ambient air around the memory subsystem or a voltage of a power signal supplied to the memory subsystem by the available memory device test resources.

13. The system according to claim 8, wherein the first request to perform the test on the memory device includes one or more operations corresponding to test conditions to be applied to the memory subsystem during the test, and wherein the available memory device test resources are further determined based on an indication of whether the available memory device test resources include a test condition component configured to generate the test conditions during the test.

14. A test rack, comprising: A first memory device test resource including a first processing device, wherein the first processing device is configured to promote execution of a test on a memory device of a memory subsystem according to a set of test conditions in response to the first memory device test resource being available to facilitate execution of the test, and wherein the test is performed at the first memory device test resource using a first dedicated test condition component and a first dedicated test resource monitoring component of the first memory device test resource; And A second memory device test resource including a second processing device, wherein the second processing device is configured to promote execution of the test on the memory device of the memory subsystem according to the set of test conditions in response to the first processing device of the first memory device test resource not being available to facilitate execution of the test, and wherein the test is performed at the second memory device test resource using a second dedicated test condition component and a second dedicated test resource monitoring component of the second memory device test resource.

15. The test rack according to claim 14, wherein the first processing device will perform operations including: Detecting that the memory subsystem has been engaged with the first memory device test resource; Identifying the test to be performed on the memory device of the memory subsystem, wherein the test includes one or more test instructions to be executed when performing the test; And Causing the one or more test instructions to be transmitted to the memory subsystem, wherein the test is performed by executing the one or more test instructions at the memory subsystem.

16. The test rack according to claim 15, wherein the first processing device will perform operations including: Receiving a first set of test results of the test performed on the memory device from the memory subsystem.

17. The test rack according to claim 15, wherein the first processing device will further perform operations including: Based on the one or more test instructions of the test to be performed on the memory device, causing the first dedicated test condition component of the first memory device test resource to generate a first test condition to be applied to the memory subsystem; and Receive data associated with one or more conditions within the first memory device test resource from the first dedicated test resource monitoring component of the first memory device test resource, where the one or more conditions include the first test condition generated by the first dedicated test condition component.

18. The test rack according to claim 17, wherein the first dedicated test condition component or the second dedicated test condition component includes at least one of a temperature controller or a voltage controller, and the first dedicated test resource monitoring component or the second dedicated test resource monitoring component includes at least one of a temperature monitoring component, a voltage monitoring component, a current monitoring component, or a humidity monitoring component.

19. The test rack according to claim 14, wherein the first processing device will perform operations including the following: Transmit a notification to the memory device test resource allocator that the first processing device is unavailable to facilitate the execution of the test at the first memory device test resource.

20. The test rack according to claim 19, wherein the second processing device will perform operations including the following: Receive a request to facilitate the execution of the test at the second memory device test resource; Detect that the memory subsystem has engaged with the second memory device test resource; Identify the test to be performed on the memory device of the memory subsystem, where the test includes one or more test instructions to be executed when performing the test; And Cause the one or more test instructions to be transmitted to the memory subsystem, where the test is performed by executing the one or more test instructions at the memory subsystem.

Images