Semiconductor package device and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor packaging apparatus and a method for manufacturing the same. The semiconductor packaging apparatus includes a first chip and a circuit layer; the first chip is located on the circuit layer, with its active surface facing the circuit layer; the semiconductor packaging apparatus defines a stress-neutral region, with the corners of the active surface of the first chip close to the stress-neutral region. This semiconductor packaging apparatus reduces the stress at stress concentration points of the first chip, thereby reducing the squeezing effect of the corners of the first chip on surrounding materials (e.g., packaging material), preventing structural fractures, and improving product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging apparatus technology, and more specifically to semiconductor packaging apparatus and its manufacturing method. Background Technology

[0002] FOCoS (Fan Out Chip on Substrate) packaging technology achieves this by using a fan-out composite chip on a typical ball grid array substrate. It offers a lower-cost solution and, in practice, provides better electrical and thermal performance than silicon interposer structures.

[0003] In the FOCoS packaging structure, due to the different thermal expansion systems of various materials, the deformation varies with temperature changes, causing the packaging structure to warp and generate internal stress. Existing FOCoS packaging structures suffer from structural fracture due to stress, leading to a decrease in product yield. Summary of the Invention

[0004] This disclosure provides a semiconductor packaging apparatus and a method for manufacturing the same.

[0005] In a first aspect, this disclosure provides a semiconductor packaging device, including a first chip and a circuit layer;

[0006] The first chip is located on the circuit layer, and the active surface of the first chip faces the circuit layer;

[0007] The semiconductor packaging device defines a stress-neutral region, and the corners of the active surface of the first chip are close to the stress-neutral region.

[0008] In some alternative embodiments, the semiconductor packaging apparatus further includes a packaging material covering the first chip.

[0009] In some alternative embodiments, the distance between the stress-neutral region and the bottom surface of the semiconductor packaging device is determined by the following equation (1):

[0010] C=A·[E1(v1+y·s)+E2(v2-y·s)] Formula (1)

[0011] Wherein, C is the distance between the stress neutral region and the bottom surface of the semiconductor packaging device, A is a preset constant, E1 is the Young's coefficient of the first fan-out layer, E2 is the Young's coefficient of the packaging material, s is the area of ​​the first fan-out layer, y is the thickness of the first fan-out layer, v1 is the volume ratio of the first fan-out layer to the semiconductor packaging device, and v2 is the volume ratio of the packaging material to the semiconductor packaging device.

[0012] In some alternative implementations, the circuit layer includes a main fan-out layer and a first fan-out layer located on the main fan-out layer, wherein the upper surface of the first fan-out layer is closer to the stress neutral region than the upper surface of the main fan-out layer, and the first chip is located on the main first fan-out layer.

[0013] In some alternative implementations, the second chip is located on the main fan-out layer.

[0014] In some alternative embodiments, the semiconductor packaging device further includes a second fan-out layer located on the main fan-out layer, the second fan-out layer and the first fan-out layer being located on the same side of the main fan-out layer, and the second chip being located on the second fan-out layer.

[0015] In some alternative implementations, the corners of the active surface of the second chip are close to the stress-neutral region.

[0016] In some alternative embodiments, the stress-neutral region is located near the midpoint of the semiconductor packaging device in the thickness direction.

[0017] In some alternative implementations, the semiconductor packaging device further includes a second chip located on the circuit layer.

[0018] In some alternative implementations, the corners of the active surface of the second chip are close to the stress-neutral region.

[0019] In some alternative implementations, the first chip is a high-bandwidth memory chip, and the second chip is an application-specific integrated circuit (ASIC) chip.

[0020] In some alternative implementations, the circuit layer includes at least two dielectric layers, wherein at least one of the dielectric layers has a different thickness than the other dielectric layers.

[0021] In some alternative implementations, the circuit layer includes a first dielectric layer and a second dielectric layer, wherein the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer, and the second dielectric layer is closer to the first chip than the first dielectric layer.

[0022] In some alternative implementations, an underfill material is provided between the first chip and the circuit layer.

[0023] In some alternative implementations, the bottom filler material is filled by molding or capillary action.

[0024] In some optional implementations, the connection between the first chip and the circuit layer is at least one of through-silicon via (TSV) connection, copper pillar connection, flexible circuit board connection, and wire connection.

[0025] In some alternative embodiments, a heat dissipation layer is provided on the surface of the encapsulation material.

[0026] In some alternative implementations, an electrical connector is provided on the bottom surface of the circuit layer.

[0027] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, including:

[0028] The main fan-out layer is formed on the substrate through repeated processes of photolithography, electroplating, and etching.

[0029] A first fan-out layer is formed on the main fan-out layer through repeated processes of photolithography, electroplating and etching, wherein the main fan-out layer and the first fan-out layer together form a circuit layer;

[0030] The first chip is electrically connected to the first fan-out layer, wherein the active surface of the first chip faces the circuit layer;

[0031] An underfill material is provided between the first chip and the first fan-out layer;

[0032] Molding is performed over the main fan-out layer to obtain a semiconductor package device, wherein the semiconductor package device defines a stress-neutral region and the corners of the active surface of the first chip are close to the stress-neutral region.

[0033] In some alternative embodiments, forming a first fan-out layer on the main fan-out layer through repeated processes of photolithography, electroplating, and etching includes:

[0034] A blocking layer is placed on the main fan-out layer, wherein the blocking layer has a cavity;

[0035] The first fan-out layer is formed within the cavity of the barrier layer through repeated processes of photolithography, electroplating, and etching.

[0036] In some alternative embodiments, prior to molding over the main fan-out layer, the method further includes:

[0037] Connect the second chip to the main fanout layer;

[0038] An underfill material is provided between the second chip and the main fan-out layer.

[0039] In some alternative embodiments, after molding over the main fan-out layer, the method further includes:

[0040] A heat dissipation layer is provided on the surface of the packaging material of the semiconductor packaging device.

[0041] In some alternative embodiments, after molding over the main fan-out layer, the method further includes:

[0042] Electrical connectors are provided on the outer surface of the circuit layer.

[0043] Thirdly, this disclosure provides a method for manufacturing a semiconductor packaging device, including:

[0044] A circuit layer is formed on a substrate through repeated processes of photolithography, electroplating, and etching.

[0045] Connect the first chip and the second chip to the circuit layer respectively;

[0046] Underfill material is provided between the first chip and the circuit layer, and between the second chip and the circuit layer, respectively;

[0047] Molding is performed over the circuit layer to obtain a semiconductor package device.

[0048] In the semiconductor packaging apparatus and manufacturing method provided in the embodiments of this disclosure, the corners of the active surface of the first chip are positioned close to the stress neutral region, which reduces the stress on the stress concentration points of the first chip, thereby reducing the squeezing effect of the corners of the first chip on the surrounding materials (such as packaging materials), avoiding corresponding structural fractures, and improving product yield. Attached Figure Description

[0049] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0050] Figure 1 This is a schematic diagram of fracture phenomena in existing technology;

[0051] Figure 2 This is a first schematic diagram of a semiconductor packaging apparatus according to an embodiment of the present invention;

[0052] Figure 3 This is a force diagram of a semiconductor packaging device according to an embodiment of the present invention;

[0053] Figure 4 This is a second schematic diagram of a semiconductor packaging apparatus according to an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of various connection methods between the first chip and the circuit layer in a semiconductor packaging device according to an embodiment of the present invention;

[0055] Figure 6 This is a schematic diagram of the arrangement of the silicon dummy layer in a semiconductor packaging apparatus according to an embodiment of the present invention;

[0056] Figure 7 This is a schematic diagram of various chip arrangement methods in a semiconductor packaging device according to an embodiment of the present invention;

[0057] Figures 8-15 This is a schematic diagram of the manufacturing process of a semiconductor packaging apparatus according to an embodiment of the present invention.

[0058] Symbol explanation:

[0059] 100 First chip 100a The first first chip

[0060] 100b Second chip, first chip; 200 Second chip

[0061] 300 Line layer 301 Main fan output layer

[0062] 302 First Fan-Out Layer 303 First Dielectric Layer

[0063] 304 Second dielectric layer 305 Third dielectric layer

[0064] 306 Fourth dielectric layer 400 Encapsulation material

[0065] 500 silicon dummy layer 600 heat dissipation layer

[0066] 700 Electrical connectors; 900 Bottom filler material

[0067] 10 Carrier 11 Barrier layer

[0068] 12 Bonding Heads 101 Through-Silicon Vias

[0069] 102 Copper pillar; 103 Flexible circuit board

[0070] 104 connecting cable Detailed Implementation

[0071] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0072] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0073] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0074] Figure 1 This is a schematic diagram of fracture phenomena in existing technology. For example... Figure 1 As shown, the first chip 100 and the second chip 200 are disposed on the circuit layer 300, and are surrounded by a packaging material 400. Due to the different thermal expansion systems of the different materials, their deformation varies with temperature changes, causing the packaging structure to warp and generate internal stress. This stress causes the edges of the first chip 100 to compress the packaging material 400, leading to breakage of the packaging material 400. Figure 1 The fracture site is indicated by a white dashed circle.

[0075] Figure 2 This is a first schematic diagram of a semiconductor packaging apparatus according to an embodiment of the present invention. The semiconductor packaging apparatus includes a first chip 100 and a circuit layer 300. The first chip 100 is located on the circuit layer 300, and the active surface of the first chip 100 faces the circuit layer 300. Here, the active surface is the surface of the chip used for external connections, for example, on... Figure 2 In the first chip 100, the active surface is the lower surface.

[0076] In this embodiment, the semiconductor packaging device defines a stress-neutral region 800, and the stress-neutral region 800 is in Figure 2 The area is shown as a dashed line. Here, the stress-neutral region refers to the region in a semiconductor packaging device where the stress is zero. For stress analysis of semiconductor packaging devices, please refer to [link to relevant documentation]. Figure 3 , Figure 3 The arrows on the right side of the semiconductor packaging device indicate the corresponding stresses, where the direction of the arrow indicates the direction of the stress, and the length of the line segment indicates the magnitude of the stress. Figure 3In the example, from top to bottom, the stress inside the semiconductor package first decreases to the left and then increases to the right. It's easy to understand that during this continuous change in stress... Figure 3 The semiconductor packaging device shown has a horizontal plane where the stress is zero; this horizontal plane is the stress-neutral region.

[0077] In this embodiment, the corner of the active surface of the first chip 100 is close to the stress neutral region 800. In one example, the distance from the corner of the active surface of the first chip 100 to the stress neutral region 800 is less than the distance from the corner of the active surface of the first chip 100 to the bottom surface of the circuit layer 300. In another example, the distance from the corner of the active surface of the first chip 100 to the stress neutral region 800 is less than a preset value, such as 5 micrometers, 10 micrometers, or 20 micrometers.

[0078] In one example, the semiconductor packaging apparatus also includes a packaging material 400 covering the first chip 100.

[0079] In one example, circuit layer 300 includes a main fan-out layer 301 and a first fan-out layer 302 located on the main fan-out layer 301, the upper surface of the first fan-out layer 302 being closer to the stress neutral region 800 than the upper surface of the main fan-out layer 301. A first chip 100 is located on the first fan-out layer 302.

[0080] like Figure 2 As shown, the first fan-out layer 302 is located above the main fan-out layer 301, and the first chip 100 is located above the first fan-out layer 302. The first fan-out layer 302 and the first chip 100 are opposite each other, and their widths are similar. The width of the first fan-out layer 302 is smaller than the width of the main fan-out layer 301.

[0081] In one example, the distance between the stress-neutral region and the bottom surface of the semiconductor package device is determined by the following equation (1):

[0082] C=A·[E1(v1+y·s)+E2(v2-y·s)] Formula (1)

[0083] Where C is the distance between the stress neutral region and the bottom surface of the semiconductor packaging device, A is a preset constant, E1 is the Young's coefficient of the first fan-out layer, E2 is the Young's coefficient of the packaging material, s is the area of ​​the first fan-out layer, y is the thickness of the first fan-out layer, v1 is the volume ratio of the first fan-out layer to the semiconductor packaging device, and v2 is the volume ratio of the packaging material to the semiconductor packaging device.

[0084] In another example, the distance between the stress-neutral region and the bottom surface of the semiconductor package is determined by the following equation (2):

[0085] C=A·[E1(v1+y·s)+E2(v2-y·s)]+E3v3+E4v4……+E8v8

[0086] Equation (2)

[0087] In this context, C, A, E1, E2, s, y, v1, and v2 have the same meanings as in the example above. E3, E4, ..., E8 represent the Young's coefficients of all parts of the semiconductor packaging device except for the packaging material and the first fan-out layer. v3, v4, ..., v8 represent the volume ratio of all parts of the semiconductor packaging device except for the packaging material and the first fan-out layer to the whole.

[0088] Comparing Equation (1) and Equation (2), it can be seen that the difference lies in whether or not all parts of the semiconductor packaging device, except for the packaging material and the first fan-out layer, are included in the calculation. Since the relevant data of the packaging material and the first fan-out layer play a major role in calculating the distance between the stress neutral region and the bottom surface of the semiconductor packaging device, a relatively accurate and reliable calculation result can also be obtained through Equation (1).

[0089] In one example, the stress-neutral region is located near the midpoint of the semiconductor package in the thickness direction. For example... Figure 2 As shown, both the stress neutral region 800 and the bottom surface of the semiconductor packaging device are horizontal, and the stress neutral region 800 is located near the middle position of the semiconductor packaging device in the thickness direction (i.e., the vertical direction in the figure). In other words, the distance from the stress neutral region 800 to the upper surface of the semiconductor packaging device is approximately the same as its distance to the lower surface of the semiconductor packaging device.

[0090] In one example, the semiconductor packaging device also includes a second chip located on the circuit layer. For example... Figure 2 As shown, the second chip 200 is located on the circuit layer 300. Specifically, the second chip 200 is located on the main fan-out layer 301. In addition, a bottom filler material 900 is disposed between the second chip 200 and the main fan-out layer 301.

[0091] In one example, the corners of the active surface of the second chip are close to the stress-neutral region. For example... Figure 2 As shown, the active surface (i.e., the lower surface in the figure) of the second chip 200 is close to the stress neutral region 800. Here, the corner of the active surface of the second chip is close to the stress neutral region. This can be because the distance from the corner of the active surface of the second chip 200 to the stress neutral region 800 is less than the distance from the corner of the active surface of the second chip 200 to the bottom surface of the circuit layer 300, or it can be because the distance from the corner of the active surface of the second chip 200 to the stress neutral region 800 is less than a preset value.

[0092] In one example, the conductor encapsulation device may further include a second fan-out layer located on the main fan-out layer 301. Figure 2 (Not shown in the image), the second fan-out layer can be located on the same side of the main fan-out layer 301 as the first fan-out layer 302, and the second chip 200 can be located on the second fan-out layer.

[0093] In one example, the first chip 100 is a high-bandwidth memory (HBM) chip, and the second chip 200 is an application-specific integrated circuit (ASIC) chip.

[0094] In one example, line layer 300 includes at least two dielectric layers, wherein at least one dielectric layer has a different thickness than the other dielectric layers. Figure 4 As shown, the circuit layer 300 includes four dielectric layers: a first dielectric layer 303, a second dielectric layer 304, a third dielectric layer 305, and a fourth dielectric layer 306. The thickness of the first dielectric layer 303 is greater than the thickness of the other three dielectric layers.

[0095] In the example above, the thickness of the first dielectric layer 303 is greater than the thickness of the second dielectric layer 304, and the second dielectric layer 304 is closer to the first chip 100 than the first dielectric layer 303. This allows for a more reasonable distribution of the thicknesses of the dielectric layers in the package structure.

[0096] In one example, an underfill material is provided between the first chip and the circuit layer. This underfill material can be filled by molding or capillary action.

[0097] In one example, the connection between the first chip and the circuit layer is at least one of through-silicon via (TSV) connection, copper pillar connection, flexible circuit board connection, and wire connection. Figure 5 This is a schematic diagram illustrating various connection methods between a first chip and a circuit layer in a semiconductor packaging apparatus according to an embodiment of the present invention. Figure 5 In the upper left diagram, the first chip 100 and the circuit layer 300 are connected via a through-silicon via 101, wherein the through-silicon via 101 is filled with a conductive material, such as metallic copper. Figure 5 In the upper right diagram, the first chip 100 and the circuit layer 300 are connected by copper pillars 102. Figure 5 In the lower left diagram, the first chip 100 and the circuit layer 300 are connected by a flexible circuit board 103. Figure 5 In the lower right diagram, the first chip 100 and the circuit layer 300 are connected by a connecting line 104. The above connection method can be selected according to specific requirements.

[0098] In one example, a heat dissipation layer is provided on the surface of the encapsulation material. For example... Figure 4As shown, a heat dissipation layer 600 is provided on the surface of the encapsulation material 400. The material of the heat dissipation layer 600 is, for example, metallic tin. This helps to improve the heat dissipation performance of the structure. In addition, a silicon dummy layer 500 is provided between the encapsulation material 400 and the heat dissipation layer 600.

[0099] In one example, electrical connectors are located on the bottom surface of the wiring layer. For example... Figure 4 As shown, an electrical connector 700 is provided on the bottom surface of the circuit layer 300. This facilitates the external connection of the semiconductor packaging device.

[0100] In one example, a silicon dummy layer may or may not be placed above the second chip. For example... Figure 6 As shown in the left-hand diagram, a silicon dummy layer 500 is disposed above the second chip 200. The silicon dummy layer 500 serves as a placeholder, thereby adjusting the position of the second chip 200. Figure 6 As shown in the diagram on the right, no silicon dummy layer is set above the second chip 200.

[0101] In one example, the number of first chips or second chips can be at least two. For example... Figure 7 The diagram at the top center shows two first chips: a first chip 100a and a second chip 100b. A second chip 200 is located between the two first chips. Figure 7 The diagram in the lower center shows that there are two first chips, namely the first chip 100a and the second chip 100b, with the second chip 200 located to the right of the two first chips.

[0102] In the semiconductor packaging apparatus provided in this embodiment, the corners of the active surface of the first chip are positioned close to the stress neutral region, which reduces the stress on the stress concentration points of the first chip, thereby reducing the squeezing effect of the corners of the first chip on the surrounding materials (such as packaging materials), avoiding corresponding structural fractures, and improving product yield.

[0103] This embodiment also provides a method for manufacturing a semiconductor packaging device. See [link to documentation]. Figures 8-15 The method includes the following steps:

[0104] The first step involves repeatedly performing photolithography, electroplating, and etching to form the main fan-out layer on the substrate. For example... Figure 8 As shown, the main fan-out layer 301 can be formed on the carrier 10 through repeated processes of photolithography, electroplating and etching.

[0105] The second step involves repeating photolithography, electroplating, and etching processes to form a first fan-out layer on the main fan-out layer. The main fan-out layer and the first fan-out layer together form a circuit layer.

[0106] In one example, the second step described above can be performed as follows: First, a barrier layer is placed on the main fan-out layer, wherein the barrier layer has a cavity. For example... Figure 9 As shown, the barrier layer 11 is placed on the main fan-out layer 301 using the bonding head 12. Next, through repeated processes of photolithography, electroplating, and etching, a first fan-out layer is formed within the cavity of the barrier layer. Figure 10 As shown, a first fan-out layer 302 is formed in the cavity of the barrier layer 11 through repeated processes of photolithography, electroplating and etching.

[0107] The third step is to electrically connect the first chip to the first fan-out layer, wherein the active surface of the first chip faces the circuit layer. For example... Figure 11 As shown, the first chip 100 is placed on the first fan-out layer 302, and the two are electrically connected by soldering. The active surface of the first chip 100 (i.e., Figure 11 The lower surface of the middle layer faces the first fan-out layer 302.

[0108] The fourth step is to apply an underfill material between the first chip and the first fan-out layer. For example... Figure 11 As shown, a bottom filler material can be provided between the first chip 100 and the first fan-out layer 302 by molding or capillary action.

[0109] The fifth step involves molding above the main fan-out layer to obtain a semiconductor package device, wherein the corners of the active surface of the first chip are close to the stress neutral region of the semiconductor package device. Figure 11 As shown, molding is performed above the main fan-out layer 301 to form a packaging material 400 above the main fan-out layer 301, thereby obtaining a semiconductor packaging device. The corners of the active surface of the first chip 100 are close to the stress neutral region of the semiconductor packaging device.

[0110] In one example, before molding above the main fan-out layer, the method further includes: first, connecting the second chip to the main fan-out layer. For example... Figure 11 As shown, the second chip 200 is connected to the main fan-out layer 301. Next, an underfill material is placed between the second chip and the main fan-out layer. (See diagram.) Figure 2 As shown, a bottom filler material is provided between the second chip 200 and the main fan-out layer 301.

[0111] In one example, after molding above the main fan-out layer, the method further includes: forming a heat dissipation layer on the surface of the packaging material of the semiconductor packaging device. This can further improve the heat dissipation performance of the packaging structure.

[0112] In one example, after molding above the main fan-out layer, the method further includes: providing electrical connections on the outer surface of the circuit layer. For example... Figure 5As shown, an electrical connector 700 is provided on the surface of the main fan-out layer 301. This facilitates the external connection of the package structure.

[0113] This embodiment also provides another method for manufacturing a semiconductor packaging device. See [link to documentation]. Figures 14-15 The method includes the following steps.

[0114] First, a circuit layer is formed on the substrate through repeated processes of photolithography, electroplating, and etching. For example... Figure 14 As shown, a circuit layer 300 can be formed on the carrier 10 through repeated processes of photolithography, electroplating, and etching. The circuit layer 300 includes four dielectric layers.

[0115] Next, connect the first chip and the second chip to the circuit layer respectively. For example... Figure 15 As shown, the first chip 100 and the second chip 200 can be connected to the circuit layer 300 by soldering.

[0116] Subsequently, underfill materials are applied between the first chip and the circuit layer, and between the second chip and the circuit layer, respectively. For example... Figure 15 As shown, underfill materials are provided between the first chip 100 and the circuit layer 300, and between the second chip 200 and the circuit layer 300, respectively. The underfill material is, for example, underfill adhesive.

[0117] Finally, molding is performed on top of the circuit layer to obtain the semiconductor package device. For example... Figure 15 As shown, molding is performed above the circuit layer 300 to fill the encapsulation material 400, thereby obtaining a semiconductor packaging device.

[0118] The method for manufacturing a semiconductor packaging device in this embodiment can achieve similar technical effects to the aforementioned semiconductor packaging device, and will not be described in detail here.

[0119] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor package device, comprising a first chip and a circuit layer; the first chip is located on the circuit layer, and a main surface of the first chip faces the circuit layer; the semiconductor package device defines a stress neutral zone, a corner of the main surface of the first chip is close to the stress neutral zone, the circuit layer comprises a main fan-out layer and a first fan-out layer located on the main fan-out layer, an upper surface of the first fan-out layer is closer to the stress neutral zone than an upper surface of the main fan-out layer, the first chip is located on the first fan-out layer, and a distance between the stress neutral zone and a bottom surface of the semiconductor package device is determined by the following formula (1): C=A·[E1(v1+y·s)+E2(v2-y·s)] formula (1) wherein C is the distance between the stress neutral zone and the bottom surface of the semiconductor package device, A is a preset constant, E1 is a Young's modulus of the first fan-out layer, E2 is a Young's modulus of a packaging material, s is an area of the first fan-out layer, y is a thickness of the first fan-out layer, v1 is a volume ratio of the first fan-out layer to the semiconductor package device, and v2 is a volume ratio of the packaging material to the semiconductor package device. The semiconductor package device further comprises a second chip located on the circuit layer.

2. The semiconductor package device of claim 1, wherein, The second chip is located on the main fan-out layer.

3. The semiconductor package device of claim 1, wherein, The semiconductor package device further comprises a second fan-out layer located on the main fan-out layer, the second fan-out layer and the first fan-out layer are located on the same side of the main fan-out layer, and the second chip is located on the second fan-out layer.

4. The semiconductor package device of claim 3, wherein, A corner of a main surface of the second chip is close to the stress neutral zone.

5. The semiconductor package device of claim 1, wherein, The stress neutral zone is located near a middle position of the semiconductor package device in a thickness direction. 6.A manufacturing method of a semiconductor package device, comprising: forming a main fan-out layer on a carrier through a repeated process of photolithography, electroplating and etching; forming a first fan-out layer on the main fan-out layer through a repeated process of photolithography, electroplating and etching, wherein the main fan-out layer and the first fan-out layer jointly form a circuit layer; electrically connecting a first chip to the first fan-out layer, wherein a main surface of the first chip faces the circuit layer; disposing an underfill material between the first chip and the first fan-out layer; molding above the main fan-out layer to obtain a semiconductor package device, wherein the semiconductor package device defines a stress neutral zone, a corner of a main surface of the first chip is close to the stress neutral zone, and a distance between the stress neutral zone and a bottom surface of the semiconductor package device is determined by the following formula (1): C=A·[E1(v1+y·s)+E2(v2-y·s)] formula (1) wherein C is the distance between the stress neutral zone and the bottom surface of the semiconductor package device, A is a preset constant, E1 is a Young's modulus of the first fan-out layer, E2 is a Young's modulus of a packaging material, s is an area of the first fan-out layer, y is a thickness of the first fan-out layer, v1 is a volume ratio of the first fan-out layer to the semiconductor package device, and v2 is a volume ratio of the packaging material to the semiconductor package device.

7. The method of claim 6, wherein, The repeated process of photolithography, electroplating and etching to form a first fan-out layer on the main fan-out layer comprises: placing a barrier layer on the main fan-out layer, wherein the barrier layer has a cavity; forming the first fan-out layer in the cavity of the barrier layer by the repeated process of photolithography, electroplating and etching.

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