Semiconductor packaging device and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor packaging device and a manufacturing method thereof. By reducing the area of ​​the conductive pillars in contact with the chip electrical connectors, the conductive pillars in the redistribution layer can still be in contact with the chip electrical connectors even if the chip is offset during the bonding process between the redistribution layer and the chip, thereby improving the product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and more particularly to a semiconductor packaging device and a manufacturing method thereof. Background Art

[0002] In the fan-out package (Fan-Out Package), according to the order of the redistribution process, it is mainly divided into two types: chip first (ChipFirst) and chip last (ChipLast). In the chip first process, the conductive pillar (Pillar) is first formed at the chip bonding pad (Diepad) and then the bonding (Recon) operation is performed to bond the redistribution layer to the chip. Due to the limitation of Recon accuracy, the chip will be offset (Dieshift), resulting in the conductive holes (Via) of the redistribution layer to be formed on the conductive pillars to be unable to be fully aligned with the conductive pillars. This may result in a lack of connection between the chip's bonding pads and the conductive holes of the redistribution layer, resulting in failure of the fan-out package and low product yield. In addition, since the conductive holes of the redistribution layer are not fully aligned with the conductive pillars, the size of the conductive holes may exceed the docking part, and the current channel formed beyond the docking part may affect the adjacent conductive pillars and generate electrical interference, which will further reduce the product yield. Summary of the Invention

[0003] The present disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0004] In a first aspect, the present disclosure provides a semiconductor packaging device, the semiconductor packaging device comprising: a chip assembly, the chip assembly comprising at least one chip, an active surface of the chip being provided with a chip electrical connector;

[0005] an adhesive layer, disposed on the chip component and covering the chip component;

[0006] a redistribution layer, disposed on the chip assembly;

[0007] The redistribution layer has a first conductive column, which passes through the adhesive layer to electrically connect the redistribution layer and the chip electrical connector. The lower surface perimeter and / or area of ​​the first conductive column is smaller than the upper surface perimeter and / or area of ​​the chip electrical connector.

[0008] In some optional embodiments, the perimeter and / or area of ​​the upper surface of the first conductive pillar is greater than the perimeter and / or area of ​​the lower surface of the first conductive pillar.

[0009] In some optional embodiments, a ratio of a circumference of the upper surface of the first conductive pillar to a circumference of the lower surface of the first conductive pillar is between 1 and 25.

[0010] In some optional embodiments, the first conductive column includes a cylindrical conductive column and an inverted frustum conductive column respectively arranged at the upper and lower parts of the first conductive column, the diameter of the cylindrical conductive column is larger than the upper surface diameter of the inverted frustum conductive column, and the inverted frustum conductive column is partially embedded in the redistribution layer.

[0011] In some optional embodiments, the ratio of the height of the inverted truncated cone conductive pillar to the height of the portion of the inverted truncated cone conductive pillar embedded in the redistribution layer is between 2 and 20.

[0012] In some optional embodiments, the diameter of the cylindrical conductive pillar is 10 microns to 50 microns; and / or the diameter of the lower surface of the inverted frustum-shaped conductive pillar is 2 microns to 10 microns.

[0013] In some optional embodiments, the height of the inverted truncated cone conductive pillar is 10 to 40 microns; and / or the height of the portion of the inverted truncated cone conductive pillar embedded in the redistribution layer is 2 to 20 microns.

[0014] In some optional embodiments, the thickness of the adhesive layer is 40 microns to 150 microns.

[0015] In some optional embodiments, the upper surface of the chip electrical connector is circular with a diameter between 10 microns and 100 microns.

[0016] In some optional embodiments, the ratio of the upper surface diameter of the chip electrical connector to the lower surface diameter of the inverted frustum-conical conductive pillar is 5 to 50.

[0017] In some optional embodiments, the exposure angle is between 30° and 80°, and the exposure angle is the angle between the cross-sectional lines of the busbar of the inverted conical conductive column and the chip electrical connector obtained by sectioning the busbar of the inverted conical conductive column and the chip electrical connector.

[0018] In some optional embodiments, the first conductive pillar comprises a metal layer and a seed layer surrounding the metal layer, wherein the seed layer comprises a copper layer with a thickness of 0.1 micrometer to 0.5 micrometer and a titanium layer with a thickness of 0.1 micrometer to 0.5 micrometer.

[0019] In some optional embodiments, the semiconductor packaging device further includes:

[0020] A substrate is provided on which the adhesive layer and the chip assembly are arranged.

[0021] In some optional embodiments, the redistribution layer further includes a second conductive column, which passes through the adhesive layer to electrically connect the redistribution layer and the intra-substrate electrical connector provided on the upper surface of the substrate, and the circumference and / or area of ​​the lower surface of the second conductive column is smaller than the circumference and / or area of ​​the upper surface of the intra-substrate electrical connector.

[0022] In some optional embodiments, the semiconductor packaging device further includes a substrate external electrical connection provided on the lower surface of the substrate.

[0023] In some optional embodiments, the semiconductor package device further includes an external electrical connection member disposed on an upper surface of the redistribution layer.

[0024] In some optional embodiments, the external electrical connector includes a fan-out electrical connector and / or a fan-in electrical connector.

[0025] In some optional embodiments, the external electrical connection includes at least one of the following: a ball grid array package solder ball, a flip chip solder ball, a land grid array package solder ball, a bump, and a conductive column.

[0026] In some optional embodiments, the semiconductor package device further includes at least one electronic component electrically connected to the redistribution layer through the external electrical connection.

[0027] In some optional embodiments, the chip assembly includes at least two chips arranged side by side.

[0028] In some optional embodiments, the chip assembly includes at least two stacked chip assembly layers, and each chip assembly layer includes at least one chip.

[0029] In some optional embodiments, the chip electrical connector is a solder pad.

[0030] In some optional embodiments, the chip electrical connector includes a fourth conductive pillar electrically connected to the chip and a micro bump bonded to the fourth conductive pillar.

[0031] In some optional embodiments, the chip electrical connector includes a fifth conductive pillar electrically connected to the chip and a first bonding pad bonded to the fifth conductive pillar. A first protective layer surrounding the fifth conductive pillar is provided on the top surface of the chip, the cross-sectional area of ​​the first bonding pad is larger than the cross-sectional area of ​​the fifth conductive pillar, and the fifth conductive pillar and the first protective layer are coplanar.

[0032] In some optional embodiments, the chip electrical connector includes a chip pad electrically connected to the chip and a second bonding pad bonded to the chip pad, the upper surface of the chip is provided with a second protective layer surrounding the chip pad, and the second bonding pad is partially embedded in the second protective layer.

[0033] In some optional embodiments, the intra-substrate electrical connector includes a substrate pad and a third bonding pad surrounding the substrate pad.

[0034] In some optional embodiments, the semiconductor packaging device further includes bonding wires electrically connecting the chip and the substrate.

[0035] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor package device, the method comprising:

[0036] forming at least one temporary conductive post on the carrier;

[0037] forming a protective layer and a seed layer on the top of each temporary conductive column;

[0038] forming a first circuit layer on the carrier board with a thickness smaller than the height of each of the temporary conductive pillars, wherein the first circuit layer surrounds the bottom of each of the temporary conductive pillars;

[0039] removing the protective layer on the top of each temporary conductive column;

[0040] Disposing a reinforcement dielectric layer on the first circuit layer, each of the temporary conductive pillars is exposed from the reinforcement dielectric layer, and the first circuit layer and the reinforcement dielectric layer form a redistribution layer;

[0041] Etching to remove an edge portion of a top portion of the temporary conductive pillar;

[0042] placing the chip assembly on a substrate;

[0043] Adhere the structure including the carrier, the temporary conductive pillars and the redistribution layer to the chip assembly and the substrate using a non-conductive adhesive;

[0044] removing the carrier board;

[0045] Etching away the seed layer on the surface of the structure, and wet etching away the temporary conductive pillars to form corresponding temporary guide holes;

[0046] dry etching each of the temporary guide holes so that each of the temporary guide holes contacts the chip electrical connector of the chip assembly or the intra-substrate electrical connector on the substrate;

[0047] Coating photoresist on each of the temporary guide holes and the surface of the structure, performing photolithography and electroplating, and then removing the photoresist to form a first conductive column in each of the temporary guide holes and a circuit pattern on the surface of the structure;

[0048] fabricating a circuit layer on the surface of the structure;

[0049] mounting electronic components on the surface of the structure;

[0050] A substrate external electrical connector is mounted on the lower surface of the substrate.

[0051] In order to solve the technical problem of low product yield caused by misalignment between the conductive pillars on the chip and the conductive holes on the redistribution layer in the existing fan-out packaging, the semiconductor packaging device and its manufacturing method provided by the present invention reduce the area of ​​the conductive pillars in contact with the chip electrical connectors. Even if the chip is offset during the bonding process between the redistribution layer and the chip, the conductive pillars can still be in contact with the chip electrical connectors, thereby improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Other features, objects and advantages of the present disclosure will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

[0053] Figure 1A is a schematic longitudinal cross-sectional view of an embodiment of a semiconductor packaging device according to the present disclosure;

[0054] Figure 1B is a schematic longitudinal cross-sectional view of another embodiment of a semiconductor packaging device according to the present disclosure;

[0055] Figure 1C is a schematic longitudinal cross-sectional view of another embodiment of a semiconductor packaging device according to the present disclosure;

[0056] Figure 1D is a schematic longitudinal cross-sectional view of another embodiment of a semiconductor packaging device according to the present disclosure;

[0057] Figure 1E is a schematic longitudinal cross-sectional view of another embodiment of a semiconductor packaging device according to the present disclosure;

[0058] Figure 1F is a schematic longitudinal cross-sectional view of another embodiment of a semiconductor packaging device according to the present disclosure;

[0059] Figure 1G is a schematic longitudinal cross-sectional view of another embodiment of a semiconductor packaging device according to the present disclosure;

[0060] Figure 2AAccording to some embodiments of the present disclosure Figure 1A An enlarged view of a portion of the dotted circle C1 shown in FIG.

[0061] Figure 2B According to some embodiments of the present disclosure Figure 1A An enlarged view of a portion of the dotted circle C shown in FIG.

[0062] Figures 3A-3O 1 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor package device manufactured at various stages according to an embodiment of the present disclosure.

[0063] Explanation of symbols:

[0064] 2-chip components; 4 redistribution layers;

[0065] 21 chip; 41 first conductive column;

[0066] 211 chip electrical connector; 411 cylindrical conductive column;

[0067] 2111 fourth conductive column; 412 inverted frustum conductive column;

[0068] 2112 micro bump; 413 metal layer;

[0069] 2113 fifth conductive column; 414 seed layer;

[0070] 2114 first bonding pad; 42 second conductive column;

[0071] 2115 first protective layer; 1 substrate;

[0072] 2116 chip pad; 11 electrical connector within substrate;

[0073] 2117 second bonding pad; 111 substrate pad;

[0074] 2118 second protective layer; 112 third bonding pad;

[0075] 3 adhesive layer; 12 substrate external electrical connection;

[0076] 5 external electrical connections; 7 bonding wires;

[0077] 6 electronic components; 8 carrier boards;

[0078] 43 first circuit layer; 9a temporary conductive column;

[0079] 9b temporary guide hole; 10 protective layer. DETAILED DESCRIPTION

[0080] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present invention and the technical effects produced by the present invention through the contents of this specification. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0081] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0082] It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0083] In addition, the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0084] refer to Figure 1A , Figure 1A FIG2 shows a schematic longitudinal cross-sectional view of an embodiment of a semiconductor packaging device 1 a according to the present disclosure.

[0085] like Figure 1A As shown, the semiconductor package device 1 a may include a chip assembly 2 , an adhesive layer 3 and a redistribution layer 4 .

[0086] in:

[0087] The chip assembly 2 includes at least one chip 21 . The active surface of the chip 21 may be provided with a chip electrical connector 211 for connecting the chip 21 to the outside.

[0088] The adhesive layer 3 may be disposed on the chip component 2 and cover the chip component 2. The adhesive layer 3 is used to bond the chip component 2 and the redistribution layer 4.

[0089] The redistribution layer 4 can be provided on the chip component and fixed to the chip component 2 via the adhesive layer 3 .

[0090] The redistribution layer 4 may include a first conductive pillar 41, which passes through the adhesive layer 3 to electrically connect the redistribution layer 4 and the chip electrical connector 211. The perimeter and / or area of ​​the lower surface of the first conductive pillar 41 is smaller than the perimeter and / or area of ​​the upper surface of the chip electrical connector 211. Because the perimeter and / or area of ​​the lower surface of the first conductive pillar 41 is smaller than the perimeter and / or area of ​​the upper surface of the chip electrical connector 211, even if the chip 21 is slightly offset during the bonding process between the first conductive pillar 41 and the chip electrical connector 211, the first conductive pillar 41 can still be bonded to the chip electrical connector 211. This avoids the problem of the packaged device product failing due to the lack of contact between the two, which may occur in existing fan-out packages, and also avoids electrical interference problems that may arise due to the first conductive pillar 41 being offset and closer to adjacent conductive pillars.

[0091] In addition, according to actual needs, various wires, through holes, buried holes or blind holes can be provided in the redistribution layer 4 to achieve circuit connection. It should be noted that the size or direction of the through holes, buried holes or blind holes is not specifically limited here. If through holes, buried holes or blind holes are provided, the through holes, buried holes or blind holes can be filled with conductive materials such as metals or metal alloys, or contain conductive materials such as metals or metal alloys. Here, the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu) or their alloys.

[0092] The chip assembly 2 may include one chip 21 , or may include two or more chips 21 .

[0093] Here, the chip 21 may be a bare die or chip including various semiconductors and / or circuits. The chip 21 may also have various functions, for example, the chip 21 may be a logic chip for implementing logical operations or a memory chip for implementing data storage.

[0094] The technical effects achieved by the semiconductor package device 1a include, but are not limited to, the following: by designing a first conductive pillar in the redistribution layer, wherein the perimeter and / or area of ​​the lower surface of the surface of the first conductive pillar contacting the chip is smaller than the perimeter and / or area of ​​the upper surface of the chip electrical connector. This ensures that even if the chip shifts slightly during the bonding process between the first conductive pillar and the chip electrical connector, the first conductive pillar can still bond with the chip electrical connector. This avoids the problem of the package device failing due to lack of contact between the two, which can occur in existing fan-out packages, and also avoids electrical interference that may arise from the first conductive pillar shifting closer to adjacent conductive pillars.

[0095] In some optional embodiments, the perimeter and / or area of ​​the upper surface of the first conductive pillar 41 can be larger than the perimeter and / or area of ​​the lower surface of the first conductive pillar 41. That is, the first conductive pillar 41 is larger at the top and smaller at the bottom. The perimeter and / or area of ​​the lower surface of the first conductive pillar 41 only needs to be smaller than the perimeter and / or area of ​​the upper surface of the chip electrical connector 211, while the perimeter and / or area of ​​the upper surface of the first conductive pillar 41 does not need to be smaller than the perimeter and / or area of ​​the upper surface of the chip electrical connector 211. This can reduce the difficulty of the manufacturing process. Moreover, since the perimeter and / or area of ​​the upper surface of the first conductive pillar 41 is larger, it is also convenient to connect the chip 21 to the outside world through the upper surface of the first conductive pillar 41 of the redistribution layer 4.

[0096] In some optional embodiments, the ratio of the circumference of the upper surface of the first conductive pillar 41 to the circumference of the lower surface of the first conductive pillar 41 is between 1 and 25. That is, the circumference of the lower surface of the first conductive pillar 41 is significantly reduced relative to the circumference of the upper surface of the first conductive pillar 41, thereby further improving the contact possibility between the first conductive pillar 41 and the chip electrical connector 211, thereby preventing possible deviation of the chip 21 during the bonding process.

[0097] In some optional embodiments, the first conductive column 41 includes a cylindrical conductive column 411 and an inverted frustum conductive column 412 respectively arranged at the upper and lower parts of the first conductive column 41, the diameter of the cylindrical conductive column is larger than the upper surface diameter of the inverted frustum conductive column, and the inverted frustum conductive column is partially embedded in the redistribution layer 4, while the other part is embedded in the adhesive layer 3.

[0098] In some optional implementations, the ratio of the height of the inverted truncated cone conductive pillar 412 to the height of the portion of the inverted truncated cone conductive pillar 412 embedded in the redistribution layer 4 is between 2 and 20.

[0099] Please refer to Figure 2A , Figure 2A According to some embodiments of the present disclosure Figure 1A An enlarged view of a portion of the dotted circle C1 shown in FIG. Figure 2A As shown, the height of the inverted truncated cone conductive pillar 412 is T, and the height of the portion of the inverted truncated cone conductive pillar 412 embedded in the redistribution layer 4 is t. The ratio of T to t, T / t, is between 2 and 20. When the first conductive pillar 41 includes a cylindrical conductive pillar 411 and an inverted truncated cone conductive pillar 412 disposed at the upper and lower portions of the first conductive pillar 41, respectively, the ratio of the circumference of the upper surface of the first conductive pillar 41 to the circumference of the lower surface of the first conductive pillar 41, i.e., the ratio of the diameter D of the cylindrical conductive pillar 411 to the diameter d of the lower surface of the inverted truncated cone conductive pillar 412, is between 1 and 25.

[0100] In some optional embodiments, the diameter D of the cylindrical conductive pillar 411 (eg Figure 2Aand / or, the diameter d of the lower surface of the inverted frustum conductive column 412 (as shown) is 10 microns to 50 microns; Figure 2A shown) is 2 microns to 10 microns.

[0101] In some optional embodiments, the height T of the inverted frustum conductive pillar 412 (eg Figure 2A and / or, the height t of the inverted frustum conductive column 412 embedded in the redistribution layer 4 portion (as shown) is 10 to 40 microns; Figure 2A shown) is 2 to 20 microns.

[0102] In some optional embodiments, the thickness A of the adhesive layer 3 (eg Figure 1A shown) is 40 microns to 150 microns.

[0103] In some optional embodiments, the upper surface of the chip electrical connector 211 has a diameter P (eg Figure 1A For example, the chip electrical connection member 211 may be a circular pad or bonding pad.

[0104] In some optional embodiments, the upper surface diameter P of the chip electrical connector 211 (eg Figure 1A As shown) and the diameter d of the lower surface of the inverted frustum conductive column (as shown Figure 2A The ratio is 5 to 50.

[0105] In some optional embodiments, the exposure angle α (e.g. Figure 2A ) is between 30° and 80°. Here, the exposure angle α is the angle between the busbar of the inverted frustum conductive pillar 412 and the cross-sectional line of the chip electrical connector 211, obtained by sectioning the busbar of the inverted frustum conductive pillar 412 and the chip electrical connector 211. If the exposure angle α is less than 30°, the aperture of the inverted frustum conductive pillar 412 will be too large, resulting in a reduced contact rate between the first conductive pillar 41 and the chip electrical connector 211; if the exposure angle α is greater than 80°, the aperture of the inverted frustum conductive pillar 412 will be too small, and the process difficulty will be very high. An exposure angle α between 30° and 80° can achieve a balance between the two.

[0106] In some optional embodiments, the first conductive pillar 41 has a metal layer 413 and a seed layer 414 surrounding the metal layer 413 . The seed layer 414 may include a copper layer with a thickness of 0.1 to 0.5 microns and a titanium layer with a thickness of 0.1 to 0.5 microns.

[0107] In some optional embodiments, the semiconductor packaging device 1a may further include: a substrate 1. The adhesive layer 3 and the chip assembly 2 are provided on the substrate 1. Here, the substrate 1 may include circuits therein and / or thereon. The substrate 1 may also include conductive traces. The substrate 1 may also include conductive pads. The substrate 1 may include semiconductor materials. The substrate 1 may also include conductive materials. The substrate 1 may also include insulating materials (such as dielectric materials). The substrate 1 may also include ceramics, bismaleimidetriazine (BT), FR4, prepreg (PP) or other suitable materials. The substrate 1 may also include opaque materials.

[0108] In some optional embodiments, the redistribution layer 4 may further include a second conductive pillar 42. The second conductive pillar 42 may pass through the adhesive layer 3 to electrically connect the redistribution layer 4 and the intra-substrate electrical connector 11 provided on the upper surface of the substrate 1. The perimeter and / or area of ​​the lower surface of the second conductive pillar 42 may be smaller than the perimeter and / or area of ​​the upper surface of the intra-substrate electrical connector 11. Since the perimeter and / or area of ​​the lower surface of the second conductive pillar 42 is smaller than the perimeter and / or area of ​​the upper surface of the intra-substrate electrical connector 11, even if the substrate 1 is slightly offset during the bonding process between the second conductive pillar 42 and the intra-substrate electrical connector 11, the second conductive pillar 42 can still be bonded to the intra-substrate electrical connector 11. Thus, the problem of the two not being able to contact each other, which may occur in existing fan-out packages, resulting in the failure of the packaged device product, will not occur. Also, the problem of electrical interference that may be caused by the second conductive pillar 42 being offset and close to the adjacent conductive pillars will not occur.

[0109] It should be noted that the second conductive pillar 42 here may also have the various properties and characteristics of the second conductive pillar 42 described above.

[0110] For example, in some optional embodiments, the perimeter and / or area of ​​the upper surface of the second conductive pillar 42 can be larger than the perimeter and / or area of ​​the lower surface of the second conductive pillar 42. That is, the second conductive pillar 42 can also be in a shape that is larger at the top and smaller at the bottom. It is only necessary that the perimeter and / or area of ​​the lower surface of the second conductive pillar 42 is smaller than the perimeter and / or area of ​​the upper surface of the electrical connector 11 in the substrate, while the perimeter and / or area of ​​the upper surface of the second conductive pillar 42 is not required to be smaller than the perimeter and / or area of ​​the upper surface of the electrical connector 11 in the substrate. This can reduce the difficulty of the manufacturing process. Moreover, since the perimeter and / or area of ​​the upper surface of the second conductive pillar 42 is larger, it is also convenient to connect the substrate 1 to the outside world through the upper surface of the second conductive pillar 42 in the redistribution layer 4.

[0111] In some optional embodiments, the ratio of the circumference of the upper surface of the second conductive pillar 42 to the circumference of the lower surface of the second conductive pillar 42 is between 1 and 25. That is, the circumference of the lower surface of the second conductive pillar 42 is significantly reduced relative to the circumference of the upper surface of the second conductive pillar 42, thereby further improving the contact possibility between the second conductive pillar 42 and the electrical connector 11 in the substrate, thereby compensating for possible deviation of the substrate 1 during the bonding process.

[0112] In some optional embodiments, the second conductive column 42 may also include a cylindrical conductive column and an inverted frustum conductive column respectively arranged at the upper and lower parts of the second conductive column 42, wherein the diameter of the cylindrical conductive column is larger than the upper surface diameter of the inverted frustum conductive column, and the inverted frustum conductive column is partially embedded in the redistribution layer 4, and the other part is embedded in the adhesive layer 3.

[0113] In some optional embodiments, the ratio of the height of the inverted truncated cone conductive pillar 412 of the second conductive pillar 42 to the height of the portion of the inverted truncated cone conductive pillar 412 embedded in the redistribution layer 4 is between 2 and 20.

[0114] In some optional embodiments, the ratio of the diameter of the cylindrical conductive pillar in the second conductive pillar 42 to the diameter of the lower surface of the inverted truncated cone conductive pillar is between 1 and 25.

[0115] In some optional embodiments, the diameter of the cylindrical conductive pillar in the second conductive pillar 42 is 10 microns to 50 microns; and / or the diameter d of the lower surface of the inverted frustum-shaped conductive pillar in the second conductive pillar 42 is 2 microns to 10 microns.

[0116] In some optional embodiments, the height of the inverted truncated cone conductive pillars in the second conductive pillars 42 is 10 to 40 microns; and / or the height of the portion of the inverted truncated cone conductive pillar embedded in the redistribution layer 4 is 2 to 20 microns.

[0117] In some optional embodiments, the upper surface of the intra-substrate electrical connector 11 is circular with a diameter between 10 micrometers and 100 micrometers. For example, the intra-substrate electrical connector 11 can be a circular pad or soldering pad.

[0118] In some optional embodiments, the ratio of the upper surface diameter of the intra-substrate electrical connector 11 to the lower surface diameter of the inverted frustum-shaped conductive pillar in the second conductive pillar 42 is 5 to 50.

[0119] In some optional embodiments, the exposure angle of the second conductive pillar 42 may also be between 30° and 80°. Here, the exposure angle of the second conductive pillar 42 is the angle between the busbar of the inverted truncated cone conductive pillar and the cross-section line of the substrate electrical connector 11, obtained by sectioning the inverted truncated cone conductive pillar and the substrate electrical connector 11 along the busbar of the inverted truncated cone conductive pillar of the second conductive pillar 42.

[0120] In some optional embodiments, the second conductive pillar 42 may include a metal layer and a seed layer surrounding the metal layer, wherein the seed layer may include a copper layer with a thickness of 0.1 to 0.5 microns and a titanium layer with a thickness of 0.1 to 0.5 microns.

[0121] In some optional embodiments, the semiconductor package device 1a may further include an external substrate electrical connector 12 provided on the lower surface of the substrate 1. The external substrate electrical connector 12 may be, for example, a solder ball, a pad, a bump, or a conductive pillar.

[0122] In some optional embodiments, the semiconductor package device 1a may further include external electrical connectors 5 disposed on the upper surface of the redistribution layer 4. The external electrical connectors 5 may be, for example, various conductive elements such as solder balls, pads, bumps, or conductive pillars.

[0123] In some optional embodiments, the external electrical connector 5 includes a fan-out electrical connector and / or a fan-in electrical connector.

[0124] In some optional embodiments, the external electrical connection member 5 may include at least one of the following: a ball grid array package solder ball, a flip chip solder ball, a land grid array package solder ball, a bump, and a conductive column.

[0125] In some optional embodiments, the semiconductor package device 1 a may further include at least one electronic component 6 electrically connected to the redistribution layer 4 through an external electrical connector 5 .

[0126] Continue to refer Figure 1B , Figure 1B The semiconductor package device 1b shown in FIG. 1 is similar to Figure 1A The antenna semiconductor package device 1a shown in FIG. 1 is different in that the chip assembly 2 may include at least two chips 21 arranged side by side. Furthermore, each chip 21 is connected to the redistribution layer 4 via a first conductive pillar 41. The semiconductor package device 1b may include at least one of the aforementioned chip assemblies 2.

[0127] Continue to refer Figure 1C , Figure 1C The semiconductor package device 1c shown in FIG. 1 is similar to Figure 1A The difference between the antenna semiconductor package device 1a shown in FIG and FIG is that the chip assembly 2 includes at least two stacked chip assembly layers, each chip assembly layer includes at least one chip 21. Moreover, each chip 21 is connected to the redistribution layer 4 through a first conductive column 41. Figure 1C As shown, the chips 21 of different chip component layers may be in a stepped shape.

[0128] Continue to refer Figure 1D , Figure 1D The semiconductor package device 1d shown in FIG. 1 is similar to Figure 1A The antenna semiconductor package device 1 a shown in FIG. 1 is different in that the chip electrical connector 211 includes a fourth conductive pillar 2111 electrically connected to the chip 21 and a micro bump 2112 bonded to the fourth conductive pillar 2111 .

[0129] Continue to refer Figure 1E , Figure 1E The semiconductor package device 1e shown in FIG. 1 is similar to Figure 1A The antenna semiconductor package device 1a shown in FIG. differs in that the chip electrical connector 211 includes a fifth conductive pillar 2113 electrically connected to the chip 21 and a first bonding pad 2114 bonded to the fifth conductive pillar 2113. A first protection layer (isolation) 2115 is provided on the top surface of the chip 21, surrounding the fifth conductive pillar 2113. The cross-sectional area of ​​the first bonding pad 2114 is larger than that of the fifth conductive pillar 2113, and the fifth conductive pillar 2113 and the first protection layer 2115 are coplanar.

[0130] Continue to refer Figure 1F , Figure 1F The semiconductor package device 1f shown in FIG. Figure 1A The antenna semiconductor packaging device 1a shown in the figure is different in that: the chip electrical connector 211 includes a chip pad 2116 electrically connected to the chip 21 and a second bonding pad 2117 bonded to the chip pad 2116, and the upper surface of the chip 21 is provided with a second protective layer 2118 surrounding the chip pad 2116, and the second bonding pad 2117 is partially embedded in the second protective layer 2118.

[0131] Please refer to Figure 2B , Figure 2B According to some embodiments of the present disclosure Figure 1A An enlarged view of a portion of the dotted circle C2 shown in FIG. Figure 2B As shown, the intra-substrate electrical connector 11 may include a substrate pad 111 and a third bonding pad 112 surrounding the substrate pad 111 .

[0132] Continue to refer Figure 1G , Figure 1G The semiconductor package device 1g shown in FIG. 1 is similar to Figure 1A The antenna semiconductor package device 1 a shown in FIG. 1 is different in that the semiconductor package device 1 g further includes bonding wires 7 electrically connecting the chip 21 and the substrate 1 .

[0133] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3G 、 Figure 3H 、 Figure 3I 、 Figure 3J 、 Figure 3K 、 Figure 3L 、 Figure 3M 、 Figure 3N and Figure 3O Schematic diagrams of longitudinal cross-sectional structures of antenna semiconductor package devices 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 3i, 3j, 3k, 3l, 3m, 3n, and 30 at various stages of manufacture according to some embodiments of the present disclosure. The figures have been simplified to facilitate a better understanding of various aspects of the present disclosure.

[0134] refer to Figure 3A , at least one temporary conductive pillar 9 is formed on a carrier 8 .

[0135] Specifically, it can be executed as follows:

[0136] First, a seed layer is grown on the carrier 8 . For example, the seed layer can be grown on the carrier by physical vapor deposition (PVD, Physical Vapor Deposition) or chemical vapor deposition (CVD, Chemical Vapor Deposition).

[0137] Then, a photoresist is laminated on the seed layer, and then photolithography is performed and electroplating is performed to form at least one temporary conductive pillar.

[0138] Finally, the photoresist is removed, thereby forming at least one temporary conductive pillar 9 on the carrier 8 .

[0139] refer to Figure 3B A protective layer 10 and a seed layer are formed on the top of each temporary conductive pillar 9a. The protective layer 10 is made of an insulating material. For example, the protective layer 10 can be formed by flipping the structure of the temporary conductive pillars 9a and the carrier 8, and then dipping the top of at least one temporary conductive pillar 9a in a non-conductive material and curing it (e.g., baking it). The seed layer can be formed using PVD or CVD.

[0140] refer to Figure 3C , a first circuit layer 43 having a thickness less than the height of each temporary conductive pillar 9a is formed on the carrier 8. Here, the first circuit layer 43 surrounds the bottom of each temporary conductive pillar 9a. Specifically, the following operations can be repeated multiple times according to actual needs to form the first circuit layer 43:

[0141] First, a dielectric layer is provided on the seed layer on the carrier 8. For example, a coating method may be used.

[0142] Then, the dielectric layer on the carrier 8 is photolithographically processed to form required vias.

[0143] Next, a seed layer is formed on the surface of the dielectric layer.

[0144] Afterwards, photoresist is coated on the surface of the formed seed layer, followed by photolithography and electroplating to fill the guide holes with metal and form a circuit pattern.

[0145] Finally, the photoresist is removed and the seed layer is etched away to form the first circuit layer 43 .

[0146] refer to Figure 3D , remove the protection layer 10 on the top of each temporary conductive pillar 9a. For example, the protection layer 10 can be removed by using a wet etching process or a dry etching process.

[0147] refer to Figure 3E A reinforcement dielectric layer 44 is provided on the first circuit layer 43 , and each temporary conductive pillar 9 a is exposed from the reinforcement dielectric layer 44 . The first circuit layer 43 and the reinforcement dielectric layer 44 form a redistribution layer 4 .

[0148] refer to Figure 3F , etching to remove the edge portion of the top of the temporary conductive column 9a.

[0149] refer to Figure 3G , the chip assembly 2 is arranged on the substrate 1. For example, it can be achieved by bonding with non-conductive adhesive.

[0150] refer to Figure 3H The structure including the carrier 8, the temporary conductive pillars 9a and the redistribution layer 4 is bonded to the chip assembly 2 and the substrate 1 using non-conductive adhesive.

[0151] refer to Figure 3I , remove the carrier board 8.

[0152] refer to Figure 3J , etching away the seed layer on the surface of the structure, and wet-etching away the temporary conductive pillars 9a to form corresponding temporary guide holes 9b.

[0153] refer to Figure 3K , dry etching is performed on each temporary guide hole 9 b so that each temporary guide hole 9 b contacts the chip electrical connector 211 of the chip assembly 2 or the intra-substrate electrical connector 11 on the substrate 1 .

[0154] refer to Figure 3L , photoresist is coated on each temporary guide hole 9b and the surface of the structure, and then photolithography and electroplating are performed, and then the photoresist is removed to form a first conductive column 41 in each temporary guide hole 9b and a circuit pattern on the surface of the structure.

[0155] refer to Figure 3M, a circuit layer is formed on the surface of the structure. The specific process may be, for example, coating a dielectric layer, followed by photolithography and then plating the circuit.

[0156] refer to Figure 3N , mounting electronic components 6 on the surface of the structure.

[0157] refer to Figure 3O , a substrate external electrical connection part 12 is installed on the lower surface of the substrate 1.

[0158] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present disclosure and the actual implementation. There may be other embodiments of the present disclosure that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A semiconductor packaging device, comprising: A chip assembly, the chip assembly comprising at least one chip, the active surface of the chip being provided with a chip electrical connector; an adhesive layer, disposed on the chip component and covering the chip component; A redistribution layer is provided on the chip assembly; The redistribution layer has a first conductive column, which passes through the adhesive layer to electrically connect the redistribution layer and the chip electrical connector. The circumference and / or area of ​​the lower surface of the first conductive column is smaller than the circumference and / or area of ​​the upper surface of the chip electrical connector. The circumference and / or area of ​​the upper surface of the first conductive column is larger than the circumference and / or area of ​​the lower surface of the first conductive column. The first conductive column includes a cylindrical conductive column and an inverted frustum conductive column respectively arranged at the upper and lower parts of the first conductive column. The diameter of the cylindrical conductive column is larger than the upper surface diameter of the inverted frustum conductive column, and the inverted frustum conductive column is partially embedded in the redistribution layer.

2. The semiconductor package device according to claim 1, wherein The ratio of the circumference of the upper surface of the first conductive pillar to the circumference of the lower surface of the first conductive pillar is between 1 and 25.

3. The semiconductor package device according to claim 1, wherein The first conductive pillar has a metal layer and a seed layer surrounding the metal layer.

4. The semiconductor package device according to claim 1, wherein The semiconductor packaging device further includes: A substrate is provided on which the adhesive layer and the chip assembly are arranged.

5. The semiconductor package device according to claim 4, wherein The redistribution layer also includes a second conductive column, which passes through the adhesive layer to electrically connect the redistribution layer and the internal electrical connector of the substrate arranged on the upper surface of the substrate, and the circumference and / or area of ​​the lower surface of the second conductive column is smaller than the circumference and / or area of ​​the upper surface of the internal electrical connector of the substrate.

6. The semiconductor package device according to claim 4 or 5, wherein: The semiconductor packaging device further includes a substrate external electrical connection member provided on the lower surface of the substrate.

7. The semiconductor package device according to claim 1, wherein The semiconductor package device further includes an external electrical connection member disposed on the upper surface of the redistribution layer.

8. A method for manufacturing a semiconductor package device, comprising: forming at least one temporary conductive post on the carrier; forming a protective layer and a seed layer on the top of each temporary conductive column; forming a first circuit layer on the carrier board with a thickness smaller than the height of each of the temporary conductive pillars, wherein the first circuit layer surrounds the bottom of each of the temporary conductive pillars; removing the protective layer on the top of each temporary conductive column; Disposing a reinforcement dielectric layer on the first circuit layer, each of the temporary conductive pillars is exposed from the reinforcement dielectric layer, and the first circuit layer and the reinforcement dielectric layer form a redistribution layer; Etching to remove an edge portion of a top portion of the temporary conductive pillar; placing the chip assembly on a substrate; Adhere the structure including the carrier, the temporary conductive pillars and the redistribution layer to the chip assembly and the substrate using a non-conductive adhesive; removing the carrier board; Etching away the seed layer on the surface of the structure and etching away the temporary conductive pillars to form corresponding temporary guide holes; dry etching each of the temporary guide holes so that each of the temporary guide holes contacts the chip electrical connector of the chip assembly or the intra-substrate electrical connector on the substrate; Coating photoresist on each of the temporary guide holes and the surface of the structure, performing photolithography and electroplating, and then removing the photoresist to form a first conductive column in each of the temporary guide holes and a circuit pattern on the surface of the structure; fabricating a circuit layer on the surface of the structure; mounting electronic components on the surface of the structure; A substrate external electrical connector is mounted on the lower surface of the substrate.

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