Semiconductor package with extended heat spreader

Abstract

A semiconductor package includes a die pad having a die attach surface, a first lead laterally separated from and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and including a first terminal on an upper surface of the semiconductor die, an interconnect clip electrically connected to the first terminal and the first lead, and a heat spreader mounted on a top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends beyond outer edge sides of the die pad. The heat spreader covers an area of the first planar section that is greater than an area of the semiconductor die. The heat spreader extends laterally beyond a first outer edge side of the die pad facing the first lead.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to semiconductor packaging, and more particularly to the cooling and interconnect features of semiconductor packaging. Background Technology

[0002] Semiconductor packages are designed to provide connectivity compatibility between semiconductor dies and external devices such as printed circuit boards (PCBs). Additionally, semiconductor packages are designed to protect semiconductor dies from potentially damaging environmental conditions, such as temperature variations, moisture, dust particles, etc. In many semiconductor packages, an important design consideration is the package's cooling capability. Many semiconductor dies generate significant amounts of heat during typical operation. An example of such devices is a power semiconductor device, which is rated to withstand considerably high voltages during normal operation, such as those exceeding 200 volts. Cooling features are typically provided within the semiconductor package to maintain the semiconductor die within a safe temperature range during operation.

[0003] A dual-sided cooling package represents a packaging design for enhanced heat dissipation. A dual-sided cooling package includes a thermally conductive element that draws heat away from the bottom of the die toward the bottom side of the package and a second thermally conductive element that draws heat away from the top of the die toward the top side of the package.

[0004] Metal clips are suitable as interconnect features in high-power applications due to their high current-carrying capacity and low thermal resistance. However, including metal interconnect clips in a double-sided cooled package introduces geometric constraints that limit the placement of the cooling features. Summary of the Invention

[0005] A semiconductor package is disclosed. According to an embodiment, the semiconductor package includes: a die pad including a die attachment surface; a first lead laterally separated from and vertically offset from the die pad; a semiconductor die mounted on the die attachment surface and including a first terminal on an upper surface of the semiconductor die opposite to the die pad; an interconnect clip electrically connected to the first terminal and the first lead; and a heat sink mounted on top of the interconnect clip. The interconnect clip includes a first planar segment interfaced with the upper surface of the semiconductor die and extending beyond the outer edge side of the die pad. The heat sink covers an area larger than the area of ​​the semiconductor die of the first planar segment. The heat sink extends laterally beyond the first outer edge side of the die pad facing the first lead.

[0006] Independently or in combination, the interconnect clip includes a second planar segment that forms a first transition bend with the first planar segment and extends perpendicularly toward the first lead, and the first transition bend is disposed in a lateral gap between the first edge side of the die pad and the inner end of the first lead.

[0007] Independently or in combination, the interconnect clip includes a third planar segment that forms a second transition bend with the second planar segment and is close to the connection surface of the first lead, and the first and third planar segments are substantially parallel to each other.

[0008] Independently or in combination, the semiconductor die includes a first outer edge facing a first lead, a second outer edge opposite to the first outer edge, and a third outer edge and a fourth outer edge extending between the first outer edge and the second outer edge, wherein a heat sink extends laterally beyond at least two of the first outer edge, the second outer edge, the third outer edge, and the fourth outer edge.

[0009] Independently or in combination, the semiconductor die also includes a second terminal on the upper surface of the semiconductor die, and the semiconductor package also includes a second lead and a conductive bonding wire, the second lead being separated from the die pad by a lateral gap between the inner end of the second lead and a first edge side of the die pad, the conductive bonding wire electrically connecting the second terminal to the second lead, the conductive bonding wire extending directly over an exposed area on the upper surface of the semiconductor die, the exposed area being the region on the upper surface of the semiconductor die including the second terminal, the conductive bonding wire extending to a fourth outer edge of the semiconductor die and exposed from the interconnect clip.

[0010] Independently or in combination, the heat sink includes a first edge surface and a second edge surface that intersect each other at an angle, a second terminal is laterally disposed between the first edge surface and a fourth outer edge of the semiconductor die, and the second edge surface extends laterally beyond the fourth outer edge of the semiconductor die.

[0011] Independently or in combination, the heat sink includes a thicker portion and a thinner portion, the lower surface of the thicker portion abutting the upper surface of the interconnect clip, and the lower surface of the thinner portion extending laterally outward from the thicker portion and spaced apart from the interconnect clip.

[0012] Independently or in combination, the thinner portion includes a first wing that extends laterally beyond the first transition bend.

[0013] Independently or in combination, the thinner portion includes a second wing that extends laterally beyond the second outer edge of the semiconductor die.

[0014] Independently or in combination, the thinner portion includes a third wing that extends laterally beyond the fourth outer edge of the semiconductor die, and wherein the third wing extends over the conductive bonding line.

[0015] Independently or in combination, the thinner portion includes a fourth wing that extends laterally beyond the third outer edge of the semiconductor die.

[0016] Independently or in combination, the radiator includes at least one chamfer between two edge faces that are substantially perpendicular to each other.

[0017] Independently or in combination, the upper surface of the heat sink, opposite to the upper surface of the interconnect clip, is corrugated.

[0018] Independently or in combination, the radiator includes at least one perforation extending through the opposing upper and lower surfaces of the radiator.

[0019] Independently or in combination, the interconnect clip includes a thicker portion and a thinner portion, wherein the lower surface of the thicker portion of the interconnect clip is close to the upper surface of the semiconductor die, and the thinner portion of the interconnect clip extends laterally outward from the thicker portion of the interconnect clip.

[0020] Whether standalone or in combination, the radiator is a generally flat structure that is directly mounted on the thicker and thinner sections.

[0021] The outer periphery of the radiator has a polygonal shape, either independently or in combination.

[0022] Independently or in combination, the outer periphery of the radiator includes an obtuse angle at the intersection between two edge faces, or a U-shaped notch formed by three edge faces. Attached Figure Description

[0023] The elements in the accompanying drawings are not necessarily proportional to each other. Similar reference numerals indicate corresponding similar parts. Features of various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail below.

[0024] include Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E Figure 1 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 1A and Figure 1B Each depicts an isometric view of the semiconductor package before encapsulation. Figure 1C A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 1D A plan view of a semiconductor package with interconnect clips and a heat sink is depicted before encapsulation. Figure 1E A cross-sectional view of a semiconductor package with interconnect clips and a heat sink after encapsulation is depicted.

[0025] include Figure 2A , Figure 2B and Figure 2C Figure 2 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 2A A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 2BA plan view of a semiconductor package with interconnect clips and a heat sink is depicted before encapsulation. Figure 2C A cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted.

[0026] include Figure 3A , Figure 3B and Figure 3C Figure 3 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 3A A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 3B A plan view of a semiconductor package with interconnect clips and a heat sink is depicted before encapsulation. Figure 3C A cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted.

[0027] include Figure 4A , Figure 4B and Figure 4C Figure 4 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 4A A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 4B A plan view of a semiconductor package with interconnect clips and a heat sink is depicted before encapsulation. Figure 4C A cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted.

[0028] include Figure 5A , Figure 5B and Figure 5C Figure 5 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 5A A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 5B This is a plan view depicting a semiconductor package with interconnect clips and a heat sink before encapsulation. Figure 5C A cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted.

[0029] include Figure 6A , Figure 6B , Figure 6C and Figure 6D Figure 6 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 6A A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 6B A plan view of a semiconductor package with interconnect clips and a heat sink is depicted before encapsulation. Figure 6C A cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted in a second lateral direction perpendicular to the current direction. Figure 6DA cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted in a first transverse direction parallel to the current direction.

[0030] include Figure 7A , Figure 7B and Figure 7C Figure 7 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 7A A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 7B A plan view of a semiconductor package with interconnect clips and a heat sink is depicted before encapsulation. Figure 7C A cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted.

[0031] include Figure 8A , Figure 8B and Figure 8C Figure 8 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 8A A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 8B A plan view of a semiconductor package with interconnect clips and a heat sink is depicted before encapsulation. Figure 8C A cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted.

[0032] include Figure 9A , Figure 9B and Figure 9C Figure 9 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 9A A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 9B A plan view of a semiconductor package with interconnect clips and a heat sink is depicted before encapsulation. Figure 9C A cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted.

[0033] include Figure 10A , Figure 10B and Figure 10C Figure 10 illustrates a semiconductor package with an extended interconnect clip and heat sink design according to an embodiment. Figure 10A A plan view of a semiconductor package with interconnect clips and no heat sink is depicted before encapsulation. Figure 10B A plan view of a semiconductor package with interconnect clips and a heat sink is depicted before encapsulation. Figure 10C A cross-sectional view of a semiconductor package with interconnect clips and a heat sink is depicted. Detailed Implementation

[0034] This document describes an embodiment of a double-sided cooled package with an advantageous interconnect clip and heat sink configuration. The interconnect clip is designed to provide a maximum surface area to accommodate a large heat sink mounted thereon, while providing electrical connection between the semiconductor die and a lead perpendicularly offset from the semiconductor die. The interconnect clip includes a large planar section that mates with the semiconductor die and extends laterally beyond the die pads of the package. This large planar section can accommodate a heat sink that also extends laterally beyond the die pads. In an embodiment, this arrangement is made possible by positioning a transition bend of the interconnect clip in the lateral gap between the die pads and the first lead. The heat sink is designed to extend beyond the semiconductor die and / or die pads in multiple different directions. In an embodiment, this is made possible by a heat sink geometry that is more complex than the simple cubic shape typical in conventional heat sink designs. For example, the heat sink may include one or more of L-shaped geometry, U-shaped geometry, notches, etc. In another example, the heat sink has a multi-thickness configuration such that the upper region of the heat sink can extend beyond the die and die pads. In either case, the heat sink provides a large cooling surface area while accommodating the bonding wire connections to the semiconductor die. When combined in a single package, the interconnect clips and heat sink allow for a much larger cooling area (e.g., at least twice the size of the semiconductor die), which beneficially improves heat dissipation capabilities.

[0035] Referring to Figures 1-2, the semiconductor package 100 includes a die pad 102, multiple conductive leads 104, a semiconductor die 106, a conductive interconnect clip 108, and a heat sink 110. Figure 1A , Figure 1B , Figure 1C , Figure 1D The encapsulated components are shown. Figure 1E A completed semiconductor package 100 is shown, comprising an electrically insulating encapsulant body 112. The encapsulant body 112 comprises an electrically insulating encapsulant material, such as ceramic, epoxy resin, thermosetting plastic, etc. The encapsulant material is formed such that the semiconductor die 106 is encapsulated, and the outer ends of the leads 104, the lower surface of the die pads 102, and the upper surface 138 of the heat sink 110 are exposed from the encapsulant material. In this way, the semiconductor package 100 can mate with a printed circuit board, wherein the leads 104 provide I / O connections, and the die pads 102 and the heat sink 110 provide dual-sided cooling for the mounted semiconductor package 100.

[0036] The die pad 102 and lead 104 comprise conductive materials, such as metals and alloys thereof, such as copper, aluminum, nickel, etc. The die pad 102 and lead 104 may be provided by a common lead frame structure constructed of a planar metal sheet. The die pad 102 includes a die attachment surface 114, which is a substantially flat and conductive surface configured to mount a semiconductor die 106 thereon. The lead includes a first lead 116 separated from the die pad 102 by a lateral gap between the first edge side 118 of the die pad 102 and the inner end of the first lead 116. The first lead 116 is physically detached from and laterally separated from the die pad 102. A connection surface 120 of the first lead 116 extends to the inner end of the first lead 116. The connection surface 120 of the first lead 116 is configured to accommodate interconnect structures, such as bonding wires, clips, etc. The connecting surface 120 is perpendicularly spaced from the die attachment surface 114. This perpendicular spacing is in a direction perpendicular to the die attachment surface 114. In the depicted embodiment, the first lead 116 includes a plurality of discrete lead portions fused together by a common pad. More generally, the first lead 116 may include any number of leads, including a single lead. The lead 104 additionally includes a second lead 122, which is similarly separated from the die pad 102 by a lateral gap between the first edge side 118 of the die pad 102 and the inner end of the second lead 122.

[0037] Semiconductor die 106 is mounted on die attachment surface 114 of die pad 102. Generally, semiconductor die 106 can have various device configurations, such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), JFET (Junction Field-Effect Transistor), diode, etc. Furthermore, semiconductor die 106 can include any of a variety of semiconductor materials, including Type IV semiconductors (e.g., silicon, silicon germanium, silicon carbide, etc.) and Type III-V semiconductors (e.g., gallium nitride, gallium arsenide, etc.). Additionally, semiconductor die 106 can be configured as a vertical device or a lateral device; a vertical device is configured to control current flowing between opposing upper and lower surfaces, while a lateral device is configured to control current flowing parallel to the main surface.

[0038] According to an embodiment, the semiconductor die 106 is configured as a discrete MOSFET device. More specifically, the semiconductor die 106 may be configured as a silicon carbide-based power MOSFET device, which is rated to control a voltage of at least 1200V.

[0039] Semiconductor die 106 is mounted with its lower surface facing die pad 102 and its upper surface facing away from die pad 102. Semiconductor die 106 includes a first terminal 124 and a second terminal 126 on the upper surface of semiconductor die 102. The first terminal 124 may be a load terminal to which a main voltage is applied, such as a source terminal, drain terminal, collector terminal, etc. The second terminal 126 may be a control terminal configured to control the conductive state of the device, such as a gate terminal, base terminal, etc. Semiconductor die 106 may additionally include a third terminal (not shown) on its rear surface. The third terminal may be another load terminal to which a main voltage is applied, such as a source terminal, drain terminal, collector terminal, etc. In one embodiment, semiconductor die 106 is a power MOSFET, the first terminal 124 is a gate terminal, the second terminal 126 is a source terminal, and the third terminal is a drain terminal. Each of these terminals may be implemented using conductive bonding pads disposed on the surface of semiconductor die 106. The third terminal can be electrically connected to the die pad 102 via a conductive adhesive (e.g., solder, sintering agent, conductive glue, etc.).

[0040] Interconnect clip 108 comprises a conductive material, such as metals and alloys thereof, such as copper, aluminum, nickel, etc. Interconnect clip 108 may be provided as a planar metal sheet and formed into any of the geometric features described herein by metalworking techniques such as punching, stamping, bending, etc.

[0041] Interconnector 108 includes a first planar segment 128, a second planar segment 130, and a third planar segment 132. The first planar segment 128, the second planar segment 130, and the third planar segment 132 may be part of a continuous and substantially uniform thickness structure, wherein each of the first planar segment 128, the second planar segment 130, and the third planar segment 132 has substantially the same thickness between its opposing upper and lower surfaces. The first planar segment 128 is parallel to and perpendicularly offset from the third planar segment 132. This perpendicular offset corresponds to the offset distance between the die attachment surface 114 and the connection surface 120 of the first lead 116. The second planar segment 130 extends perpendicularly from the first planar segment 128 toward the first lead 116.

[0042] A first transition bend 134 is disposed between a first planar segment 128 and a second planar segment 130. A second transition bend 136 is disposed between the second planar segment 130 and a third planar segment 132. These transition bends are the locations where the planes of the interconnecting clip 108 change orientation. In the depicted embodiment, the first transition bend 134 and the second transition bend 136 intersect at an acute angle between the two planes. More generally, the first transition bend 134 and the second transition bend 136 may have curved or more gradual geometry. Furthermore, the inclination angle between the second planar segment 130 and the first planar segment 128 and / or the third planar segment 132 can vary from a gentle inclination of, for example, 30 degrees to a steep inclination of, for example, 90 degrees.

[0043] Interconnect clip 108 electrically connects the first terminal 124 to the first lead 116. To achieve this connection, interconnect clip 108 is mounted in the assembly, wherein the first planar segment 128 abuts against the upper surface of the semiconductor die 106, and the third planar segment 132 abuts against the connection surface 120 of the first lead 116. Electrical contact can be achieved through direct contact or by providing a conductive medium, such as solder, sinter, adhesive, etc., between interconnect clip 108 and the first terminal 124 and / or the first lead 116.

[0044] Heat sink 110 is a discrete sheet of thermally conductive material. For example, heat sink 110 may include metals such as copper, aluminum, or alloys thereof. According to an embodiment, heat sink 110 is a continuous volume of thermally conductive material, meaning that heat sink 110 does not contain openings or cavities. Heat sink 110 is mounted on the upper surface of interconnect clip 108. This can be achieved by providing a thermally conductive adhesive (e.g., solder, sintering agent, conductive adhesive, etc.) between interconnect clip 108 and heat sink 110. During operation of semiconductor die 106, heat sink 110 draws heat away from semiconductor die 106 via interconnect clip 108. According to an embodiment, heat sink 110 includes a substantially planar upper surface 138. In the completed semiconductor package 100, this upper surface 138 of heat sink 110 may be exposed from encapsulant 112, thereby providing an interface for connection to the heat sink.

[0045] According to an embodiment, the first transition bend 134 of the interconnect clip 108 is disposed in the lateral gap between the first edge side 118 of the die pad 102 and the inner end of the first lead 116. Therefore, the first transition bend 134 is laterally outside the periphery of the die pad 102. This configuration differs from conventional vertical offset clip designs, in which an angle transition occurs directly on the chip. In embodiments utilizing this concept, the lateral distance between the first transition bend 134 and the first edge side 118 of the die pad 102 is at least 50% of the total lateral distance of the lateral gap, and in various embodiments, it can be greater than 60%, greater than 70%, greater than 80%, greater than 90%, etc.

[0046] like Figure 1C As shown, the semiconductor die 106 includes a first outer edge 140 facing the first lead 116, a second outer edge 142 opposite to the first outer edge 140, and a third outer edge 144 and a fourth outer edge 146, each extending between the first outer edge 140 and the second outer edge 142. These outer edges 140, 142, 144, and 146 form the outer periphery of the semiconductor die 106. A portion of the upper surface of the semiconductor die 106 is covered by an interconnect clip 108. Another portion of the upper surface of the semiconductor die 106 is exposed from the interconnect clip 108. This exposed portion of the upper surface extends to the second outer edge 142 of the semiconductor die 106 and includes a second terminal 126. A conductive bonding wire 186 electrically connecting the second terminal 126 to the second lead 122 extends directly over the exposed portion of the upper surface.

[0047] like Figure 1D As shown, the heat sink 110 includes a plurality of edge surfaces forming the outer periphery of the heat sink 110. The heat sink 110 is arranged in a configuration that partially overlaps with the semiconductor die 106 and the interconnect clip 108. That is, the heat sink 110 covers a portion of the interconnect clip 108.

[0048] The heat sink 110 extends laterally beyond the first outer edge 140 side of the semiconductor die 106. That is, the heat sink 110 extends beyond the semiconductor die 106 in a first lateral direction 148 parallel to the current flow direction between the first terminal 124 and the first lead 116.

[0049] According to an embodiment, the heat sink 110 has a larger area than the semiconductor die 106. Specifically, the area of ​​the heat sink 110 can be twice the size of the semiconductor die 106. This means that the outer periphery of the heat sink 110, formed by the edge surfaces of the heat sink 110, occupies a larger two-dimensional space than the outer periphery of the semiconductor die 106, formed by the outer edges of the semiconductor die 106. If the heat sink 110 has a multi-thickness configuration (e.g., as disclosed in the following embodiments), then the outer periphery of the heat sink 110 refers to the outer periphery of the thickness region with the largest area.

[0050] The large area of ​​heat sink 110 can be attributed to the geometry of interconnect clip 108, heat sink 110, or both. Specifically, heat sink 110 can extend in a first lateral direction 148 by positioning a first transition bend 134 of interconnect clip 108 in the lateral gap between the first edge side 118 of die pad 102 and the first lead 116. Simultaneously, the geometry of heat sink 110 is tailored to allow it to extend beyond the third outer edge 144 and / or fourth outer edge 146 of semiconductor die 106 in a second lateral direction 150 perpendicular to the first lateral direction 148, while accommodating the bonding wire. Various examples of these geometries are illustrated in the embodiments discussed below.

[0051] According to an embodiment, the outer periphery of the heat sink 110 has a polygonal shape. As used herein, a polygonal shape describes a closed geometry consisting of at least five linear spans, with angular intersections between each span. In other words, a polygon is more complex than a rectangle. Examples of polygonal geometries include U-shaped geometries, C-shaped geometries, rectangular geometries with a notch on one side in other cases, and geometries including obtuse angles. This configuration allows the heat sink 110 to extend in different directions while accommodating bonding wires. The polygonal heat sink 110 of Figure 1 includes sides with three linear spans, one of which is angled relative to the other two. This allows the heat sink 110 to extend laterally beyond the second outer edge 142 of the semiconductor die 106.

[0052] According to an embodiment, the heat sink 110 extends laterally beyond at least two of the first outer edge 140, the second outer edge 142, the third outer edge 144, and the fourth outer edge 146. In this way, the effective cooling surface of the heat sink 110 can be advantageously increased. Various configurations of the heat sink 110 and / or the interconnect clip 108 for achieving this extended surface area will be further described below.

[0053] Referring to FIG2, an embodiment of a semiconductor package 100 with a polygonal heat sink 110 according to an embodiment is depicted. In the embodiment of FIG2, the heat sink 110 includes a first edge surface 152 and a second edge surface 154 that intersect each other at an angle. For example, the first edge surface 152 and the second edge surface 154 may intersect each other at an angle between approximately 120 degrees and 150 degrees. A second terminal 126 is laterally disposed between the first edge surface 152 and a fourth outer edge 146 of the semiconductor die 106. The second edge surface 154 extends laterally beyond the fourth outer edge 146 of the semiconductor die 106. In the depicted embodiment, the second edge surface 154 extends directly over the fourth outer edge 146 of the semiconductor die 106. Alternatively, the second edge surface 154 may intersect the planar fourth outer edge 146 outside the die coverage area. In the depicted embodiment, the heat sink 110 also extends beyond the second outer edge 142 of the semiconductor die 106. Therefore, a larger surface area of ​​the heat sink 110 is provided.

[0054] Referring to FIG3, an embodiment of a semiconductor package 100 with a polygonal heat sink 110 according to an embodiment is depicted. In this embodiment, the heat sink 110 includes a first edge face 152, a second edge face 154, and a third edge face 156. A second terminal 126 is laterally disposed between the first edge face 152 and a fourth outer edge 146 of the semiconductor die 106. The second edge face 154 and the third edge face 156 each form a substantially perpendicular angle with the first edge face 152. As a result, the heat sink 110 includes a U-shaped notch formed by the three edge faces, the U-shaped notch accommodating the connection of the bonding wire 186. The U-shaped notch provides an exposed area for the bonding wire 186 to enter and contact the second terminal 126. In this embodiment, the heat sink 110 extends laterally beyond all four outer edges 140, 142, 144, and 146 of the semiconductor die 106. Therefore, a large surface area of ​​the heat sink 110 is provided.

[0055] Referring to FIG4, an embodiment of a semiconductor package 100 with a polygonal shape and a multi-thickness configuration of a heat sink 110 according to an embodiment is depicted. The heat sink 110 includes a thicker portion 158 and a thinner portion 160. The thickness of each portion is the shortest distance between the upper and lower surfaces of the interconnect clip 108. The multi-thickness configuration allows the heat sink 110 to extend laterally beyond the semiconductor die 106 in both a first lateral direction 148 and a second lateral direction 150. The lower surface of the thicker portion 158 is adjacent to the upper surface of the interconnect clip 108. Therefore, the thicker portion 158 forms a thermal interface with the interconnect clip 108. Meanwhile, the lower surface of the thinner portion 160 extends laterally outward from the thicker portion 158 and is spaced apart from the interconnect clip 108 in the region immediately adjacent to the thicker portion 158. This lateral extension of the interconnect clip 108 provides a larger surface area for mounting heat sinks on top of the heat sink 110.

[0056] In the embodiment of FIG4, the thinner portion 160 of the heat sink 110 includes a first wing 162 that extends laterally beyond the thicker portion 158 in a first lateral direction 148. The first wing 162 may extend laterally beyond a first transition bend 134. As shown, the first wing 162 extends beyond both the first transition bend 134 and the second transition bend 136, and directly contacts the upper surface of the interconnect clip 108 in the third planar segment 132. Therefore, the multi-thickness configuration enables the realization of a large area for cooling and thermal coupling to the heat sink structure.

[0057] Referring to FIG5, an embodiment of a semiconductor package 100 with a heat sink 110 having a polygonal shape and a multi-thickness configuration is depicted according to an embodiment. In this embodiment, the thinner portion 160 includes a second wing 164 extending laterally beyond the second outer edge 142 of the semiconductor die 106. Therefore, the effective surface contact area for cooling is further extended in the first lateral direction 148. The second wing 164 may have a similar or identical thickness and length to the first wing 162. Optionally, the second wing 162 may extend beyond the second edge side of the die pad 102 opposite the first edge side 118.

[0058] Referring to FIG6, an embodiment of a semiconductor package 100 with a heat sink 110 having a polygonal shape and a multi-thickness construction according to an embodiment is depicted. In this embodiment, the multi-thickness concept is used to extend the upper area of ​​the heat sink 110 in multiple different lateral directions. Specifically, the thinner portion 160 of the heat sink 110 includes a third wing 166 and a fourth wing 168, which extend laterally beyond the semiconductor die 106 in a second lateral direction 150. Figure 6C As shown, the third wing 166 extends laterally beyond the fourth outer edge 146 of the semiconductor die 106, and the fourth wing 164 extends laterally beyond the third outer edge 144 of the semiconductor die 106. Furthermore, due to the vertical spacing between the third wing 166 and the die attachment surface 114, the bonding wire 186 can enter the region below the third wing 166 and connect to the second terminal 126 of the semiconductor die 106. Therefore, compared to previous embodiments, features such as tilt angles or notches are not required in the edge surface of the heat sink 110 to accommodate the bonding wire. Figure 6D As shown, the third wing 166 and the fourth wing 168 can also extend in the first lateral direction 148 beyond the first outer edge 140 and beyond the first transition bend 134 and the second transition bend 136, thus providing the benefits of the first wing 162 as described above.

[0059] Referring to FIG7, an embodiment of a semiconductor package 100 with a polygonal heat sink 110 according to an embodiment is depicted. In this embodiment, the heat sink 110 includes at least one chamfer 170 between two edge faces. A chamfer is a structural feature that intersects with two edge faces to reduce the transition angle between the two edge faces. In this example, the heat sink 110 includes a first edge face 172, a second edge face 174, a third edge face 176, and a fourth edge face 178, wherein the first edge face 172 and the third edge face 176 are substantially perpendicular to each other, the second edge face 174 and the third edge face 176 are substantially perpendicular to each other, and so on. The chamfer 170 is formed by a planar edge face oriented at approximately 45 degrees relative to the two perpendicular edge faces. More generally, the angle of the chamfer 170 may vary and / or the chamfer 170 may include a rounded transition. One benefit of the chamfer 170 is the reduction of thermal stress due to the difference in the coefficients of thermal expansion of the encapsulant materials, which cause expansion or contraction, for example, from the manufacturing process or at high temperatures during operation.

[0060] Referring to FIG8, an embodiment of a semiconductor package 100 with a polygonal heat sink 110 according to an embodiment is depicted. In this embodiment, the heat sink 110 has the same two-dimensional geometry as the heat sink 110 described with reference to FIG3. Additionally, the upper surface 138 of the heat sink 110, opposite the upper surface of the interconnect clip 108, is corrugated. This means that the upper surface of the heat sink 110 includes alternating peaks and valleys. As shown, the peaks and valleys are regularly spaced and are generally rectangular in shape. More generally, the corrugated pattern may include irregular and / or non-rectangular features. One benefit of corrugation is enhanced adhesion to encapsulating materials (e.g., molding compounds). Another benefit of corrugation compared to a flat upper surface construction is increased surface area. For example, the increased surface area provides enhanced heat dissipation if an external heat sink is not used in conjunction with the device. In other words, corrugation integrates a heat sink structure into the package itself.

[0061] Referring to FIG9, an embodiment of a semiconductor package 100 with a polygonal heat sink 110 according to an embodiment is depicted. In this embodiment, the heat sink 110 has the same two-dimensional external geometry as the heat sink 110 described with reference to FIG3. Additionally, the heat sink 110 includes a plurality of through-holes 180 extending through the opposing upper and lower surfaces of the heat sink 110. As shown, the through-holes 180 are disposed in a region of the heat sink 110 extending beyond the second outer edge 142 of the semiconductor die 106. More generally, the through-holes 180 can be disposed in any region outside the periphery of the semiconductor die 106. Furthermore, the size, number, and shape of the through-holes 180 can vary. One benefit of the through-holes 180 is the enhanced adhesion to the encapsulant material 112 due to the increased surface area in contact with the encapsulant material. The enhanced adhesion provides mechanical stability to the heat sink 110, making it less prone to deviating from its intended mounting position.

[0062] Referring to FIG10, an embodiment of a semiconductor package 100 with a polygonal heat sink 110 according to an embodiment is depicted. In the embodiment of FIG10, both the interconnect clip 108 and the heat sink 110 have a different configuration than those in the previous embodiment. Specifically, the interconnect clip 108 has a multi-thickness configuration, including a thicker portion 182 and a thinner portion 184. Furthermore, the heat sink 110 has a substantially flat configuration, which is directly disposed on the thicker portion 182 and the thinner portion 184.

[0063] The thicker portion 182 of the interconnect clip 108 may have approximately the same area coverage as the semiconductor die 106 (e.g., within + / - 10%) and includes a lower surface adjacent to the upper surface of the semiconductor die 106. The thinner portion 184 of the interconnect clip 108 extends laterally outward from the thicker portion 182 and thus has a larger area than the semiconductor die 106. In the depicted example, the thinner portion 184 of the interconnect clip 108 extends laterally over the first outer edge 140, the second outer edge 142, and the third outer edge 144 of the semiconductor die 106. Furthermore, the lower wing of the thinner portion 184 extends beyond the second outer edge 142 of the semiconductor die 106 beyond the die coverage area. By raising the laterally extended plane to a plane substantially coplanar with the first lead 116, the multi-thickness interconnect clip 108 configuration demonstrates an alternative to extending the area of ​​the heat sink 110 in both the first lateral direction 148 and the second lateral direction 150. The thicker portion 182 of the interconnect clip 108 provides a mechanism for removing heat from the semiconductor die 106, while the substantially flat heat sink 110 can have a large surface area to transfer the heat to an external heat sink assembly.

[0064] The concepts described herein apply to a variety of package constructions. Generally, these package constructions include any package design in which heat dissipation is desired at the upper surface of the semiconductor die and / or in which the semiconductor die includes at least one upward-facing bonding pad that requires electrical connection. Examples of these package constructions include leaded packages, leadless packages, chip carrier packages, surface mount packages, stacked die packages, molded packages, cavity packages, etc.

[0065] As used herein, the term "substantially" encompasses both absolute conformity to the specified requirements and minor deviations from those requirements due to variations in manufacturing processes, assembly, and other factors that may cause deviations from the design objectives. The term "substantially" covers any deviations that are within process tolerances to achieve practical conformity and that the parts described herein are capable of operating as required by the application.

[0066] As used herein, the terms “electrical connection”, “direct electrical connection”, etc., describe a permanent low-impedance connection between electrical connection elements, such as direct contact between related elements or a low-impedance connection via a metal and / or highly doped semiconductor.

[0067] For ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device other than those depicted in the accompanying drawings. Furthermore, terms such as "first" and "second" are used to describe various elements, regions, sections, etc., and these terms are not intended to be limiting. Throughout the specification, similar terms indicate similar elements.

[0068] As used herein, the terms “having,” “comprising,” “including,” etc., are open-ended terms that indicate the presence of the said element or feature but do not exclude additional elements or features. The articles “a” and “said” are intended to include both plural and singular unless the context clearly indicates otherwise.

[0069] In light of the aforementioned changes and scope of application, it should be understood that this invention is not limited to the foregoing description or the accompanying drawings. Rather, it is limited only to the following claims and their legal equivalents.

Claims

1. A semiconductor package, comprising: Including die pads on the die attachment surface; A first lead that is laterally separated from and vertically offset from the die pad; A semiconductor die, which is mounted on the die attachment surface and includes a first terminal on the upper surface of the semiconductor die opposite to the die pads; An interconnecting clip electrically connected to the first terminal and the first lead; as well as A heat sink mounted on top of the interconnect clip. The interconnect clip includes a first planar segment that is connected to the upper surface interface of the semiconductor die and extends beyond the outer edge of the die pad. Wherein, the heat sink covers an area of ​​the first planar segment that is larger than the area of ​​the semiconductor die. The heat sink extends laterally beyond the first outer edge of the die pad facing the first lead. Wherein, the top surfaces of all parts of the heat sink lie in the same plane, and the outer periphery of the heat sink has a polygonal shape in the same plane, and The heat sink includes at least one chamfer between its two edge surfaces.

2. The semiconductor package according to claim 1, wherein, The interconnect clip includes a second planar segment that forms a first transition bend with the first planar segment and extends perpendicularly toward the first lead, wherein the first transition bend is disposed in a lateral gap between the first outer edge side of the die pad and the inner end of the first lead.

3. The semiconductor package according to claim 2, wherein, The interconnect clip includes a third planar segment that forms a second transition bend with the second planar segment and is close to the connection surface of the first lead, wherein the first planar segment and the third planar segment are substantially parallel to each other.

4. The semiconductor package according to claim 2, wherein, The semiconductor die includes a first outer edge facing the first lead, a second outer edge opposite to the first outer edge, and a third outer edge and a fourth outer edge extending between the first outer edge and the second outer edge, wherein the heat sink extends laterally beyond at least two of the first outer edge, the second outer edge, the third outer edge, and the fourth outer edge.

5. The semiconductor package according to claim 4, wherein, The semiconductor die further includes a second terminal on the upper surface of the semiconductor die, wherein the semiconductor package further includes a second lead and a conductive bonding wire, the second lead being separated from the die pad by a lateral gap between the first outer edge side of the die pad and the inner end of the second lead, the conductive bonding wire electrically connecting the second terminal to the second lead, wherein the conductive bonding wire extends directly over an exposed area on the upper surface of the semiconductor die, the exposed area being the region on the upper surface of the semiconductor die including the second terminal, the conductive bonding wire extending to the fourth outer edge of the semiconductor die and exposed from the interconnect clip.

6. The semiconductor package according to claim 5, wherein, The heat sink includes a first edge surface and a second edge surface that intersect each other at an angle, wherein the second terminal is laterally disposed between the first edge surface and the fourth outer edge of the semiconductor die, and wherein the second edge surface extends laterally beyond the fourth outer edge of the semiconductor die.

7. The semiconductor package according to claim 5, wherein, The heat sink includes a thicker portion and a thinner portion, wherein the lower surface of the thicker portion is close to the upper surface of the interconnect clip, and wherein the lower surface of the thinner portion extends laterally outward from the thicker portion and is spaced apart from the interconnect clip.

8. The semiconductor package according to claim 7, wherein, The thinner portion includes a first wing that extends laterally beyond the first transition bend.

9. The semiconductor package according to claim 8, wherein, The thinner portion includes a second wing that extends laterally beyond the second outer edge of the semiconductor die.

10. The semiconductor package according to claim 7, wherein, The thinner portion includes a third wing that extends laterally beyond the fourth outer edge of the semiconductor die, and wherein the third wing extends over the conductive bonding line.

11. The semiconductor package of claim 10, wherein, The thinner portion includes a fourth wing that extends laterally beyond the third outer edge of the semiconductor die.

12. The semiconductor package according to claim 2, wherein, The radiator includes at least one perforation that extends through the upper and lower surfaces of the radiator facing opposite directions.

13. The semiconductor package according to claim 1, wherein, The interconnect clip includes a thicker portion and a thinner portion, wherein the lower surface of the thicker portion of the interconnect clip is close to the upper surface of the semiconductor die, and wherein the thinner portion of the interconnect clip extends laterally outward from the thicker portion of the interconnect clip.

14. The semiconductor package of claim 13, wherein, The heat sink has a generally flat structure that is directly disposed on the thicker portion and the thinner portion.

15. The semiconductor package according to claim 1, wherein, The outer periphery of the radiator includes: The obtuse angle at the intersection between the two edge faces; or A U-shaped notch formed by three edge surfaces.

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