Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. A barrier layer surrounding a via hole is provided in an adhesive layer to block light reflected onto the adhesive layer, thereby minimizing the occurrence of hole expansion at the bottom of the via hole, improving the quality of the via hole, and thereby improving the stability of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] In an existing semiconductor structure, a redistribution layer and a substrate are bonded together by an adhesive layer, and an electrical path between the redistribution layer and the substrate is connected by a via hole.

[0003] When making via holes, laser drilling or etching can be used. In practical applications, laser drilling is generally used when using via holes with a diameter of 50 microns or more. However, when the laser penetrates the redistribution layer and the adhesive layer, it is difficult to control the laser energy. Different laser energies will result in holes of different shapes. If the laser energy is too low, it is easy to cause the bottom of the via hole to not be opened, such as Figure 1B As shown ( Figure 1B Schematic diagram of the phenomenon that the bottom of the via hole is not opened in the prior art). If the laser energy is too large, it is easy to cause the bottom of the via hole to expand, such as Figure 1A As shown ( Figure 1A (This figure is a schematic diagram of the bottom expansion phenomenon of a via hole in the prior art.) The quality of via hole production will affect the electrical connection performance between the redistribution layer and the substrate, affecting the stability of the semiconductor structure. Summary of the Invention

[0004] The present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0005] In a first aspect, the present disclosure provides a semiconductor structure comprising: a substrate; an adhesive layer disposed on the substrate; a redistribution layer disposed on the adhesive layer; a via hole penetrating the adhesive layer and the redistribution layer, the redistribution layer being electrically connected to the substrate through the via hole; and a barrier layer embedded in the adhesive layer and surrounding the via hole.

[0006] In some optional embodiments, the via hole is an inverted truncated cone structure.

[0007] In some optional embodiments, the via hole includes an upper opening, the upper opening passes through the upper surface of the redistribution layer, and the length ratio of the aperture of the upper opening to the height of the via hole is less than or equal to 1.2.

[0008] In some optional embodiments, the barrier layer is a dam structure.

[0009] In some optional embodiments, the barrier layer is a ring-shaped structure.

[0010] In some optional embodiments, the number of the annular structures is at least two, and the interval between two adjacent annular structures is 10 microns.

[0011] In some optional embodiments, the via hole has a side wall angle that is less than or equal to 100.2 degrees.

[0012] In second aspect, the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate; setting a barrier layer on the substrate; setting an adhesive layer on the substrate so that the barrier layer is embedded in the adhesive layer; setting a redistribution layer on the adhesive layer; forming a via hole penetrating the adhesive layer and the redistribution layer, the redistribution layer and the substrate are electrically connected through the via hole, the via hole including an upper opening and a lower opening, and the barrier layer is used to define the aperture of the lower opening.

[0013] In some optional embodiments, the via hole is an inverted truncated cone structure.

[0014] In some optional embodiments, the upper opening passes through the upper surface of the redistribution layer, and the length ratio of the aperture of the upper opening to the height of the via hole is less than or equal to 1.2.

[0015] In some optional embodiments, the barrier layer is a dam structure.

[0016] In some optional embodiments, the barrier layer is a ring-shaped structure.

[0017] In some optional embodiments, the number of the annular structures is at least two, and the interval between two adjacent annular structures is 10 microns.

[0018] In some optional embodiments, the via hole has a side wall angle that is less than or equal to 100.2 degrees.

[0019] In order to solve the technical problem that when the laser penetrates the redistribution layer and the bonding layer, the bottom of the via hole is not opened or the bottom of the via hole is expanded due to the difficulty in controlling the laser energy, which affects the electrical connection performance between the redistribution layer and the substrate, and further affects the stability of the semiconductor structure, in the semiconductor structure in the prior art, the circuit structure in the redistribution layer can block the oblique light in the laser energy, but in practice, some of the oblique light is still incident on the circuit structure in the redistribution layer, and then reflected on the bonding layer, causing the bottom of the via hole to expand.

[0020] The semiconductor structure and manufacturing method provided by the present disclosure provide a blocking layer surrounding the via in the bonding layer to block light reflected onto the bonding layer, thereby minimizing the occurrence of hole expansion at the bottom of the via, improving the quality of the via, and thereby improving the stability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Other features, objects and advantages of the present disclosure will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

[0022] Figure 1A Schematic diagram of the bottom expansion phenomenon of a via hole in the prior art;

[0023] Figure 1B It is a schematic diagram of the phenomenon that the bottom of the via hole is not opened in the prior art;

[0024] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure according to the present disclosure;

[0025] Figure 3 is a schematic structural diagram of an embodiment of a via hole according to the present disclosure;

[0026] Figure 4 Schematic diagram illustrating a design in which a barrier layer is provided in an adhesive layer according to the present disclosure.

[0027] Explanation of symbols:

[0028] 1-substrate, 2-adhesive layer, 3-rewiring layer, 4-conductive hole, 5-barrier layer (dam structure), 6-barrier layer (ring structure), D-aperture of upper opening, D1-position of inclined light, d-aperture of lower opening, d1-position of expanded hole, H-height, H1-height of redistribution layer, H2-height of adhesive layer, α-side wall angle. DETAILED DESCRIPTION

[0029] The following describes specific embodiments of the present disclosure in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present disclosure and the technical effects produced by the present disclosure through the contents of this specification. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0030] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present disclosure. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in the present disclosure without affecting the efficacy and purpose that can be achieved by the present disclosure. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present disclosure. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present disclosure without substantially changing the technical content.

[0031] In addition, the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0032] Figure 2 FIG1 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. As shown in FIG1 , the semiconductor structure may include: a substrate 1, an adhesive layer 2, and a redistribution layer 3. The adhesive layer 2 is disposed on the substrate 1, the redistribution layer 3 is disposed on the adhesive layer 2, a via 4 passes through the adhesive layer 2 and the redistribution layer 3, and the redistribution layer 3 is electrically connected to the substrate 1 through the via 4. A barrier layer is embedded in the adhesive layer 2 and surrounds the via 4.

[0033] Substrate 1 can be a coreless substrate or a cored substrate. It can be made of either a rigid or flexible substrate material. Rigid substrate materials, for example, can be copper-clad laminates, while flexible substrate materials, for example, can be polyimide (PI). Substrate 1 can be a BGA (Ball Grid Array) substrate and can be provided with a plurality of metal bumps and solder balls.

[0034] The adhesive layer 2 may be made of, for example, epoxy resin conductive adhesive, phenolic resin conductive adhesive, polyurethane conductive adhesive, thermoplastic resin conductive adhesive, and polyimide conductive adhesive.

[0035] Various wires, through-holes, buried vias or blind vias can be provided in the redistribution layer 3 to achieve circuit connection. It should be noted that the size or direction of the through-holes, buried vias or blind vias is not specifically limited here. If through-holes, buried vias or blind vias are provided, the through-holes, buried vias or blind vias can be filled with conductive materials such as metals or metal alloys, or contain conductive materials such as metals or metal alloys. Here, the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu) or their alloys.

[0036] The via 4 can electrically connect the substrate 1 and the redistribution layer 3 .

[0037] The barrier layer can be used to block light and is embedded in the adhesive layer 2 and surrounds the via 4. In practice, the barrier layer can define the aperture d of the lower opening of the via 4 to avoid hole shape defects of the via 4 and prevent the bottom expansion of the via 4.

[0038] The barrier layer can be made of a metal material, such as gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof, or combinations thereof. The barrier layer can be made of a material with good light absorption properties. The barrier layer can also have an uneven or relatively rough surface to absorb light. The barrier layer can also be treated to have a black oxide to absorb or attenuate light.

[0039] The blocking layer may be a blocking wall structure or a barrier structure surrounding the via hole 4 , which may better block incident light.

[0040] Please refer to Figure 3 , Figure 3 4 is a schematic structural diagram of an embodiment of the via hole 4 according to the present disclosure.

[0041] In some optional embodiments, such as Figure 3 As shown, the conducting hole 4 may be an inverted truncated cone structure.

[0042] In some optional embodiments, such as Figure 3 As shown, the via 4 may include an upper opening that passes through the upper surface of the redistribution layer 3 , and a length ratio of an aperture D of the upper opening to a height H of the via 4 is less than or equal to 1.2.

[0043] The semiconductor structure disclosed herein provides a barrier layer in the adhesive layer 2 to prevent hole expansion, and is applicable to scenarios where the length ratio of the aperture D of the upper opening of the via 4 to the height H of the via 4 is less than or equal to 1.2.

[0044] In some optional embodiments, the barrier layer may be a dam structure, such as Figure 2 The barrier layer (dam structure) 5 shown in FIG.

[0045] The blocking layer (dam structure) 5 has a simple structure. The blocking layer (dam structure) 5 can have a dam height, which can be the same as the height H2 of the adhesive layer 2. In this way, it can completely surround the conductive hole 4 passing through the adhesive layer 2 to form a barrier, completely blocking the light incident on the adhesive layer 2.

[0046] Figure 4 Schematic diagram of the design of setting a barrier layer in the adhesive layer 2 according to the present disclosure. Figure 4 As shown, for example, the aperture D of the upper opening of via 4 can be 60 microns, the aperture d of the lower opening can be 60 microns, the height H1 of the redistribution layer 3 is 30 microns, the height H2 of the adhesive layer 2 is 30 microns, and the height H of via 4 is 60 microns. That is, the length ratio of the aperture D of the upper opening of via 4 to the height H of via 4 is less than or equal to 1. The position D1 of the oblique light incident on the adhesive layer 2 may originate from light in the laser energy distribution 1 to 35 microns outside the upper opening. According to the principle of similar triangles, if a barrier layer is not embedded in the adhesive layer 2, the lower opening will be expanded at position d1. The expanded position d1 will be 1 to 35 microns outside the lower opening. Embedding a barrier layer in the adhesive layer 2 at the bottom of the via 4 can effectively block the oblique light incident on the adhesive layer 2, thereby avoiding hole shape defects in the via 4.

[0047] In some optional embodiments, the barrier layer may be a ring structure. Figure 2 The barrier layer (ring structure) 6 is shown in FIG.

[0048] The blocking layer (annular structure) 6 can form a closed and continuous barrier, which can block the light incident on the adhesive layer 2 .

[0049] In some optional embodiments, the number of the annular structures is at least two, and the interval between two adjacent annular structures is 10 microns.

[0050] Here, the number of the blocking layers (annular structures) 6 is at least two, and at least two blocking layers (annular structures) 6 can be evenly spaced 10 microns apart to effectively block light scattering and avoid hole shape defects of the via hole 4 .

[0051] In some optional embodiments, such as Figure 3 As shown, the via hole 4 has a side wall angle α, which is less than or equal to 100.2 degrees.

[0052] In practice, the energy distribution of the laser determines that the sidewall angle α of the via 4 is less than or equal to 100.2 degrees. The semiconductor structure disclosed herein, in which a barrier layer is provided in the adhesive layer 2 to prevent hole expansion, is applicable to scenarios where the sidewall angle α of the via 4 is less than or equal to 100.2 degrees.

[0053] The present disclosure provides a method for manufacturing a semiconductor structure, which may include: first, providing a substrate 1, and disposing a barrier layer on the substrate 1. Then, disposing an adhesive layer 2 on the substrate 1, such that the barrier layer is embedded in the adhesive layer 2. Finally, disposing a redistribution layer 3 on the adhesive layer 2, and forming a via 4 penetrating the adhesive layer 2 and the redistribution layer 3.

[0054] Here, the redistribution layer 3 and the substrate 1 can be electrically connected through a via 4. The via 4 includes an upper opening and a lower opening. The barrier layer is used to define the aperture d of the lower opening. For example, a CO2 (carbon dioxide) laser can be used to form the via 4.

[0055] The method for manufacturing a semiconductor structure provided by the present disclosure can control the aperture d of the lower opening of the via hole 4 by setting a barrier layer in the adhesive layer 2 for defining the aperture d of the lower opening of the via hole 4, thereby avoiding the phenomenon of hole expansion at the bottom of the via hole 4, improving the quality of the via hole, and further improving the stability of the semiconductor structure.

[0056] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalent components may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present disclosure and the actual implementation. There may be other embodiments of the present disclosure that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A semiconductor structure comprising: substrate; an adhesive layer, disposed on the substrate; a redistribution layer, disposed on the adhesive layer; a conductive hole, passing through the adhesive layer and the redistribution layer, wherein the redistribution layer is electrically connected to the substrate through the conductive hole, wherein the conductive hole includes a lower opening; A blocking layer is embedded in the adhesive layer and surrounds the conductive hole, wherein the blocking layer is an annular structure, the number of the annular structures is at least two, and the blocking layer is used to block light and define the aperture of the lower opening of the conductive hole.

2. The semiconductor structure according to claim 1, wherein The conducting hole is an inverted truncated cone structure.

3. The semiconductor structure according to claim 1, wherein The conductive via includes an upper opening that penetrates the upper surface of the redistribution layer, and a length ratio of an aperture of the upper opening to a height of the conductive via is less than or equal to 1.

2.

4. The semiconductor structure according to claim 1, wherein The barrier layer is a dam structure.

5. The semiconductor structure according to claim 1, wherein The interval between two adjacent ring structures is 10 microns.

6. The semiconductor structure according to any one of claims 1 to 5, wherein: The via hole has a side wall angle that is less than or equal to 100.2 degrees.

7. A method of manufacturing a semiconductor structure, comprising: providing a substrate; Disposing a blocking layer on the substrate, wherein the blocking layer is an annular structure, the number of the annular structures is at least two, and the blocking layer is used to block light; providing an adhesive layer on the substrate so that the barrier layer is embedded in the adhesive layer; providing a redistribution layer on the adhesive layer; A via hole is formed through the adhesive layer and the redistribution layer, the redistribution layer is electrically connected to the substrate through the via hole, the via hole includes an upper opening and a lower opening, and the barrier layer is used to define the aperture of the lower opening.

8. The method according to claim 7, wherein: The conducting hole is an inverted truncated cone structure.

9. The method according to claim 7, wherein: The upper opening passes through the upper surface of the redistribution layer, and the length ratio of the aperture of the upper opening to the height of the via is less than or equal to 1.2.

Images