Semiconductor memory device

Abstract

A semiconductor memory device includes: a logic circuit disposed on a substrate having a cell region and a peripheral region outside the cell region; a source plate defined above the logic circuit; a slit that divides the source plate into a cell source plate in the cell region and a dummy source plate in the peripheral region; and a memory cell array defined on the cell source plate. The dummy source plate is maintained at a constant voltage regardless of the operation of the memory cell array and the logic circuit.

Description

Technical Field

[0001] Various embodiments generally relate to a semiconductor memory device, and more particularly, to a semiconductor memory device having a logic circuit disposed below a memory cell array. Background Art

[0002] With the development of semiconductor manufacturing technology, semiconductor memory devices are required to be miniaturized and highly integrated. In order to meet the requirements of high integration, a peripheral under cell (PUC) structure has been proposed, in which logic circuits are arranged under a memory cell array.

[0003] Electrostatic discharge (ESD) is a failure mode that occurs when static electricity flows. The electrostatic current generated by ESD can cause damage to components such as diodes and transistors of semiconductor memory devices. For example, the high current generated by ESD applied to the PN junction of a diode can cause junction spikes, or may damage the gate dielectric layer of a transistor, thereby shorting the gate, drain, and source. Therefore, manufacturers make various efforts to protect components from the effects of ESD. Summary of the invention

[0004] Various embodiments are directed to a semiconductor memory device capable of reducing damage due to ESD.

[0005] In one embodiment, a semiconductor memory device may include: a logic circuit disposed on a substrate having a cell region and a peripheral region outside the cell region; a source plate defined above the logic circuit; a slit that divides the source plate into a cell source plate in the cell region and a dummy source plate in the peripheral region; and a memory cell array defined on the cell source plate. The dummy source plate may be maintained at a constant voltage regardless of operations of the memory cell array and the logic circuit.

[0006] In one embodiment, a semiconductor memory device may include: a logic circuit defined on a substrate having a cell area and a peripheral area outside the cell area; a cell source plate disposed above the logic circuit in the cell area; a memory cell array defined on the cell source plate; and an electrostatic discharge shielding plate disposed above the logic circuit in the peripheral area.

[0007] In one embodiment, a semiconductor memory device may include: a logic circuit defined on a substrate; a source plate disposed above the logic circuit; a slit that divides the source plate into a plurality of unit source plates and a dummy source plate; and a plurality of memory cell arrays, respectively defined on the plurality of unit source plates. The dummy source plate may be maintained at a constant voltage regardless of whether the memory cell array and the logic circuit are operating. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram showing a representation of a semiconductor memory device according to one embodiment of the present disclosure.

[0009] Figure 2 is a cross-sectional view showing a representation of a semiconductor memory device according to one embodiment of the present disclosure.

[0010] Figure 3 is a top view showing an expression of a semiconductor memory device according to one embodiment of the present disclosure.

[0011] Figure 4 is a block diagram showing a representation of a semiconductor memory device according to one embodiment of the present disclosure.

[0012] Figure 5 It is shown Figure 4 A top view of a schematic layout of a semiconductor memory device is shown.

[0013] Figure 6 yes Figure 5 Detailed top view.

[0014] Figure 7 It shows Figure 5 A cross-sectional view of a semiconductor memory device is shown.

[0015] Figure 8 is an enlarged top view showing a representation of a pad arrangement region of a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Fig. 9 is along Figure 8 A cross-sectional view taken along line AA'.

[0017] FIG. 10A to FIG. 10C 1 is a top view showing examples of dummy source plates of various shapes in a pad arrangement region of a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Fig.11 is a diagram schematically showing a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0019] Fig.12 is a block diagram schematically illustrating a computing system including a semiconductor memory device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The advantages and features of the present disclosure and methods for implementing the same will become apparent from the following description of exemplary embodiments described with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0021] The figures, sizes, ratios, angles, and numbers of elements provided in the drawings describing the embodiments of the present disclosure are merely illustrative and not restrictive. Throughout the specification, the same reference numerals represent the same elements. When describing the present disclosure, when it is determined that the detailed description of the known related art may obscure the main points or clarity of the present disclosure, its detailed description will be omitted. It should be understood that the terms "including", "having", "comprising", etc. used in the specification and claims should not be interpreted as being limited to the things listed thereafter, unless otherwise specifically stated. When an indefinite article or definite article (e.g., "one", "the") is used when referring to a singular noun, unless otherwise specifically stated, the article may include the plural form of the noun.

[0022] Even in the case where there is no explicit description, elements in the embodiments of the present disclosure should be construed as including error tolerances.

[0023] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b) may be used. These terms are only for the purpose of distinguishing one component from another component, and do not imply or suggest the essence, level, order or quantity of the components.

[0024] If a component is described as being “connected,” “coupled,” or “linked” to another component, this may mean that the component may be not only directly “connected,” “coupled,” or “linked,” but may also be indirectly “connected,” “coupled,” or “linked” via a third component. When describing a positional relationship, such as “component A on component B,” “component A above component B,” “component A below component B,” and “component A next to component B,” another component C may be disposed between component A and component B unless the term “directly” or “immediately adjacent” is explicitly used.

[0025] The features of the various exemplary embodiments of the present disclosure may be partially or completely connected, combined or separated. Technically, various interactions and operations may be performed. The various exemplary embodiments may be implemented individually or in combination.

[0026] Hereinafter, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram showing a representation of a semiconductor memory device according to one embodiment of the present disclosure.

[0028] Reference Figure 1 , a semiconductor memory device 100 according to an embodiment of the present disclosure may include a memory cell array 110 and a logic circuit 120. The logic circuit 120 may include a row decoder (X-DEC) 121, a page buffer circuit 122, and a peripheral circuit (PERI circuit) 123.

[0029] The memory cell array 110 may include a plurality of memory blocks BLK. Although not shown, each memory block BLK may include a plurality of cell strings. Each cell string may include at least one drain select transistor, a plurality of memory cells, and at least one source select transistor connected in series. Each memory cell may be a volatile memory cell or a non-volatile memory cell. Although the semiconductor memory device 100 will be described below as a vertical NAND flash memory device, it should be understood that the technical spirit of the present disclosure is not limited thereto.

[0030] The memory cell array 110 may be coupled to the row decoder 121 through row lines RL. The row lines RL may include at least one drain select line, a plurality of word lines, and at least one source select line.

[0031] The row decoder 121 may select any one memory block from the memory blocks BLK included in the memory cell array 110 in response to the row address X_A provided from the peripheral circuit 123. The row decoder 121 may transmit the operation voltage X_V provided from the peripheral circuit 123 to the row line RL connected to the memory block BLK selected from the memory blocks BLK included in the memory cell array 110.

[0032] The memory cell array 110 may be coupled to the page buffer circuit 122 through the bit lines BL. The page buffer circuit 122 may include a plurality of page buffers PB respectively coupled to the bit lines BL. The page buffer circuit 122 may receive a page buffer control signal PB_C from the peripheral circuit 123, and may transmit a data signal DATA to the peripheral circuit 123 and receive the data signal DATA from the peripheral circuit 123. The page buffer circuit 122 may control the bit lines BL arranged in the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 122 may detect data stored in the memory cells of the memory cell array 110 by sensing the signals of the bit lines BL of the memory cell array 110 in response to the page buffer control signal PB_C, and may transmit the data signal DATA to the peripheral circuit 123 according to the detected data. The page buffer circuit 122 may apply a signal to the bit lines BL based on the data signal DATA received from the peripheral circuit 123 in response to the page buffer control signal PB_C, so that data may be written into the memory cells of the memory cell array 110. The page buffer circuit 122 may write data to or read data from a memory cell coupled to a word line activated by the row decoder 121 .

[0033] The peripheral circuit 123 may receive a command signal CMD, an address signal ADD, and a control signal CTRL from outside the semiconductor memory device 100, and may send a data signal DATA to a device (e.g., a memory controller) outside the semiconductor memory device 100 and receive a data signal DATA from a device outside the semiconductor memory device 100. Based on the command signal CMD, the address signal ADD, and the control signal CTRL, the peripheral circuit 123 may output a signal for writing data into the memory cell array 110 or reading data from the memory cell array 110, such as a row address X_A and a page buffer control signal PB_C, etc. The peripheral circuit 123 may generate various voltages, including an operating voltage X_V required in the semiconductor memory device 100.

[0034] Hereinafter, in the drawings, two directions parallel to the top surface of the substrate and intersecting each other are defined as a first direction FD and a second direction SD, respectively, and a direction extending vertically from the top surface of the substrate is defined as a vertical direction VD. For example, the first direction FD may correspond to an extension direction of a word line or an arrangement direction of a bit line, and the second direction SD may correspond to an extension direction of a bit line or an arrangement direction of a word line. The first direction FD and the second direction SD may substantially intersect each other vertically. In the drawings, a direction indicated by an arrow and a direction opposite thereto represent the same direction.

[0035] Figure 2is a cross-sectional view showing a representation of a semiconductor memory device according to one embodiment of the present disclosure.

[0036] Reference Figure 2 , the semiconductor memory device 100 according to one embodiment of the present disclosure may have a peripheral under cell (PUC) structure. The logic structure P may be disposed under the memory structure C

[0037] The logic structure P may include a substrate 10 and a logic circuit 120 disposed on the substrate 10. The substrate 10 may include at least one selected from the group consisting of a single crystal silicon layer, a silicon on insulator (SOI), a silicon layer formed on a silicon germanium (SiGe) layer, a single crystal silicon layer formed on a dielectric layer, and a polysilicon layer formed on a dielectric layer. The logic circuit 120 may include a transistor TR disposed on an active region defined by an isolation layer (not shown). Although not shown, the logic circuit 120 may also include a capacitor, an inductor, and the like. The logic circuit 120 may include the above reference Figure 1 The row decoder 121, the page buffer circuit 122, and the peripheral circuit 123 are described.

[0038] A bottom dielectric layer 30 may be defined on the substrate 10 to cover the logic circuit 120. The bottom dielectric layer 30 may include silicon oxide, such as high density plasma (HDP) oxide or tetraethylorthosilicate (TEOS) oxide.

[0039] A plurality of bottom wirings UM1, UM2, and UM3 (UM1 to UM3) may be defined in the bottom dielectric layer 30. The bottom wirings UM1 to UM3 may include, for example, first to third bottom wirings UM1 to UM3 disposed in different layers along the vertical direction VD. The second bottom wiring UM2 may be disposed on a higher layer than the first bottom wiring UM1. The third bottom wiring UM3 may be disposed on a higher layer than the second bottom wiring UM2. The first bottom wiring UM1 may be coupled to the logic circuit 120 through a contact C11. The second bottom wiring UM2 may be coupled to the first bottom wiring UM1 through a contact C12. The third bottom wiring UM3 may be coupled to the second bottom wiring UM2 through a contact C13.

[0040] The memory structure C may include a source plate 20 and a memory cell array 110. The semiconductor memory device 100 and the substrate 10 may be divided into a central cell region CR and a peripheral region PR outside the cell region CR. A slit SLT may be defined in the source plate 20 to divide the source plate 20 into a unit source plate 20A and a dummy source plate 20B. The unit source plate 20A may be disposed in the cell region CR, and the dummy source plate 20B may be disposed in the peripheral region PR. The unit source plate 20A and the dummy source plate 20B may be formed in the same process step and may be made of the same conductive material. For example, the unit source plate 20A and the dummy source plate 20B may include at least one of polysilicon, tungsten (W), copper (Cu), and aluminum (Al).

[0041] The memory cell array 110 may include a plurality of vertical channels CH disposed on the cell source plates 20A, and a plurality of electrode layers 40 and a plurality of interlayer dielectric layers 42 alternately stacked along the vertical channels CH.

[0042] The electrode layer 40 may include a conductive material. For example, the electrode layer 40 may include at least one selected from a doped semiconductor, a metal, a conductive metal nitride, or a transition metal. The interlayer dielectric layer 42 may include silicon oxide. The electrode layer 40 may be formed Figure 1 The row line R1 is shown. Among the electrode layers 40, at least one electrode layer 40 from the bottom electrode layer 40 may constitute a source selection line, and at least one electrode layer 40 from the top electrode layer 40 may constitute a drain selection line. The electrode layers 40 between the source selection line and the drain selection line may constitute a word line.

[0043] Each vertical channel CH may include a channel layer 50 and a gate dielectric layer 52. The channel layer 50 may include polycrystalline silicon or single crystal silicon, and may include P-type impurities such as boron (B) in some regions thereof. The channel layer 50 may have the shape of a solid cylinder or a column that is completely filled up to its central region. In other embodiments not shown here, the channel layer 50 may have the shape of a hollow tube. In this case, a buried dielectric layer may be formed inside the hollow tube and fill the open region inside the channel layer 50. The gate dielectric layer 52 may have the shape of a straw or a cylindrical shell surrounding the outer wall of the channel layer 50. Although Figure 2Not shown, but the gate dielectric layer 52 may include a tunnel dielectric layer, a charge storage layer, and a blocking layer stacked in sequence in an inward direction starting from the outer wall of the channel layer 50. In some embodiments, the gate dielectric layer 52 may have an oxide-nitride-oxide (ONO) stacked structure in which an oxide layer, a nitride layer, and an oxide layer are stacked in sequence. The source selection transistor, the memory cell, and the drain selection transistor may be defined in a region where the electrode layer 40 surrounds the vertical channel CH.

[0044] A top dielectric layer 32 may be defined on the bottom dielectric layer 30 to cover the cell source plates 20A, the dummy source plates 20B, and the memory cell array 110. The top dielectric layer 32 may include silicon oxide, such as HDP oxide or TEOS oxide.

[0045] A plurality of top wirings TM1 and TM2 may be defined in the top dielectric layer 32. The top wirings TM1 and TM2 may include, for example, a first top wiring TM1 and a second top wiring TM2 disposed in different layers along the vertical direction VD. The second top wiring TM2 may be disposed at a layer higher in the vertical direction than the first top wiring TM1.

[0046] Each vertical channel CH of the memory cell array 110 may be coupled to one of the first top wirings TM1 through a contact C21. The first top wiring TM1 coupled to the vertical channel CH may be coupled to one of the second top wirings TM2 through a contact C22. Some of the second top wirings TM2 may constitute a bit line BL coupled to the vertical channels CH of the memory cell array 110.

[0047] The electrode layer 40 may be stacked in a stepwise manner. Each electrode layer 40 may have a pad area connected to a contact C31. The bottom end of the contact C31 may be connected to the pad area of ​​the electrode layer 40, and the top end of the contact C31 may be connected to one of the first top wirings TM1. The first top wiring TM1 may be connected to the third bottom wiring UM3 through the contact C32. The third bottom wiring UM3 may be connected to the logic circuit 120 through the contacts C11 to C13 and the bottom wirings UM1 and UM2. The electrode layer 40 may be electrically connected to the logic circuit 120 through the contact C31, the first top wiring TM1, the contact C32, the third bottom wiring UM3, the contact C13, the second bottom wiring UM2, the contact C12, the first bottom wiring UM1, and the contact C11. Therefore, an operating voltage may be provided from the logic circuit 120 to the electrode layer 40.

[0048] Contacts connecting the top wirings TM1 and TM2 and the bottom wirings UM1 to UM3 may be defined in the peripheral region PR. For example, a contact C32 connecting the first top wiring TM1 and the third bottom wiring UM3 may be defined in the peripheral region PR. The dummy source plate 20B may have an opening OP through which the contact C32 passes.

[0049] In the vertical direction VD, the dummy source plate 20B may overlap with the logic circuit 120 in the peripheral region PR, that is, the dummy source plate 20B may be vertically located above or on a portion of the logic circuit 120. A constant voltage may be loaded to the dummy source plate 20B independently of the operation of the memory cell array 110 and the logic circuit 120. For example, the constant voltage may be a ground voltage. In this case, at least one of the bottom wirings UM1 to UM3 may include a ground wiring UM_GND loaded with a ground voltage. Figure 2 An example is shown in which a third bottom wiring UM3 is configured as a ground wiring UM_GND. The dummy source plate 20B can be connected to the ground wiring UM_GND through a contact C14, so that a ground voltage can be received from the ground wiring UM_GND. Although the present embodiment shows a case where the potential loaded to the dummy source plate 20B is a ground voltage, it should be noted that the present disclosure is not limited thereto.

[0050] Regardless of whether the memory cell array 110 and the logic circuit 120 are operating, the dummy source plate 20B can be maintained at a constant voltage, thereby being used as a shield against electrostatic discharge (ESD), and the transmission of ESD to the logic circuit 120 can be suppressed. The dummy source plate 20B can be defined as an ESD shield. The dummy source plate 20B can suppress the coupling between the top wirings TM1 and TM2 disposed above the memory cell array 110 and the bottom wirings UM1 to UM3 disposed below the memory cell array 110 in the peripheral region PR. This prevents or suppresses the degradation of electrical characteristics caused by unnecessary coupling between the top wirings TM1 and TM2 and the bottom wirings UM1 to UM3.

[0051] Figure 3 is a top view showing an expression of a semiconductor memory device according to one embodiment of the present disclosure.

[0052] Reference Figure 3 , a row decoder 121, a page buffer circuit 122, and a peripheral circuit 123 that together constitute a logic circuit 120 may be disposed on the substrate 10. Figure 3 , a dotted line indicates a boundary between the cell region CR and the peripheral region PR. In the present embodiment, the row decoder 121 and the peripheral circuit 123 may be disposed in the peripheral region PR, and the page buffer circuit 122 may be disposed in the cell region CR.

[0053] The source plate 20 may be disposed on the logic circuit 120. The slit SLT may divide the source plate 20 along a boundary between the cell region CR and the peripheral region PR. The source plate 20 may be divided into a unit source plate 20A and a dummy source plate 20B by the slit SLT. The unit source plate 20A and the dummy source plate 20B may be physically and electrically isolated from each other by the slit SLT. The unit source plate 20A may be disposed in the cell region CR, and the dummy source plate 20B may be disposed in the peripheral region PR.

[0054] The memory cell array 110 may be disposed on the cell source plate 20A. When viewed from the top, the row decoder 121 may be disposed adjacent to the memory cell array 110 along the first direction FD. The row decoder 121 may extend along the second direction SD, which also serves as an arrangement direction of the row lines. Figure 3 The row decoder 121 is shown not overlapping the memory cell array 110 along the vertical direction VD, but it should be noted that the present disclosure is not limited thereto. In other embodiments, at least a portion of the row decoder 121 may overlap the memory cell array 110 along the vertical direction VD.

[0055] The page buffer circuit 122 may overlap the memory cell array 110 along the vertical direction VD. The page buffer circuit 122 may be disposed to extend along a first direction FD, which is also an arrangement direction of the bit lines.

[0056] The input / output pads PAD may be arranged in the peripheral region PR along the first direction FD. The input / output pads PAD may be external contacts of the semiconductor memory device 100 for electrically connecting to an external device (not shown here) such as a printed circuit board. When viewed from the top, the peripheral circuit 123 may be arranged adjacent to the memory cell array 110 along the second direction SD. A portion of the peripheral circuit 123 may overlap the input / output pads PAD along the vertical direction VD.

[0057] In the peripheral region PR, the dummy source plate 20B may overlap the logic circuit 120 (e.g., the row decoder 121 and the peripheral circuit 123) in the vertical direction VD. The dummy source plate 20B may be maintained at a constant voltage independently of the operation of the memory cell array 110 and the logic circuit 120, thereby serving as a shield for the logic circuit 120 against ESD.

[0058] Figure 4 is a block diagram showing a representation of a semiconductor memory device according to one embodiment of the present disclosure. Figure 5 It is shown Figure 4 A top view of a schematic layout of a semiconductor memory device is shown. Figure 6 yes Figure 5 A detailed top view of Figure 7 It shows Figure 5 A cross-sectional view of a semiconductor memory device is shown.

[0059] Reference Figure 4 , the semiconductor memory device 200 may include a plurality of planes PLANE1 to PLANE4. The semiconductor memory device 200 may have a multi-plane structure. Figures 4 to 6 A 4-plane structure is shown.

[0060] Each of the planes PLANE1 to PLANE4 may include a memory cell array 110, a row decoder 121, and a page buffer circuit 122. The planes PLANE1 to PLANE4 may share a peripheral circuit 123.

[0061] Reference Figure 5 , when viewed from the top, the planes PLANE1 to PLANE4 may be arranged in the form of a 2×2 matrix along the first direction FD and the second direction SD. The substrate 10 and the semiconductor memory device 200 may be divided into a plurality of cell regions CR corresponding to the plurality of planes PLANE1 to PLANE4, respectively, and a peripheral region PR outside the cell regions CR. Figure 5 , a dotted line indicates a boundary between the cell region CR and the peripheral region PR. The input / output pads PAD may be arranged along the first direction and adjacent to an edge of the substrate 10 along the second direction SD.

[0062] Reference Figures 5 to 7 , the logic circuit 120 may be defined on the substrate 10. The logic circuit 120 may include Figure 4 The logic circuit 120 may include a row decoder 121 and a page buffer circuit 122 included in planes PLANE1 to PLANE4, and a peripheral circuit 123 shared by planes PLANE1 to PLANE4. A bottom dielectric layer 30 may be defined on the substrate 10 to cover the logic circuit 120. The source plate 20 may be disposed on the bottom dielectric layer 30. The source plate 20 may be divided into a plurality of unit source plates 20A and a dummy source plate 20B by a slit SLT. The slit SLT may divide the source plate 20 along a boundary between the cell region CR and the peripheral region PR. Respectively, the unit source plate 20A may be disposed in the cell region CR, and the dummy source plate 20B may be disposed in the peripheral region PR.

[0063] The unit source plates 20A may be disposed adjacent to each other along the first direction FD and the second direction SD. The dummy source plates 20B may be disposed between adjacent unit source plates 20A and at the periphery of the plurality of unit source plates 20A. In each of the planes PLANE1 to PLANE4, the memory cell array 110 may be disposed on each unit source plate 20A.

[0064] exist Figure 6 In the embodiment, the peripheral circuit 123 may be disposed in two separate regions extending in the first direction FD and spaced apart in the second direction SD. Hereinafter, for ease of explanation, the first peripheral circuit 123-1 is located near an edge of the substrate 10 adjacent to the input / output pad PAD. The second peripheral circuit 123-2 is disposed at a portion closer to the center of the substrate 10 relative to the first peripheral circuit 123-1.

[0065] like Figure 6 As shown, a portion of the first peripheral circuit 123-1 may overlap a portion of the memory cell array 110 of the first plane PLANE1 and the second plane PLANE2 along the vertical direction VD. A portion of the first peripheral circuit 123-1 may also overlap the input / output pad PAD along the vertical direction VD. A portion of the second peripheral circuit 123-2 may partially overlap a portion of the memory cell array 110 of the third plane PLANE3 and the fourth plane PLANE4 along the vertical direction VD. By arranging the first peripheral circuit 123-1 to overlap the memory cell array 110 and the input / output pad PAD of the first plane PLANE1 and the second plane PLANE2, and by arranging the second peripheral circuit 123-2 to overlap the memory cell array 110 of the third plane PLANE3 and the fourth plane PLANE4, the size of the semiconductor memory device 200 may be reduced.

[0066] Refer again Figure 6 and Figure 7 , the dummy source plate 20B may overlap the logic circuit 120 in the peripheral region PR along the vertical direction VD. Regardless of whether the memory cell array 110 and the logic circuit 120 are operating, the dummy source plate 20B may be maintained at a constant voltage, thereby shielding the logic circuit 120 from the influence of ESD. The dummy source plate 20B may be disposed between the top wirings TM1 and TM2 and the bottom wirings UM1 to UM3 in the peripheral region PR. The dummy source plate 20B may be maintained at a constant voltage independent of the voltage loaded to the top wirings TM1 and TM2 and the bottom wirings UM1 to UM3, thereby suppressing unnecessary coupling between the top wirings TM1 and TM2 and the bottom wirings UM1 to UM3.

[0067] Figure 8is an enlarged top view showing a representation of a pad arrangement region of a semiconductor memory device according to an embodiment of the present disclosure, and Fig. 9 is along Figure 8 A cross-sectional view taken along line AA'.

[0068] Reference Figure 8 When viewed from the top, a pair of ESD protection circuits 124 may be disposed adjacent to the pad PAD. In the event that high voltage static electricity is suddenly introduced when a power supply voltage or data is input to the pad PAD, the ESD protection circuits 124 may discharge static electricity to the internal circuit.

[0069] Reference Fig. 9 The pad PAD may be disposed on the top dielectric layer 32 and may be exposed to the outside of the top dielectric layer 32. Along the vertical direction VD, the pad PAD may overlap the dummy source plate 20B defined or disposed between the top dielectric layer 32 and the bottom dielectric layer 30.

[0070] Each ESD protection circuit 124 may be defined or disposed on the substrate 10 and may be included in the logic circuit 120. The dummy source plate 20B may be disposed between the pad PAD and the logic circuit 120 and may overlap the pad PAD and the logic circuit 120 in the vertical direction VD. The dummy source plate 20B may be maintained at a constant voltage independent of the voltage or data input to the pad PAD. In the case where high-voltage static electricity is suddenly introduced when the power supply voltage or data is input to the pad PAD, the dummy source plate 20B may release the static electricity.

[0071] FIG. 10A to FIG. 10C is a top view showing examples of various shapes of dummy source plates in a pad arrangement region of a semiconductor memory device according to an embodiment of the present disclosure.

[0072] Reference Fig. 10A , the dummy source plate 20B may extend in the same direction as the direction in which the pads PAD are arranged. The dummy source plate 20B may have a continuous shape overlapping all the pads PAD included in the semiconductor memory device.

[0073] In other embodiments, reference Fig. 10B , the pads PAD may be grouped into a plurality of pad groups PG according to the level of the applied voltage. For example, voltages of similar levels may be applied to the pads PAD included in a single pad group PG. The dummy source plate 20B may be divided into a plurality of segments corresponding to the pad groups PG. In yet another embodiment, referring to Fig. 10C , the dummy source plate 20B may be divided into a plurality of segments each corresponding to a single pad PAD.

[0074] As is apparent from the above description, according to the embodiments of the present disclosure, by using a dummy source plate as an ESD shielding device, ESD is suppressed and the ESD is prevented from being transmitted to a logic circuit, so that damage to the logic circuit can be reduced.

[0075] According to an embodiment of the present disclosure, by shielding the wiring located below the memory cell array and the wiring located above the memory cell array from each other using a dummy source plate, unnecessary coupling between the lower wiring and the upper wiring can be suppressed. Therefore, the electrical characteristics of the semiconductor device can be improved, and the restrictions on the layout of the wiring due to harmful coupling can be reduced, thereby improving the efficiency of the wiring layout.

[0076] According to an embodiment of the present disclosure, by using a dummy source plate as a shield, there is no need to form a separate structure for shielding ESD. Therefore, by simplifying the process by removing the manufacturing steps required to form a separate structure for shielding, the manufacturing cost can be reduced and the possible failures in the manufacturing process can be reduced.

[0077] Fig.11 is a block diagram schematically illustrating a memory system including a semiconductor memory device according to one embodiment of the present disclosure.

[0078] Reference Fig.11 , a memory system 600 according to one embodiment may include a nonvolatile memory device (NVM device) 610 and a memory controller 620 .

[0079] The nonvolatile memory device 610 may be composed of the above-mentioned semiconductor memory device and may be operated in the above-mentioned manner. The memory controller 620 may be configured to control the nonvolatile memory device 610. The combination of the nonvolatile memory device 610 and the memory controller 620 may be configured as a memory card or a solid state disk (SSD). The SRAM 621 is used as a working memory of the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol of a host connected to the memory system 600.

[0080] The error correction code block (ECC) 624 detects and corrects errors included in data read from the nonvolatile memory device 610 .

[0081] The memory interface (memory I / F) 625 interfaces with the nonvolatile memory device (NVM device) 610 of the present embodiment. The processing unit (CPU) 622 performs general control operations of the memory controller 620 for data exchange.

[0082] Although not shown in the drawings, it is obvious to those skilled in the art that the memory system 600 according to the present embodiment may be additionally provided with a ROM storing code data for interfacing with a host. The nonvolatile memory device (NVM device) 610 may be provided as a multi-chip package consisting of a plurality of flash memory chips.

[0083] As described above, the memory system 600 according to the embodiment can be set as a high-reliability storage medium with a low probability of error occurrence. In particular, the non-volatile memory device of the present embodiment can be included in a memory system such as a solid-state disk (SSD) that is being actively studied recently. In this case, the memory controller 620 can be configured to communicate with an external device (e.g., a host) through one of various interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect express (PCI-E) protocol, a serial advanced technology attachment (SATA) protocol, a parallel advanced technology attachment (PATA) protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated electronic device (IDE) protocol.

[0084] Fig.12 is a block diagram schematically illustrating a computing system including a semiconductor memory device according to one embodiment of the present disclosure.

[0085] Reference Fig.12 , the computing system 700 according to one embodiment may include a memory system 710 electrically connected to a system bus 760, a microprocessor (CPU) 720, a RAM 730, a user interface 740, and a modem 750 such as a baseband chipset. In the case where the computing system 700 according to the present embodiment is a mobile device, a battery (not shown) for providing an operating voltage of the computing system 700 may be additionally provided. Although not shown in the drawings, it is obvious to a person skilled in the art to which the present embodiment belongs that the computing system 700 according to the present embodiment may be additionally provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. The memory system 710 may be configured, for example, as a solid-state drive / disk (SSD) using a non-volatile memory to store data. In addition, the memory system 710 may be configured as a fused flash memory (e.g., OneNAND flash memory).

[0086] Although exemplary embodiments of the present disclosure have been described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications, additions, and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, it should be considered that the embodiments disclosed above and in the accompanying drawings are merely illustrative and not intended to limit the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure may be interpreted in conjunction with the appended claims, and include all equivalents that fall within the scope of the appended claims.

[0087] CROSS-REFERENCE TO RELATED APPLICATIONS

[0088] This application claims the priority of Korean Patent Application No. 10-2019-0165376 filed on December 12, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: a logic circuit disposed on a substrate having a unit region and a peripheral region outside the unit region; a source plate defined above the logic circuit; a slit that divides the source plate into a unit source plate in the unit region and a dummy source plate in the peripheral region; as well as a memory cell array, the memory cell array being defined on the cell source plates, The dummy source plate is maintained at a constant voltage regardless of the operation of the memory cell array and the logic circuit.

2. The semiconductor memory device according to claim 1, further comprising: a top wiring defined above the source plate; a bottom wiring defined between the logic circuit and the source plate; as well as a contact connecting the top wiring and the bottom wiring in the peripheral region, Wherein, the dummy source plate has an opening for the contact member to pass through.

3. The semiconductor memory device according to claim 1, wherein: The unit source plate and the dummy source plate are formed of the same material.

4. The semiconductor memory device according to claim 1, wherein: A portion of the logic circuit overlaps the dummy source plate along a vertical direction perpendicular to a top surface of the substrate.

5. The semiconductor memory device according to claim 1, further comprising: a plurality of pads arranged in the peripheral region and exposed to the outside of a top dielectric layer covering the memory cell array, and the plurality of pads are spaced apart from each other, The dummy source plate overlaps with at least one of the plurality of pads along a vertical direction perpendicular to the top surface of the substrate.

6. The semiconductor memory device according to claim 5, wherein: A portion of the logic circuit overlaps a portion of the dummy source plate and at least one of the plurality of pads along the vertical direction.

7. The semiconductor memory device according to claim 5, wherein: The dummy source plate is continuous in shape and overlaps all of the plurality of pads along the vertical direction.

8. The semiconductor memory device according to claim 5, wherein: The plurality of pads are grouped into a plurality of pad groups, and the dummy source plate is divided into a plurality of sections respectively corresponding to one of the plurality of pad groups.

9. The semiconductor memory device according to claim 5, wherein: The dummy source plate is divided into a plurality of segments respectively corresponding to one of the plurality of pads.

10. A semiconductor memory device, comprising: a logic circuit defined on a substrate having a unit region and a peripheral region outside the unit region; a cell source plate, the cell source plate being disposed above the logic circuit in the cell region; a memory cell array, the memory cell array being defined on the cell source plates; as well as An electrostatic discharge shielding plate is disposed above the logic circuit in the peripheral region.

11. The semiconductor memory device according to claim 10, wherein: The cell source plate and the electrostatic discharge shielding plate are separated from each other by a slit along a boundary between the cell region and the peripheral region.

12. The semiconductor memory device according to claim 10, further comprising: a top wiring disposed above the cell source plate and the electrostatic discharge shielding plate; a bottom wiring disposed in a bottom dielectric layer covering the logic circuit between the cell source plate and the substrate and between the electrostatic discharge shielding plate and the substrate; as well as a contact connecting the top wiring and the bottom wiring in the peripheral region, Wherein, the electrostatic discharge shielding plate comprises an opening for the contact member to pass through.

13. The semiconductor memory device according to claim 10, wherein: A portion of the logic circuit overlaps a portion of the electrostatic discharge shielding plate in a vertical direction perpendicular to a top surface of the substrate.

14. The semiconductor memory device according to claim 10, further comprising: a plurality of pads arranged in the peripheral region and exposed to the outside of a top dielectric layer covering the memory cell array, The electrostatic discharge shielding plate overlaps the plurality of pads along a vertical direction perpendicular to the top surface of the substrate.

15. The semiconductor memory device according to claim 14, wherein: A portion of the logic circuit overlaps a portion of the electrostatic discharge shielding plate and at least one of the plurality of pads in the vertical direction.

16. The semiconductor memory device according to claim 15, wherein: The electrostatic discharge shielding plate is continuous in shape and overlaps all of the plurality of pads.

17. The semiconductor memory device according to claim 16, wherein: The plurality of pads are grouped into a plurality of pad groups, and the electrostatic discharge shielding plate is divided into a plurality of sections corresponding to the plurality of pad groups.

18. The semiconductor memory device according to claim 16, wherein: The electrostatic discharge shielding plate is divided into a plurality of sections, each of the plurality of sections corresponding to one of the plurality of pads.

19. A semiconductor memory device, the semiconductor memory device comprising: a logic circuit, the logic circuit being defined on the substrate; A source plate, the source plate being disposed above the logic circuit; A slit, wherein the slit divides the source plate into a plurality of unit source plates and a dummy source plate; as well as a plurality of memory cell arrays, the plurality of memory cell arrays being respectively defined on the plurality of cell source plates, Wherein, no matter whether the memory cell array and the logic circuit are operating or not, the dummy source plate is kept at a constant voltage.

20. The semiconductor memory device according to claim 19, wherein The plurality of unit source plates are arranged to be adjacent to each other along a first direction and a second direction, the first direction and the second direction are parallel to the top surface of the substrate and intersect each other, and The dummy source plate is disposed between adjacent unit source plates and at outer circumferences of the plurality of unit source plates.

Images