Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device includes a first channel pattern on a substrate and spaced apart from the substrate, the first channel pattern having a first end and a second end and a first sidewall and a second sidewall connected between the first end and the second end, the first end and the second end spaced apart from each other in a first direction parallel to a top surface of the substrate, the first sidewall and the second sidewall spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction; a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate; and a first gate electrode adjacent to the first sidewall of the first channel pattern.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2019-0165786, entitled "Three-dimensional semiconductor device", filed with the Korean Intellectual Property Office on December 12, 2019, is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiment relates to a three-dimensional semiconductor device. Background Technology

[0004] Semiconductor devices are advantageous in the electronics industry due to their small size, versatility, and / or low manufacturing cost. Semiconductor devices can include semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data operations, and hybrid semiconductor devices that incorporate both memory and logic elements. With the advancement of the electronics industry, semiconductor devices are increasingly demanding high levels of integration. For example, there are increasing requirements for high reliability, high speed, and / or versatility. The structure of semiconductor devices is gradually increasing in complexity and integration to meet these requirements. Summary of the Invention

[0005] According to some example embodiments, a three-dimensional semiconductor device may include: a first channel pattern disposed on and spaced apart from a substrate, the first channel pattern including a first end and a second end, and a first sidewall and a second sidewall located between the first end and the second end, the first end and the second end being spaced apart from each other in a first direction parallel to the top surface of the substrate, the first sidewall and the second sidewall being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction; a bit line contacting a first end of the first channel pattern, the bit line extending upward in a third direction perpendicular to the top surface of the substrate; and a first gate electrode adjacent to a first sidewall of the first channel pattern.

[0006] According to some example embodiments, a three-dimensional semiconductor device may include: a channel pattern extending in a first direction perpendicular to the top surface of a substrate, the channel pattern including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, the first and second sidewalls being spaced apart from each other in a second direction intersecting the first direction and parallel to the top surface of the substrate, the third and fourth sidewalls being spaced apart from each other in a third direction intersecting the second direction and parallel to the top surface of the substrate; a plurality of gate electrodes adjacent to the first sidewall of the channel pattern and spaced apart from each other in the first direction; and bit lines contacting the third sidewall of the channel pattern and extending in the first direction.

[0007] According to some example embodiments, a three-dimensional semiconductor device can include: first and second bit lines extending in a first direction perpendicular to a top surface of a substrate and spaced apart from each other in a second direction parallel to the top surface of the substrate; a word line located at a certain height from the top surface of the substrate, the word line extending in the second direction; a first channel pattern located on the top surface of the substrate and at the height at which the word line is located, the first channel pattern in contact with the first bit line; and a second channel pattern located on the top surface of the substrate and at the height at which the word line is located, the second channel pattern in contact with the second bit line. The word line can include a first word line protrusion between the first channel pattern and the second channel pattern. The first word line protrusion can be closer to the first channel pattern than to the second channel pattern. BRIEF DESCRIPTION OF DRAWINGS

[0008] The features will become apparent to one skilled in the art upon examination of the detailed description of the example embodiments, taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A circuit diagram presenting a three-dimensional semiconductor device according to some example embodiments is shown.

[0010] Figure 2 A perspective view presenting a three-dimensional semiconductor device according to some example embodiments is shown.

[0011] Figure 3 A circuit diagram presenting a three-dimensional semiconductor device according to some example embodiments is shown.

[0012] Figure 4 A perspective view presenting a three-dimensional semiconductor device according to some example embodiments is shown.

[0013] Figure 5 A plan view presenting a three-dimensional semiconductor device according to some example embodiments is shown.

[0014] Figure 6 A cross-sectional view taken along line I-I’ of Figure 4 or Figure 5 is shown.

[0015] Figures 7A-7M A perspective view presenting various stages in a method of manufacturing a three-dimensional semiconductor device according to some example embodiments is shown. Figure 5

[0016] A perspective view presenting a three-dimensional semiconductor device according to some example embodiments is shown. Figure 8

[0017] A perspective view presenting a three-dimensional semiconductor device according to some example embodiments is shown. Figure 9 A perspective view presenting a three-dimensional semiconductor device according to some example embodiments is shown.

[0018] Figure 10 A cross-sectional view taken along line B-B' of Figure 9 is shown.

[0019] Figure 11 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown.

[0020] Figure 12 A cross-sectional view taken along line B-B' of Figure 11 is shown.

[0021] Figure 13 A circuit diagram of a three-dimensional semiconductor device according to some example embodiments is shown.

[0022] Figure 14 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown.

[0023] Figure 15 A circuit diagram of a three-dimensional semiconductor device according to some example embodiments is shown.

[0024] Figure 16 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown.

[0025] Figure 17 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown.

[0026] Figures 18A-18F A cross-sectional view taken along line B-B' of Figure 17 is shown.

[0027] Figure 19 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown.

[0028] Figure 20 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown. DETAILED DESCRIPTION

[0029] Figure 1 A circuit diagram of a three-dimensional semiconductor device according to some example embodiments is shown.

[0030] Reference is made to Figure 1According to the present embodiment, a semiconductor device can include a memory cell transistor MCT located between a bit line BL and a word line WL intersecting each other, for example, the bit line BL and the word line WL extend along intersecting directions. A gate of the memory cell transistor MCT can be connected to the word line WL, a source of the memory cell transistor MCT can be connected to the bit line BL. A drain of the memory cell transistor MCT can be connected to a capacitor CAP. One memory cell transistor MCT and one capacitor CAP can constitute a single memory cell MC. The bit line BL can extend vertically along a third direction D3, the word line WL can extend horizontally along a second direction D2. The capacitor CAP can be replaced with any data storage element. The data storage element can be, for example, a memory element using one of a magnetic tunnel junction pattern and a variable resistive body including a phase change material.

[0031] Figure 2 A perspective view showing a three-dimensional semiconductor device according to some example embodiments is shown.

[0032] Referring to Figure 2 A channel pattern CH can be provided on the substrate 10. The substrate 10 can be, for example, a single-crystal silicon substrate, a silicon-on-insulator (SOI) substrate, or a layer or substrate formed of a semiconductor material other than silicon. The channel pattern CH can be spaced apart from the substrate 10 along a third direction D3, for example. The channel pattern CH can be insulated from the substrate 10. The channel pattern CH can include an oxide semiconductor material, for example. The oxide semiconductor material can include one or more of indium (In), gallium (Ga), zinc (Zn), and tin (Sn), for example. The oxide semiconductor material can be indium gallium zinc oxide (IGZO) including indium (In), gallium (Ga), and zinc (Zn), for example. The oxide semiconductor material can be amorphous indium gallium zinc oxide (IGZO), for example. The channel pattern CH can include a first end E1 and a second end E2 spaced apart in a first direction D1 parallel to a top surface of the substrate 10.

[0033] Between the first end E1 and the second end E2 of the channel pattern CH, the gate electrode GE can be adjacent to one sidewall of the channel pattern CH, for example, the gate electrode GE can be adjacent to and face the sidewall of the channel pattern CH that is connected between the first end E1 and the second end E2. A gate dielectric layer can be interposed between the gate electrode GE and the channel pattern CH. The gate electrode GE can be located at a height from the top surface of the substrate 10 that is the same or similar to the height at which the channel pattern CH is located. The gate electrode GE can be connected to a word line WL that extends in a second direction D2, which intersects the first direction D1 and is parallel to the top surface of the substrate 10. The gate electrode GE can include a gate line portion GEL that extends in the first direction D1 and contacts the word line WL, and can further include a gate extension portion GEP that protrudes from the gate line portion GEL toward the channel pattern CH. The gate electrode GE and the word line WL can be integrally formed as a single body, for example, the gate extension portion GEP and the gate line portion GEL of the gate electrode GE can be integral with the word line WL to define a single and seamless structure. The gate electrode GE can also be referred to or described as a portion of or a word line protrusion of the word line WL.

[0034] The first end E1 of the channel pattern CH can contact the bit line BL. The bit line BL can include a bit line line portion BLL that extends in a third direction D3 that is perpendicular to the top surface of the substrate 10, and can further include a bit line protrusion BLP that protrudes in the first direction D1 from a sidewall of the bit line line portion BLL and contacts the first end E1. The bit line line portion BLL and the bit line protrusion BLP can be integrally formed as a single body. The bit line BL can be spaced apart from the substrate 10. Alternatively, the bit line BL can be connected to a source / drain of a bit line select transistor provided on the substrate 10. The bit line BL and the word line WL can be spaced apart from each other, for example, along the first direction D1.

[0035] The second end E2 of the channel pattern CH can contact the first electrode BE. The first electrode BE can be adjacent to the second electrode TE. The second electrode TE can include an electrode line portion TEL that extends in the second direction D2, and can further include at least one electrode protrusion TEP that protrudes from a sidewall of the electrode line portion TEL toward and along (e.g., abutting) the first electrode BE. A dielectric layer can be interposed between the first electrode BE and the second electrode TE. The first electrode BE, the second electrode TE, and the dielectric layer can constitute a capacitor. The second electrode TE can be spaced apart from the substrate 10. The channel pattern CH and its adjacent gate electrode GE can constitute a single unit memory cell transistor MCT. Figure 1

[0036] ​The first electrode BE can have a bar shape, a plug shape, or a hollow cylindrical shape. When the first electrode BE has a hollow cylindrical shape, an electrode protrusion TEP of the second electrode TE can be inserted into the first electrode BE. The bit line BL, the word line WL, the gate electrode GE, the first electrode BE, and the second electrode TE can include one or more of doped polysilicon, a metal (e.g., at least one of tungsten, copper, aluminum, ruthenium, titanium, tantalum, or a combination thereof), and a metal nitride including the aforementioned metal. Figure 2 The semiconductor devices can be disposed in a plurality, and the plurality of semiconductor devices can be arranged in parallel to or symmetrically to each other.

[0037] Figure 3 A circuit diagram presenting a three-dimensional semiconductor device according to some example embodiments is shown. Figure 3 A circuit diagram presenting a three-dimensional semiconductor device according to some example embodiments is shown. Figure 1 The plurality of semiconductor devices of the circuit shown in FIG. 1 can be arranged in a first direction D1, a second direction D2, and a third direction D3.

[0038] Referring to FIG. 1, Figure 3 The plurality of bit lines BL can vertically extend in the third direction D3 from a top surface of the substrate 10. The bit lines BL can be arranged in the first direction D1 and the second direction D2. A single bit line BL can intersect a plurality of word lines WL extending in the second direction D2. Memory cells MC can be disposed on corresponding intersections between the bit lines BL and the word lines WL. The memory cells MC can each include a memory cell transistor MCT and a capacitor CAP. The bit lines BL can correspondingly be connected to first terminals of bit line selection transistors ST adjacent to the substrate 10. The bit line selection transistors ST arranged in line along the second direction D2 can have second terminals connected to corresponding bit line connection lines BLC. The bit line selection transistors ST arranged in line along the second direction D2 can further have gates connected to corresponding bit line selection lines SL. The bit line selection lines SL can extend in the second direction D2. The bit line connection lines BLC can extend in the first direction D1 and can be spaced apart from each other in the second direction D2. The bit line connection lines BLC can be adjacent to the top surface of the substrate 10. The bit line connection lines BLC can be connected to corresponding sense amplifier circuits SA. Because the bit lines BL are perpendicular to the substrate 10, it can be easy to connect ends of the bit lines BL to the bit line connection lines BLC. In addition, it can be easy to form the bit lines BL having a constant first length, and it is easy to form the bit line connection lines BLC having a constant second length.

[0039] If the bit line BL is not set to extend perpendicularly to the top surface of the substrate 10, for example, in a case where the bit line BL extends in parallel to the top surface of the substrate 10, it will be required that the end portion of the bit line BL has a stepped shape for connecting the bit line BL to the sense amplifier circuit SA. In this case, the bit line BL will have different lengths from each other, resulting in signal interference and / or signal noise due to the length difference, which in turn will reduce the reliability of the semiconductor device.

[0040] In contrast, the bit line BL in the semiconductor device according to some example embodiments is perpendicular to the substrate 10, thereby facilitating connection to the sense amplifier circuit SA via the bit line connection line BLC while maintaining a constant length. As such, the reliability of the semiconductor device according to example embodiments can be improved.

[0041] Figure 4 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown. Figure 5 A plan view of a three-dimensional semiconductor device according to some example embodiments is shown. Figure 6 A cross-sectional view taken along the line I-I’ is shown. Figure 4 Or Figure 5 A cross-sectional view taken along the line I-I’ is shown. Figures 4-6 A semiconductor device having the circuit shown in Figure 3 is shown in part. For clarity of illustration, Figure 4 Depiction of the gate dielectric layer GL, the second electrode TE, the dielectric layer DL, and the buried dielectric layer 40 is omitted.

[0042] Referring to Figure 3 and Figure 6 , the semiconductor device according to the present embodiment can include a plurality of bit lines BL extending in the third direction D3 on the substrate 10. The under-interlayer dielectric layer 20 can be interposed between the substrate 10 and the bit lines BL. The under-interlayer dielectric layer 20 can have a single-layer or multi-layer structure including one or more of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous dielectric layer. The under-interlayer dielectric layer 20 can completely cover the top surface of the substrate 10. Although not shown, the substrate 10 can be provided thereon with Figure 3 bit line selection transistors ST, and the under-interlayer dielectric layer 20 can cover the bit line selection transistors ST. The end portion of the bit line BL can pass through the under-interlayer dielectric layer 20 and be electrically connected to the source / drain regions of the bit line selection transistors ST. The under-interlayer dielectric layer 20 can be provided therein with Figure 3 bit line connection lines BLC and bit line selection lines SL.

[0043] For example, the bit lines BL can be arranged two-dimensionally along the first direction D1 and the second direction D2 to be spaced apart from each other. A single bit line BL can include a bit line line portion BLL extending in the third direction D3 and a plurality of bit line protrusions BLP protruding from a sidewall of the bit line line portion BLL in the first direction D1. For example, as shown in FIG. 1A, the bit line BL can each have a comb shape. In another example, the bit line BL can not include the bit line protrusions BLP, but can include only the bit line line portion BLL. Figure 4

[0044] The bit line protrusions BLP can contact corresponding first ends E1 of the channel patterns CH. Second ends E2 of the channel patterns CH can contact corresponding first electrodes BE. Each of the channel patterns CH can have a first sidewall SW1 and a second sidewall SW2 facing each other between the first end E1 and the second end E2. The gate interlayer dielectric patterns 30 can be interposed between the channel patterns CH. The gate interlayer dielectric patterns 30 can have a single layer or a multi-layer structure including, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous dielectric layer.

[0045] The word lines WL can be stacked on the substrate 10. The word lines WL can be spaced apart from each other. The gate interlayer dielectric patterns 30 can be interposed between the word lines WL. The word lines WL can each extend in the second direction D2. A plurality of gate electrodes GE can be connected to the word lines WL. The gate electrodes GE can each have a gate line portion GEL extending in the first direction D1 and contacting the word line WL, and a gate extension portion GEP protruding from the gate line portion GEL toward the channel pattern CH. The word line WL and its corresponding gate electrode GE can be integrally formed as a single body. The channel pattern CH can include, for example, indium gallium zinc oxide (IGZO). The IGZO can serve as a channel at a portion adjacent to the gate electrode GE to which a voltage is applied.

[0046] The gate dielectric layer GL can be interposed between the gate electrode GE and the first sidewall SW1 of the channel pattern CH. The gate dielectric layer GL can include, for example, one or more of a silicon oxide layer and a high-k dielectric layer having a dielectric constant higher than that of silicon oxide. As shown in FIG. 1A, the gate dielectric layer GL can extend to the gap between the gate electrodes GE. Figure 6

[0047] The channel pattern CH at a certain height, the gate electrode GE adjacent to the channel pattern CH, and the gate dielectric layer GL between the channel pattern CH and the gate electrode GE can constitute a single unit memory cell transistor MCT. Figure 3 Figure 4 ​​​As shown in FIG. 1, the gate electrode GE included in the first memory cell transistor MCT1 at a certain height can be disposed, for example, between the channel pattern CH included in the first memory cell transistor MCT1 and the channel pattern CH included in the second memory cell transistor MCT2 adjacent to the first memory cell transistor MCT1 along the second direction D2. The gate electrode GE included in the first memory cell transistor MCT1 can be closer to the channel pattern CH included in the first memory cell transistor MCT1 than to the channel pattern CH included in the second memory cell transistor MCT2.

[0048] The second electrode TE can be adjacent to the first electrode BE. The second electrode TE can include an electrode line portion TEL extending in the second direction D2 and a plurality of electrode protrusions TEP protruding from the electrode line portion TEL toward and along (e.g., abutting) the sidewall of the first electrode BE. The dielectric layer DL can be interposed between the first electrode BE and the second electrode TE. The first electrode BE, the second electrode TE, and the dielectric layer DL can constitute a capacitor CAP. The first electrode BE can be disposed between adjacent electrode protrusions TEP.

[0049] The lower interlayer dielectric layer 20 can be disposed on the substrate 10, and the buried dielectric layer 40 fills spaces between the word lines WL, the gate electrodes GE, the channel patterns CH, and the bit lines BL. The buried dielectric layer 40 can have a single-layer or multi-layer structure including, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous dielectric layer. The second sidewall SW2 of the channel pattern CH can directly contact the buried dielectric layer 40, for example.

[0050] According to some embodiments, the semiconductor device can include bit lines BL perpendicular to the top surface of the substrate 10, which can result in a relatively large spacing between the bit lines BL compared to a case where the bit lines BL are stacked like the word lines WL. In addition, a shielding function can be applied to the gate electrodes GE and the word lines WL disposed between the bit lines BL. As a result, parasitic capacitance between the bit lines BL can be reduced to prevent or minimize signal interference and / or signal noise, and a semiconductor device with improved reliability can also be provided.

[0051] Figures 7A-7M Stereoscopic views showing various stages in a method of manufacturing a three-dimensional semiconductor device according to some example embodiments are shown. Figure 5 Stereoscopic views showing various stages in a method of manufacturing a three-dimensional semiconductor device according to some example embodiments are shown.

[0052] Reference is made to Figure 7AA lower interlayer dielectric layer 20 can be formed on the substrate 10. A sacrificial layer 25L and a gate interlayer dielectric layer 30L can be alternately and repeatedly formed on the lower interlayer dielectric layer 20. The gate interlayer dielectric layer 30L can have a single-layer or multi-layer structure including, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous dielectric layer. The sacrificial layer 25L can include a material with etch selectivity relative to the gate interlayer dielectric layer 30L.

[0053] Reference Figure 5 and Figure 7B A first mask pattern can be formed on the gate interlayer dielectric layer 30L at the top position. When viewed in a plan view, the first mask pattern can have connections. Figure 5 The shapes of the word line WL, at least one gate electrode GE, bit line BL, channel pattern CH, and first electrode BE are shown. A first mask pattern can be used as an etching mask through which the gate interlayer dielectric layer 30L and the sacrificial layer 25L are etched to form the gate interlayer dielectric pattern 30 and the sacrificial pattern 25, respectively, while simultaneously exposing the top surface of the lower interlayer dielectric layer 20. A buried dielectric layer 40 can be formed across the entire surface of the substrate 10, and a planarization etching process can subsequently be performed to expose the top surface of the gate interlayer dielectric pattern 30 at a top location. The buried dielectric layer 40 can fill the space except for the sacrificial pattern 25 and the gate interlayer dielectric pattern 30.

[0054] Reference Figure 5 and Figure 7C The second mask pattern can be used to etch the buried dielectric layer 40 adjacent to the location where the channel pattern CH will subsequently be formed. As a result, the first via H1 can be formed to expose the top surface of the lower interlayer dielectric layer 20. The first via H1 can expose the sidewalls of the sacrificial pattern 25 and the sidewalls of the gate interlayer dielectric pattern 30.

[0055] Reference Figure 5 , Figure 7C and Figure 7D An isotropic etching process can be performed to selectively remove the portion of the sacrificial pattern 25 exposed to the first hole H1, thereby forming the first recess R1. During this stage, the gate interlayer dielectric pattern 30 may not be etched. The first recess R1 exposes the top and bottom surfaces of the gate interlayer dielectric pattern 30. A deposition process can be performed to form a channel layer filling the first recess R1 on the entire surface of the substrate 10, and subsequently, a blanket isotropic etching process can be performed to leave the channel pattern CH in the first recess R1 and completely remove the channel layer outside the first recess R1.

[0056] Reference Figure 5 , Figure 7D and Figure 7EA buried dielectric layer 40 can be additionally formed on the entire surface of the substrate 10 to fill the first hole H1, and a planarization etching process can be subsequently performed to expose the top surface of the gate interlayer dielectric pattern 30 at the top position. A third mask pattern can be used to etch the buried dielectric layer 40 adjacent to the position where the end portion of the first electrode BE is formed, as a result, a second hole H2 can be formed to expose the top surface of the lower interlayer dielectric layer 20. The second hole H2 can expose the sidewall of the sacrificial pattern 25 and the sidewall of the gate interlayer dielectric pattern 30.

[0057] Referring to Figure 5 , Figure 7E and Figure 7F , an isotropic etching process can be performed to selectively remove the portion of the sacrificial pattern 25 exposed to the second hole H2, thereby forming a second recess R2. At this stage, the gate interlayer dielectric pattern 30 can not be etched. The second recess R2 can expose the top surface and the bottom surface of the gate interlayer dielectric pattern 30. The second recess R2 can expose the second end E2 of the channel pattern CH. The second recess R2 can expose the sidewall of the buried dielectric layer 40. A deposition process can be performed to form a first electrode layer on the entire surface of the substrate 10 to fill the second recess R2, and a blanket isotropic etching process can be subsequently performed to leave the first electrode BE in the second recess R2 and completely remove the first electrode layer outside the second recess R2. At this stage, the first electrode BE can be formed to have a plug shape or a hollow cylindrical shape based on the thickness of the first electrode layer.

[0058] Referring to Figure 5 , Figure 7F and Figure 7G , a buried dielectric layer 40 can be additionally formed on the entire surface of the substrate 10 to fill the second hole H2, and a planarization etching process can be subsequently performed to expose the top surface of the gate interlayer dielectric pattern 30 at the top position. A fourth mask pattern can be used to etch the buried dielectric layer 40 adjacent to the position where the word line WL and the gate line portion GEL are to be subsequently formed, as a result, a first opening O1 and a second opening O2 can be formed to expose the top surface of the lower interlayer dielectric layer 20. The first opening O1 can expose the sidewall of the sacrificial pattern 25 and the sidewall of the gate interlayer dielectric pattern 30 at the position where the word line WL is to be subsequently formed. The first opening O1 can have a trench shape extending in the second direction D2. The second opening O2 can expose the sidewall of the sacrificial pattern 25 and the sidewall of the gate interlayer dielectric pattern 30 at the position where the gate line portion GEL is to be subsequently formed.

[0059] Referring to Figure 5 , Figure 7G and Figure 7HAn isotropic etching process can be performed to remove most of the sacrificial pattern 25 exposed to the first and second openings O1, O2 to form a third recess R3, leaving a residual sacrificial pattern 25r in contact with the channel pattern CH. At this stage, the gate interlayer dielectric pattern 30 can not be etched. The third recess R3 can expose a top surface and a bottom surface of the gate interlayer dielectric pattern 30. The third recess R3 can expose a first sidewall SW1 of the channel pattern CH. The third recess R3 can expose a sidewall of the buried dielectric layer 40.

[0060] Referring to Figure 5 , Figure 6 , Figure 7H and Figure 7I , a gate dielectric layer GL can be formed conformally over the entire surface of the substrate 10, covering the inner walls of the third recess R3 and the top and bottom surfaces of the gate interlayer dielectric pattern 30. The gate dielectric layer GL can contact the first sidewall SW1 of the channel pattern CH. A gate electrode layer can be formed over the entire surface of the substrate 10, filling the third recess R3. An isotropic etching process can be performed on the gate electrode layer and the gate dielectric layer GL, removing the gate electrode layer and the gate dielectric layer GL from the first and second openings O1, O2, leaving the gate dielectric layer GL in the third recess R3, and forming the gate electrode GE and the word line WL. The isotropic etching process can expose the top surface of the gate interlayer dielectric pattern 30 at the top location and the top surface of the buried dielectric layer 40.

[0061] Referring to Figure 5 , Figure 7I and Figure 7J , the buried dielectric layer 40 can be additionally formed over the entire surface of the substrate 10, filling the first and second openings O1, O2, and a planarization etching process can be subsequently performed to expose the top surface of the gate interlayer dielectric pattern 30 at the top location. A fifth mask pattern can be used to etch the buried dielectric layer 40 adjacent to a location where a second electrode TE and a dielectric layer DL will be subsequently formed, as a result, a third opening O3 and a fourth opening O4 can be formed to expose the top surface of the lower interlayer dielectric layer 20. The third opening O3 can be formed by etching the buried dielectric layer 40 at a location where an electrode line portion TEL will be formed, and the third opening O3 can have a trench shape extending in the second direction D2. The third opening O3 can expose an end portion of the first electrode BE and an end portion of the gate interlayer dielectric pattern 30. The fourth opening O4 can be formed by etching the buried dielectric layer 40 at a location where an electrode protrusion TEP will be subsequently formed, and the fourth opening O4 can expose a sidewall of the first electrode BE and a sidewall of the gate interlayer dielectric pattern 30.

[0062] Referring to Figure 5 , Figure 7J and Figure 7KThe dielectric layer DL can be formed conformally over the entire surface of the substrate 10, thereby conformally covering the inner walls of the third and fourth openings O3 and O4. The dielectric layer DL can cover the sidewalls and end portions of the first electrodes BE. The second electrode layer can be formed over the entire surface of the substrate 10, thereby filling the third and fourth openings O3 and O4. A blanket etch-back process or a chemical mechanical polishing (CMP) process can be performed to expose the top surface of the buried dielectric layer 40 to form the second electrodes TE in the third and fourth openings O3 and O4, and at the same time leave the dielectric layer DL in the third and fourth openings O3 and O4.

[0063] Before the dielectric layer DL is formed, the gate interlayer dielectric pattern 30 exposed to the third and fourth openings O3 and O4 can be partially removed to expose the top and bottom surfaces of the first electrodes BE. Thereafter, when the dielectric layer DL and the second electrodes TE are formed, the dielectric layer DL can cover the top and bottom surfaces of the first electrodes BE. In addition, a portion of the second electrodes TE can be interposed between the first electrodes BE.

[0064] Referring to Figure 5 , Figure 7K and Figure 7L , the sixth mask pattern can be used to partially remove the gate interlayer dielectric pattern 30 at the locations where the bit line line portions BLL will be formed later, and also to partially remove the remaining sacrificial pattern 25r between the gate interlayer dielectric patterns 30, as a result, the third holes H3 can be formed to expose the top surface of the lower interlayer dielectric layer 20. The third holes H3 can expose the sidewalls of the remaining sacrificial pattern 25r and the sidewalls of the gate interlayer dielectric pattern 30.

[0065] Referring to Figure 5 , Figure 7L and Figure 7M , the remaining sacrificial pattern 25r exposed to the third holes H3 can be removed to expose the first ends El of the channel patterns CH. A conductive layer can be formed over the entire surface of the substrate 10, thereby filling the third holes H3, and later a blanket etch-back process or a chemical mechanical polishing (CMP) process can be performed to expose the top surface of the gate interlayer dielectric pattern 30 at the top locations, and to form the bit lines BL in the third holes H3. The bit lines BL can be formed to contact the first ends El of the channel patterns CH. The above-mentioned various processes can fabricate the three-dimensional semiconductor device discussed with reference to Figures 4-6 .

[0066] Figure 8 A perspective view showing a three-dimensional semiconductor device according to some example embodiments is shown.

[0067] Referring to Figure 8According to the present embodiment, the semiconductor device can be configured such that a plurality of gate electrodes GE are connected to a single word line WL at a certain height, and the gate electrodes GE can have shapes symmetrical to each other. The shape of the first memory cell transistor MCT1 can be symmetrical to the shape of the second memory cell transistor MCT2 at the same height at which the first memory cell transistor MCT1 is positioned. The gate electrode GE included in the first memory cell transistor MCT1 can be disposed between the channel pattern CH included in the first memory cell transistor MCT1 and the gate electrode GE included in the second memory cell transistor MCT2. Other configurations can be the same as or similar to the configurations discussed with reference to Figures 4-6

[0068] Figure 9 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown. Figure 10 A cross-sectional view taken along line B-B’ of Figure 9 is shown.

[0069] Referring to Figure 9 and Figure 10 , the channel pattern CH can extend in the third direction D3, and can be parallel to the bit line BL. The channel pattern CH can include a first sidewall SW1 and a second sidewall SW2 spaced apart from each other in the second direction D2, and further include a third sidewall SW3 and a fourth sidewall SW4 spaced apart from each other in the first direction D1. A plurality of gate electrodes GE at different heights can be adjacent to the first sidewall SW1 of one channel pattern CH. A gate dielectric layer GL can be interposed between the corresponding gate electrode GE and one channel pattern CH. The third sidewall SW3 of the channel pattern CH can be in contact with a bit line protrusion BLP located at a different height and connected to one bit line section BLL at the same time. The fourth sidewall SW4 of the channel pattern CH can be in contact with a plurality of first electrodes BE located at different heights at the same time. The channel pattern CH can include indium gallium zinc oxide (IGZO). A portion of the IGZO adjacent to a gate electrode GE to which a voltage is applied can function as a channel, but a portion thereof adjacent to a gate electrode GE to which no voltage is applied does not function as a channel. In the semiconductor device shown in Figure 9 and Figure 10 , even when the channel pattern CH is shared by memory cell transistors MCT at different heights, current leakage does not occur between adjacent memory cell transistors MCT. Other configurations can be the same as or similar to the configurations discussed with reference to Figures 4-6

[0070] Figure 11 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown. Figure 12 A cross-sectional view taken along line B-B’ of Figure 11 is shown. ​​

[0071] Reference Figure 11 and Figure 12 The semiconductor device according to this embodiment can be used with Figure 9 and Figure 10 Similar to a semiconductor device, and may include a back gate line BG adjacent to the second sidewall SW2 of the channel pattern CH. The back gate line BG may also be referred to as a back gate electrode. The back gate line BG may be parallel to the channel pattern CH and may extend in a third direction D3. The back gate line BG may be parallel to the bit line BL. A back gate dielectric layer BGL may be interposed between the back gate line BG and the channel pattern CH. The back gate dielectric layer BGL may include one or more of a silicon oxide layer and a high-k dielectric layer whose dielectric constant is greater than that of silicon oxide. The back gate dielectric layer BGL may be spaced apart from the substrate 10. The back gate line BG may be supplied with a voltage different from the voltage applied to at least one of the word lines WL. For example, a positive voltage may be applied to at least one of the word lines WL, and a negative voltage may be applied to the back gate line BG. The back gate line BG may prevent current leakage in an undesirable direction within the channel pattern CH and may help control channel formation within the channel pattern CH. Other configurations may be referenced. Figure 9 and Figure 10 The configurations discussed are the same or similar.

[0072] Figure 13 A circuit diagram illustrating a three-dimensional semiconductor device according to some example embodiments is shown. Figure 14 A perspective view showing a three-dimensional semiconductor device according to some example embodiments is shown.

[0073] Reference Figure 13 and Figure 14 The semiconductor device according to this embodiment may have a circuit in which a data storage pattern SP is interposed between the gate and channel of a memory cell transistor (MCT). For example, the semiconductor device according to this embodiment may include a data storage pattern SP between a channel pattern CH and a gate electrode GE. The data storage pattern SP may include one or more of a floating gate electrode, a ferroelectric pattern, a phase change material, and a silicon nitride layer. The data storage pattern SP may be spaced apart from both the gate electrode GE and the channel pattern CH. Alternatively, when the data storage pattern SP is a ferroelectric pattern, the data storage pattern SP may be in contact with one or more of the gate electrode GE and the channel pattern CH. The gate electrode GE may not include... Figure 4 The gate extension GEP, and may have only included Figure 2The shape of the gate line portion GEL of the semiconductor device 1 is not limited to the above-described shape. For example, the gate line portion GEL can include a first sidewall SW1 and a second sidewall SW2 that are spaced apart from each other in the second direction D2, and further include a third sidewall SW3 and a fourth sidewall SW4 that are spaced apart from each other in the first direction D1. The fourth sidewall SW4 of the gate line portion GEL can be in contact with the first electrode BE or with a portion of the capacitor CAP. Other configurations can be the same as those of the semiconductor device 1 of Figure 1 and Figure 2 . Figure 13 The memory cell transistor MCT of the semiconductor device 1 can be arranged two-dimensionally or three-dimensionally to constitute a memory cell array.

[0074] Figure 15 A circuit diagram of a three-dimensional semiconductor device according to some example embodiments is shown. Figure 16 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown.

[0075] Referring to Figure 15 and Figure 16 , the semiconductor device according to the present embodiment can be the same as the semiconductor device of Figure 13 and Figure 14 , but can not include the capacitor CAP. For example, the fourth sidewall SW4 of the channel pattern CH can be in contact with a conductive pattern GC. The conductive pattern GC can include a conductive line portion GVL extending in the second direction D2, and further include at least one conductive protrusion GVP extending from a sidewall of the conductive line portion GVL toward the fourth sidewall SW4 of the channel pattern CH. The conductive pattern GC can be supplied with a power supply voltage or a ground voltage. Other configurations can be the same as those of the semiconductor device of Figure 13 and Figure 14 .

[0076] Figure 17 A perspective view of a three-dimensional semiconductor device according to some example embodiments is shown. Figures 18A-18F A cross-sectional view taken along the line B-B’ of Figure 17 is shown.

[0077] Referring to Figure 17 , the channel pattern CH can extend in the third direction D3, and can be parallel to the bit line BL. The channel pattern CH can include a first sidewall SW1 and a second sidewall SW2 that are spaced apart from each other in the second direction D2, and further include a third sidewall SW3 and a fourth sidewall SW4 that are spaced apart from each other in the first direction D1. A plurality of gate electrodes GE at different heights can be adjacent to the first sidewall SW1 of one channel pattern CH. A data storage pattern SP can be interposed between the corresponding gate electrode GE and the first sidewall SW1 of the channel pattern CH. Other configurations can be the same as those of the semiconductor device of Figure 9 .

[0078] Referring to Figure 17 and Figure 18A , the data storage patterns SP can each be a floating gate electrode FG. The floating gate electrode FG can include, for example, a polysilicon pattern doped with impurities, a polysilicon pattern not doped with impurities, or a metal-containing layer. A blocking dielectric layer BCL can be interposed between the floating gate electrode FG and the gate electrode GE. The blocking dielectric layer BCL can include, for example, one or more of a silicon oxide layer and a high-k dielectric layer having a dielectric constant greater than that of silicon oxide. A tunneling dielectric layer TL can be interposed between the corresponding floating gate electrode FG and the channel pattern CH. The tunneling dielectric layer TL can include, for example, a silicon oxide layer.

[0079] Referring to Figure 17 and Figure 18B , the data storage patterns SP can each be a ferroelectric pattern FL. The ferroelectric pattern FL can include a ferroelectric material, for example, one or more of lead zirconate titanate (PZT), lanthanum-modified lead zirconate titanate (PLZT), bismuth lanthanum titanate (BLT), barium strontium titanate (BST), and strontium bismuth tantalate (SBT), but embodiments are not limited thereto. For example, the PZT can be Pb(Zr x Ti 1-x )O3 (where 0.2 < x < 0.8), the PLZT can be (Pb 1-y La y )(Zr x Ti 1-x )O3 (where 0.2 < x < 0.8 and 0.01 < y < 0.2), the BST can be Ba x Sr 1-x TiO3 (where 0.5 < x < 1), and the SBT can be Sr x Bi y Ta2O9 (where 0.5 < x < 1.5 and 1.5 < y < 3), but embodiments are not limited thereto. The ferroelectric pattern FL can be in contact with the corresponding gate electrode GE. Also, the ferroelectric pattern FL can be in contact with the channel pattern CH.

[0080] Referring to Figure 17 and Figure 18C , the data storage pattern SP can be a ferroelectric pattern FL. The ferroelectric pattern FL can extend in the third direction D3 along the first sidewall SW1 of the channel pattern CH. The ferroelectric pattern FL can be in contact with sidewalls of the gate electrode GE and the sidewalls of the gate interlayer dielectric pattern 30 at the same time.

[0081] Referring to Figure 17 and Figure 18DThe data storage patterns SP can each be a charge storage layer SN. The charge storage layer SN can include, for example, one or more of a dielectric layer including conductive nanodots, a silicon nitride layer, a silicon oxynitride layer, a silicon rich nitride layer, a nanocrystalline silicon layer, and a stacked trap layer. A tunneling dielectric layer TL can be interposed between the corresponding charge storage layer SN and the channel pattern CH. The tunneling dielectric layer TL can be a material having a bandgap greater than a bandgap of the charge storage layer SN, for example, can be formed of a silicon oxide layer. A blocking dielectric layer BCL can be correspondingly interposed between the data storage pattern SP and the gate electrode GE. The blocking dielectric layer BCL can be, for example, one of a silicon oxide layer and a high-k dielectric layer. The high-k dielectric layer can be, for example, one or more of an aluminum oxide layer and a hafnium oxide layer. The gate interlayer dielectric pattern 30 can be interposed between data storage patterns SP adjacent to each other in the third direction D3.

[0082] Referring to Figure 17 and Figure 18E , the data storage patterns SP can be silicon oxide layers. A tunneling dielectric layer TL can be interposed between the data storage pattern SP and the channel pattern CH. A blocking dielectric layer BCL can be interposed between the corresponding data storage pattern SP and the gate electrode GE. The data storage pattern SP, the tunneling dielectric layer TL, and the blocking dielectric layer BCL can extend in the third direction D3 and can completely cover the first sidewall SW1 of the channel pattern CH.

[0083] Referring to Figure 17 and Figure 18F , the data storage patterns SP can each be a silicon oxide layer. A tunneling dielectric layer TL can be interposed between the corresponding data storage pattern SP and the channel pattern CH. A blocking dielectric layer BCL can be correspondingly interposed between the data storage pattern SP and the gate electrode GE. The data storage pattern SP, the tunneling dielectric layer TL, and the blocking dielectric layer BCL can extend to intervene between the gate electrode GE and the gate interlayer dielectric pattern 30 correspondingly.

[0084] Figure 19 A perspective view showing a three-dimensional semiconductor device according to some example embodiments is shown.

[0085] Referring to Figure 19 , the semiconductor device according to the present embodiment can be configured such that the channel pattern CH includes a first sidewall SW1 and a second sidewall SW2 spaced apart from each other in the second direction D2, and further includes a third sidewall SW3 and a fourth sidewall SW4 spaced apart from each other in the first direction D1. The gate electrode GE can be adjacent to the first sidewall SW1 of the channel pattern CH. The gate electrode GE can be connected to a word line WL. The word line WL can extend in the first direction D1. The word line WL and the gate electrode GE can be integrally formed as a single body. The gate electrode GE can be a portion of the word line WL. Other configurations can be with reference to Figure 2The configurations discussed are the same or similar.

[0086] Figure 20 A perspective view showing a three-dimensional semiconductor device according to some example embodiments is shown.

[0087] Reference Figure 20 A single gate electrode GE can be connected to a word line WL at a specific height. The gate electrode GE may include a gate line portion GEL, and further include a first gate protrusion GEP1 and a second gate protrusion GEP2 protruding from opposite side surfaces of the gate line portion GEL. According to this embodiment, the gate electrode GE may have… Figure 8 The adjacent gate electrodes GE are merged into each other. The channel pattern CH can be adjacent to each of the first gate protrusion GEP1 and the second gate protrusion GEP2. For example, a single gate electrode GE can be disposed between adjacent channel patterns CH. The first gate protrusion GEP1 and its adjacent channel pattern CH can constitute a first memory cell transistor MCT1. The second gate protrusion GEP2 and its adjacent channel pattern CH can constitute a second memory cell transistor MCT2. Other configurations can be referenced. Figures 4-6 The configurations discussed are the same or similar.

[0088] By summarizing and reviewing, the exemplary embodiments provide a three-dimensional semiconductor device with improved reliability. Specifically, the three-dimensional semiconductor device according to the exemplary embodiments includes bit lines perpendicular to the substrate, thus minimizing or preventing signal interference and / or signal noise on the bit lines. Furthermore, a simple connection can be provided between the bit lines and the sense amplifier circuitry. Additionally, the bit line selection transistor can be configured to minimize the load through the bit lines. In summary, the reliability of the three-dimensional semiconductor device can be improved.

[0089] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and explanatory sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art up to the time of filing of this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically stated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A three-dimensional semiconductor device comprising: a first channel pattern on a substrate and spaced apart from the substrate, the first channel pattern including: a first end and a second end spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connected between the first end and the second end, the first sidewall and the second sidewall spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction; a first bit line in contact with the first end of the first channel pattern, the first bit line and a second bit line extending in a third direction perpendicular to the top surface of the substrate and spaced apart from each other in the second direction; and a first gate electrode adjacent to the first sidewall of the first channel pattern, wherein the first bit line includes: a bit line line portion perpendicular to the top surface of the substrate; and a bit line protrusion protruding from a sidewall of the bit line line portion in the first direction and in contact with the first end of the first channel pattern.

2. The device of claim 1, further comprising a second channel pattern at a same height as the first channel pattern, the second channel pattern spaced apart from the first channel pattern, wherein, the first gate electrode between the first channel pattern and the second channel pattern, and wherein a distance between the first gate electrode and the first channel pattern is less than a distance between the first gate electrode and the second channel pattern.

3. The device of claim 2, further comprising a second gate electrode between the second channel pattern and the first gate electrode, a shape of the first gate electrode symmetrical to a shape of the second gate electrode with respect to a straight line extending in the first direction between the first gate electrode and the second gate electrode.

4. The device of claim 1, further comprising one of a data storage pattern and a conductive pattern, each of the data storage pattern and the conductive pattern in contact with the second end of the first channel pattern, the conductive pattern supplied with a power supply voltage or a ground voltage.

5. The device of claim 1, further comprising a back gate electrode adjacent to the second sidewall of the first channel pattern.

6. The device of claim 5, further comprising a word line on the substrate and connected to the first gate electrode, the back gate electrode extending in the third direction, parallel to the first bit line, and intersecting the word line.

7. The device of claim 1, wherein: the first channel pattern extends in the third direction and parallel to the first bit line, and the device further comprises a second gate electrode adjacent to the first sidewall of the first channel pattern and spaced apart from the first gate electrode in the third direction.

8. The device of claim 7, wherein, the first bit line includes: a bit line line portion perpendicular to the top surface of the substrate; and a first bit line protrusion and a second bit line protrusion protruding from a sidewall of the bit line line portion in the first direction, the first bit line protrusion and the second bit line protrusion spaced apart from each other in the third direction, wherein the first bit line protrusion is adjacent to the first gate electrode, and wherein the second bit line protrusion is adjacent to the second gate electrode.

9. The device of claim 1, further comprising a word line on the substrate, the word line extending in the second direction and being at a same height as the first gate electrode, and the first gate electrode extending in the first direction to contact the word line.

10. The device of claim 9, wherein, the first gate electrode comprises: a gate line portion extending in the first direction and contacting the word line; and a first gate protrusion protruding from a first sidewall of the gate line portion toward a first sidewall of the first channel pattern.

11. The device of claim 10, wherein: the first gate electrode further comprises a second gate protrusion protruding toward a second sidewall of the gate line portion, the second sidewall of the gate line portion facing the first sidewall of the gate line portion, and the device further comprises a second channel pattern adjacent to the second gate protrusion and spaced apart from the first channel pattern.

12. A three-dimensional semiconductor device, comprising: a channel pattern extending in a first direction perpendicular to a top surface of a substrate, the channel pattern comprising: a first sidewall and a second sidewall spaced apart from each other in a second direction intersecting the first direction, the second direction being parallel to the top surface of the substrate, and a third sidewall and a fourth sidewall spaced apart from each other in a third direction intersecting the second direction, the third direction being parallel to the top surface of the substrate; gate electrodes adjacent to the first sidewall of the channel pattern and spaced apart from each other in the first direction; and a first bit line and a second bit line, the first bit line contacting the third sidewall of the channel pattern, and the first bit line and the second bit line extending in the first direction and spaced apart from each other in the second direction.

13. The device of claim 12, wherein, the first bit line comprises: a bit line line portion spaced apart from the channel pattern and extending in the first direction; and bit line protrusions protruding from sidewalls of the bit line line portion toward the third sidewall of the channel pattern and spaced apart from each other in the first direction.

14. The device of claim 12, further comprising a word line connected to a corresponding gate electrode and extending in the second direction or in the third direction.

15. The device of claim 14, further comprising a back gate line adjacent to the second sidewall of the channel pattern and extending in the first direction.

16. The device of claim 12, further comprising one of a gate dielectric layer and a data storage pattern, each of the gate dielectric layer and the data storage pattern interposed between the channel pattern and a corresponding one of the gate electrodes.

17. The device of claim 12, further comprising a data storage pattern or a conductive pattern, the data storage pattern or the conductive pattern contacting the fourth sidewall of the channel pattern and spaced apart from each other in the first direction.

18. A three-dimensional semiconductor device, comprising: a first bit line and a second bit line, the first and second bit lines extending in a first direction perpendicular to a top surface of a substrate and spaced apart from each other in a second direction parallel to the top surface of the substrate; a word line located at a predetermined height from the top surface of the substrate, the word line extending in the second direction; a first channel pattern located on the top surface of the substrate and at the same height as the word line, the first channel pattern in contact with the first bit line; and a second channel pattern located on the top surface of the substrate and at the same height as the word line, the second channel pattern in contact with the second bit line, wherein the word line includes a first word line protrusion between the first channel pattern and the second channel pattern, and wherein the first word line protrusion is closer to the first channel pattern than to the second channel pattern.

19. The device of claim 18, wherein: the word line further includes a second word line protrusion located between the first word line protrusion and the second channel pattern, and a shape of the first word line protrusion is symmetrical to a shape of the second word line protrusion with respect to a straight line extending between the first and second word line protrusions in a third direction perpendicular to the first and second directions. ​

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