image sensor

Abstract

Disclosed is an image sensor including: a semiconductor substrate having a first surface and a second surface, and having a pixel region with a photoelectric conversion region; a gate electrode disposed on the pixel region and adjacent to the first surface; a first isolation structure extending from the first surface toward the second surface, the first isolation structure including: a first pixel isolation pattern surrounding the pixel region; and a first inner isolation pattern spaced apart from the first pixel isolation pattern and located between the photoelectric conversion regions; and a second isolation structure extending from the second surface toward the first surface, having a top surface vertically spaced apart from at least a portion of a bottom surface of the first isolation structure. The bottom surface of the first isolation structure is closer to the second surface of the semiconductor substrate than the first surface of the semiconductor substrate.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2019-0167053, filed on December 13, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to an image sensor, and more particularly, to a complementary metal-oxide-semiconductor (CMOS) image sensor. Background Technology

[0004] An image sensor is a semiconductor device configured to convert optical images into electrical signals. Image sensors can be classified into two types: charge-coupled device (CCD) type and complementary metal-oxide-semiconductor (CMOS) type. Typically, CMOS image sensors are referred to as "CIS". A CIS consists of multiple pixels arranged in a two-dimensional pattern, each pixel including a photodiode (PD) that converts incident light into an electrical signal. Summary of the Invention

[0005] Embodiments of the present invention provide an image sensor with improved electrical and optical properties.

[0006] According to an exemplary embodiment of the present invention, an image sensor includes: a semiconductor substrate having a first surface and a second surface, the semiconductor substrate including a pixel region having a plurality of photoelectric conversion regions; a gate electrode disposed on the pixel region and adjacent to the first surface; a first isolation structure extending from the first surface toward the second surface, the first isolation structure including: a first pixel isolation pattern surrounding the pixel region; and a first internal isolation pattern spaced apart from the first pixel isolation pattern and positioned between the plurality of photoelectric conversion regions; and a second isolation structure extending from the second surface toward the first surface, the second isolation structure having a top surface vertically spaced apart from at least a portion of the bottom surface of the first isolation structure. The bottom surface of the first isolation structure is closer to the second surface of the semiconductor substrate than the first surface of the semiconductor substrate.

[0007] According to an embodiment of the present invention, an image sensor may include: a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first surface and a second surface facing each other, and including a plurality of pixel regions; a first pixel isolation pattern disposed in the semiconductor substrate to electrically separate the first pixel region, which is one of the pixel regions, from other pixel regions; a first photoelectric conversion region and a second photoelectric conversion region disposed in the first pixel region and including impurities of a second conductivity type different from the first conductivity type; a first internal isolation pattern disposed between the first photoelectric conversion region and the second photoelectric conversion region and spaced apart from the first pixel isolation pattern; a connection region disposed between the first pixel isolation pattern and the first internal isolation pattern to connect the first photoelectric conversion region and the second photoelectric conversion region, the connection region including impurities of the second conductivity type; and a second internal isolation pattern extending from the second surface toward the connection region and spaced apart from the first surface.

[0008] According to embodiments of the present invention, an image sensor may include: a semiconductor substrate of a first conductivity type, the semiconductor substrate including a pixel region and having a first surface and a second surface facing each other in a first direction; a plurality of photoelectric conversion regions disposed in the pixel region and including impurities of a second conductivity type different from the first conductivity type; a gate electrode disposed on the photoelectric conversion region and adjacent to the first surface; a first isolation structure extending from the first surface toward the second surface, the first isolation structure including: a first pixel isolation pattern surrounding the pixel region; and a first internal isolation pattern spaced apart from the first pixel isolation pattern and located between the plurality of photoelectric conversion regions; a second isolation structure extending from the second surface toward the first surface, the second isolation structure including: a second pixel isolation pattern surrounding the pixel region; and a second internal isolation pattern connected to the second pixel isolation pattern and overlapping the pixel region; a barrier region disposed in the semiconductor substrate to cover the side surface of the first isolation structure and including impurities of the first conductivity type; and a connection region including impurities of the second conductivity type, the connection region being disposed between the first pixel isolation pattern and the first internal isolation pattern to connect the plurality of photoelectric conversion regions. Attached Figure Description

[0009] The exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments described herein.

[0010] Figure 1 This is a schematic plan view illustrating an image sensor according to an embodiment of the concept of the present invention.

[0011] Figure 2 This is a circuit diagram illustrating an image sensor according to an embodiment of the concept of the present invention.

[0012] Figure 3This is a plan view illustrating an image sensor according to an embodiment of the concept of the present invention.

[0013] Figure 4A , Figure 4B and Figure 4C They are respectively along Figure 3 The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0014] Figure 5A and Figure 5B These are plan views showing the first isolation structure and the second isolation structure, respectively.

[0015] Figure 6 It is shown Figure 4A Enlarged cross-sectional view of part AA.

[0016] Figure 7 It is along Figure 3 The cross-sectional view taken along line A-A' illustrates an image sensor according to an embodiment of the concept of the present invention.

[0017] Figure 8A and Figure 8B These are enlarged cross-sectional views, each cross-sectional view and... Figure 7 The part corresponding to "BB".

[0018] Figure 9 It is along Figure 3 A cross-sectional view taken along line C-C' illustrates an image sensor according to an embodiment of the present invention.

[0019] Figure 10A and Figure 10B These are plan views of portions of an image sensor according to an embodiment of the concept of the present invention.

[0020] Figures 11A to 11C They are respectively along Figure 10A The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0021] Figure 12 This is a plan view illustrating an image sensor according to an embodiment of the concept of the present invention.

[0022] Figure 13A and Figure 13B It is along Figure 12 The cross-sectional view taken by lines A-A' and B-B'.

[0023] Figure 14 , Figure 16 , Figure 18 and Figure 21 This is a plan view illustrating a method for manufacturing an image sensor according to an embodiment of the present invention.

[0024] Figure 15, Figure 17 , Figure 19 , Figure 20 and Figure 22 They are respectively along Figure 14 , Figure 16 , Figure 18 and Figure 21 The cross-sectional view taken along line A-A' illustrates a method for manufacturing an image sensor according to an embodiment of the present invention.

[0025] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and do not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range of values ​​or characteristics contained in the exemplary embodiments. For example, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0026] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0027] Figure 1 This is a schematic plan view illustrating an image sensor according to an embodiment of the concept of the present invention.

[0028] refer to Figure 1 The image sensor may include a pixel array area R1 and a pad area R2.

[0029] The pixel array region R1 may include a plurality of pixels P arranged in a two-dimensional manner. The pixel array region R1 may have a light-receiving surface perpendicular to a first direction D1, a thickness direction, or a vertical direction of the image sensor. The thickness direction (or vertical direction) may refer to a direction perpendicular to the first surface 100a of the semiconductor substrate 100. The pixels P may be arranged in a matrix shape or in two different directions (e.g., a second direction D2 and a third direction D3). The second direction D2 and the third direction D3 may be directions parallel to the first surface 100a of the semiconductor substrate 100. In an embodiment, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other. The pixel array region R1 may output an electrical signal generated by the incident light in each pixel P.

[0030] The pixel array region R1 may include a central region CR and an edge region ER surrounding the central region CR. When viewed in a planar view, the edge region ER may be located on the top, bottom, right, and left sides of the central region CR.

[0031] The angle of light incident on the edge region ER of the pixel array region R1 can be different from the angle of light incident on the central region CR of the pixel array region R1. Therefore, in an embodiment, the pixel P disposed in the central region CR can be configured to have a different structure than the pixel P disposed in the edge region ER. The inventive concept is not limited thereto. In an embodiment, the pixel P disposed in the central region CR can be configured to have the same structure, but a different structure than the pixel P disposed in the edge region ER.

[0032] Multiple conductive pads CP for inputting or outputting control signals and photoelectric signals can be disposed in the pad region R2. In one embodiment, the conductive pads CP may include a first pad for receiving control signals from an external device such as an image sensor controller, and a second pad for outputting photoelectric signals to an external device such as a display controller. When viewed in a plan view, the pad region R2 may be configured to surround the pixel array region R1, and the image sensor can be easily connected to the external device.

[0033] Figure 2 This is a circuit diagram illustrating an image sensor according to an embodiment of the concept of the present invention.

[0034] refer to Figure 2 Each pixel P may include a first photoelectric conversion device PD1, a second photoelectric conversion device PD2, a third photoelectric conversion device PD3, and a fourth photoelectric conversion device PD4; a first transmission transistor TX1, a second transmission transistor TX2, a third transmission transistor TX3, and a fourth transmission transistor TX4; and logic transistors RX, SX, and AX. Here, the logic transistors may include a reset transistor RX, a select transistor SX, and an amplification transistor AX. The gate electrodes of the first transmission transistor TX1, the second transmission transistor TX2, the third transmission transistor TX3, and the fourth transmission transistor TX4, the reset transistor RX, and the select transistor SX can be connected to drive signal lines TG1, TG2, TG3, TG4, RG, and SG, respectively.

[0035] The first transmission transistor TX1, the second transmission transistor TX2, the third transmission transistor TX3, and the fourth transmission transistor TX4 may each include a first gate electrode TG1, a second gate electrode TG2, a third gate electrode TG3, and a fourth gate electrode TG4, and may be electrically connected to the first photoelectric conversion device PD1, the second photoelectric conversion device PD2, the third photoelectric conversion device PD3, and the fourth photoelectric conversion device PD4, respectively. In an embodiment, the first transmission transistor TX1, the second transmission transistor TX2, the third transmission transistor TX3, and the fourth transmission transistor TX4 may be connected to a charge detection node FN or a floating diffusion region, respectively. In an embodiment, each charge detection node FN may be formed in a corresponding pixel of pixel P. The transmission transistors TX1, TX2, TX3, and TX4 in each pixel P may share a charge detection node FN. In an embodiment, each charge detection node FN may be disposed in a corresponding pixel of pixel P to be connected to the transmission transistors TX1, TX2, TX3, and TX4.

[0036] The first photoelectric conversion device PD1, the second photoelectric conversion device PD2, the third photoelectric conversion device PD3, and the fourth photoelectric conversion device PD4 can be configured to generate photocharge proportional to the amount of incident light. Each of the first photoelectric conversion device PD1, the second photoelectric conversion device PD2, the third photoelectric conversion device PD3, and the fourth photoelectric conversion device PD4 can be or include at least one of a photodiode, a phototransistor, a photogate, or a pinned photodiode (PPD).

[0037] The charge detection node FN can be configured to accumulate photocharge generated in the first photoelectric conversion device PD1, the second photoelectric conversion device PD2, the third photoelectric conversion device PD3, and the fourth photoelectric conversion device PD4. The amplifying transistor AX can be controlled by the amount of photocharge stored in the charge detection node FN.

[0038] The reset transistor RX can be configured to periodically discharge or reset the photocharge stored in the charge detection node FN. For example, the drain of the reset transistor RX can be connected to the charge detection node FN, and the source of the reset transistor RX can be connected to the power supply voltage VDD. If the reset transistor RX is turned on, the power supply voltage VDD can be applied to the charge detection node FN through the source electrode of the reset transistor RX. Therefore, the photocharge stored in the charge detection node FN can be discharged to the power supply voltage VDD through the reset transistor RX, thus resetting the charge detection node FN.

[0039] The amplifying transistor AX amplifies the potential change at the charge detection node FN and outputs the signal or pixel signal amplified by the select transistor SX to the output line VOUT. The amplifying transistor AX can be a source follower buffer amplifier configured to generate a source-drain current proportional to the amount of photocharge supplied to its gate electrode. The gate electrode of the amplifying transistor AX can be connected to the charge detection node FN, the drain of the amplifying transistor AX can be connected to the output line VOUT, and the source of the amplifying transistor AX can be connected to the drain of the select transistor SX.

[0040] The select transistor SX can be used to select the corresponding row of pixel P during a read operation. If the select transistor SX is turned on, the power supply voltage VDD applied to the drain electrode of the amplifying transistor AX can be applied to the drain electrode of the select transistor SX.

[0041] Figure 3 This is a plan view illustrating an image sensor according to an embodiment of the concept of the present invention. Figure 4A , Figure 4B and Figure 4C They are respectively along Figure 3 The cross-sectional views taken from lines A-A', B-B', and C-C'. Figure 5A and Figure 5B These are plan views showing the first isolation structure and the second isolation structure, respectively. Figure 6 It is shown Figure 4A Enlarged cross-sectional view of part AA.

[0042] refer to Figure 3 and Figures 4A to 4C An image sensor may include a photoelectric conversion layer 10, a readout circuit layer 20, and an optically transparent layer 30. For example... Figure 4A As shown, the photoelectric conversion layer 10 can be disposed between the readout circuit layer 20 and the optically transparent layer 30. For example, the readout circuit layer 20 can be disposed on the surface of the photoelectric conversion layer 10, and the optically transparent layer 30 can be disposed on the opposite surface of the photoelectric conversion layer 10.

[0043] The photoelectric conversion layer 10 may include: a semiconductor substrate 100 including a plurality of pixel regions PX; a first pixel isolation pattern 122 and a second pixel isolation pattern 132 disposed in the semiconductor substrate 100 to define the pixel regions PX; and a first internal isolation pattern 124 and a second internal isolation pattern 134 disposed in the pixel regions PX to define a plurality of photoelectric conversion regions 110 within each pixel region PX. The photoelectric conversion regions 110 can convert light incident from the outside into electrical signals.

[0044] The readout circuitry layer 20 may include readout circuitry (e.g., a MOS transistor) connected to the photoelectric conversion layer 10. The readout circuitry may include a previously referenced... Figure 2The logic transistors described. The readout circuit layer 20 can perform signal processing operations on the electrical signals generated from the photoelectric conversion layer 10.

[0045] The optically transparent layer 30 may include microlenses 330 arranged in a matrix shape, and may include color filters 320 between the microlenses 330 and the photoelectric conversion layer 10. Each color filter 320 may include one of a red, green, and blue filter, depending on the color of each unit pixel. However, in some embodiments, some color filters 320 may include infrared filters.

[0046] In one embodiment, the semiconductor substrate 100 may have a first or front surface 100a and a second or rear surface 100b opposite to each other in a first direction D1. The semiconductor substrate 100 may include a bulk silicon substrate of a first conductivity type and an epitaxial layer formed on the bulk silicon substrate and having the first conductivity type. In an embodiment, the bulk silicon substrate may be removed during the manufacturing process of the image sensor, and in this case, the semiconductor substrate 100 may be composed of an epitaxial layer of the first conductivity type. In some embodiments, the semiconductor substrate 100 may be a bulk semiconductor substrate in which a well region of the first conductivity type is disposed. The first conductivity type may be, for example, p-type.

[0047] A first isolation structure 120 extending from the first surface 100a toward the second surface 100b can be disposed in the semiconductor substrate 100. Furthermore, a second isolation structure 130 extending from the second surface 100b toward the first surface 100a can be disposed in the semiconductor substrate 100. The bottom surface 120b of the first isolation structure 120 can face the top surface 130t of the second isolation structure 130. For example, the bottom surface 120b of the first isolation structure 120 can be spaced apart from the top surface 130t of the second isolation structure 130 in the first direction D1. The bottom surface 120b of the first isolation structure 120 can overlap with the top surface 130t of the second isolation structure 130 in the first direction D1. Here, when measured in the first direction D1, the length of the first isolation structure 120 can be greater than the length of the second isolation structure 130. Compared to the first surface 100a of the semiconductor substrate 100, the bottom surface 120b of the first isolation structure 120 can be closer to the second surface 100b.

[0048] The first isolation structure 120 may include a first pixel isolation pattern 122 and a first internal isolation pattern 124. The second isolation structure 130 may include a second pixel isolation pattern 132 and a second internal isolation pattern 134. The first isolation structure 120 and the second isolation structure 130 may overlap each other in the first direction D1 and may be spaced apart from each other in the first direction D1.

[0049] The first pixel isolation pattern 122 of the first isolation structure 120 and the second pixel isolation pattern 132 of the second isolation structure 130 can separate a pixel region PX in the semiconductor substrate 100 from other pixel regions. When viewed in a plan view, the first pixel isolation pattern 122 and the second pixel isolation pattern 132 can surround the pixel region PX. In one embodiment, the first pixel isolation pattern 122 and the second pixel isolation pattern 132 can surround two adjacent pixel regions in the pixel region PX, such as... Figure 3 and Figure 4A As shown. Furthermore, a first pixel isolation pattern 122 and a second pixel isolation pattern 132 can be configured to span the area between two adjacent pixel regions in the pixel region PX. For the sake of simplicity in the figures, Figure 3 Only two pixel regions PX defined by the first pixel isolation pattern 122 and the second pixel isolation pattern 132 are shown, but the inventive concept is not limited thereto. The first pixel isolation pattern 122 and the second pixel isolation pattern 132 can be used to define, for example... Figure 1 Each pixel region (or pixel P) in the pixel array region R1 shown.

[0050] When viewed in a plan view, the first pixel isolation pattern 122 and the second pixel isolation pattern 132 may overlap each other. The bottom surface of the first pixel isolation pattern 122 may face the top surface of the second pixel isolation pattern 132. The bottom surface of the first pixel isolation pattern 122 and the top surface of the second pixel isolation pattern 132 may be adjacent to each other in a first direction D1. The first pixel isolation pattern 122 and the second pixel isolation pattern 132 may be disposed between pixel regions to prevent light incident on one of the pixel regions PX from entering a neighboring pixel region PX. In an embodiment, the pixel region may be defined by the first pixel isolation pattern 122 and the second pixel isolation pattern 132.

[0051] A first internal isolation pattern 124 and a second internal isolation pattern 134 may be disposed in each pixel region PX. The first internal isolation pattern 124 and the second internal isolation pattern 134 may be disposed between photoelectric conversion regions 110 to prevent light incident on one of the photoelectric conversion regions 110 from entering other photoelectric conversion regions 110. In an embodiment, the first internal isolation pattern 124 and the second internal isolation pattern 134 may define a photoelectric conversion region 110 in each pixel region PX. The photoelectric conversion regions 110 in each pixel region PX may be optically separated from each other by the first internal isolation pattern 124 and the second internal isolation pattern 134. The first internal isolation pattern 124 and the second internal isolation pattern 134 may electrically isolate each photoelectric conversion region 110 in each pixel region PX. The first internal isolation pattern 124 and the second internal isolation pattern 134 may overlap each other in a first direction D1. The bottom surface of the first internal isolation pattern 124 may face the top surface of the second internal isolation pattern 134. The bottom surface of the first internal isolation pattern 124 and the top surface of the second internal isolation pattern 134 may be adjacent to each other in the first direction D1.

[0052] The first internal isolation pattern 124 can be spaced apart from the first pixel isolation pattern 122, such as Figure 5A As shown. For example, the first inner isolation pattern 124 may be horizontally spaced from the first pixel isolation pattern 122. The second inner isolation pattern 134 may be connected to the second pixel isolation pattern 132, as shown. Figure 5BAs shown. For example, the second inner isolation pattern 134 can be connected to the inner sidewall of the second pixel isolation pattern 132. In an embodiment, the second inner isolation pattern 134 and the second pixel isolation pattern 132 can be configured as a single pattern. When viewed in a plan view, the first pixel isolation pattern 122 and the second pixel isolation pattern 132 can have a rectangular shape. The first inner isolation pattern 124 and the second inner isolation pattern 132 can be a cross-shaped structure having two portions extending in the second direction D2 and the third direction D3. The length of the first inner isolation pattern 124 in the second direction D2 and the third direction D3 can be less than the length of the second inner isolation pattern 134 in the second direction D2 and the third direction D3. In an embodiment, the second inner isolation pattern 134 can include a first pattern 134-1 extending in the second direction D2 and a second pattern 134-2 extending in the third direction D3. The first pattern 134-1 and the second pattern 134-2 can intersect each other. In an embodiment, the first pattern 134-1 of the second pixel isolation pattern 132, the second pattern 134-1 of the second internal isolation pattern 134, and the second pattern 134-2 of the second internal isolation pattern 134 can be arranged to divide the pixel region PX into a plurality of sub-pixel regions (e.g., four sub-pixel regions). Each of the plurality of photoelectric conversion regions 110 can be disposed in a corresponding sub-pixel region among the plurality of sub-pixel regions.

[0053] like Figure 6 As shown, the first isolation structure 120 may include a first gap-filling pattern 127 and a second gap-filling pattern 129, the second gap-filling pattern 129 being disposed between the first gap-filling pattern 127 and the semiconductor substrate 100. The refractive index of the first gap-filling pattern 127 may be different from the refractive index of the second gap-filling pattern 129. For example, the refractive index of the first gap-filling pattern 127 may be lower than the refractive index of the second gap-filling pattern 129. The first gap-filling pattern 127 may be formed of, for example, a conductive material or include at least one of, for example, conductive materials.

[0054] A barrier region 126 may be disposed in the semiconductor substrate 100 adjacent to the first isolation structure 120. The barrier region 126 may cover the side surface 120S and the bottom surface 120b of the first isolation structure 120. The barrier region 126 may contain a dopant having the same conductivity type as the semiconductor substrate 100 (e.g., a first conductivity type or P-type).

[0055] Refer again Figure 3 and Figures 4A to 4CA barrier region 126 can be formed on the side and bottom surfaces of the first pixel isolation pattern 122 and the first internal isolation pattern 124. Here, the concentration of a first conductivity type dopant in the barrier region 126 can be higher than the concentration of a first conductivity type dopant in the semiconductor substrate 100. The formation of the first isolation structure 120 may include patterning the semiconductor substrate 100 to form a deep trench, and the inner surface of the deep trench may have surface defects that generate electron-hole pairs (EHP). EHP can cause dark current problems. However, the barrier region 126 can suppress dark currents that can be caused by EHP.

[0056] A photoelectric conversion region 110 can be disposed in each pixel region PX. The photoelectric conversion region 110 can be arranged along a second direction D2 and a third direction D3 to form a matrix shape. The photoelectric conversion region 110 can generate photocharge. The amount of photocharge generated can be proportional to the intensity of the incident light. The photoelectric conversion region 110 can be formed by implanting an impurity having a different conductivity type (e.g., a second conductivity type) than the semiconductor substrate 100 into the semiconductor substrate 100. For example, the photoelectric conversion region 110 can be an impurity region containing an impurity of the second conductivity type. The junction between the semiconductor substrate 100 of the first conductivity type and the photoelectric conversion region 110 of the second conductivity type can act as a photodiode. The second conductivity type can be, for example, n-type.

[0057] In an embodiment, each photoelectric conversion region 110 may be configured to have a difference in impurity concentration between portions adjacent to the first surface 100a and the second surface 100b, thereby having a non-vanishing gradient in potential (e.g., between the first surface 100a and the second surface 100b of the semiconductor substrate 100). In an embodiment, the photoelectric conversion region 110 may include a plurality of impurity regions that are vertically stacked and have different impurity concentrations in a first direction D1.

[0058] In this embodiment, the bottom end of the photoelectric conversion region 110 may be located at a vertical level higher than the top surface 130t of the second isolation structure 130. For example, the photoelectric conversion region 110 may not be located at the same vertical level as the top surface 130t of the second isolation structure 130. Therefore, the portion of the semiconductor substrate 100 located at the same vertical level as the top surface 130t of the second isolation structure 130 may not be doped with impurities of the second conductivity type. The pixel region PX of the semiconductor substrate 100 may have a higher concentration of first conductivity type impurities than the concentration of second conductivity type impurities at the same vertical level as the top surface 130t of the second isolation structure 130.

[0059] The photoelectric conversion region 110 may include a first photoelectric conversion region 110a and a second photoelectric conversion region 110b. The second photoelectric conversion region 110b is spaced apart from the first photoelectric conversion region 110a by a first internal isolation pattern 124 disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. For example, the first photoelectric conversion region 110a may be disposed on a side surface of the first internal isolation pattern 124, and the second photoelectric conversion region 110b may be disposed on an opposite side surface of the first internal isolation pattern 124. In this specification, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may refer to two adjacent photoelectric conversion regions 110 in one of the second direction D2 and the third direction D3, rather than only two adjacent photoelectric conversion regions 110 in a pixel region PX in a specific direction.

[0060] like Figure 4C As shown, a connection region 112 can be formed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The connection region 112 may contain impurities of a second conductivity type. The connection region 112 connects the first photoelectric conversion region 110a to the second photoelectric conversion region 110b. For example, the second conductivity type impurities may be continuously distributed in the first photoelectric conversion region 110a, the connection region 112, and the second photoelectric conversion region 110b. In an embodiment, the connection region 112, and a portion of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, can be formed simultaneously using the same ion implantation process. Therefore, when measured at the same vertical level, the concentration of the second conductivity type impurities in the first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be equal to the concentration of the second conductivity type impurities in the connection region 112. The connection region 112 may be located vertically between the top surface 120t and the bottom surface 120b of the first isolation structure 120. For example, the connecting region 112 may be located vertically between the top and bottom surfaces of the first internal isolation pattern 124.

[0061] The connecting region 112 can be formed between the first internal isolation pattern 124 and the first pixel isolation pattern 122, such as Figure 4B As shown. Compared to the second surface 100b of the semiconductor substrate 100, the connection region 112 can be closer to the first surface 100a of the semiconductor substrate 100. When viewed in a plan view, the connection region 112 can overlap with the second isolation structure 130. For example, when viewed in a plan view, the connection region 112 can overlap with the second internal isolation pattern 134, but not with the second pixel isolation pattern 132. The bottom end of the connection region 112 can be located at a vertical level higher than the vertical level of the bottom ends of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0062] Device isolation layer 142 may be configured to be adjacent to a first surface 100a of semiconductor substrate 100. Device isolation layer 142 may define an active region in the portion of semiconductor substrate 100 adjacent to the first surface 100a, on which a gate structure TG and a logic transistor are disposed. Device isolation layer 142 may be formed in a trench that recesses from the first surface 100a of semiconductor substrate 100 toward a second surface 100b. Device isolation layer 142 may overlap with first isolation structure 120. For example, a portion of first isolation structure 120 may be formed in device isolation layer 142. The bottom surface of device isolation layer 142 may be closer to the first surface 100a of semiconductor substrate 100 than the bottom surface of first isolation structure 120. For example, device isolation layer 142 may have a depth less than that of first isolation structure 120.

[0063] The readout circuit layer 20 may be disposed on a first surface 100a of the semiconductor substrate 100. The readout circuit layer 20 may include readout circuitry (e.g., a MOS transistor) electrically connected to the photoelectric conversion region 110. In an embodiment, the readout circuit layer 20 may include a previously referenced... Figure 2 The described transistors are a reset transistor RX, a select transistor SX, and an amplification transistor AX. Additionally, the readout circuit layer 20 may include a connection line CL and a contact plug CT electrically connected to the MOS transistor.

[0064] In this embodiment, logic gate 104 and well-dump region 102 may be disposed on a first surface 100a of semiconductor substrate 100. Logic gate 104 and well-dump region 102 may be disposed on each pixel region PX. Logic gate 104 may include a reference. Figure 2 The gate electrodes of the reset transistor RX, amplifying transistor AX, and select transistor SX are described. A well impurity region 102 may be disposed on both sides of each logic gate 104. The well impurity region 102 may be formed adjacent to a first surface 100a of the semiconductor substrate 100. The well impurity region 102 may include impurities of a second conductivity type. The well impurity region 102 may serve as the source or drain of the reset transistor RX, amplifying transistor AX, and select transistor SX.

[0065] A gate structure TG can be disposed on the first surface 100a of the semiconductor substrate 100. Multiple gate structures TG can be disposed in each pixel region PX. When viewed in a plan view, the gate structure TG can be disposed in the central portion of each pixel region PX. Gate structures TG can be disposed on photoelectric conversion regions 110. One gate structure TG can be disposed on one photoelectric conversion region 110. For example, the number of gate structures TG in the pixel region PX can be the same as the number of photoelectric conversion regions 110. The gate structure TG may include a gate electrode GE, a gate insulating layer GI, and a gate spacer SP. The gate electrode GE can be disposed adjacent to the first surface 100a of the semiconductor substrate 100 and may include a portion extending below the first surface 100a. This portion of the gate electrode GE can be disposed within the semiconductor substrate 100, and the gate insulating layer GI can be inserted between the gate electrode GE and the semiconductor substrate 100. The side surface of the portion of the gate electrode GE disposed on the first surface 100a of the semiconductor substrate 100 can be covered by the gate spacer SP.

[0066] A floating diffusion region FD can be formed in the portion of the semiconductor substrate 100 surrounding the gate structure TG. The floating diffusion region FD can contain or be formed of a second conductivity type dopant. The floating diffusion region FD can be, for example, an n-type dopant region.

[0067] Interlayer insulating layers 212, 214, and 216 may be stacked on a first surface 100a of the semiconductor substrate 100, and in an embodiment, interlayer insulating layers 212, 214, and 216 may cover the logic transistors and gate structure TG constituting the readout circuit. Interlayer insulating layers 212, 214, and 216 may be formed of, for example, silicon oxide, silicon nitride, and / or silicon oxynitride, or include at least one of these. Connection lines CL may be disposed on each of the interlayer insulating layers 210 and may be electrically connected to the readout circuit via contact plugs CT.

[0068] The contact plug CT can be disposed in the interlayer insulating layers 212, 214, and 216. The contact plug CT can be coupled to the floating diffusion region FD, the source / drain impurity region, or the reset gate electrode RG, the amplified gate electrode AG, and the select gate electrode SG.

[0069] Each of the contact plug CT and the connecting line CL may include a barrier metal layer and a metal layer. For example, the barrier metal layer may be formed of or include at least one of a metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride). The metal layer may be formed of or include at least one of the following: tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal nitrides. In an embodiment, a silicide layer may be formed between the contact plug CT and the impurity region.

[0070] The optically transparent layer 30 may be disposed on the second surface 100b of the semiconductor substrate 100. The optically transparent layer 30 may include a buffer insulating layer 310, a color filter 320, and a microlens 330.

[0071] The buffer insulating layer 310 may cover the second surface 100b of the semiconductor substrate 100. The buffer insulating layer 310 may contact the second surface 100b of the semiconductor substrate 100 and the bottom surface 130b of the second isolation structure 130. Unless the context otherwise indicates, the term "contact" as used herein refers to direct contact (i.e., touching). The buffer insulating layer 310 may be formed of an insulating material with a refractive index different from that of the semiconductor substrate 100. For example, the buffer insulating layer 310 may be formed of or include an insulating material with a refractive index less than that of silicon. For example, the buffer insulating layer 310 may have a refractive index between about 1.4 and about 4.0. For example, the buffer insulating layer 310 may be formed of or include at least one of the following: Al2O3, CeF3, HfO2, ITO, MgO, Ta2O5, TiO2, ZrO2, Si, Ge, ZnSe, ZnS, or PbF2. The term "about" can reflect an amount, size, orientation, or layout that is changed only in a small relative manner and / or in a way that does not significantly alter the operation, function, or structure of certain elements. For example, a range from "about 0.1 to about 1" can encompass ranges such as a deviation of 0%-5% from about 0.1 and a deviation of 0%-5% from about 1, especially if such deviation maintains the same effect as the listed range. In embodiments, the buffer insulation layer 310 may be formed of or include at least one of organic materials with a high refractive index, such as silicone resins, benzocyclobutene (BCB), polyimide, acrylic acid, poly(p-xylene) C, polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), etc. In the embodiments, the buffer insulating layer 310 may be formed of, or include at least one of, strontium titanate (SrTiO3), polycarbonate, glass, bromine, sapphire, cubic zirconium oxide, potassium niobate (KNbO3), moissanite (SiC), gallium phosphide (III) (GaP), gallium arsenide (III) (GaAs).

[0072] Color filters 320 and microlenses 330 can be formed to overlap with pixel regions PX, respectively. Each color filter 320 can be configured to filter one of red, green, and blue colors, depending on the color of each unit pixel. Microlenses 330 have a convex shape and can have a predetermined radius of curvature. Each microlens 330 can be used to focus incident light onto a corresponding pixel region PX. Microlenses 330 can be formed of or comprise light-transparent resin.

[0073] In the following embodiments, for the sake of brevity, the previously described elements may be identified by the same reference numerals without repeating their redundant descriptions.

[0074] Figure 7 It is along Figure 3 The cross-sectional view taken along line A-A' illustrates an image sensor according to an embodiment of the concept of the present invention. Figure 8A and Figure 8B These are enlarged cross-sectional views, each cross-sectional view and... Figure 7 The part corresponding to "BB".

[0075] refer to Figure 7 , Figure 8A and Figure 8B The first isolation structure 120 and the second isolation structure 130 can be in contact with each other. For example, the first pixel isolation pattern 122 and the second pixel isolation pattern 132 can be in contact with each other, and the first internal isolation pattern 124 and the second internal isolation pattern 134 can be in contact with each other.

[0076] In an embodiment, such as Figure 8A As shown, the bottom surface 120b of the first isolation structure 120 can contact the top surface 130t of the second isolation structure 130. The width of the bottom surface 120b of the first isolation structure 120 can be greater than the width of the top surface 130t of the second isolation structure 130. The top surface 130t of the second isolation structure 130 can cover a portion of the bottom surface 120b of the first isolation structure 120. Another portion of the bottom surface 120b of the first isolation structure 120 can contact the barrier region 126. The barrier region 126 can be configured to cover the side surface of the first isolation structure 120 and partially cover the upper part of the side surface of the second isolation structure 130.

[0077] In an embodiment, such as Figure 8B As shown, the upper part of the second isolation structure 130 can be inserted into the first isolation structure 120. The top surface 130t of the second isolation structure 130 can be positioned at a vertical level that is higher than the bottom surface 120b of the first isolation structure 120.

[0078] Figure 9 It is along Figure 3A cross-sectional view taken along line C-C' illustrates an image sensor according to an embodiment of the present invention.

[0079] refer to Figure 9 The second pixel isolation pattern 132 and the second internal isolation pattern 134 of the second isolation structure 130 can be located at different heights. For example, the top surface 134t of the second internal isolation pattern 134 can be closer to the first surface 100a of the semiconductor substrate 100 than the top surface 132t of the second pixel isolation pattern 132. The second internal isolation pattern 134 can extend toward the connection region 112 that connects the photoelectric conversion regions 110 to each other.

[0080] Figure 10A and Figure 10B These are plan views of portions of an image sensor according to an embodiment of the concept of the present invention. Figures 11A to 11C They are respectively along Figure 10A The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0081] refer to Figures 10A to 11C The second internal isolation pattern 134 can be shifted from the center CTP of the pixel region PX toward the second pixel isolation pattern 132. For example, when with Figure 5B Compared to the previous structure, the second internal isolation pattern 134 can be shifted in the second direction D2 and the third direction D3. Conversely, the photoelectric conversion region 110 and the connection region 112 can remain unchanged. The structure of the pixel region PX according to this embodiment can be applied to... Figure 1 The pixel region PX of pixel P is located at the edge region ER of pixel P, but the inventive concept is not limited to this example.

[0082] In an embodiment, the second internal isolation pattern 134 may include a first portion P1 extending in the second direction D2 and a second portion P2 extending in the third direction D3 to intersect the first portion P1. The intersection point CSP of the first portion P1 and the second portion P2 may be spaced apart from the center CTP of the pixel region PX in both the second direction D2 and the third direction D3. Because the second internal isolation pattern 134 is shifted, it may partially overlap with the photoelectric conversion region 110. When viewed in a plan view, unlike what is described with reference to FIG4, the second internal isolation pattern 134 may not overlap with the connection region 112.

[0083] In this embodiment, the microlens 330 may be displaced together with the second internal isolation pattern 134. When viewed in a plan view, the center of the microlens 330 may be spaced apart from the center CTP of the pixel region PX. The microlens 330 may overlap with at least two adjacent pixel regions.

[0084] Figure 12This is a plan view illustrating an image sensor according to an embodiment of the concept of the present invention. Figure 13A and Figure 13B It is along Figure 12 The cross-sectional view taken by lines A-A' and B-B'.

[0085] refer to Figure 12 , Figure 13A and Figure 13B Each floating diffusion region FD can be set in a corresponding one within a pixel region PX. Multiple photodiodes in a pixel region PX can share a single floating diffusion region FD. The floating diffusion region FD can be located in the central region of the pixel region PX. When viewed in a plan view, the floating diffusion region FD can be configured to be adjacent to all gate electrodes GES located on the photoelectric conversion region 110.

[0086] In an embodiment, the first internal isolation pattern 124 may include first to fourth portions 124a, 124b, 124c, and 124d disposed near the floating diffusion region FD. The first portion 124a and the second portion 124b may be spaced apart from each other in a second direction D2, and the third portion 124c and the fourth portion 124d may be spaced apart from each other in a third direction D3. The floating diffusion region FD may be located between the first portion 124a and the second portion 124b, and between the third portion 124c and the fourth portion 124d. When viewed in a plan view, the floating diffusion region FD may overlap with the second internal isolation pattern 134 of the second isolation structure 130.

[0087] The gate structure TG can be used to transfer the charge generated in the photoelectric conversion region 110 to the floating diffusion region FD. A signal with a non-overlapping conduction period can be applied to the gate structure TG on each photoelectric conversion region 110. For example, the photodiodes in the pixel region PX can sequentially transfer charge to the floating diffusion region FD.

[0088] Figure 14 , Figure 16 , Figure 18 and Figure 21 This is a plan view illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. Figure 15 , Figure 17 , Figure 19 , Figure 20 and Figure 22 They are respectively along Figure 14 , Figure 16 , Figure 18 and Figure 21 The cross-sectional view taken along line A-A' illustrates a method for manufacturing an image sensor according to an embodiment of the present invention.

[0089] refer to Figure 14and Figure 15 A semiconductor substrate 100 of a first conductivity type (e.g., p-type) may be provided. The semiconductor substrate 100 may have a first surface 100a and a second surface 110b opposite to each other. The semiconductor substrate 100 may include a pixel region PX.

[0090] A first mask pattern MK1 may be formed on a first surface 100a of a semiconductor substrate 100 to expose a pixel region PX. The first mask pattern MK1 may include a plurality of first openings OP1, each first opening OP1 exposing a portion of the pixel region PX. Next, a lower doped region 110l may be formed in the pixel region PX. The lower doped region 110l may be formed by performing a first ion implantation process on the first surface 100a of the semiconductor substrate 100 using the first mask pattern MK1. The first ion implantation process may include implanting a second conductivity type impurity (e.g., n-type) into the first surface 100a of the semiconductor substrate 100. Impurities implanted into the semiconductor substrate 100 may be located at various depths depending on their kinetic energy. When impurities are accelerated with high energy, they may be implanted to a level close to the second surface 100b of the semiconductor substrate 100. In embodiments, the first ion implantation process may be performed using various energies to implant impurities to various depths.

[0091] The first mask pattern MK1 may include first openings OP1, each first opening OP1 exposing a portion of the pixel region PX, such as Figure 14 As shown. Therefore, multiple under-doped regions 110l can be formed in the pixel region PX.

[0092] refer to Figure 16 and Figure 17 A second mask pattern MK2 can be formed on the first surface 100a of the semiconductor chip 100. In an embodiment, the first mask pattern MK1 can be removed before forming the second mask pattern MK2. Unlike the first mask pattern MK1, the second mask pattern MK2 may include a second opening OP2 that exposes the pixel region PX.

[0093] Next, an upper doped region 110u and a connection region 112 can be formed in the pixel region PX. The upper doped region 110u and the connection region 112 can be formed by performing a second ion implantation process on the first surface 100a of the semiconductor substrate 100 using a second mask pattern MK2. The second ion implantation process may include implanting a second conductivity type (e.g., n-type) impurity into the semiconductor substrate 100 through the first surface 100a. In an embodiment, the second ion implantation process can be performed at a lower ion energy than in the first ion implantation process. Therefore, the upper doped region 110u and the connection region 112 can be formed closer to the first surface 100a of the semiconductor substrate 100 than the lower doped region 110l. The lower doped region 110l and the upper doped region 110u can be vertically connected to each other to form a photoelectric conversion region 110. The connection region 112 between the upper doped regions 110u can connect the photoelectric conversion regions 110 to each other. For example, the connection region 112 can connect two photoelectric conversion regions 110 spaced apart on a third direction D3. In this embodiment, no connecting region is provided between two photoelectric conversion regions 110 spaced apart from each other in the second direction D2. The inventive concept is not limited thereto. In this embodiment, a connecting region may also be formed between two adjacent photoelectric conversion regions in the second direction D2 to connect them to each other.

[0094] The doped region 110u and the connection region 112 can be formed simultaneously by a second ion implantation process. In an embodiment, when measured at the same vertical level, the doped region 110u and the connection region 112 can have the same concentration of impurities of the second conductivity type.

[0095] refer to Figure 18 and Figure 19 The first isolation structure 120 and the device isolation layer 142 may be formed in the semiconductor substrate 100. The first isolation structure 120 and the device isolation layer 142 may be adjacent to the first surface 100a of the semiconductor substrate 100. The device isolation layer 142 may be formed in a first trench TR1, which is disposed in the semiconductor substrate 100 and adjacent to the first surface 100a. The first isolation structure 120 may be formed in a second trench TR2, which overlaps with the first trench TR1 and is deeper than the first trench TR1.

[0096] The first trench TR1 and the second trench TR2 can be formed by anisotropically etching the semiconductor substrate 100 using a mask pattern as an etching mask. Since the semiconductor substrate 100 is anisotropically etched through the first surface 100a during the formation of the first trench TR1 and the second trench TR2, the widths of the first trench TR1 and the second trench TR2 can gradually decrease with increasing depth from the first surface 100a toward the second surface 100b. Therefore, the widths of the device isolation layer 142 and the first isolation structure 120, which respectively fill the first trench TR1 and the second trench TR2, can gradually decrease with increasing depth from the first surface 100a toward the second surface 100b.

[0097] A planarization process can be performed to remove a portion of the semiconductor substrate 100 or reduce the vertical thickness of the semiconductor substrate 100. As a result of the planarization process, the first isolation structure 120 and the device isolation layer 142 may have top surfaces that are coplanar with each other.

[0098] refer to Figure 20 The gate structure TG can be formed on the first surface 100a of the semiconductor substrate 100. Forming the gate structure TG may include: patterning the first surface 100a of the semiconductor substrate 100 to form a gate recess region; forming a gate insulating layer GI to conformally cover the inner surface of the gate recess region; forming a gate conductive layer to fill the gate recess region; patterning the gate conductive layer to form a gate electrode GE; and forming a gate isolator SP on the side surface of the gate electrode GE. In an embodiment, when the gate structure TG is formed, the gate electrode of the readout circuit can be formed together with the gate structure TG.

[0099] A floating diffusion region FD can be formed in the semiconductor substrate 100 and adjacent to the gate structure TG. The floating diffusion region FD can be formed by implanting a second conductivity type impurity into the semiconductor substrate 100. In an embodiment, when the floating diffusion region FD is formed, the source / drain regions of the logic transistor can be formed together with the floating diffusion region FD.

[0100] Next, interlayer insulating layers 212, 214, and 216 can be formed on the first surface 100a of the semiconductor substrate 100 to cover the gate structure TG and the logic transistor. At least one of the interlayer insulating layers 212, 214, and 216 can be formed of a material with good gap-filling properties and can have a flat-top surface. For example, at least one of the interlayer insulating layers can be formed of or include at least one of the following: high-density plasma (HDP) oxide, Tonen silazane (TOSZ), spin-coated glass (SOG), undoped quartz glass (USG), etc.

[0101] The contact plug CT and the connecting line CL can be formed in the interlayer insulating layers 212, 214, and 216, and the contact plug CT can be coupled to the floating diffusion region FD, and the connecting line CL can be connected to the contact plug CT. The contact plug CT and the connecting line CL can be formed of or include at least one of the following: copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), or alloys thereof.

[0102] Refer again Figure 21 and Figure 22 The second isolation structure 130 may be formed on the second surface 100b of the semiconductor substrate 100. A thinning process of the semiconductor substrate 100 may be performed prior to the formation of the second isolation structure 130. The thinning process may include grinding and / or polishing the second surface 100b of the semiconductor substrate 100, and anisotropically or isotropically etching the semiconductor substrate 100. The semiconductor substrate 100 may be inverted for the thinning process. A portion of the semiconductor substrate 100 may be removed by grinding or polishing processes.

[0103] Next, the second surface 100b of the semiconductor substrate 100 can be patterned to form a third trench TR3. When viewed in a plan view, the third trench TR3 can overlap with the first isolation structure 120. A second isolation structure 130 can be formed in the third trench TR3. The second isolation structure 130 can be formed to completely fill the third trench TR3. The formation of the third trench TR3 can include forming a mask pattern (not shown) on the second surface 100b of the semiconductor substrate 100 and using the mask pattern as an etching mask to anisotropically etch the semiconductor substrate 100. Since the semiconductor substrate 100 is anisotropically etched through the second surface 100b during the formation of the third trench TR3, the width of the third trench TR3 can gradually decrease with increasing depth from the second surface 100b of the semiconductor substrate 100 toward the first surface 100a of the conductor substrate 100. Therefore, the width of the second isolation structure 130 filling the third trench TR3 can also gradually decrease with increasing depth from the second surface 100b toward the first surface 100a.

[0104] Return to reference Figure 4A A buffer insulating layer 310, a color filter layer 220, and a microlens 230 can be formed on the second surface 100b of the semiconductor substrate 100.

[0105] According to embodiments of the present invention, an image sensor with improved electrical and optical properties can be provided.

[0106] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: A semiconductor substrate having a first surface and a second surface, the semiconductor substrate including a pixel region having a plurality of photoelectric conversion regions; A gate electrode is disposed on the pixel region and adjacent to the first surface; A first isolation structure extends from the first surface toward the second surface, the first isolation structure comprising: a first pixel isolation pattern surrounding the pixel region; and a first internal isolation pattern spaced apart from the first pixel isolation pattern and located between the plurality of photoelectric conversion regions; and A second isolation structure extends from the second surface toward the first surface, and the second isolation structure has a top surface that is vertically spaced apart from at least a portion of the bottom surface of the first isolation structure. Wherein, compared to the first surface of the semiconductor substrate, the bottom surface of the first isolation structure is closer to the second surface of the semiconductor substrate. The image sensor further includes: A barrier region is disposed in the semiconductor substrate to cover the side surface of the first isolation structure. The photoelectric conversion region includes impurities of a second conductivity type, and Wherein, the barrier region and the semiconductor substrate include impurities of a first conductivity type different from the second conductivity type, and the first concentration of the first conductivity type impurities in the barrier region is higher than the second concentration of the first conductivity type impurities in the semiconductor substrate.

2. The image sensor according to claim 1, in, The pixel region includes a connection region disposed between the first pixel isolation pattern and the first internal isolation pattern to connect two adjacent photoelectric conversion regions among the plurality of photoelectric conversion regions. The connection region includes impurities, and the impurities in the connection region have the same second conductivity type as the impurities in the photoelectric conversion region.

3. The image sensor according to claim 2, in, The connection area is located vertically and horizontally between the top and bottom surfaces of the first internal isolation pattern.

4. The image sensor according to claim 2, in, The connecting area vertically overlaps with the second isolation structure.

5. The image sensor according to claim 1, in, The first pixel isolation pattern and the second isolation structure are vertically spaced apart from each other.

6. The image sensor according to claim 1, in, The pixel region of the semiconductor substrate includes a first impurity of a first conductivity type. The photoelectric conversion region includes a second impurity of a second conductivity type different from the first conductivity type, and Wherein, when measured at the same vertical level from the second surface of the semiconductor substrate toward the first surface, the concentration of the first impurity in the pixel region is higher than the concentration of the second impurity.

7. The image sensor according to claim 1, in, The first isolation structure includes a first gap-filling pattern and a second gap-filling pattern, wherein the second gap-filling pattern is disposed between the first gap-filling pattern and the semiconductor substrate. The refractive index of the first gap-filling pattern is different from that of the second gap-filling pattern.

8. The image sensor according to claim 1, in, The second isolation structure includes a second pixel isolation pattern and a second inner isolation pattern, wherein the second pixel isolation pattern surrounds the pixel region and the second inner isolation pattern is connected to the second pixel isolation pattern and located in the pixel region.

9. The image sensor according to claim 8, in, The second internal isolation pattern includes a first pattern and a second pattern, wherein the first pattern extends parallel to the second surface and the second pattern is configured to intersect with the first pattern.

10. The image sensor according to claim 1, in, The width of the first isolation structure decreases in the direction toward the second surface, and The width of the second isolation structure decreases in the direction toward the first surface.

11. The image sensor according to claim 1, further comprising: The readout circuit layer is disposed on the first surface and includes a connection line electrically connected to the gate electrode; as well as Microlenses on the second surface.

12. An image sensor, comprising: Semiconductor substrate including impurities of the first conductivity type, The semiconductor substrate has a first surface and a second surface opposite to each other, and includes a plurality of pixel regions; A first pixel isolation pattern is disposed in the semiconductor substrate to electrically isolate a first pixel region, which is one of the plurality of pixel regions, from the other pixel regions in the plurality of pixel regions. A first photoelectric conversion region and a second photoelectric conversion region are disposed in the first pixel region, and include impurities of a second conductivity type different from the first conductivity type; A first internal isolation pattern is disposed between the first photoelectric conversion region and the second photoelectric conversion region, and is spaced apart from the first pixel isolation pattern; A connection region is disposed between the first pixel isolation pattern and the first internal isolation pattern to connect the first photoelectric conversion region and the second photoelectric conversion region to each other, the connection region including impurities of the second conductivity type; as well as A second internal isolation pattern is disposed in the first pixel region and extends from the second surface toward the connection region and is vertically spaced from the first surface. The image sensor further includes: A barrier region is disposed in the semiconductor substrate to cover the side surfaces of the first internal isolation pattern and the first pixel isolation pattern. The barrier region includes impurities of the first conductivity type, and the first concentration of the first conductivity type impurities in the barrier region is higher than the second concentration of the first conductivity type impurities in the semiconductor substrate.

13. The image sensor according to claim 12, in, The impurities of the second conductivity type in the connection region and the impurities of the second conductivity type in the second photoelectric conversion region have the same concentration at the same vertical level.

14. The image sensor according to claim 12, in, Compared to the second surface, the top surface of the second internal isolation pattern is closer to the first surface.

15. The image sensor according to claim 12, further comprising: The gate electrode is disposed adjacent to the first surface. The connection region is closer to the first surface than the second surface.

16. An image sensor, comprising: A semiconductor substrate including impurities of a first conductivity type, the semiconductor substrate including a pixel region and having a first surface and a second surface, the second surface being opposite to the first surface in the vertical direction; Multiple photoelectric conversion regions are disposed in the pixel region and include impurities of a second conductivity type different from the first conductivity type; A gate electrode is disposed on the photoelectric conversion region and is adjacent to the first surface; A first isolation structure extends from the first surface toward the second surface, the first isolation structure comprising: a first pixel isolation pattern surrounding the pixel region; and a first internal isolation pattern spaced apart from the first pixel isolation pattern and located between two adjacent photoelectric conversion regions in the plurality of photoelectric conversion regions; A second isolation structure extends from the second surface toward the first surface, the second isolation structure comprising: a second pixel isolation pattern surrounding the pixel region; and a second inner isolation pattern connected to the second pixel isolation pattern and located in the pixel region; A barrier region is disposed in the semiconductor substrate to cover the side surface of the first isolation structure and includes impurities of the first conductivity type; and A connection region, including impurities of the second conductivity type, is disposed between the first pixel isolation pattern and the first internal isolation pattern to connect two adjacent photoelectric conversion regions among the plurality of photoelectric conversion regions. Wherein, the first concentration of impurities of the first conductivity type in the barrier region is higher than the second concentration of impurities of the first conductivity type in the semiconductor substrate.

17. The image sensor according to claim 16, in, The length of the second internal isolation pattern in the vertical direction is different from the length of the second pixel isolation pattern in the vertical direction.

18. The image sensor according to claim 16, in, The first pixel isolation pattern and the second isolation structure are vertically spaced apart from each other.

19. The image sensor according to claim 16, in, The length of the first pixel isolation pattern in the vertical direction is greater than the length of the second pixel isolation pattern in the vertical direction.

Images