Dynamic allocation of computing resources for electronic design automation operations

Abstract

A system (100) may include a group of computing engines (101, 102, 103). The computing engines may be configured to perform electronic design automation (EDA) operations on a hierarchical data set (220) representing an integrated circuit (IC) design. The system (100) may also include a dynamic resource balancing engine (110) configured to: allocate computing resources to the group of computing engines; and reallocate specific computing resources allocated to the first computing engine based on an operation priority of an EDA operation performed by a second computing engine, an idle indicator (310, 330) for the first computing engine, or a combination of the two.

Description

Background Art

[0001] Electronic circuits, such as integrated microcircuits, are used in almost every aspect of modern society, from automobiles to microwave ovens to personal computers. The design of a microcircuit may involve a number of steps referred to as a "design flow". The specific steps of the design flow typically depend on the type of microcircuit being designed, its complexity, the design team, and the microcircuit manufacturer or foundry that will manufacture the microcircuit. Electronic design automation (EDA) applications support the design and verification of circuits before they are manufactured. EDA applications may include various functions, tools, or features for testing or verifying the design at various stages of the design flow, such as by executing software simulators and / or hardware simulators for error detection. Summary of the invention

[0002] The disclosed embodiments include systems, methods, devices, and logic that can support dynamic allocation of computing resources for EDA operations.

[0003] In one example, a method may be performed, carried out, or otherwise implemented by a computing system. The method may include allocating computing resources to a set of computing engines, each computing engine configured to perform EDA operations on a hierarchical dataset representing an integrated circuit (IC) design, and dynamically reallocating specific computing resources from a first computing engine to a second computing engine based on an operation priority of the EDA operation performed by the second computing engine, an idle indicator for the first computing engine, or a combination of both.

[0004] In another example, a system may include a group of computing engines, and each computing engine may be configured to perform EDA operations on a hierarchical data set representing an IC design. The system may also include a dynamic resource balancing engine, the dynamic resource balancing engine configured to: allocate computing resources to the group of computing engines; and reallocate specific computing resources allocated to a first computing engine based on an operation priority of an EDA operation performed by a second computing engine, an idle indicator for the first computing engine, or a combination of the two.

[0005] In yet another example, a non-transitory machine-readable medium may store processor-executable instructions that, when executed, may cause a system to: allocate computing resources to a set of computing engines, each computing engine configured to perform EDA operations on a hierarchical data set representing a circuit design, and dynamically reallocate specific computing resources from a first computing engine to a second computing engine based on an operation priority of the EDA operation performed by the second computing engine, an idle indicator for the first computing engine, or a combination of both. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Certain examples are described in the following detailed description and with reference to the following figures.

[0007] Figure 1 An example of a computing system that supports dynamic allocation of computing resources for EDA operations is shown.

[0008] Figure 2 An example of EDA operation-based resource reallocation by a dynamic resource balancing engine is shown.

[0009] Figure 3 An example of idleness-based resource reallocation by a dynamic resource balancing engine is shown.

[0010] Figure 4 An example of logic that a system may implement to support dynamic allocation of computing resources for EDA operations is shown.

[0011] Figure 5 An example of a system that supports dynamic allocation of computing resources for EDA operations is shown. DETAILED DESCRIPTION

[0012] The following disclosure relates to EDA applications and CAD systems that can be used to facilitate the design and manufacture of circuits. As technology improves, modern circuit designs may include billions and more components. In order to support the continued increase in circuit design complexity, EDA applications may include various features, such as high-order synthesis, schematic capture, transistor or logic simulation, field solvers, functional and physical verification, geometry processing, equivalence checking, design rule checking, mask data preparation, etc.

[0013] The execution of EDA applications and processes may require significant computing resources, and the computing environment may vary between different entities using EDA applications for circuit design and verification. The computing environment configured to execute EDA applications and processes may range from 16 CPUs to 10,000 CPUs or more. As circuit designs continue to increase in complexity, the computing requirements of EDA applications will also continue to increase. Therefore, improvements in the computing performance and capabilities of computing systems used to execute EDA applications will provide significant technical benefits.

[0014] The features described herein can support the dynamic allocation of computing resources for the execution of EDA operations. Specifically, the dynamic resource allocation features described herein (also referred to as dynamic resource balancing features) can provide specific criteria and mechanisms, by which computing resources can be dynamically distributed during the execution of EDA processes (EDA process) and basic EDA operations. The various dynamic load balancing features described herein can be specific to the EDA process for circuit design, and exemplary load balancing criteria include resource reallocation based on EDA operations and resource reallocation based on idle (e.g., at the execution tail of EDA operations). This dynamic resource balancing specific to EDA operations can improve the computing efficiency and computing effectiveness of EDA computing systems.

[0015] Figure 1 An example of a computing system 100 that supports dynamic allocation of computing resources for EDA operations is shown. The computing system 100 may include a single or multiple computing devices, such as an application server, a computing node, a data server, a desktop or laptop computer, a smart phone or other mobile device, a tablet device, an embedded controller, etc. The computing system 100 may have the ability to dynamically reallocate computing resources between different computing engines that perform EDA processes and operations on a circuit design, based on a particular EDA operation priority or execution state.

[0016] In conjunction with the various dynamic resource balancing features described herein, computing system 100 may implement, utilize, or otherwise support dynamic resource allocation, as described in U.S. Patent Application No. 15 / 873,827 (the '827 application), filed on January 17, 2018, and entitled "DYNAMICDISTRIBUTED RESOURCE MANAGEMENT," which is incorporated herein by reference in its entirety. Computing resources used and allocated by computing system 100 may be maintained and allocated according to the various dynamic allocation mechanisms described in the '827 application and according to the various criteria and resource balancing features described herein.

[0017] The computing system 100 may include various computing resources for performing EDA processes and operations. As an exemplary embodiment, Figure 1 The computing system 100 shown in FIG. 1 includes computing engines 101, 102, and 103. The computing engines 101, 102, and 103 may be used as separate entities (whether physical or logical) capable of performing EDA calculations for an EDA process (e.g., a design rule checking process or an optical proximity correction process).

[0018] Each compute engine may be implemented as a combination of hardware and software, and thus may include physical computing resources (e.g., CPU, memory, network resources, etc.) and processor-executable instructions (e.g., workflow processes, instruction scheduling logic, resource acquisition or thread activation instructions, etc.) to support EDA computations. In operation, the compute engines may operate in parallel, for example, each compute engine may act as a command server to perform EDA operations on a specific portion of an IC (integrated circuit) design or to perform specific groups of EDA operations to provide parallelism and operation-level concurrency in EDA process execution. For example, Figure 1 The computational engines 101, 102, and 103 shown in FIG. 1 may perform EDA operations on a hierarchical data set representing an IC design.

[0019] EDA applications can be executed in various types of computing environments, including computing environments that are entirely or partially cloud-computing. In this way, computing system 100 (including computing engines 101, 102, and 103) can be implemented in part via a public cloud, a private cloud, or a hybrid cloud. Additionally or alternatively, EDA applications can be executed (whether in whole or in part) via a software-as-a-service (SaaS) distribution model, and the computing resources comprising computing system 100 can be (e.g., with respect to EDA application users) external (off-premise), internal (on-premise), or a combination of the two. The various EDA features described herein can be implemented as part of a SaaS distribution model or via a cloud computing implementation.

[0020] As described in more detail herein, computing system 100 can dynamically balance computing resources assigned to different computing engines according to various balancing criteria. In doing so, computing system 100 can improve computing efficiency by reallocating computing resources (e.g., physical CPUs, memory, or any other computing resources used for operation execution) according to the priority of EDA operations, idle computing engines, or various other factors. This dynamic resource allocation and balancing can be performed by dynamic resource balancing engine 110, for example, Figure 1shown.

[0021] The computing system 100 can implement the dynamic resource balancing engine 110 (and its components) in a variety of ways (e.g., hardware and programming). The programming for the dynamic resource balancing engine 110 can take the form of processor-executable instructions stored on a non-transitory machine-readable storage medium, and the hardware for the dynamic resource balancing engine 110 can include a processor for executing these instructions. The processor can take the form of a single processor or a multi-processor system, and in some examples, the computing system 100 utilizes the same computing system features or hardware components (e.g., a common processor or common storage medium for the dynamic resource balancing engine 110 and computing engines 101, 102, and 103) to implement multiple engine components or system elements.

[0022] In operation, the dynamic resource balancing engine 110 may allocate computing resources to a group of computing engines, such as computing engines 101, 102, and 103. As used herein, computing resources may include any physical or logical resources used for the execution of EDA operations. Computing resources may therefore include physical CPUs (including remote resources), network adapters, I / O bandwidth, memory (physical or virtual), scheduling time slots for the use of specific computing elements, etc. In operation, the dynamic resource balancing engine 110 may also reallocate specific computing resources allocated to a first computing engine (e.g., computing engine 101) based on the operational priority of the EDA operation performed by a second computing engine (e.g., computing engine 102), an idle indicator for the first computing engine, or a combination of the two.

[0023] These and other dynamic resource balancing features are described in more detail below. Various balancing criteria specific to the execution of EDA applications are described, including reallocation of computing resources based on specific EDA operations or types of operations, idle-based reallocation (e.g., at the end of an EDA operation), and other approaches.

[0024] Figure 2 An example of resource reallocation based on EDA operations performed by the dynamic resource balancing engine 110 is shown. Figure 2 In the example shown in FIG. 1 , the computing system may perform EDA operations to perform various EDA operations on the circuit layout 210. The circuit layout 210 may be any representation of a circuit design such as an integrated circuit, a system-on-a-chip (SOC), a printed circuit board (PCB), etc. Such a computing system may support representations of the circuit layout 210 in a hierarchical format, such as as Figure 2 The hierarchical data set 220 is shown in FIG.

[0025] Hierarchical dataset 220 may take the form of any hierarchical representation of a circuit design (e.g., circuit layout 210). In this regard, hierarchical dataset 220 (which may be in the form of a hierarchical database) may include various hierarchies in the circuit representation to provide computational efficiency. The hierarchy in hierarchical dataset 220 may include a hierarchy of design elements (e.g., combining individual circuit structures into larger circuit structures), a hierarchy of the stacking order of individual layers in an integrated circuit, or a hierarchy in other hierarchical forms.

[0026] In some examples, hierarchical data set 220 may include various design cells that represent circuit layouts in a cell-based hierarchy. Hierarchical cells may encapsulate individual design structures (e.g., electrode contacts) that may be grouped to form other hierarchical cells (e.g., NAND gates) at higher hierarchical levels that may be further grouped into other hierarchical cells at other higher hierarchical levels. In this manner, hierarchical data set 220 may represent various design hierarchies in circuit layout 210. Such a hierarchical structure may support parallelism and operation-level concurrency for EDA application execution.

[0027] The dynamic resource balancing engine 110 may allocate computing resources for performing EDA operations on the hierarchical dataset 220 or a portion thereof delineated therefrom. In some examples, the dynamic resource balancing engine 110 identifies specific portions (e.g., specific layers or hierarchical units) of the hierarchical dataset 220 to be assigned to different computing engines for EDA computations. Additionally or alternatively, the dynamic resource balancing engine 110 may issue different EDA operations to different computing engines for execution on the hierarchical dataset 220 (or a selected portion thereof). Thus, the computing engine 101 may perform a first EDA operation on a portion of the hierarchical dataset 220 (e.g., perform a multi-patterning color operation on a metal 1 layer of the circuit layout 210), while the computing engine 102 may (simultaneously) perform a second EDA operation on a different portion of the hierarchical dataset 220 (e.g., perform a design rule checking operation on a metal 2 layer of the circuit layout 210).

[0028] The computational complexity of EDA operations may vary, and some EDA operations may use (e.g., consume) outputs generated from other EDA operations. That is, EDA operations may have different timing, computational, or dependency requirements. To address this difference in requirements and complexity, the dynamic resource balancing engine 110 may reallocate resources between computing engines to prioritize the execution of selected EDA operations. This reallocation of computing resources between computing engines used to execute EDA applications may be based on preconfigured or determined EDA operation priorities.

[0029] For illustration, upon instantiation of an EDA application, dynamic resource balancing engine 110 may allocate a fixed set of computing resources to computing engines 101, 102, and 103 for use in executing EDA operations assigned to each respective computing engine. At any point during execution of the EDA application, dynamic resource balancing engine 110 may reallocate computing resources allocated to a given computing engine to a different computing engine based on the operational priority of the EDA operations being executed by the given computing engine, by a different computing engine, or by both.

[0030] As a specific example, the dynamic resource balancing engine 110 can prioritize EDA operations in a critical execution path of an EDA process of an EDA application. Various EDA processes, such as layout-versus-schematic (LVS) verification, design rule check (DRC), design for manufacturing (DFM) processes, and optical proximity correction (OPC), etc., can be performed on the hierarchical data set 220. Each such EDA process may include a critical execution path of EDA operations, particularly a critical execution path of EDA operations when executed on the hierarchical data set 220. The critical execution path may represent a critical path for the execution time of executing the EDA process (e.g., a sequence of EDA operations in the EDA process with the longest execution time).

[0031] The dynamic resource balancing engine 110 can determine the critical execution path of a specific EDA process (e.g., LVS verification) through graph analysis in various EDA operations (which include a specific EDA process). For example, the dynamic resource balancing engine 110 can represent the EDA process as a graph, with each node representing an EDA operation on a different hierarchical portion of the circuit design, and the edges between the nodes representing input dependencies and including traversal (e.g., calculation) costs. Therefore, the dynamic resource balancing engine 110 can determine or otherwise identify the critical execution path for executing the EDA process.

[0032] During execution of the EDA process, the dynamic resource balancing engine 110 may provide additional computing resources to any one or more computing engines performing EDA operations in a critical execution path of the EDA process. To this end, the dynamic resource balancing engine 110 may identify specific computing engines performing EDA operations on a critical execution path (e.g., a critical execution path of the EDA process) and reallocate computing resources allocated to different computing engines performing EDA operations that are not on the critical execution path.

[0033] In some examples, the computing engine itself may provide an indication of the operational priority to the dynamic resource balancing engine 110. Figure 2 , compute engine 103 provides operation priority indicator 230 to dynamic resource balancing engine 110, which operation priority indicator may indicate that the EDA operation performed by compute engine 103 is on the critical execution path. In other examples (e.g., as described above), dynamic resource balancing engine 110 itself may determine the critical execution path and determine which compute engine or engines are performing EDA operations along the critical execution path.

[0034] In response to determining that compute engine 103 (in this example) is executing an EDA operation on a critical execution path, dynamic resource balancing engine 110 may reallocate computing resources from other compute engines to compute engine 103. Figure 3 In the example shown in , the dynamic resource balancing engine 110 sends a reallocation instruction 240 to the computing engine 102 , in response to which the computing engine 102 may release computing resources for acquisition / use by the computing engine 103 . Figure 2 Reallocated computing resources 250 are shown, which may be released by computing engine 102 and acquired by computing engine 103 in response to reallocation instructions 240 issued by dynamic resource balancing engine 110 .

[0035] In some embodiments, the dynamic resource balancing engine 110 can reallocate computing resources based on a specific EDA operation type. Since the computational complexity of EDA operations may be different, the dynamic resource balancing engine 110 can set a priority for EDA operations with higher computational complexity, latency, or timing requirements. Such operation priority can be indicated by an operation priority indicator message (e.g., as part of an operation priority indicator 230) sent from the computing engine, which can indicate the type of EDA operation that is set to a priority by the computing engine. The dynamic resource balancing engine 110 can issue a reallocation instruction 240 in response to receiving an operation priority indicator 230 from the computing engine 103, wherein the operation priority indicator 230 indicates a high priority EDA operation being performed by the computing engine 103.

[0036] EDA operation priorities may be specified, identified, or determined in various ways. In some examples, the dynamic resource balancing engine 110 maintains a priority list of EDA operation types, and such a priority list may be user-configurable or pre-configured. In other examples, the dynamic resource balancing engine 110 may implement or consult a specific load balancing criterion that may specify a specific EDA operation (or EDA operation type) and a corresponding resource reallocation action. As a specific exemplary EDA operation type, the dynamic resource balancing engine 110 may allocate additional computing resources to a computing engine that performs a fill operation, a multiple patterning operation, a high-performance compute (HPC) operation, or any other EDA operation that is otherwise identified as being computationally complex. On the other hand, the dynamic resource balancing engine 110 may, for example, release computing resources for EDA operations of lower computational complexity by reallocating a subset of computing resources allocated to a computing engine that performs a Boolean-based EDA operation or other EDA operation with lower complexity or with reduced computational requirements or dependencies.

[0037] In some instances, the dynamic resource balancing engine 110 can determine the priority of EDA operations based on the specific hierarchical level at which the EDA operations are operating. As an example, the dynamic resource balancing engine 110 can set different resource allocation priorities for various layers of the IC (integrated circuit) design. As a specific example, the dynamic resource balancing engine 110 can set the priority of the front-end alignment layer of the IC design to be higher than other layers, for example, by reallocating computing resources from another computing engine performing EDA operations on the metal 10 layer to a computing engine performing EDA operations on the metal 1 layer or the metal 2 layer. This hierarchical level-based priority and resource reallocation can be configured by a system administrator to allocate additional computing resources to hierarchical levels with specific physical characteristics (thicker IC layers with increased computing requirements, such as metal 1 layers and metal 2 layers) or to hierarchical levels that are computationally complex / resource intensive in terms of processing requirements.

[0038] As another example based on the priority of EDA operations, the dynamic resource balancing engine 110 can set priorities for EDA operations with reduced parallelization capabilities. In some embodiments, the computing engine can instantiate other computing engines used to perform sub-portions of the EDA operation. In this case, the computing engine can actually act as a command server to start an execution thread (for example, by acquiring local or remote computing resources) to process the EDA operation or part thereof. This instantiated computing engine can be referred to as a command computing engine. The computing engine instantiated by the command computing engine (which can be referred to as an instantiated computing engine) can operate on a selected data set assigned by the command computing engine. These instantiated computing engines can improve parallelism and support operation-level concurrency to more effectively perform EDA operations on the hierarchical data set 220 as a logically separated execution unit.

[0039] In some embodiments, the instantiated computing engine does not need to access or understand the different hierarchies of the data in the hierarchical data set 220, but instead performs EDA operations on a subset of the data provided by the command computing engine. However, some EDA operations may specifically require knowledge of the hierarchy or span multiple hierarchical layers, and therefore may not be suitable for independent execution by the instantiated computing engine. Such EDA operations may require access to the hierarchical data set 220, and may need to be performed by the command computing engine itself rather than by an instantiated pseudo computing engine. In this case, the dynamic resource balancing engine 110 can prioritize the execution of these level-related EDA operations by allocating additional computing resources to the command computing engine, for example, by extracting the additional computing resources from the computing resources allocated to the instantiated computing engine or other computing engines performing low-priority EDA operations.

[0040] As described above, the dynamic resource balancing engine 110 can dynamically change the computing resources allocated to different computing engines executing EDA applications. By utilizing operation-level concurrency and using balancing criteria based on operation priorities (whether explicitly set for specific operation types or based on critical execution paths), the dynamic resource balancing engine 110 can improve the EDA computing system to reduce execution time, improve operational efficiency, and reduce overall resource consumption. This dynamic resource balancing can reduce EDA application execution time by 10% or more, thereby improving the computing efficiency of the EDA computing system.

[0041] Although various individual balancing criteria are described above, the dynamic resource balancing engine 110 may utilize any of the described balancing criteria in combination. Additionally or alternatively, the dynamic resource balancing engine 110 may reallocate computing resources between various computing engines to efficiently use idle resources at various connections where EDA operations are performed, for example, as described below in Figure 3 Described in .

[0042] Figure 3 An example of idle-based resource reallocation by the dynamic resource balancing engine 110 is shown. Figure 3 , compute engines 101, 102, and 103 perform EDA operations on hierarchical dataset 220, which may provide a hierarchical representation of circuit layout 210. Specifically, dynamic resource balancing engine 110 may identify when various compute engines have idle (e.g., unused) compute resources, and reallocate any such idle compute resources accordingly.

[0043] The computing engine may include underutilized or idle computing resources at various points during the execution of EDA operations. These points may include the execution tail of the EDA process in the EDA application. For illustration, different computing engines (e.g., computing engines 101, 102, and 103) may be used as command computing engines, each of which is assigned to perform various EDA processes, and each EDA process may include an associated set of EDA operations. The command computing engine may instantiate other computing engines to help perform the EDA process, thereby improving parallelism and operation concurrency. When each command computing engine (and the computing engines instantiated separately) executes different EDA processes, the dynamic resource balancing engine 110 (or the command computing engine itself) may continuously reallocate resources when these computing engines complete the execution of the assigned EDA operations.

[0044] As the compute engine approaches completion of an EDA operation or EDA process (e.g., during the tail of execution), opportunities for parallelization may decrease because critical execution paths may require serial execution of EDA operations. Such EDA operations executed at the end of an EDA process may be referred to as the EDA operation tail, which will result in unused computing resources during the execution of the EDA operation. In some cases, the "tail" of EDA operation execution or the EDA operation tail may refer to the last 10% of execution time or the last 10% of an EDA instruction set, however other percentages or metrics may also be considered to measure the end of an EDA operation sequence.

[0045] Such a situation may occur when multiple command computing engines reach the tail of the execution of the EDA process, where the dynamic resource balancing engine 110 can reallocate idle computing resources to other computing engines to improve computing efficiency. In this regard, the dynamic resource balancing engine 110 can improve the overall utilization of computing resources in the computing environment (particularly during the "tail" of the execution of EDA operations).

[0046] In operation, the dynamic resource balancing engine 110 can identify idle or unused computing resources during the tail of the EDA operation in various ways. In some embodiments, the dynamic resource balancing engine 110 polls various computing engines of the computing system to determine resource utilization. This polling can occur at periodic or irregular (e.g., user-triggered) moments. As another example, the computing engine itself can communicate with an idle indicator to alert the dynamic resource balancing engine 110 to the idle computing resources of the computing engine.

[0047] An example of an idle indicator is shown in Figure 3 In Figure 3 In the embodiment of the present invention, computing engine 101 sends idle indicator 310 to dynamic resource balancing engine 110. Idle indicator 310 can take the form of any communication indicating that the computing engine has idle / unused computing resources. In some examples, idle indicator 310 can indicate a specific computing resource allocated to computing engine 101 that is not used or a utilization percentage of a specific computing resource allocated to computing engine 101 (e.g., 60% utilization, which would indicate that 40% of the allocated computing resources can be reallocated).

[0048] In response, the dynamic resource balancing engine 110 may send a reallocation instruction 320 to the computing engine 101, which Figure 3The computing engine 101 releases the computing resources that are subsequently acquired by the computing engine 102. In a similar manner, the computing engine 103 may send an idle indicator 330 to the dynamic resource balancing engine 110. In response to the idle indicator 330, the dynamic resource balancing engine 110 may issue a reallocation instruction 340 to the computing engine 103, so that the computing engine 103 may release the computing resources, which are subsequently acquired by the computing engine 102.

[0049] exist Figure 3 In the example shown in , when the EDA process executed by compute engines 101 and 103 is nearing completion or reaching completion, compute engines 101 and 103 may be at a point of execution that is part of the “tail” of the EDA operation. Dynamic resource balancing engine 110 may identify unused computing resources and reallocate them to other compute engines that have not yet reached the “tail” of the EDA operation, in this case compute engine 102. By doing so, dynamic resource balancing engine 110 may improve the efficiency of execution of the EDA application by providing increased computing power to compute engine 102, without reducing the computing efficiency of compute engines 101 and 103 (which may only require a subset of computing resources during execution of the tail of the EDA operation).

[0050] Although various resource balancing examples are described with respect to the EDA operation tail, the dynamic resource balancing engine 110 can also utilize any idle computing resources at any point in time to reallocate resources to the computing engine. By doing so, the dynamic resource balancing engine 110 can improve computing efficiency and increase resource utilization, which can improve the computing output and operation of the EDA system.

[0051] As described above, the dynamic resource balancing engine 110 can dynamically reallocate computing resources during the execution of the EDA application. In addition, the dynamic resource balancing engine 110 can support any of the described dynamic resource balancing features (e.g., reallocation based on EDA operations when computing resources are fully utilized) regardless of whether the computing engine has idle / unused computing resources. By flexibly supporting such resource reallocation-specific executions of EDA operations, the dynamic resource balancing engine 110 can provide various technical advantages described herein.

[0052] Figure 4An example of logic 400 is shown, which a system can implement to support dynamic allocation of computing resources for EDA operations. In some examples, computing system 100 can implement logic 400 as hardware, executable instructions stored on a machine-readable medium, or a combination of the two. Computing system 100 can implement logic 400 via dynamic resource balancing engine 110, for example, through which computing system 100 can implement or execute logic 400 as a method for supporting dynamic allocation of computing resources for EDA operations. The following description of logic 400 is provided using dynamic resource balancing engine 110 as an implementation example. However, various other implementation options of the system are also possible.

[0053] In implementation logic 400, dynamic resource balancing engine 110 may allocate computing resources to a group of computing engines, each of which is configured to perform EDA operations on a hierarchical data set representing a circuit design (402). Dynamic resource balancing engine 110 may also dynamically reallocate specific computing resources from a first computing engine to a second computing engine based on an operation priority of the EDA operation performed by the second computing engine, an idle indicator for the first computing engine, or a combination of both (404).

[0054] Although through Figure 4 An exemplary dynamic resource balancing feature is shown and described, but logic 400 may also include any number of additional or alternative steps. Logic 400 may additionally or alternatively implement any other dynamic resource balancing feature described herein, such as any other dynamic resource balancing feature with respect to dynamic resource balancing engine 110.

[0055] Figure 5 An example of a system 500 that supports dynamic allocation of computing resources for EDA operations is shown. System 500 may include processor 510, which may take the form of a single processor or multiple processors. One or more processors 510 may include a central processing unit (CPU), a microprocessor, or any hardware device suitable for executing instructions stored on a machine-readable medium. System 500 may include machine-readable medium 520. Machine-readable medium 520 may take the form of any non-transitory electronic, magnetic, optical, or other physical storage device that stores executable instructions, such as a Figure 5 Thus, the machine-readable medium 520 may be, for example, a random access memory (RAM) such as a dynamic random access memory (DRAM), a flash memory, a spin transfer torque memory, an electrically erasable programmable read-only memory (EEPROM), a storage drive, an optical disk, or the like.

[0056] System 500 may execute instructions stored on machine-readable medium 520 via processor 510. Execution of the instructions may cause system 500 to perform any dynamic resource balancing features described herein, including any features according to dynamic resource balancing engine 110.

[0057] For example, dynamic resource balancing instructions 522 executed by processor 510 may cause system 500 to: allocate computing resources to a group of computing engines, each computing engine being configured to perform EDA operations on a hierarchical data set representing a circuit design; and dynamically reallocate specific computing resources from the first computing engine to the second computing engine based on an operation priority of the EDA operation performed by the second computing engine, an idle indicator for the first computing engine, or a combination of both.

[0058] The systems, methods, devices, and logic described above, including computing engines 101, 102, and 103 and dynamic resource balancing engine 110, can be implemented in many different ways in a variety of different combinations of hardware, logic, circuits, and executable instructions stored on machine-readable media. For example, computing engines 101, 102, and 103, dynamic resource balancing engine 110, or a combination thereof may include circuits in a controller, microprocessor, or application-specific integrated circuit (ASIC), or may be implemented with discrete logic or components, or may be implemented with a combination of other types of analog or digital circuits combined on a single integrated circuit or distributed among multiple integrated circuits. A product, such as a computer program product, may include a storage medium and machine-readable instructions stored on the medium, which, when executed in an endpoint, computer system, or other device, cause the device to perform operations according to any of the above descriptions (including according to any features of computing engines 101, 102, and 103, dynamic resource balancing engine 110, or a combination of the two).

[0059] The processing capabilities of the systems, devices, and engines described herein (including the systems of computing engines 101, 102, and 103 and the dynamic resource balancing engine 110) can be distributed among multiple system components, such as between multiple processors and memories, optionally including multiple distributed processing systems or cloud / network elements. Parameters, databases, and other data structures can be stored and managed separately, can be merged into a single memory or database, can be logically and physically organized in many different ways, and can be implemented in a variety of ways including data structures (e.g., linked lists), hash tables, or implicit storage mechanisms. Programs can be part of a single program (e.g., a subroutine), separate programs, programs distributed across multiple memories and processors, or implemented in a variety of different ways (e.g., libraries (e.g., shared libraries)).

[0060] Although various examples have been described above, many more implementations are possible.

Claims

1. A method for supporting dynamic allocation of computing resources for EDA operations, comprising: By calculating system(100,500): Allocating computing resources to a set of computing engines (101, 102, 103), each computing engine (101, 102, 103) being configured to perform electronic design automation (EDA) operations on a hierarchical data set (220) representing an integrated circuit design; as well as dynamically reallocating specific computing resources from the first computing engine to the second computing engine based on an operational priority of an EDA operation performed by the second computing engine, an idle indicator (310, 330) for the first computing engine, or a combination of both; Wherein dynamically reallocating the specific computing resource based on the idle indicator (310, 330) for the first computing engine comprises: identifying that the EDA process being executed by the first computing engine has reached an end of EDA operations that require serial execution of specific EDA operations of the EDA process; as well as The particular computing resource is identified as an idle resource not used by the first computing engine during a tail portion of the EDA operation of the EDA process, wherein the particular EDA operation of the EDA process is performed serially during the tail portion of the EDA operation.

2. The method according to claim 1, wherein: Dynamically reallocating the specific computing resources based on the operation priority of the EDA operation includes: A determination is made that the EDA operation performed by the second computing engine is on a critical execution path of an EDA process, and in response, the particular computing resource is reallocated to the second computing engine.

3. The method according to claim 1, wherein: Dynamically reallocating the specific computing resources based on the operation priority of the EDA operation includes: determining an operation type of the EDA operation performed by the second computing engine; and In response to determining that the operation type of the EDA operation is a fill operation or a multi-patterning operation, the specific computing resource is reallocated to the second computing engine.

4. The method according to claim 1, wherein: Dynamically reallocating the specific computing resources based on the operation priority of the EDA operation includes: determining a circuit layer on which the EDA operation performed by the second computing engine operates; and In response to determining that the circuit layer is a metal 1 layer or a metal 2 layer, the specific computing resource is reallocated to the second computing engine.

5. A system (100) supporting dynamic allocation of computing resources for EDA operations, comprising: a set of computing engines (101, 102, 103), each computing engine configured to perform electronic design automation (EDA) operations on a hierarchical data set (220) representing an integrated circuit IC design; and A dynamic resource balancing engine (110) configured to: Allocating computing resources to the set of computing engines (101, 102, 103); and reallocating specific computing resources allocated to the first computing engine based on an operation priority of an EDA operation performed by a second computing engine, an idle indicator (310, 330) for the first computing engine, or a combination of both; The dynamic resource balancing engine (110) is configured to dynamically reallocate the specific computing resource based on the idle indicator (310, 330) for the first computing engine by the following steps: identifying that the EDA process being executed by the first computing engine has reached an end of EDA operations that require serial execution of specific EDA operations of the EDA process; as well as The particular computing resource is identified as an idle resource not used by the first computing engine during a tail portion of the EDA operation of the EDA process, wherein the particular EDA operation of the EDA process is performed serially during the tail portion of the EDA operation.

6. The system (100) according to claim 5, wherein: The dynamic resource balancing engine (110) is configured to dynamically reallocate the specific computing resources based on the operation priority of the EDA operation by: A determination is made that the EDA operation performed by the second computing engine is on a critical execution path of an EDA process, and in response, the particular computing resource is reallocated to the second computing engine.

7. The system (100) according to claim 5, wherein: The dynamic resource balancing engine (110) is configured to dynamically reallocate the specific computing resources based on the operation priority of the EDA operation by: determining an operation type of the EDA operation performed by the second computing engine; as well as In response to determining that the operation type of the EDA operation is a fill operation or a multi-patterning operation, the specific computing resource is reallocated to a second computing engine.

8. The system (100) of claim 5, wherein: The dynamic resource balancing engine (110) is configured to dynamically reallocate the specific computing resources based on the operation priority of the EDA operation by: determining a circuit layer operated by the EDA operation performed by the second computing engine; as well as In response to determining that the circuit layer is a metal 1 layer or a metal 2 layer, the specific computing resource is reallocated to the second computing engine.

9. A non-transitory machine-readable medium (520) comprising instructions (522) which, when executed by a processor (510), cause a system (500) to: Allocating computing resources to a set of computing engines (101, 102, 103), each computing engine being configured to perform electronic design automation (EDA) operations on a hierarchical data set (220) representing a circuit design; as well as dynamically reallocating specific computing resources from the first computing engine to the second computing engine based on an operational priority of an EDA operation performed by the second computing engine, an idle indicator (310, 330) for the first computing engine, or a combination of both; The instructions for dynamically reallocating the specific computing resource based on the idle indicator (310, 330) for the first computing engine include instructions that, when executed by the processor (510), cause the system (500) to: identifying that the EDA process being executed by the first computing engine has reached an end of EDA operations that require serial execution of specific EDA operations of the EDA process; as well as The particular computing resource is identified as an idle resource not used by the first computing engine during a tail portion of the EDA operation of the EDA process, wherein the particular EDA operation of the EDA process is performed serially during the tail portion of the EDA operation.

10. The non-transitory machine-readable medium (520) of claim 9, wherein: The instructions to dynamically reallocate the specific computing resources based on the operational priority of the EDA operations include instructions that, when executed by the processor (510), cause the system (500) to: A determination is made that the EDA operation performed by the second computing engine is on a critical execution path of an EDA process, and in response, the particular computing resource is reallocated to the second computing engine.

11. The non-transitory machine-readable medium (520) of claim 9, wherein: The instructions to dynamically reallocate the specific computing resources based on the operational priority of the EDA operations include instructions that, when executed by the processor (510), cause the system (500) to: determining an operation type of the EDA operation performed by the second computing engine; as well as In response to determining that the operation type of the EDA operation is a fill operation or a multi-patterning operation, the specific computing resource is reallocated to the second computing engine.

12. The non-transitory machine-readable medium (520) of claim 9, wherein: The instructions to dynamically reallocate the specific computing resources based on the operational priority of the EDA operations include instructions that, when executed by the processor (510), cause the system (500) to: determining a circuit layer operated by the EDA operation performed by the second computing engine; as well as In response to determining that the circuit layer is a metal 1 layer or a metal 2 layer, the specific computing resource is reallocated to the second computing engine.

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