Data processing apparatus and device

Abstract

The application provides a data processing device and equipment. The data processing device comprises a plurality of input buses, an enqueuing management module, a queue management module and a cache module. The plurality of input buses are connected with input ends of the enqueuing management module. Output ends of the enqueuing management module are connected with input ends of the cache module. Management ends of the cache module are connected with input ends of the queue management module. The cache module comprises a plurality of cache areas. The plurality of cache areas are linked list cache areas. Each cache area is provided with an idle pointer pool. The queue management module comprises a plurality of data queues. The plurality of data queues are queues realized by linked lists. The plurality of data queues share the plurality of cache areas. Each cache area corresponds to at least one data queue. Each data queue corresponds to one cache area. The line head blocking problem is avoided. The data processing efficiency is improved. On the basis of saving the cache, flexible small-granularity channel selection scheduling is realized.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a data processing device and equipment. Background Technology

[0002] In network processing engines, there's a constant need to improve performance metrics, but limitations imposed by chip area, resources, and manufacturing processes prevent unlimited increases in clock speed or simply piling on resources to meet performance demands. Therefore, system design often employs parallel buses to enhance performance. This can be understood as breaking down the entire system into smaller parts, utilizing multiple pipelines to work simultaneously and improve chip efficiency. This design approach also reduces implementation complexity. However, a challenge this presents is the increased number of internal data buses. The number of internal buses and interface buses is often mismatched because they typically operate at different frequencies and follow different protocols. Bridging internal and external interfaces results in many-to-many bus crossovers.

[0003] Currently, bridging between the input bus and the output bus can be achieved using a crossbar.

[0004] However, the above method has two problems. First, there is a problem of line blockage. That is, if the data slices that come in earlier have not yet been output, the data slices that come in later, even if they can be output, still need to wait, which leads to low data processing efficiency. Second, the path selection is not flexible enough. Summary of the Invention

[0005] This application provides a data processing apparatus and device to solve the technical problems of low data processing efficiency and insufficient flexibility in path selection in current data processing devices.

[0006] This application provides a data processing apparatus, including:

[0007] The system includes multiple input buses, an enqueue management module, a queue management module, and a cache module. The input buses are all connected to the input of the enqueue management module, the output of the enqueue management module is connected to the input of the cache module, and the management terminal of the cache module is connected to the input of the queue management module. The cache module includes multiple cache areas, which are linked list cache areas, each with a free pointer pool. The queue management module includes multiple data queues, all implemented using linked lists. Each node in a data queue includes a data slice and the address of the next hop of that data slice. The multiple data queues share the multiple cache areas, each cache area corresponds to at least one data queue, and each data queue corresponds to one cache area.

[0008] The queuing management module is used to determine the first target buffer corresponding to the target input bus that receives the target data slice; wherein, the target data slice includes the identifier of the first target data queue to which the target data slice belongs, and the input bus corresponds one-to-one with the buffer;

[0009] The caching module is used to determine a target free pointer based on the target free pointer pool of the first target cache area, and store the target data slice in the target free pointer;

[0010] The queue management module is used to update the tail pointer of the first target data queue to the target free pointer, and to update the address of the next hop of the tail node before the target data slice is enqueued to the target free pointer.

[0011] This application provides a data processing device, including any of the data processing apparatuses described in this application.

[0012] Further details regarding the above embodiments and other aspects of this application, as well as their implementations, are provided in the accompanying drawings, detailed description, and claims. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the structure of a data processing apparatus provided in one embodiment;

[0014] Figure 2 A schematic diagram of another data processing apparatus provided in one embodiment;

[0015] Figure 3 This is a schematic diagram of the structure of a queue management module provided in one embodiment. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0017] In current crossbar-based network processing engines, data slices entering from the same input bus can form a queue, waiting for output. Due to the first-in, first-out (FIFO) queue mechanism, the data slice at the front of the queue is processed first. Meanwhile, the output buffers for data slices later in the queue may be idle, but because they haven't received a time slice, they cannot be output. This results in low data processing efficiency and inflexible path selection.

[0018] To enable the network processing engine to adapt to more application scenarios, the various modules of the chip core need to be flexibly bridged to achieve different business processing requirements, such as inner-layer packet parsing, traffic shaping, and table lookup frequency requirements. This requires flexible path selection within the chip.

[0019] This application provides a data processing apparatus that improves upon the aforementioned crossbar method, aiming to solve the technical problems of low data processing efficiency and insufficient flexibility in path selection in current data processing devices.

[0020] Figure 1 This is a schematic diagram of the structure of a data processing apparatus provided in one embodiment. Figure 1 As shown, the data processing device provided in this embodiment includes: multiple input buses, an enqueue management module 11, a queue management module 13, and a cache module 12.

[0021] Multiple input buses are connected to the input terminals of the enqueue management module 11, and the output terminal of the enqueue management module 11 is connected to the input terminal of the buffer module 12. The management terminal of the buffer module 12 is connected to the input terminal of the queue management module 13.

[0022] The cache module 12 includes multiple cache areas. Each input bus corresponds to one cache area. Each cache area has a free pointer pool. The queue management module 13 includes multiple data queues, which share multiple cache areas. Each cache area corresponds to at least one data queue, and each data queue corresponds to one cache area.

[0023] The queuing management module 11 is used to determine the first target buffer corresponding to the target input bus that receives the target data slice. The target data slice includes the identifier of the first target data queue to which it belongs.

[0024] The cache module 12 is used to determine the target free pointer based on the target free pointer pool of the first target cache area, and store the target data slice in the target free pointer.

[0025] The queue management module 13 is used to update the tail pointer of the first target data queue to the target free pointer.

[0026] In one embodiment, the data processing apparatus in this application may be a network processing engine.

[0027] In the data processing device of this embodiment, each input bus corresponds to a buffer, and each buffer corresponds to at least one data queue. That is, each input bus corresponds to at least one data queue. Each data queue corresponds to one buffer, meaning that data slices in the same data queue are stored in the same buffer. In other words, data slices from different input buses cannot enter the same data queue.

[0028] In this embodiment, data slices input from a certain input bus are stored in a designated data queue in the buffer corresponding to that input bus. The designated data queue is determined based on the identifier of the data queue carried in the data slice. Compared to storing all data slices input from a certain input bus in the same queue, the data processing device in this embodiment effectively distributes data input from the same input bus into different data queues. Therefore, the head-of-queue data slices in these different data queues can be processed within one clock cycle, avoiding line-end blocking problems and improving data processing efficiency.

[0029] In this embodiment, a data slice refers to data of a preset length after a complete data packet has been divided. A data packet can be divided into at least one data slice.

[0030] In one embodiment, the number of buffers can be greater than or equal to the number of input buses to ensure that data slices for each clock cycle on the input buses can be stored in the buffers.

[0031] like Figure 1 As shown, the depth of the P buffers depends on the product of the maximum number of data queues Q and the maximum amount of data that can be cached in each data queue.

[0032] The following describes in detail the execution process of the data processing device in this embodiment receiving and storing data.

[0033] When the target input bus receives a target data slice, the queuing management module 11 determines the first target buffer corresponding to the target input bus.

[0034] In the first implementation, the queuing management module 11 specifically determines the first target buffer corresponding to the target input bus based on the pre-determined mapping relationship between the input bus and the buffer.

[0035] In the second implementation, the device further includes multiple selectors configured in the queuing management module 11. Each selector corresponds one-to-one with a buffer. In this implementation, the queuing management module 11 further determines the first target buffer corresponding to the target input bus that receives the target data slice based on the mapping relationship between the input bus and the buffer sent by the control device, and controls the selector corresponding to the first target buffer to connect the target input bus and the first target buffer.

[0036] In this implementation, because a selector is set up, it can select one input bus from N input buses. Therefore, the correspondence between the input bus and the buffer can be flexibly configured through the control device, which expands the application scenarios of the data processing device.

[0037] In one embodiment, the identifier of the first target data queue included in the target data slice is used to indicate the target logical port on the target input bus. In other words, data slices in the same data queue in this embodiment are data slices of the same logical port on the same input bus. In this embodiment, the total number of data queues needs to be greater than or equal to the total number of virtual ports. This embodiment can place data slices of the same logical port on the same input bus in the same queue, realizing flexible path selection scheduling at the virtual port granularity.

[0038] The cache module 12 determines the target free pointer for storing the target data slice from the target free pointer pool of the first target cache area, and stores the target data slice in the target free pointer.

[0039] Since the target data slice belongs to the first target data queue, after storing the target data slice in the target free pointer, the tail pointer of the first target data queue needs to be updated.

[0040] The queue management module 13 updates the tail pointer of the first target data queue to the target free pointer that stores the target data slice.

[0041] The following concrete example illustrates the above process. In a given clock cycle, suppose a data slice is input from input bus 0. This data slice carries the identifier of data queue 1. Input bus 0 corresponds to buffer 0. The enqueue management module 11 determines that the buffer corresponding to input bus 0 is buffer 0. The buffer module 12 determines a free pointer from the free pointer pool of buffer 0 and stores the data slice in that free pointer. The queue management module 13 updates the tail pointer of data queue 1 to this free pointer. In the next clock cycle, suppose another data slice is input from input bus 0. This data slice carries the identifier of data queue 2. The enqueue management module 11 determines that the buffer corresponding to input bus 0 is buffer 0. The buffer module 12 determines another free pointer from the free pointer pool of buffer 0 and stores the data slice in that free pointer. The queue management module 13 updates the tail pointer of data queue 2 to this free pointer. This achieves the distribution of data input from the same input bus across different data queues.

[0042] In one embodiment, multiple buffer areas are linked list buffer areas. Multiple data queues are all queues implemented using linked lists. Each node in a data queue includes a data slice and the address of the next hop for that data slice. That is, the first target data queue is a queue implemented using linked lists. Each node in the first target data queue includes a data slice and the address of the next hop for that data slice. In this embodiment, in addition to updating the tail pointer, the queue management module 13 also needs to update the address of the next hop of the tail node before the target data slice is enqueued to the target free pointer to ensure the linked list is not interrupted. Implementing queues using linked lists allows for the storage of data slices using non-contiguous addresses in the buffer area, improving buffer utilization. Furthermore, compared to simple linked list scheduling, this embodiment, due to the presence of multiple queues, enables flexible routing.

[0043] In one embodiment, it is also necessary to identify the correspondence between the data queue and the buffer in the data queue. If the first target data queue is empty when the target data slice enters the first target data queue, the queue management module 13 is also used to identify the correspondence between the first target data queue and the first target buffer in the first target data queue. This is so that after the data queue issues a dequeue request, the data slice can be quickly retrieved from the buffer corresponding to the data queue, thereby improving dequeue efficiency.

[0044] The data processing apparatus provided in this embodiment includes: multiple input buses, an enqueue management module, a queue management module, and a cache module. The multiple input buses are all connected to the input terminals of the enqueue management module, the output terminal of the enqueue management module is connected to the input terminal of the cache module, and the management terminal of the cache module is connected to the input terminal of the queue management module. The cache module includes multiple cache areas, which are linked list cache areas, and each cache area has a free pointer pool. The queue management module includes multiple data queues, which are all queues implemented using linked lists. Each node of a data queue includes a data slice and the address of the next hop of the data slice. The multiple data queues share multiple cache areas, and each cache... Each buffer area corresponds to at least one data queue, and each data queue corresponds to one buffer area. The enqueue management module is used to determine the first target buffer area corresponding to the target input bus to which the target data slice is received. The target data slice includes the identifier of the first target data queue to which the target data slice belongs. The input bus and the buffer area correspond one-to-one. The buffer module is used to determine the target free pointer according to the target free pointer pool of the first target buffer area and store the target data slice in the target free pointer. The queue management module is used to update the tail pointer of the first target data queue to the target free pointer, and to update the address of the next hop of the tail node before the target data slice is enqueued to the target free pointer. It has the following technical effects: First, since the data input from the same input bus is distributed in different data queues, the head data slices in these different data queues can all be processed in one clock cycle. On the one hand, it avoids the line head blocking problem and improves data processing efficiency; on the other hand, it realizes flexible small-granular path selection scheduling. Second, multiple buffer areas are linked list buffer areas and the data queues are implemented using linked lists, saving buffer space. Compared with simple linked list scheduling, it also has the advantage of flexible path selection.

[0045] Figure 2 This is a schematic diagram of another data processing apparatus provided in one embodiment. The data processing apparatus provided in this embodiment... Figure 1 Based on the illustrated embodiment and various optional solutions, dequeue processing of data slices can also be implemented. This embodiment will provide a detailed description of the specific process of dequeue processing. Figure 2 As shown, the data processing device also includes: multiple output buses, a scheduler management module 15, and a dequeue management module 14.

[0046] The input terminal of the scheduler management module 15 is connected to the output terminal of the queue management module 13. The output terminal of the scheduler management module 15 is connected to the first input terminal of the dequeue management module 14. The output terminal of the buffer module 12 is connected to the second input terminal of the dequeue management module 14, and the output terminal of the dequeue management module 14 is connected to multiple output buses. The scheduler management module 15 includes multiple schedulers. Each scheduler corresponds to one output bus. Figure 3 As shown, the number of schedulers and output buses is M.

[0047] The scheduler management module 15 is used to determine the target scheduler corresponding to the second target data queue when a dequeue request is received from the second target data queue.

[0048] The target scheduler determines whether to authorize the dequeueing of the head data slice of the second target data queue based on a preset authorization policy.

[0049] The dequeue management module 14 is used to read the first data slice of the second target data queue from the second target buffer corresponding to the second target data queue when the target scheduler authorizes the dequeue of the first data slice of the second target data queue, and output the first data slice of the second target data queue from the output bus corresponding to the target scheduler.

[0050] In one implementation, when the second target data queue is not empty, the second target data queue can send a dequeue request to the scheduler management module.

[0051] In another implementation, the queue management module 13 also includes multiple packet-length queues. Figure 3 This is a schematic diagram of the structure of a queue management module provided in one embodiment. Figure 3 As shown, there is a one-to-one correspondence between the data queue and the packet-length queue. The packet-length queue can also be a queue implemented using a linked list.

[0052] In this implementation, the caching module 12 is further configured to determine the data volume of the target data packet when it is determined that the target data slice includes the end-of-line character of the target data packet to which the target data slice belongs, and store the data volume in the target free pointer. The queue management module 13 is further configured to update the tail pointer of the packet length queue corresponding to the first target data queue to the target free pointer, and update the address of the next hop of the tail node of the packet length queue corresponding to the first target data queue before the data volume is enqueued to the target free pointer.

[0053] In this implementation, when the second target data queue determines that its corresponding packet length queue is not empty, it sends a dequeue request to the scheduler management module 15.

[0054] In this implementation, when segmenting data packets, the first data slice of the packet carries the packet's start symbol, and the last data slice carries the packet's end symbol. The number of nodes in each packet length queue represents the number of data packets formed by the data slices in the data queue corresponding to that packet length queue.

[0055] Setting up a packet length queue allows for the management of packet length information for data packets belonging to a data slice. This facilitates the determination of whether to authorize a dequeue request from a second target data queue based on the authorization policy and the packet length queue, thereby improving the efficiency of the authorization determination process.

[0056] In another implementation, when the second target data queue determines that it meets the preset dequeue rules, it sends a dequeue request to the scheduler management module 15.

[0057] When the scheduler management module 15 receives a dequeue request from the second target data queue, it determines the target scheduler corresponding to the second target data queue.

[0058] It should be noted that the relationship between data queues and schedulers can be one-to-one, multiple data queues to one scheduler, or one data queue to multiple schedulers. This can be flexibly configured according to actual needs. For example, assuming there are 128 data queues and 8 schedulers, the data queues can be divided into 8 groups of 16 data queues each. These 8 groups of data queues are then connected to the 8 schedulers.

[0059] The preset authorization strategy in this embodiment may include any one or a combination of the following strategies: whole packet scheduling requirements, queue service category priority, 802.3BR protocol, scheduling slots for Media Access Control (MAC) or Flexible Ethernet technology, token bucket shaping, etc. Different schedulers can be decoupled, and different output buses can be independently scheduled without interference. Alternatively, different schedulers may be coupled; in this case, the coupling relationship is determined by the required scheduling relationship between the output buses, and can be a priority relationship, a slot scheduling relationship, or a shaping relationship.

[0060] When the dequeue management module 14 determines that the target scheduler has authorized the dequeue of the head data slice of the second target data queue, it reads the head data slice of the second target data queue from the second target buffer corresponding to the second target data queue and outputs the head data slice of the second target data queue from the output bus corresponding to the target scheduler.

[0061] In one embodiment, if a data queue corresponds to multiple schedulers, the scheduler management module 15 may determine that there are multiple target schedulers corresponding to the second target data queue, and at least two of these target schedulers authorize the dequeueing of the head data slice of the second target data queue. In this embodiment, the caching module 12 is used to select one target scheduler from the at least two target schedulers that authorize the dequeueing of the head data slice of the second target data queue as the final target scheduler.

[0062] Correspondingly, in terms of outputting the head data slice of the second target data queue from the output bus corresponding to the target scheduler, the dequeue management module 14 is specifically used to output the head data slice of the second target data queue from the output bus corresponding to the final target scheduler.

[0063] In this embodiment, the caching module 12 can select one target scheduler from at least two target schedulers dequeued from the head data slice of the authorized second target data queue as the final target scheduler based on the principle of fair round-robin, so as to achieve load balancing.

[0064] In this embodiment, the cache module 12 can reverse select the final target scheduler, further improving the flexibility of data processing.

[0065] In one embodiment, after the head data slice of the second target data queue is output from the output bus corresponding to the target scheduler, the queue management module 13 is further used to update the head pointer of the second target data queue to the address of the next data slice of the head data slice.

[0066] Cache module 12 is also used to reclaim the address of the head data slice into the free pointer pool of the second target cache.

[0067] In one embodiment, the second target data queue is a queue implemented using a linked list. Each node in the second target data queue includes a data slice and the address of the next hop of the data slice.

[0068] The data processing device provided in this embodiment can be designed according to the following steps.

[0069] Step 1: Determine the number of input buses. The required number of input buses can be determined based on the internal module interfaces to meet the internal system design requirements.

[0070] Step 2: Determine the number of output buses. Based on the number of interfaces on the panel side, determine how many sets of output buses are needed to meet performance and user access requirements.

[0071] Step 3: Determine the number of data queues that the device needs to provide.

[0072] Step 4: When a data slice from each input bus enters the device, it enters the designated queue according to the identifier of the data queue it carries, and waits for scheduling. Data slices from different input buses cannot enter the same data queue.

[0073] Step 5: Each output bus corresponds to a scheduler. Customizable scheduling strategies allow data queues to be attached to the scheduler corresponding to the desired output bus based on the configuration. Fine-grained configuration is possible here, with each data queue individually configured with its corresponding output bus.

[0074] Based on the above steps, a data processing device can be constructed that satisfies the requirements of arbitrary mapping for multiple inputs and multiple outputs, and also enables arbitrary mapping of logic ports within the bus. This data device achieves flexible bridging between input and output buses, as well as flexible mapping between multiple virtual channels. It can bridge any number of input buses with any number of output buses and share any number of data queues, allowing any queue on any internal bus to be mapped to any queue on the output bus. Furthermore, it enables flexible scheduling of the data flow.

[0075] The data processing apparatus provided in this embodiment further includes: multiple output buses, a scheduler management module, and a dequeue management module. The input end of the scheduler management module is connected to the output end of the queue management module, the output end of the scheduler management module is connected to the first input end of the dequeue management module, the output end of the buffer module is connected to the second input end of the dequeue management module, and the output end of the dequeue management module is connected to multiple output buses. The scheduler management module includes multiple schedulers, each corresponding to one of the output buses. When the scheduler management module receives a dequeue request from a second target data queue, it determines the target scheduler corresponding to the second target data queue. The target scheduler determines whether to authorize the dequeue of the head data slice of the second target data queue according to a preset authorization policy. When the dequeue management module determines that the target scheduler authorizes the dequeue of the head data slice of the second target data queue, it reads the head data slice of the second target data queue from the second target buffer corresponding to the second target data queue and outputs the head data slice of the second target data queue from the output bus corresponding to the target scheduler. It has the following technical effects: Since the data input from the same input bus is distributed in different data queues, multiple data queues can issue dequeue requests in one clock cycle, increasing the number of data slices that can be dequeued in each clock cycle. While saving buffer, it further avoids the line head blocking problem, realizes flexible scheduling of data flow, and improves the throughput of data processing device.

[0076] This embodiment also provides a data processing device, which includes the data processing apparatus provided in any of the above embodiments and optional implementations. Its implementation process and technical principles are similar and will not be repeated here.

[0077] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0078] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0079] Embodiments of this application can be implemented by executing computer program instructions through a data processor of a data processing device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0080] Any block diagram of logical flow in the accompanying drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored in memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Multifunction Discs, DVDs, or CDs), etc. Computer-readable media may include non-transitory storage media. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (FGPAs), and processors based on multi-core processor architectures.

[0081] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of this application. Therefore, the proper scope of this application will be determined by the claims.

Claims

1. A data processing apparatus, characterized by, The device comprises: a plurality of input buses, an enqueuing management module, a queue management module and a cache module, the plurality of input buses are connected with the input end of the enqueuing management module, the output end of the enqueuing management module is connected with the input end of the cache module, the management end of the cache module is connected with the input end of the queue management module; the cache module comprises a plurality of cache areas, the plurality of cache areas are linked list cache areas, each cache area is provided with a free pointer pool; the queue management module comprises a plurality of data queues, the plurality of data queues are queues realized by using linked lists, each node of the data queue comprises a data slice and the address of the next hop of the data slice, the plurality of data queues share the plurality of cache areas, each cache area corresponds to at least one data queue, and each data queue corresponds to a cache area; the enqueuing management module is used for determining a first target cache area corresponding to a target input bus receiving a target data slice; wherein the target data slice comprises the identifier of a first target data queue to which the target data slice belongs, and the input bus is in one-to-one correspondence with the cache area; the cache module is used for determining a target free pointer according to the target free pointer pool of the first target cache area, and storing the target data slice in the target free pointer; the queue management module is used for updating the tail pointer of the first target data queue to the target free pointer, and updating the address of the next hop of the tail node before the target data slice is enqueued to the target free pointer.

2. The apparatus of claim 1, wherein, The device further comprises a plurality of output buses, a scheduler management module and a dequeuing management module, the input end of the scheduler management module is connected with the output end of the queue management module, the output end of the scheduler management module is connected with the first input end of the dequeuing management module, the output end of the cache module is connected with the second input end of the dequeuing management module, and the output end of the dequeuing management module is connected with the plurality of output buses; the scheduler management module comprises a plurality of schedulers, and the scheduler is in one-to-one correspondence with the output bus; the scheduler management module is used for determining a target scheduler corresponding to a second target data queue when receiving the dequeuing request of the second target data queue; the target scheduler determines whether to authorize the head data slice of the second target data queue to be dequeued according to a preset authorization strategy; the dequeuing management module is used for reading the head data slice of the second target data queue from a second target cache area corresponding to the second target data queue and outputting the head data slice of the second target data queue from an output bus corresponding to the target scheduler when it is determined that the target scheduler authorizes the head data slice of the second target data queue to be dequeued.

3. The apparatus of claim 2, wherein, After the head data slice of the second target data queue is output from the output bus corresponding to the target scheduler, the queue management module is further used for updating the head pointer of the second target data queue to the address of the next data slice of the head data slice. The cache module is further configured to recycle the address of the head data slice into the free pointer pool of the second target cache area.

4. The apparatus of claim 2 or 3, wherein, The queue management module further comprises a plurality of packet length queues, the data queue corresponding to the packet length queue one by one; the packet length queue is a queue realized by using a linked list, each node of the packet length queue comprising a packet length and an address of a next hop of the packet length; The cache module is further configured to, when it is determined that the target data slice comprises an end symbol of a target data packet to which the target data slice belongs, determine a data amount of the target data packet and store the data amount in the target free pointer; The queue management module is further configured to update a tail pointer of the packet length queue corresponding to the first target data queue to the target free pointer, and update an address of a next hop of a tail node of the packet length queue corresponding to the first target data queue before the data amount is enqueued to the target free pointer.

5. The apparatus of claim 4, wherein, When the second target data queue determines that the packet length queue corresponding to the second target data queue is not empty, the dequeue management module sends the dequeue request to the scheduler management module.

6. The device of any one of claims 1-3, wherein, If the first target data queue is empty when the target data slice enters the first target data queue, the queue management module is further configured to identify the correspondence between the first target data queue and the first target cache area in the first target data queue.

7. The device of any one of claims 1-3, wherein, The enqueue management module is specifically configured to determine, according to a predetermined mapping relationship between an input bus and a cache area, a first target cache area corresponding to a target input bus on which a target data slice is received.

8. The device of any one of claims 1-3, wherein, The enqueue management module further comprises a plurality of selectors, the selector corresponding to the cache area one by one; Each selector is connected to the plurality of input buses; The enqueue management module is further specifically configured to determine, according to the mapping relationship between the input bus and the cache area sent by the control device, the first target cache area corresponding to the target input bus on which the target data slice is received, and control the selector corresponding to the first target cache area to communicate the target input bus and the first target cache area.

9. The device of any one of claims 1-3, wherein, The identifier of the first target data queue is used to indicate a target logical port on the target input bus.

10. The apparatus of claim 2 or 3, wherein, When the target scheduler is a plurality of target schedulers, and at least two of the plurality of target schedulers authorize the head data slice of the second target data queue to be dequeued, the cache module is configured to select one target scheduler from the at least two target schedulers that authorize the head data slice of the second target data queue to be dequeued as a final target scheduler; In terms of outputting the head data slice of the second target data queue from an output bus corresponding to the target scheduler, the dequeue management module is specifically configured to output the head data slice of the second target data queue from an output bus corresponding to the final target scheduler.

11. A data processing device, characterized by The data processing device of any one of claims 1-10. The data processing device of any one of claims 1-10.

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