Method for forming a semiconductor device

Abstract

A method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls are opposite each other. The method also includes depositing a first dielectric material on a top of the opening at a first deposition rate, and depositing a second dielectric material on the first dielectric material and on the first and second sidewalls at a second deposition rate. The second dielectric material and the first and second sidewalls trap a pocket of gas. The method also includes performing a processing procedure on the second dielectric material.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to methods for forming semiconductor devices. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each having greater functionality and smaller feature sizes than the previous generation. In the course of IC development, functionality (e.g., the number of interconnected devices per chip area) generally has increased, and geometry size (e.g., the smallest component or line that can be produced using a manufacturing process) has decreased. This scaling down process generally has SUMMARY

[0003] Embodiments of the present invention provide a method for forming a semiconductor device, comprising: forming an opening between first and second sidewalls of respective first and second terminals, wherein the first and second sidewalls are opposite to each other; depositing a first dielectric material on top of the opening at a first deposition rate; depositing a second dielectric material on the first dielectric material and on the first and second sidewalls at a second deposition rate, wherein the second dielectric material and the first and second sidewalls trap an air pocket; and performing a processing on the second dielectric material.

[0004] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a gate structure and a source / drain (S / D) contact on a substrate; depositing a first dielectric material, wherein: a first portion of the first dielectric material is on top of a sidewall of the gate structure; and a second portion of the first dielectric material is on top of a sidewall of the S / D contact; depositing a second dielectric material, wherein: a first portion of the second dielectric material is on the first portion of the first dielectric material and on the sidewall of the gate structure; and a second portion of the second dielectric material is on the second portion of the first dielectric material and on the sidewall of the S / D contact, wherein the deposition of the second dielectric material is continued until the first and second portions of the second dielectric material contact each other; and performing an oxygen processing on the deposited second dielectric material.

[0005] Yet another embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming an opening above a top surface of a substrate and between a first terminal and a second terminal of a semiconductor device; depositing a first dielectric material, wherein: a first portion of the first dielectric material is on a top portion of a sidewall of the first terminal; and a second portion of the first dielectric material is on a top portion of a sidewall of the second terminal; depositing a second dielectric material, wherein: a first portion of the second dielectric material is on the first portion of the first dielectric material; and a second portion of the second dielectric material is on the second portion of the first dielectric material, wherein a pocket of gas is trapped in the opening surrounded by the second dielectric material, the first terminal and the second terminal, and the substrate; and performing an oxygen treatment process on the deposited second dielectric material. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the present invention can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that, for the sake of relative clarity, not every component of the embodiments can be shown to scale in the drawings. In fact, the dimensions of the various components can be arbitrarily increased or decreased for clarity of presentation and discussion.

[0007] Figure 1 is an isometric view of a semiconductor structure according to some embodiments.

[0008] Figures 2 to 6 is a cross-sectional view of a semiconductor structure as various portions are formed according to some embodiments.

[0009] Figure 7 is a flowchart of a method of forming a bilayer seal structure in a semiconductor structure according to some embodiments.

[0010] Figure 8 shows chemical reactions that occur during the formation of a bilayer seal structure in a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific embodiments or examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and second component are in direct contact forming, and can also include embodiments where additional components can be formed between the first component and second component such that the first component and second component can not be in direct contact. Furthermore, the present application can be repeated with reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0012] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0013] As used herein, the term "nominal" refers to a desired or target value for a characteristic or parameter of an assembly or process operation, as well as values above and / or below the desired value, set during the design phase of a product or process. The range of values is typically due to minor variations in manufacturing processes or tolerances.

[0014] The terms "about" and "substantially" as used herein indicate a value for a given quantity that can vary based on the particular technical node associated with the subject semiconductor device. In some embodiments, based on the particular technical node, the terms "about" and "substantially" can indicate a value for a given quantity that varies by, for example, 5% of a target value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the target value).

[0015] The fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a pitch that is less than is obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0016] As planar semiconductor devices such as metal oxide semiconductor field effect transistors ("MOSFETs") are scaled down through various technology nodes, other methods of increasing device density and speed have been proposed. One method is the fin field effect transistor ("finFET") device, which is a three-dimensional FET including the formation of a fin-shaped channel extending from a substrate. FinFETs are compatible with conventional complementary metal oxide semiconductor (CMOS) processes, and their three-dimensional structure allows them to be scaled substantially while maintaining gate control and mitigating short channel effects. Gate stacks are used in both planar and three-dimensional FETs for controlling the conductivity of the semiconductor device. A gate stack including a gate dielectric layer and a gate electrode for a finFET device can be formed by replacing a gate process in which a polysilicon sacrificial gate structure is replaced by a metal gate structure. A gate dielectric layer such as a high-k dielectric layer (e.g., a dielectric layer having a dielectric constant greater than about 3.9) is formed between the channel and the gate electrode. Spacers can be disposed on the sidewalls of the gate stack to protect the gate structure during fabrication processes such as ion implantation, gate replacement processes, epitaxial source / drain structure formation, and other suitable processes. Air gaps can be used in place of the spacers to lower the effective dielectric constant, which in turn can reduce parasitic capacitance and improve device performance. The air gaps can be formed by depositing a sealing material over an opening between terminals of the semiconductor device such that an air pocket is trapped between the terminals. Because the dielectric constant of air is generally lower than dielectric materials, the effective dielectric constant can be reduced. However, gaps in the sealing material can cause defects in the semiconductor device. For example, the fabrication processes used to form the air gap structure typically involve multiple etching and cleaning processes that can etch through portions of the sealing material through the gaps and cause damage to the air gap, such as causing collapse of the sealing material or trapping chemical solutions within the air gap. Damaged air gap structures can cause defects in the semiconductor device and result in low device yield, or even device failure.

[0017] To address the aforementioned drawbacks, the present invention provides a semiconductor device and a method for manufacturing the same, providing a simple and cost-effective structure and process for generating a seamless sealing layer in the semiconductor device. The seamless sealing layer can be used to seal openings and form air gaps between terminals of the semiconductor device. Specifically, a double-layer sealing material can be formed by depositing a first sealing material, depositing a second sealing material, and performing at least one processing step on the deposited first and second sealing materials. The first and second sealing materials can be dielectric materials. In some embodiments, silicon carbide (SiCO) can be used to form the first and second sealing materials. The first sealing material is deposited on portions of opposite sidewalls facing the top of the opening, and the second sealing material is deposited on the first sealing material and on exposed surfaces in the opening. The second sealing material is deposited on the first sealing material on the opposite sidewalls. The deposition process of the second sealing material continues at least until the second sealing material from the opposite sidewalls merges to form a closed space between the opposite sidewalls. Processing steps can be performed on the deposited first and second sealing materials such that gaps are removed by expansion of at least the second sealing material. In some embodiments, the processing step can be an annealing process performed in an oxygen-saturated environment. In some embodiments, the first sealing material can be deposited at a higher deposition rate than the second sealing material. In some embodiments, precursors such as tetramethyldisiloxane (TMDSO), hydrogen, oxygen, and any other suitable precursors can be used to form the first and second sealing materials. The sealing material is formed by depositing a double-layer sealing material (such as silicon carbide) and subsequently processing the deposited double-layer sealing material, which prevents damage to the underlying structures, such as oxidation of the metal source / drain structures.

[0018] Figure 1 This is an isometric view of an exemplary fin field-effect transistor (finFET) structure. Figures 2 to 7 Various exemplary semiconductor structures and manufacturing processes according to some embodiments are provided, illustrating the formation of multi-spacer structures with air gaps and sealing materials. The manufacturing processes provided herein are exemplary, and alternative processes according to the invention can be performed (although not shown in these figures).

[0019] Figure 1 This is an isometric view of a finFET according to some embodiments. The finFET 100 may be included in a microprocessor, memory cell, or other integrated circuit. Figure 1 The view of FinFET 100 shown is for illustrative purposes and may not be drawn to scale. FinFET 100 may include other suitable structures, such as additional spacers, padding layers, contact structures, and any other suitable structures, for clarity shown in [the image / description]. Figure 1 Not shown in the image.

[0020] The finFET 100 can be formed on a substrate 102 and can include a fin structure 104 having a fin region 121 and S / D regions 106, gate structures 108 disposed on the fin structure 104, spacers 110 disposed on opposite sides of each gate structure 108, and a shallow trench isolation (STI) region 112. Figure 1 Five gate structures 108 are shown. However, based on the disclosure herein, the finFET 100 can have more or fewer gate structures. Moreover, the finFET 100 can be incorporated into an integrated circuit by using other structural components such as S / D contact structures, gate contact structures, conductive vias, conductive lines, dielectric layers, and passivation layers, which are omitted herein for clarity.

[0021] The substrate 102 can be a semiconductor material such as silicon. In some embodiments, the substrate 102 includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 102 includes (i) elemental semiconductors such as germanium; (ii) compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) alloy semiconductors including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, indium gallium phosphide, indium gallium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide; or (iv) combinations thereof. Moreover, the substrate 102 can be doped (e.g., a p-type substrate or an n-type substrate) according to design requirements. In some embodiments, the substrate 102 can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic).

[0022] The fin structure 104 represents a current carrying structure of the finFET 100 and can traverse along the Y-axis and through the gate structures 108. The fin structure 104 can include (i) portions of the fin region 121 under the gate structures 108 and (ii) the S / D regions 106 disposed on the portions of the fin region 121, formed on opposite sides of each gate structure 108. The portions of the fin region 121 of the fin structure 104 under the gate structures 108 (not shown in FIG. 1) can extend above the STI region 112 and can be wrapped by a respective one of the gate structures 108. The fin region 121 on opposite sides of the gate structure 108 can be etched back so that the S / D regions 106 can be epitaxially grown on the etched back portions of the fin region 121. Figure 1 The fin structure 104 represents a current carrying structure of the finFET 100 and can traverse along the Y-axis and through the gate structures 108. The fin structure 104 can include (i) portions of the fin region 121 under the gate structures 108 and (ii) the S / D regions 106 disposed on the portions of the fin region 121, formed on opposite sides of each gate structure 108. The portions of the fin region 121 of the fin structure 104 under the gate structures 108 (not shown in FIG. 1) can extend above the STI region 112 and can be wrapped by a respective one of the gate structures 108. The fin region 121 on opposite sides of the gate structure 108 can be etched back so that the S / D regions 106 can be epitaxially grown on the etched back portions of the fin region 121.

[0023] The fin region 121 of the fin structure 104 can comprise a similar material as the substrate 102. The S / D region 106 can comprise an epitaxially grown semiconductor material. In some embodiments, the epitaxially grown semiconductor material is the same material as the substrate 102. In some embodiments, the epitaxially grown semiconductor material comprises a different material than the substrate 102. The epitaxially grown semiconductor material can comprise: (i) a semiconductor material such as germanium and silicon; (ii) a compound semiconductor material such as gallium arsenide and aluminum gallium arsenide; or (iii) a semiconductor alloy such as silicon germanium and phosphorous gallium arsenide. Other materials for the fin structure 104 are within the scope of the present disclosure.

[0024] In some embodiments, the S / D region 106 can be grown by: (i) chemical vapor deposition (CVD) (such as by low pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or a suitable CVD process); (ii) a molecular beam epitaxy (MBE) process; (iii) a suitable epitaxial process; and (iv) combinations thereof. In some embodiments, the S / D region 106 can be grown by an epitaxial deposition / partial etch process that repeats the epitaxial deposition / partial etch process at least once. Such a repeated deposition / partial etch process is also referred to as a “cyclic deposition etch (CDE) process.” In some embodiments, the S / D region 106 can be grown by selective epitaxial growth (SEG), in which an etch gas is added to promote selective growth of the semiconductor material on exposed surfaces of the fin structure, but not on insulating materials (e.g., the dielectric material of the STI region 112). Other methods of epitaxially growing the S / D region 106 are within the scope of the present disclosure.

[0025] The S / D region 106 can be a p-type region or an n-type region. In some embodiments, the p-type S / D region 106 can comprise SiGe and can be in-situ doped with p-type dopant such as boron, indium, and gallium during epitaxial growth. For p-type in-situ doping, p-type dopant precursors such as diborane (B2H6), boron trifluoride (BF3), and other p-type dopant precursors can be used. In some embodiments, the n-type S / D region 106 can comprise Si and can be in-situ doped with n-type dopant such as phosphorous and arsenic during the epitaxial growth process. For n-type in-situ doping, n-type dopant precursors such as phosphine (PH3), arsine (AsH3), and other n-type dopant precursors can be used. In some embodiments, the S / D region 106 is not in-situ doped and an ion implantation process is performed to dope the S / D region 106.

[0026] The spacers 110 can include a spacer portion 110a formed on the sidewalls of the gate structures 108 and in contact with the dielectric layer 118, a spacer portion 110b formed on the sidewalls of the fin structures 104, and a spacer portion 110c formed as a protective layer on the STI region 106. Each spacer portion can also be a multi-spacer structure including more than one spacer structure. For example, the spacer portion 110a can include more than one spacer and an air gap formed between the gate structures 108 and the fin structures 104. A sealing material can be formed over the air gap to enclose and protect the air gap from subsequent manufacturing processes. For simplicity, the air gap and the sealing material are not shown in Figure 1 The spacers 110 can include an insulating material such as silicon oxide, silicon nitride, low-k materials, and combinations thereof. The spacers 110 can have a low-k material with a dielectric constant less than 3.9 (e.g., less than 3.5, 3, and 2.8). Since the air gap can have a dielectric constant of about 1, the effective dielectric constant of the spacers 110 can be further reduced compared to spacers formed using low-k materials. The low-k material for the spacers 110 can be formed using a suitable deposition process such as atomic layer deposition (ALD). In some embodiments, the spacers 110 can be deposited using CVD, LPCVD, UHVCVD, RPCVD, physical vapor deposition (PVD), any other suitable deposition process, and combinations thereof. The sealing material can be formed by depositing a first sealing material on top of the openings formed between the gate structures 108 and the S / D regions 106, and subsequently depositing a second sealing material on the first sealing material to form an enclosure with air trapped in the openings. Other materials and thicknesses of the spacers 110 and the sealing material are within the scope of the present disclosure.

[0027] Each gate structure 108 can include a gate electrode 116, a dielectric layer 118 adjacent to and in contact with the gate electrode 116, and a gate capping layer 120. The gate structures 108 can be formed by a gate replacement process.

[0028] In some embodiments, the dielectric layer 118 can be formed using a high-k dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9). The dielectric layer 118 can be formed by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), e-beam evaporation, or other suitable processes. In some embodiments, the dielectric layer 118 can include (i) a layer of silicon oxide, silicon nitride, and / or silicon oxynitride, (ii) a high-k dielectric material such as hafnium oxide (Hf02), Ti02, HfZrO, Ta203, HfSi04, Zr02, and ZrSi02, (iii) a high-k dielectric material with an oxide of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu), or (iv) a combination thereof. The high-k dielectric layer can be formed by ALD and / or other suitable methods. In some embodiments, the dielectric layer 118 can include a single layer or a stack of insulating material layers. Other materials and formation methods for the dielectric layer 118 are within the scope of the present disclosure. For example, portions of the dielectric layer 118 are formed on horizontal surfaces such as the top surface of the STI region 112. Although not visible in Figure 1 FIG. 1A, the dielectric layer 118 can also be formed on the top and sidewalls of the fin region 121 underneath the gate electrode 116. As shown in Figure 1 FIG. 1A, in some embodiments, the dielectric layer 118 is also formed between the sidewall of the gate electrode 116 and the spacer portion 110a. In some embodiments, the thickness 118t of the dielectric layer 118 is in a range from about 1 nm to about 5 nm.

[0029] The gate electrode 116 can include a gate work function metal layer 122 and a gate metal fill layer 124. In some embodiments, the gate work function metal layer 122 is disposed on the dielectric layer 118. The gate work function metal layer 122 can include a single metal layer or a stack of metal layers. The stack of metal layers can include metals having similar or different work functions from one another. In some embodiments, the gate work function metal layer 122 can include, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), metal alloys, and combinations thereof. The gate work function metal layer 122 can be formed using suitable processes, such as ALD, CVD, PVD, plating, or combinations thereof. In some embodiments, the gate work function metal layer 122 has a thickness 122t in a range from about 2 nm to about 15 nm. Other materials, formation methods, and thicknesses for the gate work function metal layer 122 are within the scope of the present disclosure.

[0030] The gate metal fill layer 124 can include a single metal layer or a stack of metal layers. The stack of metal layers can include metals different from one another. In some embodiments, the gate metal fill layer 124 can include suitable conductive materials, such as Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Co, Ni, TiC, TiAlC, TaAlC, metal alloys, and combinations thereof. The gate metal fill layer 124 can be formed by ALD, PVD, CVD, or other suitable deposition processes. Other materials and formation methods for the gate metal fill layer 124 are within the scope of the present disclosure.

[0031] In some embodiments, the gate capping layer 120 can have a thickness 120t in a range from about 5 nm to about 50 nm and can protect the gate structure 108 during subsequent processing of the finFET 100. The gate capping layer 120 can include nitride materials, such as silicon nitride, silicon-rich nitride, and silicon oxynitride. Other materials for the gate capping layer 120 are within the scope of the present disclosure.

[0032] The STI regions 112 can electrically isolate the finFET 100 from adjacent active and passive elements (not shown here) integrated or deposited on the substrate 102. The STI regions 112 can have a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and other suitable insulating materials. In some embodiments, the STI regions 112 can include a multi-layer structure. The cross-sectional shape of the fin structure 104, the S / D regions 106, the gate structure 108, the spacers 110, and the STI regions 112 are exemplary and are not intended to be limiting.

[0033] Figures 2 to 6 Various exemplary semiconductor structures and fabrication processes are provided according to some embodiments showing the formation of a spacer structure with an air gap and a seamless seal layer. Figure 7 is a flowchart of a method 700 of forming an air gap and a seamless seal layer in a semiconductor structure according to some embodiments of the present invention. Other operations in the method 700 can be performed based on the disclosure herein. Moreover, the operations of the method 700 can be performed in a different order and / or altered.

[0034] An air gap with a seamless seal layer can provide the benefit of reducing and / or eliminating damage to the air gap formed between the spacer structure. The fabrication process can be used to form a planar semiconductor device or a vertical semiconductor device such as a finFET. In some embodiments, Figures 2 to 7 The fabrication process shown in Figure 1 may be used to form a semiconductor structure similar to the finFET structure described above in Figure 1 As can be seen from the cut line A-A’ shown in Figures 2 to 7 the semiconductor structure shown can be similar to the finFET 100 during different stages of fabrication.

[0035] Referring to operation 702 of Figure 7 According to some embodiments, a source / drain region and a gate stack are formed on a substrate. Figure 2 is a cross-sectional view of a semiconductor structure 200 after three adjacent gate structures 208 and two source / drain contacts 230 are formed above the substrate. The substrate can include a fin region 221. Each gate stack such as the gate structure 208 includes a gate dielectric layer 218 and a gate electrode 216. The gate dielectric layer 218 can be formed on the sidewalls and the bottom surface of the gate electrode 216. A channel region for a semiconductor device such as a finFET can be formed in the fin region 221 and below the gate structure 208.

[0036] The fin region 221 can be a charge carrying semiconductor structure formed on a substrate. For example, the fin region 221 can be similar to the fin structure 104 described above in Figure 1The fin region 221 can include a semiconductor material, such as germanium, silicon, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, any suitable material, and combinations thereof, in some embodiments. The fin region 221 can be doped with p-type or n-type dopants in some embodiments.

[0037] The gate dielectric layer 218 can be formed on the fin region 221 and can be formed using a high-k dielectric material. The gate dielectric layer 218 can be deposited by CVD, ALD, PVD, e-beam evaporation, or other suitable process. In some embodiments, the gate dielectric layer 218 can include a high-k dielectric material, such as Hf02. In some embodiments, the gate dielectric layer 218 can include Ti02, HfZrO, Ta203, HfSi04, Zr02, and ZrSi02. In some embodiments, the gate dielectric layer 218 can be similar to the dielectric layer 118 described above in Figure 1

[0038] The gate electrode 216 can be formed on the gate dielectric layer 218 and can include a single metal layer or a stack of metal layers. The gate structure 208 can also include a work function layer and is not shown in Figure 2 for simplicity. The stack of metal layers can include metals having similar or different work functions from each other. In some embodiments, the gate electrode 216 can be formed of a conductive material, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, Ag, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloys, and combinations thereof. The gate electrode 216 can be formed using suitable deposition processes, such as ALD, CVD, PVD, plating, and combinations thereof. Other materials and formation methods for the gate electrode 216 are within the scope of the present disclosure. In some embodiments, the gate electrode 216 can be formed using a gate replacement process, in which a polysilicon gate is removed and a metal gate electrode is formed in place of the removed polysilicon gate.

[0039] ​Spacer structures can be formed on the sidewalls of the gate structures 208. In some embodiments, the gate structures can include a gate electrode, a dielectric layer, a spacer, any other suitable structure, and are collectively referred to as a gate structure for ease of reference. In some embodiments, spacers 210 and 212 can be formed on the sidewalls of the gate dielectric layer 218 and on the top surface of the fin region 221. The spacer structures are formed on the sidewalls of the gate structures 208 to protect the gate structures 208 during subsequent processing. In some embodiments, the spacers 210 can have an L-shaped cross-section, where a vertical portion is formed on the sidewalls of the gate dielectric layer 218 and a horizontal portion is formed on the top surface of the fin region 221. The spacers 210 can be formed using a dielectric material, such as silicon carbon nitride, silicon nitride, silicon oxide, any suitable dielectric material, and combinations thereof. In some embodiments, for spacers 210 formed using silicon carbon nitride, the carbon atomic content can be less than about 30%. In some embodiments, the carbon atomic content of the spacers 210 can be between about 20% and about 30%. Additional spacers, such as spacers 212, can also be formed. For example, the spacers 212 can be formed on the horizontal portion of the spacers 210, on the top surface of the fin region 221, or on both. In some embodiments, the spacers 212 can be formed using a dielectric material, such as silicon. In some embodiments, the material forming the spacers 210 and 212 can have a high etch selectivity (e.g., greater than about 10) such that when the spacers 212 are removed, the spacers 210 can remain substantially intact. In some embodiments, the spacers 210 and 212 can be formed using any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon on glass (SOG), tetraethyl orthosilicate (TEOS), PE oxide, HARP formed oxide, and combinations thereof. In some embodiments, the spacers 210 and 212 can be formed using a low-k dielectric material.

[0040] Source / drain (S / D) regions 240 can be formed in the fin region 221. The S / D regions 240 can be p-type regions or n-type regions. In some embodiments, the p-type S / D regions 240 can include SiGe and can be in-situ doped using p-type dopant, such as boron, indium, and gallium, during an epitaxial growth process. For p-type in-situ doping, a p-type dopant precursor, such as B2H6, BF3, and other p-type dopant precursors, can be used. In some embodiments, the n-type S / D regions 240 can include Si and can be in-situ doped using n-type dopant, such as phosphorus and arsenic, during an epitaxial growth process. For n-type in-situ doping, an n-type dopant precursor, such as PH3, AsH3, and other n-type dopant precursors, can be used. In some embodiments, the S / D regions 240 are not in-situ doped and an ion implantation process is performed to dope the S / D regions 240. In some embodiments, the S / D regions can be similar to the S / D regions described above in Figure 1S / D regions 106 described in the Background.

[0041] Source / drain (S / D) contacts 230 can be in physical and electrical contact with source / drain regions 240. S / D contacts 230 can be formed by depositing a conductive material between adjacent gate structures 208. For example, openings can be formed between spacers 212 to expose underlying S / D regions 240. A deposition process can be performed to deposit a conductive material in the openings such that an electrical connection can be made. In some embodiments, a contact etch stop layer (CESL) 214 can be deposited in the openings prior to depositing the conductive material. Examples of conductive material deposition processes can include PVD, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations thereof. A planarization process can be performed after the deposition process such that the top surfaces of gate electrodes 216, spacers 210 and 212, CESL 214, and conductive / drain contacts 230 can be substantially coplanar (e.g., a planar surface). In some embodiments, S / D contacts 230 can be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations thereof.

[0042] Similar to Figure 1 finFET 100 described in the Background, semiconductor structure 200 can be formed on a substrate with fin regions 221 protruding from STI regions. From Figure 2 The STI regions are not visible in the cross-sectional view of semiconductor structure 200 shown, but for ease of description, the top surface of the STI regions is represented by dashed lines 222.

[0043] Referring to operation 704 of Figure 7 According to some embodiments, one or more spacers are removed to form openings between terminals of a semiconductor device. Figure 3is a cross-sectional view of the semiconductor device after removal of one or more spacers to form an opening. One or more of the spacers between the gate electrode 216 and the S / D contacts 230 can be removed. For example, the spacer 212 can be removed to form an opening 302 surrounded by the spacer 210 and the CESL 214. One or more etching processes can be used to remove the spacer 212. In some embodiments, the spacer 212 can be removed using an etching process that has a high etch selectivity with respect to other structures in the semiconductor structure 200 while leaving the other exposed structures intact. For example, the spacer 212 can be formed using silicon carbonitride, and a wet etching process and / or a plasma etch can be used to selectively remove the spacer 212. For example, the spacer 212 can be formed using a silicon material and a capacitively coupled plasma (CCP) etching process that uses nitrogen tetrafluoride and hydrogen gas as precursors and to selectively remove the spacer 212. In some embodiments, the plasma etching process can be performed at a temperature between about 0 °C to about 100 °C. For example, the processing temperature can be between about 0 °C to about 30 °C, between about 30 °C to about 60 °C, between about 60 °C to about 100 °C, or any suitable temperature range. In some embodiments, the plasma etching process can be performed at a chamber pressure between about 500 mTorr and about 5 Torr. For example, the chamber pressure can be between about 500 mTorr and about 2 Torr, between about 2 Torr and about 5 Torr, or any suitable pressure.

[0044] Figures 4A to 4C is a cross-sectional view showing a seamless seal material formed in an opening of a semiconductor device, according to some embodiments. Figures 4A to 4C is Figure 3 is a zoomed-in view of the region 304 of Figures 4A to 4C the structures shown, and are not shown for simplicity.

[0045] Referring to operation 706 of Figure 7 , according to some embodiments, a first seal material is deposited on at least a corner of an opening in a semiconductor device. Figure 4Ais a cross-sectional view showing the semiconductor device after deposition of a first encapsulation material. The first encapsulation material 412 is deposited on top surfaces of the gate electrode 216, the gate dielectric layer 218, the S / D contacts 230, and the CESL 214. In some embodiments, the first encapsulation material 412 can also be deposited in the opening 302. For example, the first encapsulation material 412 can be deposited on the sidewalls of the spacers 210 and the CESL 214. In some embodiments, the first encapsulation material 412 can be deposited on the bottom of the opening 302, such as on the top surface of the horizontal portion of the spacers 210 formed on the fin region 221. In some embodiments, the first encapsulation material 412 can also be formed on the fin region 221 if a portion of the top surface of the fin region 221 is exposed between the spacers 210 and the CESL 214. The first encapsulation material 412 can include a corner portion 412A formed on the spacers 210 and the CESL 214. The top surfaces of the spacers 210 and the CESL 214 can have rounded corners 410A and 414A, respectively, to facilitate the growth of the corner portion 412A of the first encapsulation material 412. The curved surfaces of the rounded corners 410A and 414A can reduce the formation of voids or discontinuities in the first encapsulation material 412 compared to corners having right angles or sharp edges. The corner portion 412A of the first encapsulation material 412 can contour the curved surfaces of the rounded corners 410A and 414A. The first encapsulation material can have a horizontal portion 412B formed on top surfaces of the gate electrode 216, the gate dielectric layer 218, and the S / D contacts 230 to protect them from subsequent manufacturing processes. For example, the horizontal portion 412B can prevent oxidation of the underlying materials during subsequent etching or processing. The thickness T1 of the horizontal portion 412B can be between about 10 nm and about 40 nm. In some embodiments, the thickness T1 can be between about 10 nm and about 15 nm, between about 15 nm and about 30 nm, between about 30 nm and about 40 nm, or any suitable thickness. An increase in the thickness T1 can provide better protection for the underlying structures (e.g., metal contacts or gate structures) from subsequent processing, such as etching or cleaning processes. Additionally, the thickness T1 can be adjusted to provide a nominal opening profile of the opposing corner portions 412A. For example, increasing the thickness T1 can decrease the distance between the opposing corner portions 412A, which in turn can form a larger volume air gap by reducing the amount of second encapsulation material deposited underneath the corner portions 412A.

[0046] The first sealing material 412 can influence the volume of the subsequently formed air gap between the gate electrode 216 and the S / D contact 230 by adjusting the depth of the first sealing material 412 extending into the opening 302. Specifically, the corner portion 412A of the first sealing material 412 can extend into the opening 302 by being formed on the sidewalls of the spacer 210 and CESL 214. The opening 302 can have a depth H1, and a greater extension depth H2 of the corner portion 412A in the opening 302 can provide a smaller subsequently formed air gap in the opening 302. Figure 4A (Not shown in the image). For example, a larger value of the H2 to H1 ratio can leave a smaller volume in the opening 302 for the air gap to be formed. In some embodiments, the opening 302 has a height H1 that can be between about 30 nm and about 60 nm. In some embodiments, the extension depth H2 can be between about 10 nm and about 20 nm. In some embodiments, the H1 to H2 ratio can be between about 11 and about 2. In some embodiments, a planarization process such as chemical mechanical polishing (CMP) can be performed on the first sealing material 412, and the heights H1 and H2 can be reduced. For example, after the planarization process, the height H1 can be between about 25 nm and about 55 nm, and the height H2 can be between about 5 nm and about 15 nm.

[0047] The first sealing material 412 can be formed using any suitable dielectric material. In some embodiments, the first sealing material 412 can be formed using a material that provides sufficient mechanical strength to support the air gap structure and chemical resistance to prevent the subsequent chemical processes from affecting. In some embodiments, the first sealing material 412 can include silicon-oxygen or silicon-carbon crosslinks. For example, the first sealing material 412 can be formed using a silicon oxycarbide material. The oxygen and carbon atomic content of the silicon oxycarbide material can be adjusted to achieve various properties of the first sealing material 412. For example, increasing the oxygen atomic content of the first sealing material 412 can reduce the current leakage in the first sealing material 412. Increasing the carbon atomic content in the first sealing material 412 can provide increased etch selectivity of the first sealing material 412 relative to adjacent structures such as the spacers 210 and 214. In some embodiments, the silicon atomic content of the first sealing material 412 formed using silicon oxycarbide can be between about 28% and about 35%. For example, the silicon atomic content can be between about 28% to about 31%, between about 31% to about 35%, or any suitable range. In some embodiments, the oxygen atomic content of the first sealing material 412 can be between about 35% to about 52%. For example, the oxygen atomic content can be between about 35% to about 45%, between about 45% to about 52%, or any suitable range. In some embodiments, the carbon atomic content of the first sealing material 412 can be between about 15% to about 35%. For example, the carbon atomic content can be between about 15% to about 25%, between about 25% to about 35%, or any suitable range. In some embodiments, the first sealing material 412 can be deposited using radical CVD, CVD, ALD, LPCVD, UHVCVD, RPCVD, PVD, any other suitable deposition process, and combinations thereof. In some embodiments, the first sealing material 412 can be deposited using a radical CVD process with an ion filter.

[0048] Referring to Figure 7deposition of the first sealing material 412 can include one or more operations. For example, the deposition can include a first operation 706A of flowing a precursor into a deposition chamber. The precursor can provide one or more of the following bonding types: silicon-oxygen, silicon-hydrogen, and silicon-carbon. In some embodiments, the precursor is in a gas phase and can include, for example, tetramethyl disiloxane (TMDSO), hydrogen, and oxygen. Other suitable precursors can also be included. The flow rate ratio of hydrogen to oxygen can be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow rate ratio of hydrogen to oxygen can be between about 20 and about 30. The deposition can also include a second operation 706B that includes activating a plasma and is used to activate the precursor in its gas phase to form silicon-oxygen and silicon carbon crosslinks. The deposition process can include a third operation 706C of a treatment process to reduce the oxygen content from the deposited sealing material. The treatment process can be performed in a chamber environment of hydrogen gas. In some embodiments, the treatment process can be performed in a chamber environment of any suitable type of gas, such as argon, nitrogen, and any suitable gas. In some embodiments, the deposition process can be performed at a temperature between about 300 °C to about 700 °C. For example, the deposition temperature can be between about 300 °C to about 500 °C, between about 500 °C to about 700 °C, and at any suitable temperature. In some embodiments, the deposition and treatment processes can be performed in a cycle, such as a cycle process deposition-treatment process. For example, the deposition and treatment process can be followed by another deposition and treatment process until a nominal thickness or quality of the first sealing material is reached. In some embodiments, the cycle process can include flowing a precursor into the deposition chamber and performing a series of activation / treatment processes. In some embodiments, the cycle process can include sequentially performing the following operations: flowing a precursor, activating the precursor, and performing a treatment. In some embodiments, the flow of the precursor can be performed between a series of activation / treatment processes. Figure 8 An exemplary chemical reaction that occurs during the deposition of the first sealing material 412 is shown.

[0049] The deposition rate can be adjusted by various deposition parameters. A greater deposition rate can facilitate greater accumulation of the first sealing material on the curved surfaces 410A and 414A. A lower deposition rate can provide a greater extension depth H2 of the first sealing material 412 in the opening 302. Greater deposition rates can be obtained by adjusting various suitable processing parameters. In some embodiments, the deposition process can be performed at a deposition rate greater than about For example, the deposition process can be performed at a rate of about and about In some embodiments, the deposition rate can be between about and about between about 0.5 Torr and about 12 Torr. For example, the chamber pressure can be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 7 Torr, between about 7 Torr and about 12 Torr, and any other suitable range / value. As another example, a chamber pressure between about 4.5 Torr and about 5.5 Torr can provide a deposition rate of about 35 A / min, while a chamber pressure between about 6 Torr and about 7 Torr can provide a lower deposition rate of about 20 A / min. In some embodiments, a lower chamber pressure or a greater plasma power during deposition can provide a greater deposition rate. In some embodiments, the chamber pressure can be between about 0.5 Torr and about 12 Torr. For example, the chamber pressure can be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 7 Torr, between about 7 Torr and about 12 Torr, and any other suitable range / value. As another example, a chamber pressure between about 4.5 Torr and about 5.5 Torr can provide a deposition rate of about 35 A / min, while a chamber pressure between about 6 Torr and about 7 Torr can provide a lower deposition rate of about 20 A / min.

[0050] The plasma power level of deposition can also affect the deposition rate. Greater plasma power levels can provide greater deposition rates. In some embodiments, the plasma power level can be between about 500 W and about 3000 W. For example, the plasma power level can be between about 500 W and about 1000 W, between about 1000 W and about 2000 W, between about 2000 W and about 3000 W, and any other suitable power level.

[0051] The density of the first sealing material 412 can also be adjusted by deposition parameters. Increasing the density of the sealing material 412 can provide greater mechanical support and improved chemical resistance. In some embodiments, the first sealing material 412 can have a density greater than about 2.0 g / cm 3 . For example, the density of the first sealing material 412 can be between about 2 g / cm 3 and about 2.2 g / cm 3 . In some embodiments, the density can be between about 2.2 g / cm 3 and about 3.2 g / cm 3 . In some embodiments, greater density can be obtained by lower chamber processing pressure and higher plasma power levels. In some embodiments, the chamber processing pressure can be between about 0.5 Torr and about 12 Torr. For example, the chamber processing pressure can be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 8 Torr, between about 8 Torr and about 12 Torr, and any other suitable range or value. In some embodiments, the plasma power level can be between about 500 W and about 3000 W. For example, the plasma power level can be between about 500 W and about 2000 W, between about 2000 W and about 3000 W, and any other suitable range or value. In some embodiments, the deposition process can use radical-triggered chemical reactions with an ion filter. The use of an ion filter in a plasma deposition process can improve the consistency of the deposited first sealing material 412.

[0052] The dielectric constant of the first sealing material 412 may be less than about 5. In some embodiments, the first sealing material 412 may have a dielectric constant between about 3.2 and about 5. The lower dielectric constant of the first sealing material 412 may result in lower parasitic capacitance at the terminals of the semiconductor device 200. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E at 2MV / cm. -8 A / cm 2 .

[0053] Optional processing techniques can be performed on the first sealing material 412 to further increase the amount of internal crosslinking and / or improve its density. For example, a hydrogen annealing process can be performed to reduce the oxygen content and to form additional Si-C-Si bonds in the first sealing material 412. The hydrogen treatment process can also remove chemical byproducts such as H2O. In some embodiments, the optional processing techniques can be performed for less than about 1 minute and more than about 5 seconds. For example, the processing techniques can be performed for about 40 seconds to about 1 minute. In some embodiments, the optional processing techniques can be performed at a chamber pressure below about 5 Torr. For example, the chamber pressure can be set to about 3 Torr. In some embodiments, the optional processing techniques can be performed at an elevated temperature. For example, the processing temperature can be set to greater than about 300°C. In some embodiments, the processing temperature can be about 350°C. In some embodiments, increasing the processing time, decreasing the chamber pressure, and / or increasing the processing temperature can increase the density and produce more crosslinking in the first sealing material 412.

[0054] refer to Figure 7 In operation 708, according to some embodiments, a second sealing material is deposited on the first sealing material and in the opening. Figure 4B This is a cross-sectional view of the semiconductor device after the deposition of the second sealing material. The second sealing material 432 is deposited on portions of the surfaces of the first sealing material 412, the spacer 210, and the CESL 214. The second sealing material 432 may include at least: (i) a corner portion 432A deposited on a corner portion 412A of the first sealing material 412; (ii) a horizontal portion 432B deposited on a 412B of the first sealing material 412; and (iii) a vertical portion 432C deposited on the sidewalls of the spacer 210 and the CESL 214. In some embodiments, the second sealing material 432 may be deposited on the bottom of the opening 302, such as on the top surface of the horizontal portion of the spacer 210 formed on the fin region 221.

[0055] The second sealing material 432 can be deposited using any suitable deposition process. For example, the second sealing material 432 can be deposited using a CVD process. The semiconductor structure 200 can be loaded into a deposition chamber and the sealing material subsequently blanket deposited. Since the precursors in the deposition chamber have a lower likelihood of contacting the surfaces of the spacers 210 and CESL 214 compared to the top surface of the horizontal portions 412B, due to the precursors having to move through the openings formed between the opposing corner portions 412A of the first sealing material 412 to deposit on the exposed surfaces of the openings 302. Thus, the sealing material is deposited at a much lower rate in the openings 302 underneath the corner portions 412A. As the sealing material gradually accumulates on the opposing corner portions 412A of the first sealing material 412 to form corner portions 432A of the second sealing material 432, the corner portion 432A deposited over one corner portion 412A will merge with another corner portion 432A deposited over the opposing corner portion 412A at regions 440. At the regions 440, a gap 450 is formed between adjacent corner portions 432A of the second sealing material 432. The thickness T2 of the horizontal portions 432B can be between about 20 nm to about 50 nm. In some embodiments, the thickness T2 can be between about 20 nm and about 30 nm, between about 30 nm and about 40 nm, between about 40 nm and about 50 nm, or any suitable thickness. In some embodiments, the sum of the thicknesses T1 and T2 can be between about 40 nm to about 80 nm. In some embodiments, the sum of the thicknesses T1 and T2 can be greater than 80 nm. Deposition of the second sealing material 432 can continue until the openings between the corner portions 412A of the first sealing material 412 are closed. The increase in thickness T2 can provide the benefit of ensuring that the openings between the corner portions 412A are closed by deposition of the second sealing material 432 and that an air gap has been formed.

[0056] The second sealing material 432 can influence the volume of the air gap subsequently formed between the gate electrode 216 and the S / D contacts 230 by adjusting the depth of the second sealing material 432 extending into the openings 302. Specifically, the vertical portions 432C of the second sealing material extend into the openings 302 by forming on the sidewalls of the spacers 210 and CESL 214. The distance H3 between the gap 450 and the bottom surface of the openings 302 can be between about 20 nm to about 50 nm. A greater depth H3 can provide a greater air gap 442 formed between the gate electrode 216 and the S / D contacts 230. The distance H4 between the lower end of the vertical portions 432C and the bottom surface of the openings 302 can be between about 0 to about 45 nm.

[0057] The second sealing material 432 can be formed using any suitable dielectric material. In some embodiments, the second sealing material 432 can be formed using a material that provides sufficient bond strength to the first sealing material 412. In some embodiments, the second sealing material 432 can include silicon-oxygen or silicon-carbon crosslinks. For example, the second sealing material 432 can be formed using a silicon oxycarbide material. In some embodiments, the silicon, oxygen, and carbon atomic content of the second sealing material 432 after its deposition process can be similar to those of the first sealing material 412. In some embodiments, those atomic contents between the first and second sealing materials 412 can be different. In some embodiments, the second sealing material 432 can be deposited using a radical CVD, CVD, ALD, LPCVD, UHVCVD, RPCVD, PVD, any other suitable deposition process, and combinations thereof. In some embodiments, the second sealing material 432 can be deposited using a radical CVD process with an ion filter. In some embodiments, the deposition of the second sealing material 432 can be similar to the deposition process of the first sealing material 412. For example, the deposition process of the second sealing material 432 can include a first operation 708A of flowing a precursor into a deposition chamber. In some embodiments, the second sealing material 432 can be formed by a CVD process using a precursor including, for example, tetramethyldisiloxane (TMDSO), hydrogen gas, and oxygen gas. Other suitable precursors can also be used. The flow rate ratio of hydrogen gas to oxygen gas can be greater than about 20 to minimize oxidation of the underlying material while promoting the chemical reactions required for deposition. For example, the flow rate ratio of hydrogen gas to oxygen gas can be between about 20 and about 30. The deposition can also include a second operation 708B including activating a plasma and for activating the precursor in its gas phase to form silicon-oxygen and silicon-carbon crosslinks. In some embodiments, the deposition process can be performed at a temperature between about 300 °C to about 700 °C. For example, the deposition temperature can be between about 300 °C to about 450 °C, between about 450 °C to about 700 °C, and at any other suitable temperature. The deposition process can also include a third operation 708C in which a processing process is performed on the second sealing material 432. In some embodiments, the processing process can be an annealing process performed in an oxygen gas environment. In some embodiments, the processing process can be similar to the processing process described below with reference to operation 710. In some embodiments, the processing process can be different. In some embodiments, the third operation 708C can include an annealing process performed in a deposition chamber filled with a non-reactive gas such as argon. In some embodiments, the third operation 708C can be a processing process performed using hydrogen gas. In some embodiments, the cycle process can include flowing a precursor into a deposition chamber and performing a series of activation / processing processes. In some embodiments, the cycle process can include sequentially performing the following operations: flowing a precursor, activating the precursor, and performing a processing.In some embodiments, the flow of the precursor can be performed between a series of activation / processing processes. Figure 8 An exemplary chemical reaction that occurs during the deposition of the second sealing material 432 is shown.

[0058] The deposition rate can be adjusted using various deposition parameters. The second sealing material 432 can be deposited at a lower deposition rate than the first sealing material 412. In some embodiments, the second sealing material 432 can be a substantially conformal film deposition above the corner portion 412A and the horizontal portion 412B of the first sealing material 412. A higher deposition rate can promote greater accumulation of the second sealing material at the corner portion 412A. A lower deposition rate allows the second sealing material 432 to extend more into the opening 302. A higher deposition rate can be obtained by adjusting various suitable processing parameters. In some embodiments, it can be less than approximately The deposition process is performed at a deposition rate of approximately [missing information]. For example, it can be performed at approximately [missing information]. Peace Treaty The deposition process is performed at a rate between [specific values]. In some embodiments, a lower chamber pressure or a higher plasma power during deposition can provide a higher deposition rate. In some embodiments, the chamber pressure can be between about 0.5 Torr and about 12 Torr. For example, the chamber pressure can be between 0.5 Torr and about 3 Torr, between about 3 Torr and about 7 Torr, between about 7 Torr and about 12 Torr, and any other suitable range / value.

[0059] The plasma power level used for deposition also affects the deposition rate. A higher plasma power level can provide a higher deposition rate. In some embodiments, the plasma power level can be between about 500 W and about 3000 W. For example, the plasma power level can be between about 500 W and about 1000 W, between about 1000 W and about 2000 W, between about 2000 W and about 3000 W, and any other suitable power level.

[0060] The density of the second sealing material 432 can also be adjusted by deposition parameters. Increasing the density of the second sealing material 432 can provide greater mechanical support and improved chemical resistance. In some embodiments, the second sealing material 432 can have a density greater than about 2.0 g / cm³. 3 The density. For example, the density of the second sealing material 432 can be approximately 2 g / cm³. 3 and approximately 2.5 g / cm 3 Between [specific values]. In some embodiments, the density can be approximately 2.2 g / cm³. 3 Approximately 2.5 g / cm³ 3Between. In some embodiments, a higher density can be achieved by using a lower chamber processing pressure and a higher plasma power level. In some embodiments, the chamber processing pressure can be between about 0.5 Torr and about 12 Torr. For example, the chamber processing pressure can be between about 0.5 Torr and about 3 Torr, between about 3 Torr and about 8 Torr, between about 8 Torr and about 12 Torr, and any other suitable range or value. In some embodiments, the plasma power level can be between about 500 W and about 3000 W. For example, the plasma power level can be between about 500 W and about 2000 W, between about 2000 W and about 3000 W, and any other suitable range or value. In some embodiments, the deposition process can use a chemical reaction triggered by free radicals of an ion filter. Using an ion filter in the plasma deposition process can improve the consistency of the deposited second sealing material 432.

[0061] The dielectric constant of the second sealing material 432 may be the same as or different from that of the first sealing material 412. For example, the dielectric constant of the second sealing material 432 may be less than about 5. In some embodiments, the second sealing material 432 may have a dielectric constant between about 3.2 and about 5. In some embodiments, the leakage current in the semiconductor structure 200 may be less than about 1E at 2MV / cm. -8 A / cm 2 .

[0062] refer to Figure 7 Operation 710, according to some embodiments, involves performing a processing procedure on the first and second sealing materials of the sealing layer. Figure 4Cis a cross-sectional view showing the semiconductor device after a processing procedure is performed. A processing procedure 435 can be performed on the second encapsulation material 432 to remove a gap, such as gap 450. For example, an oxygen anneal procedure can be performed such that the second encapsulation material 432 physically expands and forms additional bonds at the gap 450. During the oxygen anneal procedure, some of the Si-C-Si bonds in the second encapsulation material 432 can change to Si-O-Si bonds. In some embodiments, the overall carbon atomic ratio of the second encapsulation material 432 can decrease by about 5% to about 15%. In some embodiments, the processing procedure 435 can change the silicon, oxygen, and carbon atomic content of the second encapsulation material 432. For example, prior to the processing procedure 435, the second encapsulation material 432 can have a similar atomic content composition as the first encapsulation material 412. After the processing procedure 435, the atomic content of the second encapsulation material 432 can change. For example, the processing procedure 435 using an oxygen anneal procedure can increase the oxygen atomic content in the second encapsulation material 432. Thus, the second encapsulation material 432 can have a higher oxygen atomic content than the first encapsulation material 412. In some embodiments, increasing the oxygen atomic content in the second encapsulation material 432 can cause the second encapsulation material 432 to physically expand, resulting in additional bonds being formed at the gap 450. In some embodiments, the oxygen atomic content of the second encapsulation material 432 can be between about 40% to about 60%. For example, the oxygen atomic content can be between about 40% to about 45%, between about 45% to about 50%, between about 50% to about 60%, or any suitable range. In some embodiments, the carbon atomic content of the second encapsulation material 432 can be lower than the carbon atomic content of the first encapsulation material 412. For example, the carbon atomic content of the second encapsulation material 432 can be between about 10% to about 25%. In some embodiments, the carbon atomic content can be between about 10% to about 15%, between about 15% to about 25%, or any suitable range. In some embodiments, the silicon atomic content of the second encapsulation material 432 formed using silicon oxide of carbon can be between about 25% to about 40%. For example, the silicon atomic content can be between about 25% to about 33%, between about 33% to about 40%, or any suitable range. The oxygen processing procedure can be performed for less than about 1 minute. For example, the processing procedure can be performed for about 40 seconds to about 1 minute. In some embodiments, the oxygen flow rate for the processing procedure 435 can be between about 1 seem and about 10 seem. For example, the oxygen flow rate can be between about 1 seem and about 3 seem, between about 3 seem and about 5 seem, between about 5 seem and about 10 seem, and any other suitable value. The oxygen anneal procedure can remove any gaps, such as gap 450, such that the region 440 contains the second encapsulation material 432 without any gaps.

[0063] Reference Figure 7Operation 712, according to some embodiments, involves performing a planarization process on the seamless sealing layer. Figure 5 This is a cross-sectional view of a semiconductor device after the planarization process has been performed. For example... Figure 5 As shown, a seamless sealing material 532 is formed on the semiconductor structure 200, trapping air pockets to form an air gap 542 between the terminals of the semiconductor structure 200 and a substrate such as the fin region 221. The seamless sealing material 532 can be formed between and in physical contact with the spacer 210 and CESL 214. The seamless sealing material 532 can also be... Figure 5 Other structural contacts are not shown. A planarization process can be used to remove portions of the first sealing material 412 and the second sealing material 432. The planarization process can continue until the top surfaces of the gate electrode 216, gate dielectric layer 218, spacer 210, CESL 214, and S / D contact 230 are exposed and substantially flush. After the planarization process, the remaining portions of the first and second sealing materials 412 and 432 can form a seamless sealing material 532. The air pockets trapped by the seamless sealing material 532 can form an air gap 542 between the terminals of the semiconductor structure 200, such as the gate structure 208 and the S / D contact 230. In some embodiments, the air gap 542 may comprise different types of air. For example, the air gap 542 may comprise oxygen, hydrogen, helium, argon, nitrogen, any other suitable type of air, and combinations thereof. A lower deposition rate of the seamless sealing material 532 can produce an air gap 542 with a smaller volume. For example, a seamless sealing material 532 can be formed by depositing a first sealing material 412 and a second sealing material 432, and the lower deposition rate of the second sealing material 432 can provide an air gap 542 with a shorter height, resulting in a smaller air gap volume. Since the air gap 542 can have a dielectric constant of about 1, the effective dielectric constant of spacer 210 and air gap 542 can be lower compared to the spacer structure composed of spacer 210 and CESL 214.

[0064] refer to Figure 7 Operation 714, according to some embodiments, forms a dielectric layer and an interconnect structure. Figure 6 This is a cross-sectional view showing the dielectric layer and interconnect structure formed on a semiconductor device.

[0065] A dielectric layer 620 can be formed on the top surface of the gate electrode 216, gate dielectric layer 218, spacers 210, seamless seal material 532, CESL 214, S / D contacts 230, and other suitable structures. In some embodiments, the dielectric layer 620 can be an etch stop layer. The dielectric layer 620 can be formed using a low-k dielectric material (e.g., a dielectric layer having a dielectric constant lower than about 3.9), such as silicon oxide. An interlayer dielectric (ILD) layer 650 can be formed on the dielectric layer 620. The ILD layer 650 can be formed from a low-k dielectric material. For example, the ILD layer 650 can be formed using silicon oxide. In some embodiments, the dielectric layer 620 and the ILD layer 650 can be formed using CVD, ALD, PVD, flowable CVD (FCVD), sputtering, any suitable deposition process, and combinations thereof. Contacts can be formed in the ILD 650 to establish electrical connections from the S / D contacts 230 and the gate electrode 216 to external circuitry, such as a peripheral circuit formed on top of the semiconductor structure 200. A gate via 616 can be formed in the ILD 650 and extend through the dielectric layer 620 to make physical contact with the gate electrode 216. Similarly, S / D vias 630 can be formed by a patterning and etching process. For example, openings can be formed in the ILD 650 and through the dielectric layer 620 to expose the gate electrode 216 and the S / D contacts 216, respectively. A deposition process can be performed to deposit a conductive material in the openings such that electrical connections can be made. Examples of the deposition process can be PVD, sputtering, electroplating, electroless plating, any suitable deposition process, and combinations thereof. A planarization process can be performed after the deposition process such that the top surfaces of the ILD 650, the gate via 616, and the S / D vias 630 can be substantially coplanar (e.g., flush). In some embodiments, the gate via 616 and the S / D vias 630 can be formed using tungsten, aluminum, cobalt, silver, any suitable conductive material, and combinations thereof.

[0066] Various embodiments of the present invention provide semiconductor devices and methods of fabricating the same to provide a simple and cost-effective structure and process for creating a seamless seal layer in a semiconductor device. The seamless seal layer can be used to seal openings and form air gaps between terminals of the semiconductor device to reduce the effective dielectric constant, which in turn can improve device performance. The bilayer seal material can be formed by depositing a first seal material, depositing a second seal material, and performing at least one processing on the deposited first and second seal materials.

[0067] In some embodiments, a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls are opposite each other. The method also includes depositing a first dielectric material on top of the opening at a first deposition rate, and depositing a second dielectric material on the first dielectric material and on the first and second sidewalls at a second deposition rate. The second dielectric material and the first and second sidewalls trap a pocket of gas. The method also includes performing a processing procedure on the second dielectric material.

[0068] In the above method, wherein depositing the first dielectric material includes flowing tetramethyl disiloxane (TMDSO) into a deposition chamber.

[0069] In the above method, wherein depositing the first dielectric material includes flowing tetramethyl disiloxane (TMDSO) into a deposition chamber, depositing the first dielectric material also includes flowing hydrogen and oxygen into the deposition chamber.

[0070] In the above method, wherein depositing the second dielectric material includes flowing tetramethyl disiloxane into a deposition chamber.

[0071] In the above method, wherein depositing the second dielectric material includes depositing first and second portions of the second dielectric material on the first and second sidewalls, respectively.

[0072] In the above method, wherein depositing the second dielectric material includes depositing first and second portions of the second dielectric material on the first and second sidewalls, respectively, depositing the first and second portions of the second dielectric material includes depositing the second dielectric material until the first and second portions of the second dielectric material contact each other.

[0073] In the above method, wherein the second deposition rate is less than the first deposition rate.

[0074] In the above method, wherein the processing procedure includes an oxygen anneal process.

[0075] In the above method, wherein performing the processing procedure includes inflating the second dielectric material during the processing procedure.

[0076] In the above method, further comprising another processing procedure on the deposited first dielectric material.

[0077] In some embodiments, a method for forming a semiconductor device includes forming a gate structure and source / drain (S / D) contacts on a substrate. The method further includes depositing a first dielectric material. A first portion of the first dielectric material is located on top of a sidewall of the gate structure. A second portion of the first dielectric material is located on top of a sidewall of the S / D contact. The method further includes depositing a second dielectric material. A first portion of the second dielectric material is located on the first portion of the first dielectric material and on a sidewall of the gate structure. A second portion of the second dielectric material is located on the second portion of the first dielectric material and on a sidewall of the S / D contact. Deposition of the second dielectric material continues until the first and second portions of the second dielectric material are in contact with each other. The method further includes performing an oxygen treatment process on the deposited second dielectric material.

[0078] In the above method, the first dielectric material is deposited at a higher deposition rate than that of the second dielectric material.

[0079] The above method also includes performing a hydrogen treatment process on the deposited first dielectric material.

[0080] The above method also includes forming an air pocket surrounded by the second dielectric material, the gate structure, the source / drain contacts, and the substrate.

[0081] In the above method, depositing the second dielectric material includes: forming a gap between the first and second portions of the second dielectric material when the first and second portions of the second dielectric material are in contact with each other; and removing the gap during the oxygen treatment process.

[0082] In some embodiments, a method for forming a semiconductor device includes forming an opening over a top surface of a substrate and between a first terminal and a second terminal of the semiconductor device. The method further includes depositing a first dielectric material. A first portion of the first dielectric material is located on top of a sidewall of the first terminal. A second portion of the first dielectric material is located on top of a sidewall of the second terminal. The method further includes depositing a second dielectric material. A first portion of the second dielectric material is located on top of the first portion of the first dielectric material. A second portion of the second dielectric material is located on top of the second portion of the first dielectric material. An air pocket is trapped in the opening surrounded by the second dielectric material, the first terminal, the second terminal, and the substrate. The method further includes performing an oxygen treatment process on the deposited second dielectric material.

[0083] In the above method, the first dielectric material is deposited at a higher deposition rate than that of the second dielectric material.

[0084] The above method also includes performing a hydrogen treatment process on the deposited first dielectric material.

[0085] In the above method, further comprising forming a spacer on sidewalls of the first terminal and on a top surface of the substrate.

[0086] In the above method, wherein depositing the second dielectric material comprises forming a gap between the first portion and the second portion of the second dielectric material when the first portion and the second portion of the second dielectric material are in contact with each other, and removing the gap during the oxygen treatment process.

[0087] It should be understood that the detailed description and summary are intended to be explanatory only and not to be limiting. The abstract of the disclosure, which can be abbreviated, sets forth one or more but not all exemplary embodiments as contemplated by the inventors and, thus, can not be construed as limiting the disclosure or any exemplification embodiment thereof.

[0088] The foregoing summary of the application outlines features of several embodiments so that those skilled in the art can better understand the aspects of the application. Those skilled in the art should understand that they can readily apply the conception of the application as a basis for the design and construction of other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments presented herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the application, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the application.

Claims

1. A method for forming a semiconductor device, comprising: forming an opening between first and second sidewalls of respective first and second terminals, wherein the first and second sidewalls are opposite to each other; depositing a first dielectric material on a top of the opening at a first deposition rate, wherein the top of the opening has a rounded corner, wherein a corner portion of the first dielectric material contours a curved surface of the rounded corner; performing a hydrogen anneal process on the first dielectric material to form additional Si-C-Si bonds in the first dielectric material; depositing a second dielectric material on the first dielectric material and on the first and second sidewalls at a second deposition rate, wherein a corner portion of the second dielectric material is formed on the corner portion of the first dielectric material, and wherein the second dielectric material extends beyond the first dielectric material to be in direct contact with the first and second sidewalls, and the second dielectric material and the first and second sidewalls trap an air pocket; and performing an oxygen treatment process on the second dielectric material, wherein during the oxygen treatment process, some of the Si-C-Si bonds in the second dielectric material become Si-O-Si bonds, after the oxygen treatment process, an oxygen atom content of the second dielectric material is greater than an oxygen atom content of the first dielectric material, wherein performing the oxygen treatment process includes inflating the second dielectric material during the oxygen treatment process and forming additional bonds at a gap between adjacent corner portions of the second dielectric material.

2. The method of claim 1, wherein, Depositing the first dielectric material includes flowing tetramethyl disiloxane (TMDSO) into a deposition chamber.

3. The method of claim 2, wherein, Depositing the first dielectric material further includes flowing hydrogen and oxygen into the deposition chamber.

4. The method of claim 1, wherein, Depositing the second dielectric material includes flowing tetramethyl disiloxane into a deposition chamber.

5. The method of claim 1, wherein, Depositing the second dielectric material includes depositing first and second portions of the second dielectric material on the first and second sidewalls, respectively.

6. The method of claim 5, wherein, Depositing the first and second portions of the second dielectric material includes depositing the second dielectric material until the first and second portions of the second dielectric material contact each other.

7. The method of claim 1, wherein, The second deposition rate is less than the first deposition rate.

8. The method of claim 1, wherein, The oxygen treatment process includes an oxygen anneal process.

9. The method of claim 1, wherein, A ratio of a depth of the opening to an extension depth of the corner portion of the first dielectric material is between 11 and 2.

10. The method of claim 1, further comprising another treatment process on the deposited first dielectric material.

11. A method for forming a semiconductor device, comprising: forming a gate structure and a source / drain (S / D) contact on a substrate, wherein a spacer is formed on a sidewall of the gate structure, and a contact etch stop layer is formed on a sidewall of the S / D contact, wherein a top portion of the spacer and the contact etch stop layer has a rounded corner, respectively; depositing a first dielectric material, wherein: a first portion of the first dielectric material is on a top of the sidewall of the spacer; and a second portion of the first dielectric material is on top of a sidewall of the contact etch stop layer, wherein a corner portion of the first dielectric material contours a curved surface of the rounded corner; performing a hydrogen anneal process on the first dielectric material to form additional Si-C-Si bonds in the first dielectric material; depositing a second dielectric material, wherein: a first portion of the second dielectric material is on the first portion of the first dielectric material and on the sidewall of the spacer and extends beyond the first portion of the first dielectric material to be in direct contact with the sidewall of the spacer; and a second portion of the second dielectric material is on the second portion of the first dielectric material and on the sidewall of the contact etch stop layer and extends beyond the second portion of the first dielectric material to be in direct contact with the sidewall of the contact etch stop layer, wherein the second dielectric material is continued to be deposited until the first and second portions of the second dielectric material are in contact with each other; and performing an oxygen treatment process on the deposited second dielectric material, wherein during the oxygen treatment process, some of the Si-C-Si bonds in the second dielectric material become Si-O-Si bonds, after the oxygen treatment process, the oxygen atom content of the second dielectric material is greater than the oxygen atom content of the first dielectric material.

12. The method of claim 11, wherein, depositing the first dielectric material at a higher deposition rate than a deposition rate of the second dielectric material.

13. The method of claim 11, further comprising performing a hydrogen treatment process on the deposited first dielectric material.

14. The method of claim 11, further comprising forming a pocket of air surrounded by the second dielectric material, the gate structure, the source / drain contact, and the substrate.

15. The method of claim 11, wherein, depositing the second dielectric material includes: forming a gap between the first and second portions of the second dielectric material when the first and second portions of the second dielectric material are in contact with each other; and removing the gap during the oxygen treatment process.

16. A method for forming a semiconductor device, comprising: forming an opening above a top surface of a substrate and between a first terminal and a second terminal of a semiconductor device; depositing a first dielectric material, wherein a top portion of the opening has a rounded corner, wherein a corner portion of the first dielectric material contours a curved surface of the rounded corner, wherein: a first portion of the first dielectric material is on top of a sidewall of the first terminal; and a second portion of the first dielectric material is on top of a sidewall of the second terminal; performing a hydrogen anneal process on the first dielectric material to form additional Si-C-Si bonds in the first dielectric material; depositing a second dielectric material, wherein: a first portion of the second dielectric material is on the first portion of the first dielectric material; and a second portion of the second dielectric material is on the second portion of the first dielectric material. a second portion of the second dielectric material is located on the second portion of the first dielectric material, wherein an air pocket is trapped in the opening surrounded by the second dielectric material, the first terminal and the second terminal, and the substrate, a corner portion of the second dielectric material is formed on a corner portion of the first dielectric material, and wherein the second dielectric material extends beyond the first dielectric material to be in direct contact with sidewalls of the first terminal and the second terminal; and performing an oxygen treatment process on the deposited second dielectric material, wherein during the oxygen treatment process, a portion of Si-C-Si bonds in the second dielectric material become Si-O-Si bonds, after the oxygen treatment process, an oxygen atom content of the second dielectric material is greater than an oxygen atom content of the first dielectric material, wherein performing the oxygen treatment process includes inflating the second dielectric material during the oxygen treatment process and forming additional bonds at a gap between adjacent corner portions of the second dielectric material.

17. The method of claim 16, wherein, depositing the first dielectric material at a higher deposition rate than a deposition rate of the second dielectric material.

18. The method of claim 16, further comprising performing a hydrogen treatment process on the deposited first dielectric material.

19. The method of claim 16, further comprising forming spacers on sidewalls of the first terminal and on a top surface of the substrate.

20. The method of claim 16, wherein, depositing the second dielectric material includes: forming a gap between the first portion and the second portion of the second dielectric material when the first portion and the second portion of the second dielectric material are in contact with each other; and removing the gap during the oxygen treatment process.

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