Display panel and display device including the same

Abstract

A display panel and a display device including the same are provided. The display device includes: a first display panel configured to emit light from a first display element along a first direction to display an image, the first display panel including a main display area and a component area; a second display panel arranged below the first display panel and including a second display area, the second display area being configured to emit light from the second display element along the first direction to display an image; and a component arranged below the first display panel and configured to receive light from outside the display device.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0170207 filed in the Korean Intellectual Property Office on December 18, 2019, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] One or more embodiments of the present disclosure relate to a display panel and a display device including the display panel, and more particularly, to a display panel including an extended display area so that an image can be displayed even in an area where electronic components are arranged, and a display device including the display panel. Background Art

[0003] Recently, the use of display devices has been diversified. In addition, as display devices become thinner and lighter, their use range has gradually expanded.

[0004] Display devices are used in various ways, and thus they have been designed to have various shapes. In addition, functions that can be combined or associated with display devices are increasing. Summary of the invention

[0005] One or more embodiments include a display panel and a display device including the display panel, the display panel including an extended display area so that an image can be displayed even in an area where a component as an electronic element is arranged. However, it should be understood that the embodiments described herein are for description purposes only and are not intended to limit the present disclosure.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the disclosed presented embodiments.

[0007] According to one or more embodiments, a display device includes: a first display panel, configured to emit light from a first display element along a first direction to display an image, the first display panel including a main display area and a component area; a second display panel, located below the first display panel and including a second display area, the second display area being configured to emit light from the second display element along the first direction to display an image; and a component, arranged below the first display panel and configured to receive light from outside the display device.

[0008] The second display element may correspond to an edge of the component area, and the component may overlap the component area.

[0009] When the display device is in use and displays an image, the image displayed on the second display panel by the second display element may be displayed in conjunction with the image displayed in the component area.

[0010] The display device may further include: a movement driver configured to move the second display panel relative to the first display panel; and a controller configured to control the movement driver, wherein the component may be located on the second display panel and on one side of the second display area.

[0011] The mobile driver can be configured to move the second display panel according to a command of the controller so that the component corresponds to the component area when the component is operated, and the mobile driver can move the second display panel according to a command of the controller so that the second display area corresponds to the component area when the component is not operated.

[0012] The component area may include a first component area and a second component area, and at least one of a resolution and a pixel arrangement structure of the first component area may be different from a resolution and a pixel arrangement structure of the second component area.

[0013] The first display element may include a first auxiliary display element and a second auxiliary display element in the component area, wherein a thickness of a first pixel electrode of the first auxiliary display element may be greater than a thickness of a second pixel electrode of the second auxiliary display element, and the first pixel electrode may include a reflective layer.

[0014] The first display element may include a first auxiliary display element in the component area, the first auxiliary display element including a pixel electrode, the pixel electrode including a first pixel electrode portion and a second pixel electrode portion, wherein the first pixel electrode portion and the second pixel electrode portion may have different thicknesses, and wherein the first pixel electrode portion may include a stacked first transparent electrode layer, a reflective layer, and a second transparent electrode layer, and the second pixel electrode portion may extend from the first transparent electrode layer.

[0015] The second display element may include an inorganic light emitting diode, and each of the inorganic light emitting diodes may be arranged between the first electrode and the second electrode, which may be located at different layers.

[0016] The second display element may include an inorganic light emitting diode, and each of the inorganic light emitting diodes may be arranged between the first electrode and the second electrode, which may be located at the same layer.

[0017] The component may include a first component and a second component configured to perform different functions, and the first component and the second component may be located at the same substrate.

[0018] The components may include one or more of an imaging device, an infrared sensor, a solar cell, and / or a flash.

[0019] The resolution of the main display area can be greater than the resolution of the component area.

[0020] The first display panel may include a substrate and a bottom metal layer disposed between the substrate and some of the first display elements, and the bottom metal layer may define a bottom hole corresponding to at least a portion of the component area.

[0021] According to one or more embodiments, a display panel includes: a substrate including a main display area and a component area; a main display element arranged in the main display area; and auxiliary display elements arranged in the component area, wherein the auxiliary display elements include a first auxiliary display element and a second auxiliary display element, a thickness of a first pixel electrode of the first auxiliary display element is greater than a thickness of a second pixel electrode of the second auxiliary display element, and the first pixel electrode may include a reflective layer.

[0022] A pixel arrangement structure of a main sub-pixel including a main display element may be the same as a pixel arrangement structure of an auxiliary sub-pixel including an auxiliary display element.

[0023] A first subpixel including one or more of the first auxiliary display elements may be smaller than a second subpixel including one or more of the second auxiliary display elements and configured to display the same color as the first subpixel.

[0024] The first auxiliary display element and the second auxiliary display element may be provided as one body, the first pixel electrode may include a first transparent electrode layer, a reflective layer, and a second transparent electrode layer, and the second pixel electrode may extend from the first transparent electrode layer.

[0025] The display panel may further include a bottom metal layer disposed between the substrate and the first auxiliary display element, wherein the bottom metal layer may define a bottom hole corresponding to the second auxiliary display element.

[0026] The resolution of the main display area can be greater than the resolution of the component area. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects and features of the embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a perspective view of a display device according to an embodiment;

[0029] Figure 2 is a cross-sectional view of a portion of a display device according to an embodiment;

[0030] Figure 3 Can be included in Figure 1 A plan view of a display panel in a display device;

[0031] Figure 4A and Figure 4Bis a diagram of a pixel circuit according to an embodiment of the present disclosure;

[0032] Figure 5 is a plan view of a pixel arrangement structure applicable to a main display area of ​​a display panel according to an embodiment;

[0033] FIG. 6A to FIG. 6D is a plan view of a pixel arrangement structure applicable to a component area of ​​a display panel according to various embodiments;

[0034] Figure 7 is a cross-sectional view of a portion of a display panel according to an embodiment;

[0035] Figure 8 According to one embodiment, Figure 6C A cross-sectional view of a component area of ​​a display panel taken along line II';

[0036] Fig. 9 According to another embodiment, Figure 6C A cross-sectional view of a component area of ​​a display panel taken along line II';

[0037] Fig.10 is a plan view of a display device according to an embodiment;

[0038] Fig.11A and Fig. 11B is a cross-sectional view of a portion of a display device according to an embodiment of the present disclosure;

[0039] Fig.12 Is applicable to Fig.11A and Fig. 11B a plan view of a second display panel;

[0040] Fig.13A and Fig. 13B is a cross-sectional view of a portion of a display device according to another embodiment;

[0041] Fig.14A and Fig. 14B Is applicable to Fig.13A and Fig. 13B A plan view of an embodiment of a second display panel;

[0042] Fig.15 is a plan view of a second display area of ​​a second display panel according to an embodiment;

[0043] Fig.16 It is along Fig.15 A cross-sectional view taken along line II-II';

[0044] Fig.17 and Fig.18 is a plan view of a second display area of ​​a second display panel according to another embodiment of the present disclosure;

[0045] Fig.19 yes Fig.17 and Fig.18 A perspective view of a light emitting diode;

[0046] Fig. 20 It is along Fig.17 An example of a cross-sectional view taken along line III-III'; and

[0047] Fig.21 is a cross-sectional view of a portion of a display device according to an embodiment. DETAILED DESCRIPTION

[0048] Now will make detailed reference to embodiment, the example of embodiment is shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this respect, the present embodiment can have different forms, and should not be construed as being limited to the description set forth herein. Therefore, the embodiment is described below only by reference to the accompanying drawings to explain the aspects of this specification. As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. Throughout the disclosure, the statement "at least one of a, b and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or variations thereof.

[0049] Hereinafter, the present embodiment is described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are given to the same or corresponding elements, and their repeated description may be omitted.

[0050] It will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, the layer, region, or component may be directly or indirectly formed on the other layer, region, or component. That is, for example, there may be intermediate layers, regions, or components. For ease of explanation, the size of the elements in the drawings may be exaggerated or reduced. In other words, because the size and thickness of the components in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0051] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part discussed below may be named as the second element, component, region, layer or part.

[0052] For ease of explanation, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship between one element or feature and another (other) element or feature as shown in the figure. It will be understood that, in addition to the orientation shown in the figure, the spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as "below" or "below" or "below" other elements or features will then be positioned as "above" other elements or features. Therefore, the example terms "below" and "below" can cover both above and below orientations. The device can be positioned otherwise (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0053] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0054] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limitations of the present disclosure. As used herein, the singular forms "one" and "a (kind / person)" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "include", "comprise" and their variations are used in this specification, the stated features, wholes, steps, operations, elements, components and / or their groups are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups is not excluded.

[0055] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the term "using" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively. In addition, the term "exemplary" is intended to refer to an example or illustration.

[0056] The electronic device or electrical device and / or any other related device or component according to the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform various functions described herein. Computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as a random access memory (RAM) as an example). Computer program instructions can also be stored in other non-transient computer-readable media (such as a CD-ROM, a flash drive, etc. as an example). In addition, those skilled in the art should recognize that, without departing from the spirit and scope of the exemplary embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed across one or more other computing devices.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0058] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0059] Figure 1 is a perspective view of a display device 1 according to the embodiment.

[0060] Reference Figure 1 , the display device 1 includes a display area DA and a peripheral area DPA outside the display area DA. The display area DA includes a component area CA and a main display area MDA at least partially surrounding the component area CA. That is, the component area CA and the main display area MDA can display images separately or together. The peripheral area DPA may be a region where no display elements (e.g., Figure 2The display area DA may be completely surrounded by the peripheral area DPA.

[0061] exist Figure 1 1 shows that one component area CA is located inside the main display area MDA. In another embodiment, the display device 1 may include two or more component areas CA, and the shapes and sizes of the plurality of component areas CA may be different from each other. When viewed in a direction substantially perpendicular to the top surface of the display device 1, the component area CA may have various shapes, such as a circle, an ellipse, a polygon including a quadrilateral, a star shape, and a diamond shape. In addition, although in Figure 1 , when viewed in a direction approximately perpendicular to the top surface of the display device 1, the component area CA is arranged in the center of the top (+y direction) of the main display area MDA having a substantially quadrilateral shape, but the component area CA can be arranged on one side of the main display area MDA having a quadrilateral shape (for example, the top right side or the top left side of the main display area MDA).

[0062] The display device 1 may display an image by using a plurality of main sub-pixels Pm arranged in the main display area MDA and a plurality of auxiliary sub-pixels Pa arranged in the component area CA.

[0063] As shown below Figure 2 As described, the component 40 may be arranged below the component area CA. The component 40 may be a camera using infrared light or visible light, and may include an imaging device. Optionally, the component 40 may include a solar cell, a flash, an illumination sensor, a proximity sensor, and / or an iris sensor. Optionally, the component 40 may include the ability to receive sound. In order to minimize or reduce functional restrictions on the component 40, the component area CA may include a transmission area TA, and light and / or sound output from the component 40 to the outside or traveling from the outside toward the component 40 may pass through the transmission area TA. According to an embodiment, in a display panel and a display device 1 including the display panel, when light is transmitted through the component area CA, its transmittance may be 10% or more, more preferably, 25% or more, 40% or more, 50% or more, 85% or more, or 90% or more.

[0064] A plurality of auxiliary sub-pixels Pa may be arranged in the component area CA. The plurality of auxiliary sub-pixels Pa may display an image, such as a predetermined image, by emitting light. The image displayed in the component area CA is an auxiliary image and may have a resolution lower than that of the image displayed in the main display area MDA. That is, the component area CA includes a transmission area TA through which light and sound may pass, and in the case where the sub-pixels are not arranged in the transmission area TA, the number of auxiliary sub-pixels Pa that may be arranged per unit area in the component area CA may be less than the number of main sub-pixels Pm that may be arranged per unit area in the main display area MDA.

[0065] Figure 2 is a cross-sectional view of a portion of the display device 1 according to the embodiment.

[0066] Reference Figure 2 The display device 1 may include a display panel 10, a window 50 on the display panel 10, and a component 40 as an electronic component corresponding to the component area CA. The display panel 10 may include a display element, and the component 40 may be located below the display panel 10.

[0067] The display panel 10 may include a substrate 100, a display layer DISL on the substrate 100, a thin film encapsulation layer TFEL on the display layer DISL, and a light function layer PF. The thin film encapsulation layer TFEL may be used as a sealing member for sealing the display layer DISL. In addition, the display panel 10 may further include a panel bottom cover PB, and the panel bottom cover PB may be disposed under the substrate 100.

[0068] The substrate 100 may include an insulating material such as glass, quartz and / or a polymer resin. The substrate 100 may be a rigid substrate or a bendable, foldable and / or rollable flexible substrate.

[0069] The display layer DISL may include a circuit layer, a display element layer, and insulating layers IL and IL′. The circuit layer includes thin film transistors TFT and TFT′ on the substrate 100 . The display element layer includes an organic light emitting diode OLED as a display element.

[0070] The main thin film transistor TFT and the organic light emitting diode OLED connected thereto may be arranged in the main display area MDA of the display panel 10 to implement the main sub-pixel Pm. The auxiliary thin film transistor TFT' and the auxiliary organic light emitting diode OLED' connected thereto may be arranged in the component area CA of the display panel 10 to implement the auxiliary sub-pixel Pa.

[0071] In addition, the transmission area TA may be disposed in the assembly area CA. The transmission area TA may be an area through which light / sound emitted from or incident to the assembly 40, which is disposed to correspond to the assembly area CA, may pass.

[0072] The bottom metal layer BML may be disposed in the component area CA. The bottom metal layer BML may be disposed below the auxiliary thin film transistor TFT'. The bottom metal layer BML may block external light from reaching the auxiliary thin film transistor TFT', etc. For example, the bottom metal layer BML may block light (light emitted from the component 40) from reaching the pixel circuit PC driving the auxiliary sub-pixel Pa (e.g., Figure 4A and Figure 4B In an embodiment, a constant voltage or signal may be applied to the bottom metal layer BML to reduce or prevent the pixel circuit PC from being damaged by electrostatic discharge.

[0073] The thin film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 2 A first inorganic encapsulating layer 131 and a second inorganic encapsulating layer 133 are shown with an organic encapsulating layer 132 therebetween.

[0074] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may include at least one inorganic insulating material of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 340 may include a polymer material. The polymer material may include an acryl resin, an epoxy resin, polyimide, and polyethylene.

[0075] The panel cover bottom PB may be attached to the back side of the substrate 100 to support and protect the substrate 100. The panel cover bottom PB may include an opening PB_OP corresponding to the assembly area CA. The panel cover bottom PB may improve the light transmittance of the assembly area CA by including the opening PB_OP. The panel cover bottom PB may include polyethylene terephthalate (PET) or polyimide (PI).

[0076] The area of ​​the assembly area CA may be greater than the area of ​​the area in which the assembly 40 is arranged. Therefore, the area of ​​the opening PB_OP of the panel bottom cover PB may not coincide with the area of ​​the assembly 40.

[0077] In addition, a plurality of components 40 may be arranged in the component area CA. The functions of the plurality of components 40 may be different from each other. For example, the plurality of components 40 may include at least two of a camera (imaging device), a solar cell, a flash, a proximity sensor, an illumination sensor, and an iris sensor.

[0078] The light function layer PF may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside to the display device 1 (or incident on the display device 1).

[0079] In an embodiment, the anti-reflection layer may include an optical plate, the optical plate including a retarder and / or a polarizer. The retarder may include a film-type retarder or a liquid crystal retarder. The retarder may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may include a film-type polarizer or a liquid crystal polarizer. The film-type polarizer may include a stretched synthetic resin film, and the liquid crystal polarizer may include liquid crystals arranged in a predetermined arrangement. In an embodiment, the anti-reflection layer may include a black matrix and a color filter.

[0080] The window 50 may be disposed on the top surface of the display panel 10 to cover the top surface of the display panel 10. Thus, the window 50 may protect the top surface of the display panel 10.

[0081] In some embodiments, a touch electrode layer may be further arranged between the thin film encapsulation layer TFEL and the optical function layer PF, and the touch electrode layer senses touch input. Although the thin film encapsulation layer TFEL is shown as a sealing member in the present embodiment, the embodiment is not limited thereto. For example, a sealing substrate attached to the substrate 100 using a sealant or glass frit may be used as a member for sealing the display layer DISL.

[0082] Figure 3 Can be included in Figure 1 FIG. 1 is a plan view of a display panel 10 in a display device of FIG. 1 . In an exemplary embodiment, the plan view is an orthogonal projection looking down at the display device 1 .

[0083] Reference Figure 3 , various elements constituting the display panel 10 are arranged on a substrate 100. The substrate 100 includes a display area DA and a peripheral area DPA surrounding the display area DA. The display area DA includes a main display area MDA and an assembly area CA, the main display area MDA displays a main image, and the assembly area CA includes a transmission area TA and displays an auxiliary image. The auxiliary image may form a complete image in conjunction with the main image, or may be an image independent of the main image.

[0084] A plurality of main sub-pixels Pm are arranged in the main display area MDA. Each of the main sub-pixels Pm may be implemented by using a display element such as an organic light emitting diode OLED. Each main sub-pixel Pm may be defined as an emission area of ​​an organic light emitting diode OLED arranged in the main display area MDA, and may emit red light, green light, blue light, or white light. The main display area MDA may be covered by a sealing member and protected from external air or moisture, etc.

[0085] The component area CA may be located on one side of the main display area MDA. A plurality of auxiliary sub-pixels Pa are arranged in the component area CA. Each of the plurality of auxiliary sub-pixels Pa may be implemented by using a display element such as an organic light emitting diode OLED. Each auxiliary sub-pixel Pa may be defined as an emission area of ​​an organic light emitting diode OLED arranged in the component area CA, and may emit red light, green light, blue light, or white light. The component area CA may be covered by a sealing member and protected from external air or moisture, etc.

[0086] The assembly area CA may include a transmission area TA. The transmission area TA may surround the plurality of auxiliary sub-pixels Pa. Alternatively, the transmission area TA and pixel groups may be arranged in a lattice configuration, the pixel groups including pixels from the plurality of auxiliary sub-pixels Pa.

[0087] Because the component area CA includes the transmissive area TA, the resolution of the component area CA may be smaller than the resolution of the main display area MDA. For example, the resolution of the component area CA may be 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, or 1 / 16 of the resolution of the main display area MDA. For example, the resolution of the main display area MDA may be about 400 ppi or more, and the resolution of the component area CA may be about 200 ppi or more or about 100 ppi.

[0088] The pixel circuit PC (for example, in the Figure 4A and Figure 4B The pixel circuit PC shown in FIG. 1 may be electrically connected to an external circuit arranged in the peripheral area DPA. The first scan driving circuit SDRV1, the second scan driving circuit SDRV2, the terminal unit PAD, the driving voltage supply line 11, and the common voltage supply line 13 may be arranged in the peripheral area DPA.

[0089] The first scan drive circuit SDRV1 may apply a scan signal to each of the pixel circuits PC through the scan lines SL, and the pixel circuits PC drive sub-pixels (i.e., the main sub-pixel Pm and the auxiliary sub-pixel Pa). The first scan drive circuit SDRV1 may apply an emission control signal to each pixel circuit PC through the emission control line EL. The second scan drive circuit SDRV2 may be located on the opposite side of the first scan drive circuit SDRV1, and the main display area MDA is between them. The second scan drive circuit SDRV2 may be substantially parallel to the first scan drive circuit SDRV1. Some of the pixel circuits PC of the main sub-pixels Pm in the main display area MDA may be electrically connected to the first scan drive circuit SDRV1, and the remaining pixel circuits PC of the pixel circuits PC of the main sub-pixels Pm in the main display area MDA may be electrically connected to the second scan drive circuit SDRV2. Some of the pixel circuits PC of the auxiliary sub-pixels Pa in the component area CA may be electrically connected to the first scan drive circuit SDRV1, and the remaining pixel circuits PC of the pixel circuits PC of the auxiliary sub-pixels Pa in the component area CA may be electrically connected to the second scan drive circuit SDRV2. In some embodiments, the second scan drive circuit SDRV2 may be omitted.

[0090] The terminal unit PAD may be disposed on one side of the substrate 100. The terminal unit PAD is exposed without being covered by the insulating layer and is connected to the display circuit board 31. The display driver 32 may be disposed on the display circuit board 31. The display driver 32 may generate a control signal transmitted to the first scan driving circuit SDRV1 and the second scan driving circuit SDRV2. In addition, for example, Figure 4A and Figure 4B As shown in , the display driver 32 may supply a driving voltage ELVDD to the driving voltage supply line 11, and a common voltage ELVSS to the common voltage supply line 13. The driving voltage ELVDD may be applied to the pixel circuit PC of the sub-pixel (i.e., the main sub-pixel Pm and the auxiliary sub-pixel Pa) through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS may be applied to the counter electrode of the display element (e.g., the organic light emitting diode OLED) through the common voltage supply line 13. The display driver 32 generates a data signal, and the generated data signal may be transmitted to the pixel circuit PC of the sub-pixel (i.e., the main sub-pixel Pm and the auxiliary sub-pixel Pa) through the fan-out wiring FW and the data line DL connected to the fan-out wiring FW.

[0091] The driving voltage supply line 11 may extend in the x direction under the main display area MDA. The common voltage supply line 13 may have a ring shape having one open side and partially surrounding the main display area MDA.

[0092] Figure 4A and Figure 4B is a diagram of an embodiment of a pixel circuit PC for driving sub-pixels (ie, a main sub-pixel Pm and an auxiliary sub-pixel Pa) according to an embodiment of the present disclosure.

[0093] Reference Figure 4A , the pixel circuit PC can be connected to the organic light emitting diode OLED, and can realize the light emission of the sub-pixel. The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2 and a storage capacitor Cst. The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and transmits the data signal Dm input through the data line DL to the driving thin film transistor T1 in response to the scan signal Sn input through the scan line SL.

[0094] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage transmitted from the switching thin film transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0095] The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current I flowing from the driving voltage line PL through the organic light emitting diode OLED in response to the voltage stored in the storage capacitor Cst. OLED The organic light emitting diode OLED can be driven by using a driving current I OLED To emit light with a predetermined brightness.

[0096] although Figure 4A A case where the pixel circuit PC includes two thin film transistors and one storage capacitor is described, but the present disclosure is not limited thereto.

[0097] Reference Figure 4B In the embodiment, the pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6 and a second initialization thin film transistor T7.

[0098] although Figure 4B The case where each pixel circuit PC includes signal lines SL, SL-1, EL and DL, initialization voltage line VL and drive voltage line PL is shown, but the present disclosure is not limited thereto. In another embodiment, at least one of the signal lines SL, SL-1, EL and DL and the initialization voltage line VL can be shared by pixels adjacent to each other.

[0099] The drain electrode of the driving thin film transistor T1 can be electrically connected to the organic light emitting diode OLED through the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin film transistor T2, and converts the driving current I OLED Supply to the organic light emitting diode OLED.

[0100] The gate electrode of the switching thin film transistor T2 is connected to the scan line SL, the source electrode of the switching thin film transistor T2 is connected to the data line DL, the drain electrode of the switching thin film transistor T2 is connected to the source electrode of the driving thin film transistor T1, and is connected to the driving voltage line PL through the operation control thin film transistor T5.

[0101] The switching thin film transistor T2 is turned on in response to the scan signal Sn transmitted through the scan line SL, and performs a switching operation to transmit the data signal Dm transmitted through the data line DL to the source electrode of the driving thin film transistor T1 .

[0102] The gate electrode of the compensation thin film transistor T3 may be connected to the scan line SL. The source electrode of the compensation thin film transistor T3 may be connected to the drain electrode of the driving thin film transistor T1, and is connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The drain electrode of the compensation thin film transistor T3 may be connected to one of the electrodes of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and the driving thin film transistor T1 is diode-connected by connecting the gate electrode of the driving thin film transistor T1 to the drain electrode of the driving thin film transistor T1.

[0103] The gate electrode of the first initialization thin film transistor T4 may be connected to the previous scan line SL-1. The drain electrode of the first initialization thin film transistor T4 may be connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 may be connected to one of the electrodes of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and may perform an initialization operation of initializing the voltage of the gate electrode of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the gate electrode of the driving thin film transistor T1.

[0104] The gate electrode of the operation control thin film transistor T5 may be connected to the emission control line EL. The source electrode of the operation control thin film transistor T5 may be connected to the driving voltage line PL. The drain electrode of the operation control thin film transistor T5 is connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0105] The gate electrode of the emission control thin film transistor T6 may be connected to the emission control line EL. The source electrode of the emission control thin film transistor T6 may be connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the emission control thin film transistor T6 may be electrically connected to the pixel electrode of the organic light emitting diode OLED. The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL, and then the driving voltage ELVDD is transmitted to the organic light emitting diode OLED, and the driving current I OLED Flow through the organic light emitting diode OLED.

[0106] The gate electrode of the second initialization thin film transistor T7 may be connected to the previous scan line SL-1. The source electrode of the second initialization thin film transistor T7 may be connected to the pixel electrode of the organic light emitting diode OLED. The drain electrode of the second initialization thin film transistor T7 may be connected to the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and may initialize the pixel electrode of the organic light emitting diode OLED.

[0107] although Figure 4B The case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1 is shown, but the present disclosure is not limited thereto. In some embodiments, the first initialization thin film transistor T4 may be connected to the previous scan line SL-1 and driven in response to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., the next scan line) and driven in response to a signal transmitted through the separate signal line.

[0108] The other electrode of the storage capacitor Cst may be connected to the driving voltage line PL. The one of the electrodes of the storage capacitor Cst may be connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4.

[0109] The counter electrode (eg, cathode) of the organic light emitting diode OLED receives the common voltage ELVSS. The organic light emitting diode OLED receives the driving current I from the driving thin film transistor T1. OLED And glow.

[0110] The number of thin film transistors, the number of storage capacitors and the circuit design are not limited to the reference Figure 4A and Figure 4BThe pixel circuit PC described above may be modified into other various suitable forms as understood by those skilled in the art.

[0111] The same pixel circuit PC or different pixel circuits PC may be applied to the main sub-pixel Pm and the auxiliary sub-pixel Pa, and the pixel circuit PC drives the main sub-pixel Pm and the auxiliary sub-pixel Pa. For example, the pixel circuit PC driving the main sub-pixel Pm and the auxiliary sub-pixel Pa may include Figure 4B The pixel circuit PC shown in FIG. In other embodiments, Figure 4B The pixel circuit PC shown in FIG. 1 is used as the pixel circuit PC for driving the main sub-pixel Pm, and can be used Figure 4A The pixel circuit PC shown in FIG. 1 serves as the pixel circuit PC for driving the auxiliary sub-pixel Pa. FIG.

[0112] Figure 5 is a plan view of a pixel arrangement (or arrangement) structure applicable to a main display area MDA of a display panel 10 according to an embodiment.

[0113] A plurality of main sub-pixels Pm may be arranged in the main display area MDA. In this specification, a sub-pixel is the smallest unit for realizing an image and refers to an emission area. In the case where an organic light emitting diode OLED is used as a display element, the emission area may be defined by an opening of a pixel defining layer.

[0114] like Figure 5 As shown in FIG. 1 , the main sub-pixels Pm arranged in the main display area MDA may be Structural layout. is a registered trademark of Samsung Display Co., Ltd. The red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb may emit red light, green light, and blue light, respectively.

[0115] A plurality of red sub-pixels Pr and a plurality of blue sub-pixels Pb are alternately arranged on a first row 1N, a plurality of green sub-pixels Pg are separated from each other at predetermined intervals on an adjacent second row 2N, a plurality of blue sub-pixels Pb and a plurality of red sub-pixels Pr are alternately arranged on an adjacent third row 3N, and a plurality of green sub-pixels Pg are separated from each other at predetermined intervals on an adjacent fourth row 4N. This pixel arrangement is repeated until the Nth row. In this case, the blue sub-pixel Pb and the red sub-pixel Pr may be larger than the green sub-pixel Pg.

[0116] A plurality of red sub-pixels Pr and a plurality of blue sub-pixels Pb on the first row 1N and a plurality of green sub-pixels Pg on the second row 2N may be arranged alternately. Thus, a plurality of red sub-pixels Pr and a plurality of blue sub-pixels Pb are alternately arranged on the first column 1M, a plurality of green sub-pixels Pg are separated from each other at predetermined intervals on the adjacent second column 2M, a plurality of blue sub-pixels Pb and a plurality of red sub-pixels Pr are alternately arranged on the adjacent third column 3M, and a plurality of green sub-pixels Pg are separated from each other at predetermined intervals on the adjacent fourth column 4M. This pixel arrangement is repeated until the Mth column.

[0117] When the pixel arrangement structure is expressed differently, in a virtual quadrilateral VS having the center point of the green subpixel Pg at its center point, the red subpixel Pr is arranged at the first and third vertices facing each other of the virtual quadrilateral VS, and the blue subpixel Pb is arranged at the second and fourth vertices as the remaining vertices. In this case, the virtual quadrilateral VS may include a rectangle, a rhombus, a square, etc., and may be variously modified.

[0118] This pixel arrangement is referred to herein as Matrix structure or structure, and by adopting a rendering driver that presents colors by sharing adjacent pixels, high resolution can be achieved with a small number of pixels.

[0119] Despite Figure 5 A plurality of main sub-pixels Pm are shown in FIG. The plurality of main sub-pixels Pm may be arranged in a matrix structure, but the embodiment is not limited thereto. For example, the plurality of main sub-pixels Pm may be arranged in various structures such as a stripe structure, a mosaic structure, a delta arrangement structure, etc.

[0120] FIG. 6A to FIG. 6D is a plan view of a pixel arrangement structure in an assembly area CA according to various embodiments.

[0121] Reference Fig. 6A , a plurality of auxiliary sub-pixels Pa may be arranged in the component area CA as shown. Each of the plurality of auxiliary sub-pixels Pa may emit red light, green light, blue light, or white light.

[0122] The assembly area CA may include a pixel group PG and a transmission area TA, the pixel group PG including at least one auxiliary sub-pixel Pa. The pixel group PG and the transmission area TA may be alternately arranged in the x-direction and the y-direction in a lattice configuration, for example. Fig. 6A In the embodiment shown in , the assembly area CA includes a plurality of pixel groups PG and a plurality of transmission areas TA.

[0123] The pixel group PG may be defined as a sub-pixel set in which a plurality of auxiliary sub-pixels Pa are grouped in predetermined units. Fig. 6A FIG. 4 shows that a pixel group PG includes eight auxiliary sub-pixels Pa. Fig. 6A FIG. 4 shows a pixel group PG including two red sub-pixels Pr, four green sub-pixels Pg and two blue sub-pixels Pb. Structural layout.

[0124] The basic unit U may be repeatedly arranged in the x direction and the y direction in the assembly area CA, and a predetermined number of pixel groups PG and a predetermined number of transmission areas TA are grouped in the basic unit U. Fig. 6A In the example, the basic unit U may have a configuration in which two pixel groups PG and two transmission areas TA around the two pixel groups PG are grouped into a quadrangle. The basic unit U divides a repeated shape without meaning a disconnection of the configuration.

[0125] For example, Figure 5 As shown in , a corresponding unit U' may be provided in the main display area MDA, the corresponding unit U' having the same area as that of the basic unit U. In this case, the number of main sub-pixels Pm included in the corresponding unit U' may be greater than the number of auxiliary sub-pixels Pa included in the basic unit U. That is, in one embodiment, the number of auxiliary sub-pixels Pa included in the basic unit U may be 16, and the number of main sub-pixels Pm included in the corresponding unit U' may be 32. The number of auxiliary sub-pixels Pa and the number of main sub-pixels Pm per the same area may be provided at a ratio of 1:2.

[0126] like Fig. 6A As shown in FIG. 1 , the arrangement structure of the auxiliary sub-pixels Pa in the component area CA is The pixel arrangement structure in which the resolution of the component area CA is 1 / 2 of the resolution of the main display area MDA is referred to herein as structure.

[0127] Reference Figure 6B , the pixel arrangement structure of the auxiliary sub-pixel Pa in the component area CA may be a stripe structure. That is, the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb may be arranged in parallel in the x direction. In this case, the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb may all have long sides in the y direction. Figure 6B Differently, the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb may be arranged in parallel in the y direction. In this case, the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb may each have a long side in the x direction.

[0128] like Figure 6BAs shown in , the shape and size of the auxiliary sub-pixel Pa may be different from the shape and size of the main sub-pixel Pm. For example, the size of the red sub-pixel Pr among the auxiliary sub-pixels Pa may be larger than the size of the red sub-pixel Pr among the main sub-pixels Pm. In addition, the area occupied by the pixel group PG in the basic unit U may be 1 / 4 of the area of ​​the basic unit U, and the remaining area may be set as the transmission area TA.

[0129] The number of auxiliary sub-pixels Pa included in the pixel group PG or the arrangement of the auxiliary sub-pixels Pa may be changed according to the desired resolution of the component area CA. For example, the auxiliary sub-pixels Pa may be arranged in a stripe structure, a mosaic structure, a triangle structure, etc., and the resolution of the component area CA may be 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, 1 / 16, etc. of the resolution of the main display area MDA.

[0130] Reference Figure 6C , the auxiliary sub-pixel Pa arranged in the component area CA may include a first auxiliary sub-pixel Pa1 and a second auxiliary sub-pixel Pa2 implemented by display elements having different transmittances. For example, the pixel electrode of the display element implementing the first auxiliary sub-pixel Pa1 may include a reflective layer, and the pixel electrode of the display element implementing the second auxiliary sub-pixel Pa2 may include a transparent electrode. Therefore, the area in which the second pixel group PG2 including the second auxiliary sub-pixel Pa2 is arranged may be a semi-transmission area STA that partially transmits light. That is, the semi-transmission area STA may be defined as an area having a higher transmittance than the transmittance of the area in which the first pixel group PG1 is arranged and having a lower transmittance than the transmittance of the transmission area TA, the first pixel group PG1 including the first auxiliary sub-pixel Pa1, and the auxiliary sub-pixel Pa is not arranged in the transmission area TA. Because the second pixel group PG2 is arranged, the transmittance of the component area CA can be ensured, and at the same time, the resolution of the component area CA can be improved.

[0131] Despite Figure 6C 1 shows that the transmission area TA is arranged in the assembly area CA, but in an embodiment in which the semi-transmission area STA is arranged, the transmission area TA may not be provided. The shape and pixel arrangement structure of the second auxiliary sub-pixel Pa2 arranged in the semi-transmission area STA may be variously changed. For example, the first auxiliary sub-pixel Pa1 may be arranged in Structural arrangement: the second auxiliary sub-pixels Pa2 may be arranged in a stripe structure.

[0132] Reference Fig.6D, the auxiliary sub-pixel Pa arranged in the component area CA may include a first auxiliary sub-pixel Pa1 and a second auxiliary sub-pixel Pa2 implemented by display elements having different transmittances. For example, the pixel electrode of the display element implementing the first auxiliary sub-pixel Pa1 may include a reflective layer, and the pixel electrode of the display element implementing the second auxiliary sub-pixel Pa2 may include a transparent electrode. In this embodiment, the size W_Pa1 of the first auxiliary sub-pixel Pa1 may be smaller than the size W_Pa2 of the second auxiliary sub-pixel Pa2 that produces the same color. Under the same conditions, the brightness of the second auxiliary sub-pixel Pa2 may be smaller than the brightness of the first auxiliary sub-pixel Pa1, and the brightness of the first auxiliary sub-pixel Pa1 may be adjusted by reducing the size of the first auxiliary sub-pixel Pa1.

[0133] Figure 7 is a cross-sectional view of the display panel 10 according to the embodiment, including a cross-sectional view of the main display area MDA and the assembly area CA.

[0134] Reference Figure 7 , the display panel 10 includes a main display area MDA and an assembly area CA. The main sub-pixel Pm is arranged in the main display area MDA, and the auxiliary sub-pixel Pa and the transmission area TA are arranged in the assembly area CA.

[0135] The main display area MDA may include a main thin film transistor TFT and a main storage capacitor Cst included in the main pixel circuit PC and an organic light emitting diode OLED arranged as a main display element. The component area CA may include an auxiliary thin film transistor TFT' and an auxiliary storage capacitor Cst' included in the auxiliary pixel circuit PC' and an auxiliary organic light emitting diode OLED' arranged as an auxiliary display element. The display panel 10 may include a transmission hole TAH corresponding to the transmission area TA.

[0136] Hereinafter, a structure in which elements included in the display panel 10 are stacked is described.

[0137] As described above, substrate 100 may include insulating materials such as glass, quartz and polymer resins. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate and / or cellulose acetate propionate. The substrate 100 may be a rigid substrate or a flexible substrate that is bendable, foldable and / or rollable. The substrate 100 may have a multilayer structure including a layer containing a polymer resin and an inorganic layer.

[0138] The buffer layer 111 may be located on the substrate 100, reduce or block the penetration of foreign matter, moisture or external air from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material (such as an oxide or a nitride), an organic material, or an organic / inorganic composite material, and may include a single layer or multiple layers including an inorganic material and an organic material. A barrier layer may also be arranged between the substrate 100 and the buffer layer 111, the barrier layer blocking the penetration of external air. In some embodiments, the buffer layer 111 may include silicon oxide (SiO 2 ) or silicon nitride (SiN x ). The buffer layer 111 may include a first buffer layer 111 a and a second buffer layer 111 b that are stacked.

[0139] The bottom metal layer BML may be disposed between the first buffer layer 111a and the second buffer layer 111b in the component area CA. In other embodiments, the bottom metal layer BML may be disposed between the substrate 100 and the first buffer layer 111a. The bottom metal layer BML may be disposed under the auxiliary thin film transistor TFT' to reduce or prevent the auxiliary thin film transistor TFT' from being degraded by light emitted from a component or the like.

[0140] In addition, the bottom metal layer BML can be connected to the line GCL arranged on different layers through a contact hole. The bottom metal layer BML can receive a constant voltage or signal from the line GCL. For example, the bottom metal layer BML can receive a driving voltage ELVDD or a scan signal (e.g., a scan signal Sn). Because the bottom metal layer BML receives a constant voltage or signal, the possibility of electrostatic discharge can be significantly reduced. The bottom metal layer BML may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu). The bottom metal layer BML may include a single layer or multiple layers containing the above materials.

[0141] In some embodiments, the bottom metal layer BML may correspond to the assembly area CA. In this case, the bottom metal layer BML may include a bottom hole BMLH overlapping the transmission area TA. In some embodiments, the shape and size of the transmission area TA may be defined by the shape and size of the bottom hole BMLH.

[0142] The main thin film transistor TFT and the auxiliary thin film transistor TFT' may be arranged on the buffer layer 111. The main thin film transistor TFT may include a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1, and the auxiliary thin film transistor TFT' may include a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main thin film transistor TFT may be connected to the organic light emitting diode OLED of the main display area MDA to drive the organic light emitting diode OLED. The auxiliary thin film transistor TFT' may be connected to the auxiliary organic light emitting diode OLED' of the assembly area CA to drive the auxiliary organic light emitting diode OLED'.

[0143] The first semiconductor layer A1 and the second semiconductor layer A2 may be arranged on the buffer layer 111 and may include polycrystalline silicon. In other embodiments, the first semiconductor layer A1 and the second semiconductor layer A2 may include amorphous silicon. In other embodiments, the first semiconductor layer A1 and the second semiconductor layer A2 may include an oxide semiconductor, and the oxide semiconductor includes at least one oxide of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti) and zinc (Zn). The first semiconductor layer A1 and the second semiconductor layer A2 may include a channel region, a source region and a drain region, and the source region and the drain region are doped with impurities.

[0144] The second semiconductor layer A2 may overlap the bottom metal layer BML with the second buffer layer 111b therebetween. In some embodiments, the width of the second semiconductor layer A2 may be less than the width of the bottom metal layer BML. Therefore, when viewed in a direction perpendicular to the substrate 100, the second semiconductor layer A2 may completely overlap the bottom metal layer BML.

[0145] The first gate insulating layer 112 may cover the first semiconductor layer A1 and the second semiconductor layer A2. The first gate insulating layer 112 may include an inorganic insulating material such as silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or zinc oxide (ZnO 2 ). The first gate insulating layer 112 may include a single layer or a plurality of layers including an inorganic insulating material.

[0146] The first gate electrode G1 and the second gate electrode G2 are arranged on the first gate insulating layer 112 to overlap with the first semiconductor layer A1 and the second semiconductor layer A2, respectively. The first gate electrode G1 and the second gate electrode G2 may include a single layer or multiple layers including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti). For example, the first gate electrode G1 and the second gate electrode G2 may each be a single layer including molybdenum (Mo).

[0147] The second gate insulating layer 113 may cover the first gate electrode G1 and the second gate electrode G2. The second gate insulating layer 113 may include an inorganic insulating material such as silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or zinc oxide (ZnO 2 ). The second gate insulating layer 113 may include a single layer or a plurality of layers including an inorganic insulating material.

[0148] A first top electrode CE2 of the main storage capacitor Cst and a second top electrode CE2 ′ of the auxiliary storage capacitor Cst′ may be disposed on the second gate insulating layer 113 .

[0149] The first top electrode CE2 may overlap the first gate electrode G1 below the first top electrode CE2 in the main display area MDA. The first gate electrode G1 and the first top electrode CE2 overlapping each other with the second gate insulating layer 113 therebetween may constitute a main storage capacitor Cst. The first gate electrode G1 may serve as a first bottom electrode CE1 of the main storage capacitor Cst.

[0150] The second top electrode CE2' may overlap the second gate electrode G2 below the second top electrode CE2' in the assembly area CA. The second gate electrode G2 and the second top electrode CE2' overlapping each other with the second gate insulating layer 113 therebetween may constitute an auxiliary storage capacitor Cst'. The second gate electrode G2 may serve as a second bottom electrode CE1' of the auxiliary storage capacitor Cst'.

[0151] The first top electrode CE2 and the second top electrode CE2' may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and include a single layer or a multilayer containing the above materials.

[0152] The interlayer insulating layer 115 may cover the first top electrode CE2 and the second top electrode CE2′. The interlayer insulating layer 115 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or zinc oxide (ZnO 2 ).

[0153] The first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as an inorganic insulating layer IL, and the inorganic insulating layer IL may include a first hole H1 corresponding to the transmission area TA. The first hole H1 may expose the top surface of the buffer layer 111 or the substrate 100. The first hole H1 may include an opening in each of the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115, which are overlapped with each other and correspond to the transmission area TA. The openings may be formed by separate processes, respectively, or formed concurrently (e.g., simultaneously) by the same process. In the case where the opening is formed by a separate process, the inner surface of the first hole H1 may not be smooth and may have a step difference like a step shape.

[0154] In other embodiments, the inorganic insulating layer IL may include a groove instead of the first hole H1 exposing the buffer layer 111. In other embodiments, the inorganic insulating layer IL may not include the first hole H1 or the groove corresponding to the transmission area TA. Since the inorganic insulating layer IL generally includes an inorganic insulating material having excellent light transmittance, even if the inorganic insulating layer IL does not include a hole or a groove corresponding to the transmission area TA, the inorganic insulating layer IL may have sufficient transmittance to allow the component 40 to transmit / receive a sufficient amount of light (e.g., see FIG. 1 ). Figure 2 ).

[0155] The source electrodes S1 and S2 and the drain electrodes D1 and D2 are arranged on the interlayer insulating layer 115. The source electrodes S1 and S2 and the drain electrodes D1 and D2 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and include a single layer or a multilayer including the above materials. For example, the source electrodes S1 and S2 and the drain electrodes D1 and D2 may include a multilayer structure of Ti / Al / Ti.

[0156] The first planarization layer 117 may cover the source electrodes S1 and S2 and the drain electrodes D1 and D2. The first planarization layer 117 may have a flat top surface so that the first and second pixel electrodes 121 and 121' disposed thereon are formed to be flat.

[0157] The first planarization layer 117 may include an organic material or an inorganic material and have a single-layer structure or a multi-layer structure. The first planarization layer 117 may include a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) and / or polystyrene (PS)), a polymer derivative having a phenolic group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a paraxylene-based polymer and / or a vinyl alcohol-based polymer. The first planarization layer 117 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), and / or zinc oxide (ZnO 2 After forming the first planarization layer 117, chemical mechanical polishing may be performed on a top surface of the first planarization layer 117 to provide a flat top surface.

[0158] The first planarization layer 117 may include a second hole H2 corresponding to the transmission area TA. The second hole H2 may overlap the first hole H1. Figure 7 2 shows that the second hole H2 is larger than the first hole H1. In other embodiments, the first planarization layer 117 may cover the edge of the first hole H1 of the inorganic insulating layer IL, and the area of ​​the second hole H2 may be smaller than that of the first hole H1.

[0159] The first planarization layer 117 may include an opening exposing one of the first source electrode S1 and the first drain electrode D1 of the main thin film transistor TFT, and the first pixel electrode 121 may be electrically connected to the main thin film transistor TFT by contacting the first source electrode S1 or the first drain electrode D1 through the opening. In addition, the first planarization layer 117 may include an opening exposing one of the second source electrode S2 and the second drain electrode D2 of the auxiliary thin film transistor TFT', and the second pixel electrode 121' may be electrically connected to the auxiliary thin film transistor TFT' by contacting the second source electrode S2 or the second drain electrode D2 through the opening.

[0160] The first pixel electrode 121 and the second pixel electrode 121' may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and / or aluminum zinc oxide (AZO). The first pixel electrode 121 and the second pixel electrode 121' may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and / or a compound thereof. For example, the first pixel electrode 121 and the second pixel electrode 121' may have a reflective layer containing ITO, IZO, ZnO and / or In on and / or below the reflective layer. 2 O 3 In this case, the first pixel electrode 121 and the second pixel electrode 121' may have a stack structure of ITO / Ag / ITO.

[0161] The pixel defining layer 119 may cover the edge of the first pixel electrode 121 and the second pixel electrode 121'. The pixel defining layer 119 includes a first opening OP1 and a second opening OP2 respectively overlapping the first pixel electrode 121 and the second pixel electrode 121' and defining the emission regions of the sub-pixels Pm and Pa respectively. The pixel defining layer 119 may substantially prevent or prevent arcing etc. from occurring at the edge of the pixel electrode (i.e., the first pixel electrode 121 and the second pixel electrode 121') by increasing the distance between the edge of the pixel electrode (i.e., the first pixel electrode 121 and the second pixel electrode 121') and the counter electrode 123 above the pixel electrode (i.e., the first pixel electrode 121 and the second pixel electrode 121'). The pixel defining layer 119 may include an organic insulating material including polyimide, polyamide, acrylic resin, benzocyclobutene, HMDSO and / or phenolic resin, and the pixel defining layer 119 may be formed by spin coating.

[0162] The pixel defining layer 119 may include a third hole H3 located in the transmission area TA. The third hole H3 may overlap the first hole H1 and the second hole H2. The transmittance of the transmission area TA may be improved by the first to third holes H1, H2, and H3. A portion of the counter electrode 123 described below may be arranged on the inner sidewalls of the first to third holes H1, H2, and H3.

[0163] The first emission layer 122b and the second emission layer 122b' are respectively arranged inside the first opening OP1 and the second opening OP2 of the pixel defining layer 119, and the first emission layer 122b and the second emission layer 122b' respectively correspond to the first pixel electrode 121 and the second pixel electrode 121'. The first emission layer 122b and the second emission layer 122b' may include a polymer material or a low molecular weight material, and may emit red light, green light, blue light or white light.

[0164] The organic functional layer 122e may be disposed on and / or below the first emission layer 122b and the second emission layer 122b'. The organic functional layer 122e may include the first functional layer 122a and / or the second functional layer 122c. In some embodiments, the first functional layer 122a or the second functional layer 122c may be omitted.

[0165] The first functional layer 122a may be arranged below the first emission layer 122b and the second emission layer 122b'. The first functional layer 122a may include a single layer or multiple layers including an organic material. The first functional layer 122a may include a hole transport layer (HTL) having a single layer structure. The first functional layer 122a may include a hole injection layer (HIL) and / or the HTL. In some embodiments, the first functional layer 122a may be arranged as a whole to correspond to the main sub-pixel Pm in the main display area MDA and the auxiliary sub-pixel Pa in the component area CA. Therefore, the first functional layer 122a may be arranged to correspond to the transmission area TA.

[0166] The second functional layer 122c may be arranged on the first emission layer 122b and the second emission layer 122b'. The second functional layer 122c may include a single layer or multiple layers including an organic material. The second functional layer 122c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). In some embodiments, the second functional layer 122c may be provided as a whole to correspond to the main sub-pixel Pm in the main display area MDA and the auxiliary sub-pixel Pa in the component area CA. Therefore, the second functional layer 122c may be arranged to correspond to the transmission area TA.

[0167] The counter electrode 123 is arranged on the second functional layer 122c. The counter electrode 123 may include a conductive material having a small work function. For example, the counter electrode 123 may include a (semi) transparent layer, and the (semi) transparent layer includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy thereof. In some embodiments, the counter electrode 123 may also include ITO, IZO, ZnO and / or In on / below the (semi) transparent layer containing the above materials. 2 O 3The counter electrode 123 may be provided as one body (ie, one continuous layer that may be deposited concurrently) to correspond to the main sub-pixel Pm in the main display area MDA and the auxiliary sub-pixel Pa in the assembly area CA.

[0168] The layers from the first pixel electrode 121 to the opposing electrode 123 in the main display area MDA may constitute an organic light emitting diode OLED. The layers from the second pixel electrode 121 ′ to the opposing electrode 123 in the assembly area CA may constitute an auxiliary organic light emitting diode OLED′.

[0169] A top layer 150 may be formed on the counter electrode 123, the top layer 150 including an organic material. The top layer 150 may be a layer prepared to protect the counter electrode 123 and simultaneously improve light extraction efficiency. The top layer 150 may include an organic material having a refractive index higher than that of the counter electrode 123. In some embodiments, the top layer 150 may include stacked layers having different refractive indices. For example, the top layer 150 may include a stacked high refractive index layer / low refractive index layer / high refractive index layer. In this case, the refractive index of the high refractive index layer may be 1.7 or greater, and the refractive index of the low refractive index layer may be 1.3 or less.

[0170] The top layer 150 may also include lithium fluoride (LiF). Alternatively, the top layer 150 may also include an inorganic insulating material such as silicon oxide (SiO 2 ) and / or silicon nitride (SiN x ).

[0171] The first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the roof layer 150 may each include a transmissive hole TAH corresponding to the transmissive area TA. That is, the first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the roof layer 150 may each include an opening corresponding to the transmissive area TA. The areas of the openings may be substantially the same. For example, the area of ​​the opening of the counter electrode 123 may be substantially the same as the area of ​​the transmissive hole TAH.

[0172] When the transmission hole TAH corresponds to the transmission area TA, the transmission hole TAH may overlap the transmission area TA. In this case, the area of ​​the transmission hole TAH may be smaller than the area of ​​the first hole H1 formed in the inorganic insulating layer IL. Figure 7It is shown in the figure that the width Wt of the transmission hole TAH is smaller than the width W1 of the first hole H1. Here, the area of ​​the transmission hole TAH may be defined as the area of ​​the opening with the smallest area among the openings constituting the transmission hole TAH. The area of ​​the first hole H1 may be defined as the area of ​​the opening with the smallest area among the openings constituting the first hole H1. Although it is shown in the drawings that the width Wt of the transmission hole TAH is equal to the width of the bottom hole BMLH of the bottom metal layer BML, the embodiment is not limited thereto. In some embodiments, the width Wt of the transmission hole TAH may be greater than the width of the bottom hole BMLH of the bottom metal layer BML.

[0173] A portion of the counter electrode 123 is removed at the transmission hole TAH, by which the transmittance of the transmission area TA can be significantly improved. The counter electrode 123 can be formed by various methods. For example, the counter electrode 123 including an opening can be formed by forming a layer using a material for the counter electrode 123, and then removing the portion corresponding to the transmission area TA by laser lift-off. In some embodiments, when the counter electrode 123 is formed, the counter electrode 123 including an opening can be formed by metal self-patterning (MSP). In some embodiments, when the counter electrode 123 is formed, the counter electrode 123 including an opening can be formed by fine metal mask (FMM) patterning.

[0174] Figure 8 According to the first embodiment, Figure 6C A cross-sectional view of the component area CA of the display panel 10 taken along the line II'. Figure 8 Because the same reference numerals denote Figure 7 The components are the same as the components of the present invention, so their repeated descriptions can be omitted.

[0175] Reference Figure 8 , a first auxiliary subpixel Pa1 and a second auxiliary subpixel Pa2 are arranged in the assembly area CA. The first auxiliary subpixel Pa1 may correspond to an emission region of the first organic light emitting diode OLED1, and the second auxiliary subpixel Pa2 may correspond to an emission region of the second organic light emitting diode OLED2.

[0176] The first pixel electrode 1211 of the first organic light emitting diode OLED1 may include a reflective layer 1211b. Since the first pixel electrode 1211 includes the reflective layer 1211b, light generated by the second emission layer 122b' of the first organic light emitting diode OLED1 may be reflected by the reflective layer 1211b and emitted from the substrate 100 in the top direction (+z direction). That is, the light emission efficiency in the top direction of the substrate 100 may be improved. In an embodiment, the first pixel electrode 1211 may include a first transparent electrode layer 1211a, a reflective layer 1211b, and a second transparent electrode layer 1211c stacked in sequence.

[0177] The first transparent electrode layer 1211a and the second transparent electrode layer 1211c may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and / or aluminum zinc oxide (AZO).

[0178] The reflective layer 1211b may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a composite thereof.

[0179] The second pixel electrode 1212 of the second organic light emitting diode OLED2 may include a transparent conductive material without a reflective layer. The second pixel electrode 1212 may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and / or aluminum zinc oxide (AZO).

[0180] Since the second pixel electrode 1212 includes a transparent conductive material but does not include a reflective layer, at least a portion of external light can pass through the second pixel electrode 1212. That is, light / signals emitted from the component 40 or light and / or signals incident to the component 40 can pass through the second organic light emitting diode OLED2. The region in which the second organic light emitting diode OLED2 is arranged is referred to as a semi-transmission region STA. The semi-transmission region STA may be a region in which a display element (e.g., the second organic light emitting diode OLED2) that can transmit light is arranged and has a small light transmittance.

[0181] Because the second pixel electrode 1212 of the second organic light emitting diode OLED2 does not include a reflective layer, the luminous efficiency of the second organic light emitting diode OLED2 in the top direction of the substrate 100 may be lower than that of the first organic light emitting diode OLED1. Under the same conditions, the brightness of the second auxiliary subpixel Pa2 may be lower than that of the first auxiliary subpixel Pa1.

[0182] The second pixel electrode 1212 may be formed concurrently (e.g., simultaneously) while the first transparent electrode layer 1211a of the first pixel electrode 1211 is formed. In some embodiments, a portion of the second pixel electrode 1212 may be formed while the first transparent electrode layer 1211a of the first pixel electrode 1211 is formed, and the remaining portion of the second pixel electrode 1212 may be formed while the second transparent electrode layer 1211c of the first pixel electrode 1211 is formed. Therefore, the thickness t2 of the second pixel electrode 1212 may be less than the thickness t1 of the first pixel electrode 1211.

[0183] The first organic light emitting diode OLED1 may be driven by the first pixel circuit PC1, and the second organic light emitting diode OLED2 may be driven by the second pixel circuit PC2. In the present embodiment, the second pixel circuit PC2 may be arranged to minimally overlap the second pixel electrode 1212. The bottom metal layer BML may be arranged to overlap the bottom of the first pixel circuit PC1 and the second pixel circuit PC2. The bottom metal layer BML may include a bottom hole BMLH2 corresponding to the semi-transmission area STA.

[0184] Fig. 9 According to the second embodiment, Figure 6C A cross-sectional view of the component area CA of the display panel 10 taken along the line II'. Fig. 9 Because the same reference numerals denote Figure 7 The components are the same as the components of the present invention, so their repeated descriptions can be omitted.

[0185] Reference Fig. 9 , one organic light emitting diode OLED arranged in the assembly area CA may include two emission regions, and the emission regions may correspond to the first auxiliary sub-pixel Pa1 and the second auxiliary sub-pixel Pa2, respectively.

[0186] In the present embodiment, the pixel electrode 1211 of the organic light emitting diode OLED may include a first pixel electrode portion 1211P and a second pixel electrode portion 1212P, the first pixel electrode portion 1211P includes a reflective layer 1211b, and the second pixel electrode portion 1212P includes a transparent conductive material. The pixel defining layer 119 may define an emission region by including a first opening OP1 and a second opening OP2, the first opening OP1 exposing a portion of the first pixel electrode portion 1211P, and the second opening OP2 exposing a portion of the second pixel electrode portion 1212P.

[0187] The first pixel electrode portion 1211P may include a first transparent electrode layer 1211a, a reflective layer 1211b, and a second transparent electrode layer 1211c stacked in sequence. The second pixel electrode portion 1212P may be provided by extending the first transparent electrode layer 1211a and / or the second transparent electrode layer 1211c of the first pixel electrode portion 1211P. The second pixel electrode portion 1212P may include only the first transparent electrode layer 1211a, or may include the first transparent electrode layer 1211a and the second transparent electrode layer 1211c stacked.

[0188] Since the second pixel electrode portion 1212P does not include the reflective layer 1211b and includes a transparent conductive material, external light can pass through a portion of the organic light emitting diode OLED. The second pixel electrode portion 1212P of the organic light emitting diode OLED may be arranged in the semi-transmission area STA. The bottom metal layer BML may include a bottom hole BMLH2 corresponding to the semi-transmission area STA.

[0189] Because the second pixel electrode portion 1212P of the organic light emitting diode OLED does not include a reflective layer, the brightness of the second auxiliary sub-pixel Pa2 may be lower than the brightness of the first auxiliary sub-pixel Pa1. The thickness t2 of the second pixel electrode portion 1212P may be lower than the thickness t1 of the first pixel electrode portion 1211P. Because the first auxiliary sub-pixel Pa1 and the second auxiliary sub-pixel Pa2 are implemented by one organic light emitting diode OLED, the first auxiliary sub-pixel Pa1 and the second auxiliary sub-pixel Pa2 may be driven concurrently (e.g., simultaneously) by one pixel circuit PC1.

[0190] Fig.10 is a plan view of a display panel 10 and components under the display panel 10 according to an embodiment.

[0191] Reference Fig.10 The component area CA may include a plurality of component areas CA1, CA2, CA3 in the display area DA. The component areas CA1, CA2, CA3 may have a circular shape and may be arranged inside the main display area MDA and surrounded by the main display area MDA.

[0192] The component area CA may include a first component area CA1 on the top center of the display panel 10, a second component area CA2 on the bottom left side of the display panel 10, and a third component area CA3 on the bottom right side of the display panel 10. The first to third components 41, 42, and 43 may be arranged below the display panel 10 to correspond to the first to third component areas CA1, CA2, and CA3, respectively. The first to third components 41, 42, and 43 may be cameras that capture (or shoot) images. In this case, since images can be captured at various angles, images can be compensated based on images captured by the first to third components 41, 42, and 43.

[0193] In the case of providing a plurality of component areas CA, the pixel arrangement structures and resolutions of the respective component areas CA may be different from each other. For example, the first component area CA1 may adopt Fig. 6A The pixel arrangement structure shown in FIG. 1 may be a second component area CA2. Figure 6B The pixel arrangement structure shown in FIG. 1 and the third component area CA3 may adopt Figure 6C or Fig.6D The pixel arrangement structure shown in .

[0194] Fig.11A and Fig. 11B is a cross-sectional view of a portion of a display device 1 according to an embodiment of the present disclosure, and Fig.12 is a plan view of a second display panel 20 that may be included in the display device 1 .

[0195] Reference Fig.11A and Fig. 11B , the display device 1 may further include a second display panel 20 below the first display panel 10. The first display panel 10 may be a reference Figures 1 to 10 The second display panel 20 may include a substrate 200, a circuit layer on the substrate 200, a light emitting diode ED as a display element, and an insulating layer IL between the substrate 200 and the light emitting diode ED, wherein the circuit layer includes a thin film transistor TFT.

[0196] The second display panel 20 may include a hole 20H corresponding to the assembly area CA of the first display panel 10. The assembly 40 may be disposed under the second display panel 20 to correspond to the hole 20H.

[0197] like Fig. 11B As shown in , the second display panel 20 may be attached to the first display panel 10. In this embodiment, an optically transparent resin OCR may fill the inside of the hole 20H of the second display panel 20. OCR has optical transparency, and thus can improve visibility.

[0198] In addition, a light guide layer GUIL may be arranged on the light emitting diode ED. The light guide layer GUIL may diffuse the light emitted from the light emitting diode ED. The light guide layer GUIL may include an acryl-based material and / or polymethyl methacrylate (PMMA). In order to substantially prevent or prevent the light diffused from the light guide layer GUIL from being emitted in a lateral direction, a light leakage prevention layer 201 may also be arranged around the light emitting diode ED (i.e., around the second display panel 20). The light leakage prevention layer 201 may include a black pigment, a black dye, chromium (Cr), and chromium oxide (CrO x ) at least one of.

[0199] The light emitting diodes ED arranged on the second display panel 20 may be arranged to correspond to the edge of the assembly area CA. In some embodiments, the light emitting diodes ED may be arranged to correspond to the edge of the assembly 40. That is, the light emitting diodes ED may surround the assembly 40, for example, Fig.12 (wherein the light emitting diode ED is included in the sub-pixel Ps). In some embodiments, the light emitting diode ED may surround the hole 20H of the second display panel 20. The light emitting diode ED may include an inorganic light emitting diode having a micron size or a nanometer size.

[0200] The sub-pixels Ps of the second display panel 20 may be implemented by light emitting diodes ED. The sub-pixels Ps of the second display panel 20 may include red sub-pixels Pr, green sub-pixels Pg, blue sub-pixels Pb, and / or white sub-pixels Pw. The sub-pixels Ps may be arranged in a circular shape around the hole 20H. Thus, a second display area DA2 in which the sub-pixels Ps are arranged in a ring shape may be provided.

[0201] One side of the second display panel 20 may be connected to a second display circuit board 25. The second display circuit board 25 may include a second display driver 27 that drives the second display panel 20. The second display driver 27 may generate a signal that controls the brightness and color of the sub-pixel Ps of the second display panel 20 in response to a driving signal of the first display panel 10 and a driving signal of the component 40.

[0202] For example, in the case where a red image is displayed on the component area CA of the first display panel 10, the second display driver 27 may generate a signal to drive the red sub-pixel Pr of the second display panel 20. In the case where a scarlet image is displayed on the component area CA of the first display panel 10, the second display driver 27 may generate a signal to drive the red sub-pixel Pr and the blue sub-pixel Pb of the second display panel 20.

[0203] Since the component area CA of the first display panel 10 includes the transmissive area TA, the brightness of an image displayed in the component area CA may be lower than the brightness of an image displayed in the main display area MDA.

[0204] In the present embodiment, since an image is displayed in the second display area DA2 overlapping the assembly area CA by using the second display panel 20, visibility of the image may be improved by compensating for brightness and color of the assembly area CA.

[0205] As described above, the first display panel 10 may include a plurality of component areas CA, and the second display panel 20 may include a light emitting diode ED for each component area CA, the light emitting diode ED surrounding the component area CA. In this case, the sub-pixels Ps arranged in the second display panel 20 may be driven individually according to the color realized in each component area CA. For example, in the case where the first component area is red and the second component area is green, the red sub-pixel Pr may be driven in a portion of the second display panel 20 corresponding to the first component area, and the green sub-pixel Pg may be driven in a portion of the second display panel 20 corresponding to the second component area.

[0206] Fig.13A and Fig. 13B is a cross-sectional view of a portion of a display device 1 according to another embodiment. Fig.14A and Fig. 14B is a plan view of a second display panel 20 that may be included in the display device 1 .

[0207] Reference FIG. 13A to FIG. 14B , the display device 1 may further include a second display panel 20 below the first display panel 10. The first display panel 10 may be a reference Figures 1 to 10 Description of the display panel.

[0208] The second display panel 20 may include a substrate 200, a circuit layer on the substrate 200, a light emitting diode ED as a display element, and an insulating layer IL between the substrate 200 and the light emitting diode ED, the circuit layer including a thin film transistor TFT. In addition, the component 40 may be arranged on the second display panel 20. That is, the component 40 may be mounted on the second display panel 20 and may constitute a part of the second display panel 20.

[0209] like Fig. 14BAs shown in , a plurality of components 40 may be provided. A first component 41 and a second component 42 may be mounted on the second display panel 20. In some embodiments, the first component 41 may include a camera that captures an image, and the second component 42 may include a flash provided with a light emitting diode (LED). In some embodiments, the first component 41 may include a camera that captures an image, and the second component 42 may include a solar cell. The number of components 40 mounted on the second display panel 20 may be three or more. As described above, the component 40 may include various components such as an infrared sensor, an iris sensor, and an ultrasonic sensor.

[0210] When the area of ​​the second display panel 20 in which the light emitting diodes ED are arranged is referred to as the second display area DA2, the assembly 40 may be arranged on one side of the second display area DA2. The area of ​​the second display area DA2 may correspond to the area of ​​the assembly area CA of the first display panel 10.

[0211] The second display panel 20 can move relative to the first display panel 10 at a predetermined interval. That is, the second display panel 20 can move on the xy plane while maintaining a predetermined interval with the first display panel 10 in the z direction. The second display panel 20 can be moved by a moving driver 21 configured as a linear motor or the like, for example, as shown in FIG. Fig.13A and Fig. 13B The mobile driver 21 can be driven by a command of the controller 23 .

[0212] In some embodiments, the second display panel 20 can move in coordination with the operation of the assembly 40. For example, Fig.13A As shown in , in the case where the assembly 40 is in operation, the second display panel 20 may be arranged so that the assembly 40 overlaps the assembly area CA of the first display panel 10. In addition, as Fig. 13B As shown in FIG. 4 , in a case where the assembly 40 is not operating, the second display panel 20 may be arranged such that the second display area DA2 in which the light emitting diodes ED are arranged overlaps the assembly area CA.

[0213] The sub-pixels Ps implemented by the light-emitting diodes ED may be arranged in the second display area DA2. The sub-pixels Ps may include red, green, blue and / or white sub-pixels. In some embodiments, when the sub-pixels Ps arranged in the second display area DA2 overlap with the first display panel 10, the sub-pixels Ps may be arranged to correspond to the transmission area TA. In some embodiments, when the sub-pixels Ps arranged in the second display area DA2 overlap with the first display panel 10, the sub-pixels Ps may be arranged to surround the edge of the component area CA. The sub-pixels Ps may be arranged in various pixel arrangement structures, such as a strip structure, a circular structure and / or structure.

[0214] Fig.15 is a plan view of the second display area DA2 of the second display panel 20 according to the embodiment. Fig.16 It is along Fig.15 2 is a cross-sectional view of the second display area DA2 taken along line II-II'.

[0215] Reference Fig.15 and Fig.16 In this embodiment, each sub-pixel Ps may be implemented by a light emitting diode ED, which is an inorganic micro light emitting diode LED as a display element. The second display panel 20 may include a thin film transistor layer TFTL and an emission element layer EML arranged on a substrate 200. At least one thin film transistor TFT and at least one capacitor may be arranged in the thin film transistor layer TFTL. The light emitting diode ED, which is an inorganic micro light emitting diode LED used as a display element, is arranged in the emission element layer EML. Fig.16 An example having two thin film transistors TFT is shown, and one of the two thin film transistors TFT is connected to the light emitting diode ED.

[0216] The buffer layer 211 may be disposed on the substrate 200 . The thin film transistor TFT and the light emitting diode ED may be disposed on the buffer layer 211 .

[0217] The substrate 200 may include glass or plastic. The buffer layer 211 may block the penetration of impurities through the substrate 200, may flatten the surface of the substrate 200, and may include a material including silicon oxide (SiO 2 ) and / or silicon nitride (SiN x ) of a single layer or multiple layers of inorganic material.

[0218] The thin film transistor TFT includes an active layer A3, a gate electrode G3, a source electrode S3 and a drain electrode D3. The active layer A3 may include a semiconductor material and include a source region, a drain region and a channel region between the source region and the drain region. The gate electrode G3 is formed on the active layer A3 to correspond to the channel region. The source electrode S3 and the drain electrode D3 are electrically connected to the source region and the drain region of the active layer A3, respectively. The gate insulating layer 213 is arranged between the active layer A3 and the gate electrode G3, and the gate insulating layer 213 includes an inorganic material. The interlayer insulating layer 215 is arranged between the gate electrode G3 and the source electrode S3 and the drain electrode D3. The planarization layer 217 is arranged on the source electrode S3 and the drain electrode D3. Each of the interlayer insulating layer 215 and the planarization layer 217 may include an organic insulating material or an inorganic insulating material, or may include an organic insulating material and an inorganic insulating material arranged alternately.

[0219] The bank 219 is disposed on the planarization layer 217, and defines the area of ​​the sub-pixel Ps. The bank 219 includes a recessed portion RP in which the light-emitting diode ED is accommodated. The height of the bank 219 may be determined by the height and viewing angle of the light-emitting diode ED. The size (e.g., width) of the recessed portion RP may be determined by the resolution of the second display panel 20, the sub-pixel density, etc. In some embodiments, the height of the light-emitting diode ED may be higher than the height of the bank 219. Although Fig.15 An example is shown in which the recessed portion RP has a quadrangular shape, but the embodiment is not limited thereto and the recessed portion RP may have various shapes such as a polygon, a rectangle, a circle, a conical shape, an ellipse, and / or a triangle.

[0220] The first electrode 221 is arranged along the side surface and the bottom surface of the recessed portion RP and the top surface of the bank 219 around the recessed portion RP. The first electrode 221 is electrically connected to the source electrode S3 or the drain electrode D3 of the thin film transistor TFT through the through hole in the planarization layer 217. Fig.16 It is shown in FIG. 2 that the first electrode 221 is electrically connected to the drain electrode D3 .

[0221] The embankment 219 serves as a light blocking portion having a low light transmittance, and can reduce or prevent color mixing of multiple lights emitted from adjacent light emitting diodes ED by blocking light emitted to the side of the light emitting diodes ED. In addition, the embankment 219 can improve the contrast of the second display panel 20 by absorbing and blocking incident light from the outside. The embankment 219 may include a material that absorbs at least a portion of the light, a light reflecting material, and / or a light scattering material. For example, the embankment 219 may include a semi-transparent or opaque insulating material relative to visible light (e.g., light in a wavelength range from about 280 nm to about 750 nm). The bank 219 may include an organic insulating material such as polyethylene terephthalate (PET), polyethersulfone, polyvinyl butyral, polyphenylene oxide, polyamide, polyetherimide, norbornene-based resin, methacrylic resin, thermoplastic resin (such as cyclic polyolefin), epoxy resin, phenolic resin, polyurethane resin, acrylic resin, vinyl ester resin, imide-based resin, urethane-based resin, urea resin, thermosetting resin (such as melamine resin), polystyrene, polyacrylonitrile and / or polycarbonate, but the bank 219 is not limited thereto. The bank 219 may include an inorganic insulating material, for example, an inorganic oxide such as silicon oxide (SiO 2 ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), titanium oxide (TiO x ), tantalum oxide (TaO x ), zinc oxide (ZnO x), and / or inorganic nitrides, such as silicon nitride (SiN x ), but the embankment 219 is not limited thereto. In some embodiments, the embankment 219 may include an opaque material such as a black matrix. The insulating black matrix material may include an organic resin, a glass paste, and / or a resin or paste containing a black pigment, metal particles (e.g., nickel, aluminum, molybdenum, or an alloy thereof), metal oxide particles (e.g., chromium oxide), and / or metal nitride particles (e.g., chromium nitride). In some embodiments, the embankment 219 may include a dispersion Bragg reflector DBR having a high reflectivity or a specular reflector containing a metal.

[0222] A light emitting diode ED, which is an inorganic light emitting diode having a micron size, is arranged in the recessed portion RP of the embankment 219. Here, microns may represent a size of about 1 μm to about 100 μm, but the embodiment is not limited thereto and is applicable to light emitting diodes having a larger or smaller size. The light emitting diodes ED may be picked up individually or collectively from a wafer by a transfer mechanism, transferred to the substrate 200, and then accommodated in the recessed portion RP of the substrate 200. In some embodiments, after the embankment 219 and the first electrode 221 are formed, the light emitting diode ED may be accommodated in the recessed portion RP of the substrate 200. The light emitting diode ED may emit light within a predetermined wavelength belonging to a wavelength range from ultraviolet light to visible light. For example, the light emitting diode ED may include a red, green, blue, or white light emitting diode LED, or an ultraviolet light emitting diode LED.

[0223] The light emitting diode ED may include a pn diode 250, a first contact electrode 225, and a second contact electrode 227. The first contact electrode 225 and / or the second contact electrode 227 may include at least one layer, and may include various conductive materials including metals, conductive oxides, and / or conductive polymers. The first contact electrode 225 and / or the second contact electrode 227 may selectively include a reflective layer, such as a silver layer. The first contact electrode 225 is electrically connected to the first electrode 221, and the second contact electrode 227 is electrically connected to the second electrode 223. The pn diode 250 may include a p-doped layer 251 in the lower portion, at least one quantum well layer 253, and an n-doped layer 255 in the upper portion. In another embodiment, the doped layer 255 in the upper portion may be a p-doped layer, and the doped layer 251 in the lower portion may be an n-doped layer. The pn diode 250 may have a straight sidewall or a tapered sidewall from top to bottom or from bottom to top.

[0224] The first electrode 221 may include a reflective electrode and may include at least one layer. For example, the first electrode 221 may include a metal such as aluminum, molybdenum, titanium, tungsten, silver, gold, or an alloy thereof. The first electrode 221 may include a transparent conductive oxide (TCO) such as ITO, IZO, ZnO, and / or In2 O 3 ), a transparent conductive layer and a reflective layer, the transparent conductive layer comprising a conductive material such as a carbon nanotube film or a transparent conductive polymer. In some embodiments, the first electrode 221 may include three layers, including a top transparent conductive layer, a bottom transparent conductive layer and a reflective layer therebetween.

[0225] The second electrode 223 may include a transparent or semi-transparent electrode. For example, the second electrode 223 may include a transparent conductive oxide (TCO) such as ITO, IZO, ZnO, or In 2 O 3 ) and at least one of a conductive material such as a carbon nanotube film or a transparent conductive polymer. The second electrode 223 serves as a common electrode common to the sub-pixels Ps and may be formed on the entire surface of the substrate 200.

[0226] The passivation layer 240 surrounds the light emitting diode ED inside the recessed portion RP. The passivation layer 240 covers the embankment 219 and the light emitting diode ED. Because the passivation layer 240 is formed above the light emitting diode ED (for example, at a height that does not cover the second contact electrode 227), the second contact electrode 227 is exposed. The passivation layer 240 may include an organic insulating material. For example, the passivation layer 240 may include at least one of acrylamide, polymethyl methacrylate (PMMA), benzocyclobutene (BCB), polyimide, acrylate, epoxy resin, and polyester. The second electrode 223 is formed on the passivation layer 240, and the second electrode 223 is electrically connected to the exposed second contact electrode 227 of the light emitting diode ED.

[0227] When a voltage is applied to the first electrode 221 and the second electrode 223 , the light emitting diode ED emits light, and the size of each sub-pixel Ps may be defined by a recessed portion RP of the bank 219 in which the light emitting diode ED is disposed.

[0228] Fig.17 and Fig.18 is a plan view of the second display area DA2 of the second display panel 20 according to an embodiment of the present disclosure.

[0229] Reference Fig.17 The sub-pixels Ps in the second display area DA2 may be provided by a plurality of light emitting diodes 275 (eg, Fig.18 The light emitting diode 275 may be disposed between the first electrode 271 and the second electrode 273 to emit light.

[0230] The first electrode 271 may include an anode electrode of the light emitting diode 275, and the second electrode 273 may include a cathode electrode of the light emitting diode 275. Each of the first electrode 271 and the second electrode 273 may include an electrode trunk portion 271S and 273S extending in a first direction (e.g., x direction) and one or more electrode branch portions 271B and 273B extending and branching from the electrode trunk portions 271S and 273S in a second direction (e.g., y direction) intersecting the first direction (x direction).

[0231] The first electrode 271 may include a first electrode trunk portion 271S extending along a first direction (e.g., x direction) and at least one first electrode branch portion 271B branching from the first electrode trunk portion 271S and extending along a second direction (e.g., y direction).

[0232] The first electrode trunk portion 271S may be electrically separated from the first electrode trunk portion 271S driving the sub-pixel Ps adjacent in the first direction (e.g., the x direction). The first electrode trunk portion 271S may be separated from the first electrode trunk portion 271S of the sub-pixel Ps adjacent in the first direction (e.g., the x direction). The first electrode trunk portion 271S may be connected to the thin film transistor through the first electrode contact hole CNTD.

[0233] The first electrode branch portion 271B may be separated from the second electrode stem portion 273S in the second direction (eg, y direction). The first electrode branch portion 271B may be separated from the second electrode branch portion 273B in the first direction (eg, x direction).

[0234] The second electrode 273 may include a second electrode trunk portion 273S extending in a first direction (eg, x direction) and a second electrode branch portion 273B branching from the second electrode trunk portion 273S and extending in a second direction (eg, y direction).

[0235] The second electrode trunk portion 273S may be connected to the second electrode trunk portion 273S driving the sub-pixel Ps adjacent in the first direction (e.g., the x direction). The second electrode branch portion 273B may be separated from the first electrode trunk portion 271S in the second direction (e.g., the y direction). The second electrode branch portion 273B may be separated from the first electrode branch portion 271B in the first direction (e.g., the x direction). The second electrode branch portion 273B may be arranged between the first electrode branch portions 271B in the first direction (e.g., the x direction).

[0236] Despite Fig.17 271B and the second electrode branch portion 273B extend in the second direction (e.g., the y direction), but the embodiment is not limited thereto. For example, each of the first electrode branch portion 271B and the second electrode branch portion 273B may have a partially bent or curved shape, or one of the first electrode branch portion 271B and the second electrode branch portion 273B may surround the other of the first electrode branch portion 271B and the second electrode branch portion 273B.

[0237] As an example in Fig.18 2 shows that the second electrode 273 has a circular shape, the first electrode 271 surrounds the second electrode 273, a circular hole HOL is formed between the first electrode 271 and the second electrode 273, and the second electrode 273 receives a cathode voltage through the second electrode contact hole CNTS. Fig.18 In the embodiment, since the light emitting diodes 275 are arranged in various directions, uniform brightness can be provided at various viewing angles.

[0238] As long as at least some areas of the first electrode 271 and the second electrode 273 are separated from each other to face each other, and a space in which the light-emitting diode 275 can be arranged is formed between the first electrode 271 and the second electrode 273, each of the first electrode branch portion 271B and the second electrode branch portion 273B can be formed into any shape.

[0239] The light emitting diode 275 may be arranged between the first electrode 271 and the second electrode 273. One end of the light emitting diode 275 may be electrically connected to the first electrode 271, and the other end of the light emitting diode 275 may be electrically connected to the second electrode 273. The plurality of light emitting diodes 275 may be separated from each other. The plurality of light emitting diodes 275 may be aligned to be substantially parallel to each other.

[0240] The light emitting diode 275 may have a shape such as a rod, a wire, and a tube. For example, the light emitting diode 275 may be formed as Fig.19 . However, the shape of the light emitting diode 275 is not limited thereto, and the light emitting diode 275 may have a polygonal prism shape such as a cube, a cuboid, or a hexagonal prism, or a shape having an outer surface extending in one direction and having a partial inclination. The length of the light emitting diode 275 may have a range from about 1 μm to about 10 μm or from about 2 μm to about 6 μm, preferably from about 3 μm to about 5 μm. In addition, the diameter of the light emitting diode 275 may have a range from about 300 nm to about 700 nm, and the aspect ratio of the light emitting diode 275 may be about 1.2 to about 100.

[0241] like Fig.17 As shown in FIG. 1 , the contact electrode 274 may include a first contact electrode 274a and a second contact electrode 274b. The first contact electrode 274a and the second contact electrode 274b may have a shape extending in the second direction (eg, the y direction).

[0242] The first contact electrode 274a may be disposed on and connected to the first electrode branch portion 271B. The first contact electrode 274a may contact one end of the light emitting diode 275. The first contact electrode 274a may be disposed between the first electrode branch portion 271B and the light emitting diode 275. Therefore, the light emitting diode 275 may be electrically connected to the first electrode 271 through the first contact electrode 274a.

[0243] The second contact electrode 274b may be disposed on and connected to the second electrode branch portion 273B. The second contact electrode 274b may contact the other end of the light emitting diode 275. The second contact electrode 274b may be disposed between the second electrode branch portion 273B and the light emitting diode 275. Therefore, the light emitting diode 275 may be electrically connected to the second electrode 273 through the second contact electrode 274b.

[0244] The width (or length in the first direction (e.g., x direction)) of the first contact electrode 274a may be greater than the width (or length in the first direction (e.g., x direction)) of the first electrode branch portion 271B, and the width (or length in the first direction (e.g., x direction)) of the second contact electrode 274b may be greater than the width (or length in the first direction (e.g., x direction)) of the second electrode branch portion 273B.

[0245] The outer bank 235 may be disposed between the sub-pixels Ps. The outer bank 235 may extend along the second direction (eg, the y direction). The length of each sub-pixel Ps in the first direction (eg, the x direction) may be defined by the distance between the outer banks 235.

[0246] Fig.19 yes Fig.17 and Fig.18 A perspective view of a light emitting diode 275 is shown.

[0247] Reference Fig.19 The light emitting diode 275 may include a first semiconductor layer 275a, a second semiconductor layer 275b, an active layer 275c, an electrode layer 275d and an insulating layer 275e.

[0248] The first semiconductor layer 275a may include, for example, an n-type semiconductor having a first conductivity type. The first semiconductor layer 275a may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with n-type impurities. For example, in the case where the light emitting diode 275 emits light in the blue band, the first semiconductor layer 275a may include AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with n-type impurities. x Ga y In 1-x-y The first semiconductor layer 275a may be doped with a first conductive type dopant such as silicon (Si), germanium (Ge), selenium (Se) and / or tin (Sn). For example, the first semiconductor layer 275a may include n-GaN doped with n-type Si.

[0249] The second semiconductor layer 275b may include, for example, a p-type semiconductor having a second conductivity type. The second semiconductor layer 275b may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with p-type impurities. For example, in the case where the light emitting diode 275 emits light in the blue or green band, the second semiconductor layer 275b may include AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with p-type impurities. x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). The second semiconductor layer 275b may be doped with a second conductive type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca) and / or barium (Ba). In an embodiment, the second semiconductor layer 275b may include p-GaN doped with p-type Mg.

[0250] The active layer 275c may be arranged between the first semiconductor layer 275a and the second semiconductor layer 275b. The active layer 275c may include a material having a single quantum well structure or a multi-quantum well structure. In the case where the active layer 275c includes a material having a multi-quantum well structure, the active layer 275c may have a structure in which quantum layers and well layers are alternately stacked multiple times. Alternatively, the active layer 275c may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, or may include a semiconductor material of Group 3 to Group 5 according to the wavelength band of the emitted light.

[0251] The active layer 275c can emit light by the recombination of electron-hole pairs according to the electrical signal applied from the first semiconductor layer 275a and the second semiconductor layer 275b. The light emitted by the active layer 275c is not limited to the light in the blue band. The active layer 275c can emit light in the red or green band. For example, in the case where the active layer 275c emits light in the blue band, the active layer 275c may include materials such as AlGaN and AlGaInN. For example, in the case where the active layer 275c has a multi-quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layer may include materials such as AlGaN or AlGaInN, and the well layer may include materials such as GaN or AlInN. For example, the active layer 275c may include AlGaInN as a quantum layer, and may include AlInN as a well layer. As described above, the active layer 275c may emit blue light having a central band ranging from about 450nm to about 495nm.

[0252] Light emitted from the active layer 275c may be emitted not only from the longitudinal outer surface of the light emitting diode 275 but also from two opposite side surfaces of the light emitting diode 275. That is, the directivity of light emitted from the active layer 275c is not limited to one direction.

[0253] The electrode layer 275d may include an ohmic contact electrode or a Schottky contact electrode. The light emitting diode 275 may include at least one electrode layer 275d. When the light emitting diode 275 is electrically connected to the first electrode 271 or the second electrode 273, the resistance between the light emitting diode 275 and the first electrode 271 or the second electrode 273 is reduced due to the electrode layer 275d. The electrode layer 275d may include at least one conductive metal material such as aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO and / or indium tin zinc oxide (ITZO). The electrode layer 275d may include a semiconductor material doped with n-type impurities or p-type impurities. The electrode layer 275d may include the same material or different materials, and is not limited thereto.

[0254] The insulating layer 275e may be arranged to surround the outer surfaces of the first semiconductor layer 275a, the second semiconductor layer 275b, the active layer 275c, and the electrode layer 275d. The insulating layer 275e protects the first semiconductor layer 275a, the second semiconductor layer 275b, the active layer 275c, and the electrode layer 275d. The insulating layer 275e may expose two opposite end portions of the light emitting diode 275 in the length direction. That is, one end of the first semiconductor layer 275a and one end of the electrode layer 275d may be exposed without being covered by the insulating layer 275e. The insulating layer 275e covers the active layer 275c and may cover only a portion of the outer surfaces of the first semiconductor layer 275a and the second semiconductor layer 275b, and / or covers only a portion of the outer surface of the electrode layer 275d.

[0255] The insulating layer 275e may include a material having insulating properties, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN) and / or aluminum oxide (Al 2 O 3 ). The insulating layer 275e can reduce or prevent an electrical short circuit that may occur when the active layer 275c directly contacts the first electrode 271 and / or the second electrode 273, and the electrical signal is transmitted to the light emitting diode 275 through the first electrode 271 and / or the second electrode 273. In addition, because the insulating layer 275e covers the active layer 275c and protects the outer surface of the light emitting diode 275, the degradation of the emission efficiency can be reduced or prevented.

[0256] Fig. 20 It is along Fig.17 FIG. 1 is a cross-sectional view of an example of the second display panel 20 taken along line III-III′.

[0257] Reference Fig. 20 , the second display panel 20 may include a thin film transistor layer TFTL and an emission element layer EML disposed on the substrate 200 . Fig. 20 The thin film transistor layer TFTL is similar to the reference Fig.16 The described thin film transistor layers TFTL are substantially the same.

[0258] The emission element layer EML may include a first inner bank 231, a second inner bank 233, a first electrode 271, and a second electrode 273 (formed by Fig. 20 ), a contact electrode 274, a light emitting diode 275, a first insulating layer 281, a second insulating layer 282 and a third insulating layer 283.

[0259] The first inner bank 231, the second inner bank 233, and the outer bank 235 may be arranged on the planarization layer 217. The first inner bank 231, the second inner bank 233, and the outer bank 235 may protrude relative to the top surface of the planarization layer 217. Although the first inner bank 231, the second inner bank 233, and the outer bank 235 may have a trapezoidal cross-sectional shape, the embodiment is not limited thereto. Each of the first inner bank 231, the second inner bank 233, and the outer bank 235 may include a bottom surface, a top surface, and a side surface, the bottom surface contacts the top surface of the planarization layer 217, the top surface faces the bottom surface, and the side surface is between the top surface and the bottom surface. The side surface of the first inner bank 231, the side surface of the second inner bank 233, and the side surface of the outer bank 235 may be inclined.

[0260] The first inner bank 231 may be separated from the second inner bank 233. The first inner bank 231 and the second inner bank 233 may include an organic layer including an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, and / or a polyimide resin.

[0261] The first electrode branch portion 271B may be disposed on the first inner bank 231, and the second electrode branch portion 273B may be disposed on the second inner bank 233. The first electrode branch portion 271B may be connected to the first electrode trunk portion 271S, and the first electrode trunk portion 271S may be connected to the drain electrode D3 of the thin film transistor TFT through the first electrode contact hole CNTD. Therefore, the first electrode 271 may receive a voltage from the drain electrode D3 of the thin film transistor TFT.

[0262] The first electrode 271 and the second electrode 273 may include a conductive material having a high reflectivity. For example, the first electrode 271 and the second electrode 273 may include a metal such as silver (Ag), copper (Cu) and / or aluminum (Al). Therefore, the light emitted from the light emitting diode 275 that travels to the first electrode 271 and the second electrode 273 may be reflected by the first electrode 271 and the second electrode 273, and may travel above the light emitting diode 275.

[0263] The first insulating layer 281 may be arranged on the first electrode 271 and the second electrode branch portion 273B. The first insulating layer 281 may be arranged to cover the first electrode trunk portion 271S, the first electrode branch portion 271B (the first electrode branch portion 271B arranged on the side surface of the first inner bank 231), and the second electrode branch portion 273B (the second electrode branch portion 273B arranged on the side surface of the second inner bank 233). The first electrode branch portion 271B on the top surface of the first inner bank 231 and the second electrode branch portion 273B on the top surface of the second inner bank 233 may be exposed due to not being covered by the first insulating layer 281. The first insulating layer 281 may be arranged on the outer bank 235. The first insulating layer 281 may include an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0264] The light emitting diode 275 may be disposed on the first insulating layer 281 disposed between the first inner bank 231 and the second inner bank 233. One end of the light emitting diode 275 may be adjacent to the first inner bank 231, and the other end of the light emitting diode 275 may be adjacent to the second inner bank 233.

[0265] The second insulating layer 282 may be disposed on the light emitting diode 275. The second insulating layer 282 may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0266] The first contact electrode 274a may be disposed on the first electrode branch portion 271B exposed and not covered by the first insulating layer 281, and may contact one end of the light emitting diode 275. The first contact electrode 274a may also be disposed on the second insulating layer 282.

[0267] The third insulating layer 283 may be disposed on the first contact electrode 274a. The third insulating layer 283 may be disposed to cover the first contact electrode 274a to electrically separate the first contact electrode 274a from the second contact electrode 274b. The third insulating layer 283 may include an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0268] The second contact electrode 274b may be disposed on the second electrode branch portion 273B exposed and not covered by the first insulating layer 281 and may contact the other end of the light emitting diode 275. The second contact electrode 274b may also be disposed on the second insulating layer 282 and the third insulating layer 283.

[0269] As described above, each sub-pixel Ps in the second display area DA2 may be implemented by a plurality of light emitting diodes 275. Figures 15 to 20The described light emitting diode 275 or ED driving the sub-pixel Ps is applicable to the first display panel 10 .

[0270] Fig.21 is a cross-sectional view of a portion of the display device 1 according to the embodiment. Fig.21 In, with Figure 2 The same reference numerals as those in the drawings represent the same components.

[0271] Reference Fig.21 , the display device 1 includes a display panel 10 and a component chip 60 .

[0272] The component chip 60 may be arranged to correspond to the component area CA of the display panel 10. The component chip 60 includes a substrate 300 and a plurality of components 41, 42, and 43 arranged on the substrate 300. That is, the plurality of components 41, 42, and 43 may be formed together in one component chip 60. The substrate 300 may include a semiconductor chip package substrate. For example, the substrate 300 may include amorphous silicon.

[0273] The plurality of components 41, 42 and 43 may include a first component 41, a second component 42 and a third component 43, and each component may have different functions. For example, the first component 41 may be an imaging device and may include an array including a plurality of photodiodes PD. The second component 42 may include an infrared sensor. The third component 43 may include a flash configured as a light emitting diode. The driver of each component may be separately disposed outside the component chip 60.

[0274] A plurality of light emitting diodes for realizing an image may be arranged on the component chip 60. Optionally, the component chip 60 may be mounted on a reference Fig.13A and Fig. 13B In this case, the component chip 60 may move relative to the display panel 10 according to a driving state of the display panel 10.

[0275] According to the embodiment, a display panel including an expanded display area so that an image can be displayed even in an area where components as electronic elements are arranged and a display device including the display panel can be realized. However, the scope of the present disclosure is not limited to this effect.

[0276] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims and their equivalents.

Claims

1. A display device, comprising: A first display panel configured to emit light from a first display element in a first direction to display an image, the first display panel comprising a main display area and a component area; a second display panel located below the first display panel and comprising a second display area, the second display area being configured to emit light from a second display element along the first direction to display an image; as well as a component located below the first display panel and configured to receive light from outside the display device, The second display element corresponds to an edge of the component area.

2. The display device according to claim 1, wherein: The component overlaps the component area.

3. The display device according to claim 2, wherein: When the display device is in use and displays an image, the image displayed on the second display panel by the second display element is displayed in conjunction with the image displayed in the component area.

4. The display device according to claim 1, further comprising: a moving driver configured to move the second display panel relative to the first display panel; as well as a controller configured to control the moving drive, The component is located on the second display panel and on one side of the second display area.

5. The display device according to claim 4, wherein: The moving driver is configured to move the second display panel according to a command of the controller so that the component corresponds to the component area when the component is operated, and The movement driver is configured to move the second display panel according to a command of the controller so that the second display area corresponds to the component area when the component is not operated.

6. The display device according to claim 1, wherein: The component area includes a first component area and a second component area, and At least one of a resolution and a pixel arrangement structure of the first component area is different from a resolution and a pixel arrangement structure of the second component area.

7. The display device according to claim 1, wherein: The first display element includes a first auxiliary display element and a second auxiliary display element in the component area, and The thickness of the first pixel electrode of the first auxiliary display element is greater than the thickness of the second pixel electrode of the second auxiliary display element, and the first pixel electrode includes a reflective layer.

8. The display device according to claim 1, wherein: The first display element includes a first auxiliary display element in the component area, the first auxiliary display element includes a pixel electrode, the pixel electrode includes a first pixel electrode portion and a second pixel electrode portion, wherein the first pixel electrode portion and the second pixel electrode portion have different thicknesses, and The first pixel electrode portion includes a stacked first transparent electrode layer, a reflective layer, and a second transparent electrode layer, and the second pixel electrode portion extends from the first transparent electrode layer.

9. The display device according to claim 1, wherein: The second display element includes an inorganic light emitting diode, and each of the inorganic light emitting diodes is between a first electrode and a second electrode located at different layers.

10. The display device according to claim 1, wherein: The second display element includes an inorganic light emitting diode, and each of the inorganic light emitting diodes is between a first electrode and a second electrode located at the same layer.

11. The display device according to claim 1, wherein: The assembly includes a first assembly and a second assembly configured to perform different functions, and the first assembly and the second assembly are located at a same substrate.

12. The display device according to claim 1, wherein: The components include an imaging device, an infrared sensor, a solar cell and / or a flash.

13. The display device according to claim 1, wherein: The resolution of the main display area is greater than the resolution of the component area.

14. The display device according to claim 1, wherein: The first display panel includes a substrate and a bottom metal layer between the substrate and some of the first display elements, and The bottom metal layer defines a bottom hole corresponding to at least a portion of the component area.

15. A display panel, comprising: A substrate, including a main display area and a component area; A main display element, located in the main display area; as well as an auxiliary display element, located in the component area, Wherein, the auxiliary display element comprises a first auxiliary display element and a second auxiliary display element, and The thickness of the first pixel electrode of the first auxiliary display element is greater than the thickness of the second pixel electrode of the second auxiliary display element, and the first pixel electrode includes a reflective layer.

16. The display panel according to claim 15, wherein: A pixel arrangement structure of a main sub-pixel including the main display element is the same as a pixel arrangement structure of an auxiliary sub-pixel including the auxiliary display element.

17. The display panel according to claim 15, wherein: A first subpixel including one or more of the first auxiliary display elements is smaller than a second subpixel including one or more of the second auxiliary display elements and configured to display the same color as the first subpixel.

18. The display panel according to claim 15, wherein: The first auxiliary display element and the second auxiliary display element are integrated into one body. The first pixel electrode includes a first transparent electrode layer, the reflective layer and a second transparent electrode layer, and The second pixel electrode extends from the first transparent electrode layer.

19. The display panel according to claim 15, further comprising a bottom metal layer between the substrate and the first auxiliary display element, in, The bottom metal layer defines a bottom hole corresponding to the second auxiliary display element.

20. The display panel according to claim 15, wherein: The resolution of the main display area is greater than the resolution of the component area.

Images