A zero current detection circuit and detection method thereof

Abstract

The present invention provides a zero-current detection circuit and method. The circuit includes a transformer, a first detection module, a second detection module, and a signal processing module. The transformer is used to sense the zero-crossing signal of the inductor current in a bridgeless power factor correction circuit and reduce sampling loss by utilizing its saturation characteristics. The first detection module is used to generate the zero-current detection voltage signal required for the negative half-cycle, and the second detection module is used to generate the zero-current detection voltage signal required for the positive half-cycle. The signal processing module is used to combine and generate the zero-current detection signal required by the circuit for the entire power frequency cycle. The present invention aims to utilize the saturation characteristics of the transformer to reduce sampling loss, thereby improving system efficiency.

Description

Technical Field

[0001] The present invention relates to the field of active power factor correction converters, in particular to zero current detection. Background Art

[0002] With the rapid development of modern industry, nonlinear loads in power systems are increasing. These nonlinear loads generate harmonic currents that are injected into the power grid, distorting the voltage waveform and severely polluting the grid environment. To reduce the severe harmonic pollution caused by the frequent use of power electronic devices, power factor correction (PFC) circuits are often introduced to ensure that the input current harmonics meet preset harmonic requirements. Furthermore, the development trend of PFC circuits, like that of most power supply products, is towards high efficiency and high power density.

[0003] Compared to traditional bridge PFC circuits, bridgeless PFC circuits reduce losses in the input rectifier bridge. Consequently, they offer numerous advantages, including low conduction losses, low common-mode interference, and high component utilization. Furthermore, bridgeless PFC can achieve zero voltage switching (ZVS) under specific control conditions, leading to increasing research interest in bridgeless PFC.

[0004] Taking the totem pole bridgeless PFC circuit as an example, Figure 1 The figure shows a totem-pole bridgeless PFC circuit. Because the Si MOS transistor's body diode has a long reverse recovery time, significant reverse recovery losses occur in continuous current mode (CCM). Therefore, totem-pole bridgeless PFC circuits are not suitable for operating in CCM. In both critical current mode (CRM) and discontinuous current mode (DCM), the Si MOS transistor's body diode is turned off with zero current, resulting in virtually no reverse recovery losses. This helps totem bridgeless PFC achieve high efficiency. Therefore, how to simply and effectively detect the inductor current zero crossing in CRM mode is a pressing issue for designers.

[0005] A bridgeless circuit can use a series resistor for current detection, such as Figure 2 As shown, the solution is that the sampling resistor is connected between the AC power supply and the first energy storage circuit, or between the first energy storage circuit and the half-bridge switching circuit, or between the AC power supply and the rectifier circuit. However, the sampling loss of this solution is large, and the sampling ground and the power ground are not common, requiring isolated drive, output voltage differential sampling, and a complex control circuit. In addition, the bridgeless circuit can use the winding for zero current detection and adopt edge detection, such as Figure 3As shown, this solution can only work in diode rectification mode, which increases additional sampling loss and is not easy to expand to other bridgeless PFC circuits. Summary of the Invention

[0006] In response to the shortcomings of the existing technology, the present invention provides a zero-current detection circuit and method for a bridgeless power factor correction circuit. These circuits can be easily expanded to other PFC circuit applications, such as interleaved PFC circuits, and can also utilize the saturation characteristics of the transformer to reduce the sampling loss of the bridgeless power factor correction circuit, thereby improving the operating efficiency of the system.

[0007] The present invention provides a zero current detection circuit for a bridgeless power factor correction circuit, comprising a mutual inductor, a first detection module, a second detection module and a signal processing module; the mutual inductor is used to be connected to one end of a main power inductor of the bridgeless power factor correction circuit, the first detection module and the second detection module are respectively connected to the two ends of a secondary side of the mutual inductor, the first input end of the signal processing module is connected to the output end of the first detection module, and the second input end of the signal processing module is connected to the output end of the second detection module; the mutual inductor is used to sense the zero-crossing signal of the inductor current of the bridgeless power factor correction circuit and reduce sampling loss according to its saturation characteristics, the first detection module is used to generate a zero current detection voltage signal required for a negative half-cycle, the second detection module is used to generate a zero current detection voltage signal required for a positive half-cycle, and the signal processing module is used to combine and generate the zero current detection signal required by the circuit in the entire power frequency cycle.

[0008] As a specific embodiment of the mutual inductor, it includes a primary inductance unit and a secondary inductance unit, the first end of the primary inductance unit is connected to one end of the input voltage source, and the second end of the primary inductance unit is connected to one end of the main power inductance of the bridgeless power factor correction circuit; the secondary inductance unit includes a first inductor and a second inductor, the first end of the first inductor is connected to one end of the first detection module, the second end of the first inductor is connected to the control circuit reference ground and the first end of the second inductor, and the second end of the second inductor is connected to one end of the second detection module.

[0009] As a specific implementation of the first detection module, it includes a resistor R1, a diode D1 and a resistor R2, one end of the resistor R1 is connected to the mutual inductor, the other end of the resistor R1 is connected to the cathode of the diode D1 and one end of the resistor R2, and the connection point is the output end of the first detection module, the anode of the diode D1 is connected to the other end of the resistor R2, and the connection point is connected to the reference ground of the control circuit.

[0010] As a specific implementation of the second detection module, it includes a resistor R3, a diode D2 and a resistor R4. One end of the resistor R3 is connected to the mutual inductor, and the other end of the resistor R3 is connected to the cathode of the diode D2 and one end of the resistor R4. The connection point serves as the output end of the second detection module. The anode of the diode D2 is connected to the other end of the resistor R4, and the connection point is connected to the reference ground of the control circuit.

[0011] As a specific implementation of the signal processing module, it includes an OR logic gate circuit and a delay circuit, wherein the first input end of the OR logic gate circuit is connected to the output end of the first detection module, the second input end of the OR logic gate circuit is connected to the output end of the second detection module, and the output end of the OR logic gate circuit is connected to the input end of the delay circuit, and the output end of the delay circuit is used to output the zero current detection signal of the bridgeless power factor correction circuit.

[0012] Another specific implementation of the signal processing module includes a comparator combination circuit, a delay circuit, a signal blanking circuit and a signal output circuit; the comparator combination circuit is used to generate a square wave signal, including a comparator U1, a comparator U2 and an OR logic gate circuit, the first input end of the comparator U1 is connected to the output end of the first detection module, the second input end of the comparator U1 is connected to the reference voltage Vref, and the output end of the comparator U1 is connected to the first input end of the OR logic gate circuit; the first input end of the comparator U2 is connected to the output end of the second detection module, the second input end of the comparator U2 is connected to the reference voltage Vref, the output end of the comparator U2 is connected to the second input end of the OR logic gate circuit, and the output end of the OR logic gate circuit is connected to the input end of the delay circuit; the blanking circuit is used to shield the zero current detection false trigger signal, the input end of the signal blanking circuit is connected to the output end of the delay circuit, and the output end of the signal blanking circuit is connected to the input end of the signal output circuit; the output end of the signal output circuit is used to output the zero current detection signal of the bridgeless power factor correction circuit.

[0013] Preferably, the signal blanking circuit comprises a monostable trigger.

[0014] Preferably, the signal output circuit includes an AND logic gate circuit.

[0015] The present invention also provides a zero current detection method for a bridgeless power factor correction circuit, comprising the following steps:

[0016] a current zero-crossing detection step, detecting the zero-crossing signal of the inductor current of the bridgeless power factor correction circuit through a mutual inductor, and utilizing the saturation characteristics of the mutual inductor to make the voltage of the terminal directly connected to the bridgeless power factor correction circuit zero, thereby reducing sampling loss;

[0017] a zero current detection voltage signal generating step, generating zero current detection voltage signals of positive and negative half cycles through a detection module;

[0018] The zero current detection voltage signal output step outputs the zero current detection signal required for the entire power frequency cycle.

[0019] A specific process of the step of outputting the zero current detection voltage signal is that the zero current detection signals of the positive and negative half cycles are combined and then pass through a delay circuit and then output.

[0020] Another specific process of the zero current detection voltage signal output step is that the zero current detection signals of the positive and negative half cycles are combined and passed through a delay circuit, followed by signal blanking to shield the zero current detection false trigger signal, and then output.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. It can realize reliable sampling of ZCD (zero current detection), reduce negative current, reduce sampling loss and improve system efficiency;

[0023] 2. This circuit can be easily expanded to other PFC circuit applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Totem pole bridgeless PFC circuit diagram;

[0025] Figure 2 A circuit diagram of a zero current detection solution in the prior art;

[0026] Figure 3 Circuit diagram of the second zero current detection scheme of the prior art;

[0027] Figure 4 A schematic diagram of a circuit according to a first embodiment of the present invention;

[0028] Figure 5 A timing diagram of the operation of the zero current detection circuit in the first embodiment of the present invention;

[0029] Figure 6 Schematic diagram of the main conduction during the positive half-cycle of the PFC circuit in the first embodiment of the present invention;

[0030] Figure 7 Schematic diagram of the auxiliary tube conduction during the positive half-cycle of the PFC circuit in the first embodiment of the present invention;

[0031] Figure 8 A circuit diagram of a second embodiment of the present invention;

[0032] Figure 9 A timing diagram of the operation of the zero current detection circuit in the second embodiment of the present invention; DETAILED DESCRIPTION

[0033] First embodiment

[0034] like Figure 4 FIG. 1 is a circuit diagram of a first embodiment of the present invention.

[0035] A zero current detection circuit for a bridgeless power factor correction circuit includes a mutual inductor 201, a first detection module 202, a second detection module 203 and a signal processing module 204.

[0036] The transformer 201 is used to sense the zero-crossing signal of the inductor current of the bridgeless power factor correction circuit, utilizing the transformer saturation characteristics to reduce zero-current detection sampling loss and improve system efficiency. The transformer 201 includes a primary inductor unit and a secondary inductor unit. The primary inductor unit includes an inductor L1, the same-name end of the inductor L1 is connected to one end of the input voltage source, and the opposite-name end of the inductor L1 is connected to one end of the main power inductor L of the bridgeless power factor correction circuit; the secondary inductor unit includes an inductor L2 and an inductor L3, the same-name end of the inductor L2 is connected to one end of the first detection module 202, the opposite-name end of the inductor L3 is connected to one end of the second detection module 203, and the opposite-name end of the inductor L2 and the same-name end of the inductor L3 are connected to the control circuit reference ground GND.

[0037] The first detection module 202 is used to generate the zero-current detection voltage signal required for the negative half-cycle. It includes a resistor R1, a diode D1, and a resistor R2. One end of the resistor R1 is connected to the same-name terminal of the inductor L2. The other end of the resistor R1 is connected to the cathode of the diode D1 and one end of the resistor R2. The connection point is the output end of the first detection module 202. The anode of the diode D1 and the other end of the resistor R2 are connected to the control circuit reference ground GND. The voltage at the output end of the first detection module 202 is determined by the voltage across the primary inductor unit of the transformer, the turns ratio, and the resistance. Wherein, V1 is the output terminal voltage of the first detection module 202, Vs1 is the voltage across the inductor L2 of the secondary inductor unit of the transformer, R1 is the resistance value of the resistor R1, R2 is the resistance value of the resistor R2, Vp is the voltage across the primary inductor unit of the transformer, and N is the turns ratio of the transformer.

[0038] The second detection module 203 is used to generate the zero-current detection voltage signal required for the positive half-cycle. It includes a resistor R3, a diode D2, and a resistor R4. One end of the resistor R3 is connected to the opposite-polarity terminal of the inductor L3. The other end of the resistor R3 is connected to the cathode of the diode D2 and one end of the resistor R4. The connection point is the output end of the second detection module 203. The anode of the diode D2 and the other end of the resistor R4 are connected to the control circuit reference ground GND. The voltage at the output end of the second detection module 203 is determined by the voltage across the primary inductor unit of the transformer, the turns ratio, and the resistance. Wherein, V2 is the output terminal voltage of the second detection module 203, Vs2 is the voltage across the inductor L2 of the secondary inductor unit of the transformer, R3 is the resistance value of the resistor R3, R4 is the resistance value of the resistor R4, Vp is the voltage across the primary inductor unit of the transformer, and N is the turns ratio of the transformer.

[0039] The signal processing module 204 includes an OR logic gate circuit OR1 and a delay circuit. The first input end of the OR logic gate circuit OR1 is connected to the output end of the first detection module 202, the second input end thereof is connected to the output end of the second detection module 203, and the output end thereof is connected to the input end of the delay circuit. The delay circuit is used to set a trigger delay time so that when the inductor current is reduced to 0 or close to 0, the output end generates a zero current detection signal ZCD of the bridgeless power factor correction circuit, thereby realizing zero voltage turn-on of the switch tube.

[0040] Taking the positive half cycle of the sinusoidal alternating voltage as an example (the positive half cycle is when the L line voltage is higher than the N line voltage), the detailed working principle of the zero current detection circuit of the bridgeless power factor correction circuit is as follows:

[0041] Specific timings such as Figure 5 As shown, I L is the inductor current, V AB is the voltage between the same-name terminal of the primary inductance unit of the transformer and the other end of the main power inductor L of the bridgeless power factor correction circuit, Vp is the voltage across the primary inductance unit of the transformer, Vs1 is the voltage across the inductor L2 of the secondary inductance unit of the transformer, and Vs2 is the voltage across the inductor L2 of the secondary inductance unit of the transformer. Vs1 and Vs2 are divided by resistors to obtain V1 and V2 respectively;

[0042] At t0, the main power MOS tube Q2 of the PFC circuit is in the on state. Figure 6 As shown in the circuit, the main power inductor L is excited, and the inductor current I L When the current flowing through the inductor L1 rises to the forward saturation current threshold Isat (the saturation threshold is set relatively small, close to 0), the inductor L1 coil is saturated. At this time, the inductor L1 is close to a short-circuit state, and the voltage Vp across it drops to 0, that is, V1 and V2 are both 0;

[0043] At t0-t1, the main power MOS tube Q2 of the PFC circuit is still in the on state, and the inductor current I L Continue to increase, the inductor current I L Still greater than the forward saturation current threshold Isat, the transformer is in saturation state, Vp = 0, and there is almost no sampling loss in the circuit;

[0044] At t1-t2, the main power MOS tube Q2 is turned off, and the PFC circuit power MOS tube Q1 is turned on. Figure 7As shown in the circuit, the main power inductor L is demagnetized and the inductor current I L Decrease, due to the inductor current I L It is still greater than the forward saturation current threshold Isat, so the transformer is still in saturation state, Vp = 0, and there is almost no sampling loss in the circuit;

[0045] At time t2-t3, the main power MOS tube Q2 is in the off state, and the power MOS tube Q1 is in the on state. At time t2, when the current flowing through the inductor L1 drops below the forward saturation current threshold Isat, the transformer desaturates, and the voltage Vp across the inductor L1 coil is subjected to negative voltage. Since the voltages across the inductors L2 and L3 coils simultaneously satisfy the following relationship:

[0046]

[0047] Therefore, both Vs1 and Vs2 are negative voltages. Due to the reference ground GND, diode D1 is subjected to forward voltage and is turned on. The output voltage V1 is clamped by diode D1 and is a negative voltage close to zero. Conversely, diode D2 is subjected to reverse voltage and is turned off. The output voltage V2 is a positive voltage.

[0048] Inductor current I L After dropping to zero, it increases in the reverse direction until t3. The inductor current I L When the negative saturation current threshold -Isat is reached, the transformer is saturated again. Similarly, at this time, the inductor L1 is close to a short-circuit state, and the voltage Vp across it drops to 0.

[0049] At time t3-t4, the main power MOS tube Q2 is in the off state, and the power MOS tube Q1 is in the on state. At this time, the negative inductor current is still greater than the negative saturation current threshold -Isat, the mutual inductor is in the saturation state, Vp = 0, and there is almost no sampling loss in the circuit at this time;

[0050] At time t4-t5, the main power MOS transistor Q2 turns on again, the power MOS transistor Q1 turns off, and the negative inductor current decreases. However, the negative inductor current is still greater than the negative saturation current threshold -Isat during this stage, the transformer is in saturation, Vp = 0, and there is almost no sampling loss in the circuit.

[0051] At time t5, the main power MOS tube Q2 is in the on state. When the negative current flowing through the transformer inductor L1 coil drops to the negative saturation current threshold -Isat, the transformer inductor L1 desaturates and the voltage Vp across it is subjected to positive voltage. Therefore, Vs1 and Vs2 are both positive voltages. Due to the reference ground GND, the diode D1 is subjected to reverse voltage and cuts off at this moment, and the output voltage V1 is a positive voltage. Conversely, at this moment, the diode D2 is subjected to forward voltage and turns on. The output voltage V2 is clamped by the diode D2 and is a negative voltage close to zero.

[0052] Until time t6, when the current flowing through the primary inductor L1 of the transformer rises to the forward saturation current threshold Isat again, the transformer is saturated again;

[0053] Similarly, the detailed working principle of the negative half cycle will not be repeated here.

[0054] Comparing the existing technology with the present invention, the zero-current detection circuit is designed to utilize the saturation characteristics of the transformer. When the current flowing through the transformer's primary inductor reaches its saturation current threshold, the transformer saturates. At this point, the voltage Vp across its primary coil is nearly zero (approaching a short-circuit state), and the sampling circuit is virtually lossless, thus reducing sampling losses and improving system efficiency.

[0055] Second embodiment

[0056] Figure 8 This is the second embodiment of the present invention, which is different from the first embodiment in that the signal processing module 204 includes a comparator combination circuit, a delay circuit, a signal blanking circuit and a signal output circuit. The comparator combination circuit includes an OR logic gate circuit OR2, a comparator U1 and a comparator U2. The first input end of the comparator U1 is connected to the output end of the first detection module 202, the second input end of the comparator U1 is connected to the reference value Vref, the output end of the comparator U1 is connected to the first input end of the OR logic gate circuit OR2, the first input end of the comparator U2 is connected to the output end of the second detection module 203, the second input end of the comparator U2 is connected to the reference value Vref, the output end of the comparator U2 is connected to the second input end of the OR logic gate circuit OR2, and the output end of the OR logic gate circuit OR2 is connected to the input end of the delay circuit. The delay circuit, the signal blanking circuit and the signal output circuit are connected in series in sequence. The output end of the signal output circuit outputs the zero current detection signal ZCD of the bridgeless power factor correction circuit to achieve zero voltage turn-on of the switch tube.

[0057] It is used to improve the reliability of the zero current detection circuit and prevent false triggering signals from affecting the normal operation of the system.

[0058] The positive half cycle working timing diagram of the second embodiment of the present invention is as follows: Figure 9 As shown, I L Main power inductor current, V Q2 is the positive half-cycle driving voltage signal, V ZCD1 V is the voltage signal output by the comparator combination circuit after the delay circuit. ZCD2 It is a processing signal inside the signal blanking circuit, V ZCD It is the voltage signal output by the signal blanking circuit.

[0059] The operating principle of the comparator combination circuit is that when the output voltage V1 of the first detection module 202 or the output voltage V2 of the second detection module 203 is greater than Vref, the output of the comparator U1 or U2 outputs a high level; otherwise, it outputs a low level square wave signal. The reference value Vref should be set appropriately and not too large. Because at high input voltage peaks, the output voltage difference (Vo-Vin) between the input voltage and the output voltage is small, the transformer secondary voltage (V1 or V2) may not reach the comparator reference value Vref, resulting in the circuit failing to detect the ZCD signal, causing abnormal inductor current and affecting the system THD value.

[0060] The signal blanking circuit is used to shield the voltage signal V output by the comparator combination circuit after the delay circuit. ZCD1 To eliminate the false trigger signal in the circuit, the signal blanking function can be realized by using a monostable trigger.

[0061] Depend on Figure 9 It can be seen that at the peak of the inductor current, V ZCD1 A false trigger signal occurs, because V ZCD2 It is a low level signal, so the false trigger signal is blanked and then output V ZCD Therefore, this embodiment can achieve reliable sampling of the zero current detection signal.

[0062] The above disclosure is only a preferred embodiment of the present invention, but the present invention is not limited thereto. Any modifications made to the present invention by any technician in this field without departing from the core idea of the present invention should fall within the scope of protection of the claims of the present invention.

Claims

1. A zero current detection circuit for a bridgeless power factor correction circuit, characterized in that: The invention comprises a mutual inductor, a first detection module, a second detection module and a signal processing module; the mutual inductor is used to be connected to one end of the main power inductor of the bridgeless power factor correction circuit, the first detection module and the second detection module are respectively connected to the two ends of the secondary side of the mutual inductor, the first input end of the signal processing module is connected to the output end of the first detection module, and the second input end of the signal processing module is connected to the output end of the second detection module; the mutual inductor is used to sense the inductor current zero-crossing signal of the bridgeless power factor correction circuit and reduce the sampling loss according to its saturation characteristics, the first detection module is used to generate the zero current detection voltage signal required for the negative half cycle, and the second detection module is used to generate the zero current detection voltage signal required for the positive half cycle. The current detection voltage signal, the signal processing module is used to combine and generate the zero current detection signal required by the circuit in the entire power frequency cycle; the transformer is provided with a positive saturation current threshold and a negative saturation current threshold of the primary side, the positive saturation current threshold is less than the positive inductance current peak value of the bridgeless power factor correction circuit, the absolute value of the negative saturation current threshold is less than the absolute value of the negative inductance current peak value of the bridgeless power factor correction circuit, when the primary side inductance current value of the transformer is greater than the negative saturation current threshold and less than the positive saturation current threshold, it is not saturated, when the primary side inductance current value of the transformer is less than or equal to the negative saturation current threshold or greater than or equal to the positive saturation current threshold, it is saturated.

2. The zero current detection circuit according to claim 1, wherein: The mutual inductor includes a primary inductance unit and a secondary inductance unit, the first end of the primary inductance unit is connected to one end of the input voltage source, and the second end of the primary inductance unit is connected to one end of the main power inductor of the bridgeless power factor correction circuit; the secondary inductance unit includes a first inductor and a second inductor, the first end of the first inductor is connected to one end of the first detection module, the second end of the first inductor is connected to the control circuit reference ground and the first end of the second inductor, and the second end of the second inductor is connected to one end of the second detection module.

3. The zero current detection circuit according to claim 1, wherein: The first detection module includes a resistor R1, a diode D1 and a resistor R2. One end of the resistor R1 is connected to the mutual inductor, and the other end of the resistor R1 is connected to the cathode of the diode D1 and one end of the resistor R2. The connection point is the output end of the first detection module. The anode of the diode D1 is connected to the other end of the resistor R2, and the connection point is connected to the reference ground of the control circuit.

4. The zero current detection circuit according to claim 1, wherein: The second detection module includes a resistor R3, a diode D2 and a resistor R4. One end of the resistor R3 is connected to the mutual inductor, and the other end of the resistor R3 is connected to the cathode of the diode D2 and one end of the resistor R4. The connection point serves as the output end of the second detection module. The anode of the diode D2 is connected to the other end of the resistor R4, and the connection point is connected to the reference ground of the control circuit.

5. The zero current detection circuit according to claim 1, wherein: The signal processing module includes an OR logic gate circuit and a delay circuit, wherein the first input end of the OR logic gate circuit is connected to the output end of the first detection module, the second input end of the OR logic gate circuit is connected to the output end of the second detection module, and the output end of the OR logic gate circuit is connected to the input end of the delay circuit, and the output end of the delay circuit is used to output the zero current detection signal of the bridgeless power factor correction circuit.

6. The zero current detection circuit according to claim 1, wherein: The signal processing module includes a comparator combination circuit, a delay circuit, a signal blanking circuit and a signal output circuit; the comparator combination circuit is used to generate a square wave signal, including a comparator U1, a comparator U2 and an OR logic gate circuit, the first input end of the comparator U1 is connected to the output end of the first detection module, the second input end of the comparator U1 is connected to the reference voltage Vref, and the output end of the comparator U1 is connected to the first input end of the OR logic gate circuit; the first input end of the comparator U2 is connected to the output end of the second detection module, the second input end of the comparator U2 is connected to the reference voltage Vref, the output end of the comparator U2 is connected to the second input end of the OR logic gate circuit, and the output end of the OR logic gate circuit is connected to the input end of the delay circuit; the blanking circuit is used to shield the zero current detection false trigger signal, the input end of the signal blanking circuit is connected to the output end of the delay circuit, and the output end of the signal blanking circuit is connected to the input end of the signal output circuit; the output end of the signal output circuit is used to output the zero current detection signal of the bridgeless power factor correction circuit.

7. The zero current detection circuit according to claim 6, wherein: The signal blanking circuit includes a monostable trigger.

8. The zero current detection circuit according to claim 6, wherein: The signal output circuit includes an AND logic gate circuit.

9. A zero current detection method for a bridgeless power factor correction circuit, characterized in that: The steps include: a current zero-crossing detection step, detecting the zero-crossing signal of the inductor current of the bridgeless power factor correction circuit through a mutual inductor, and utilizing the saturation characteristics of the mutual inductor to make the voltage of the terminal directly connected to the bridgeless power factor correction circuit zero, thereby reducing sampling loss; a zero current detection voltage signal generating step, generating zero current detection voltage signals of positive and negative half cycles through a detection module; a zero current detection voltage signal output step, outputting the zero current detection signal required for the entire power frequency cycle; Wherein: the transformer is provided with a positive saturation current threshold and a negative saturation current threshold of the primary side, the positive saturation current threshold is less than the positive inductance current peak value of the bridgeless power factor correction circuit, the absolute value of the negative saturation current threshold is less than the absolute value of the negative inductance current peak value of the bridgeless power factor correction circuit, when the primary side inductance current value of the transformer is greater than the negative saturation current threshold and less than the positive saturation current threshold, it is not saturated, and when the primary side inductance current value of the transformer is less than or equal to the negative saturation current threshold or greater than or equal to the positive saturation current threshold, it is saturated.

10. The zero current detection method according to claim 9, characterized in that: The specific process of the zero current detection voltage signal output step is as follows: The zero current detection signals of the positive and negative half cycles are combined and passed through the delay circuit before being output; Alternatively, the zero current detection signals of the positive and negative half cycles are combined and passed through a delay circuit, followed by signal blanking to shield the zero current detection false trigger signal, and then output.

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