Packaging structure and manufacturing method thereof

Abstract

A packaging structure includes a circuit substrate, a semiconductor package, a cover structure, and a plurality of first spacer structures. The semiconductor package is disposed on the circuit substrate and electrically connected to the circuit substrate. The cover structure is disposed on the circuit substrate and covers the semiconductor package, wherein the cover structure is attached to the circuit substrate by an adhesive material. The plurality of first spacer structures surround the semiconductor package, wherein the first spacer structure is sandwiched between the cover structure and the circuit substrate, and includes a top portion in contact with the cover structure and a bottom portion in contact with the circuit substrate.

Description

Technical Field

[0001] The present disclosure is related to a packaging structure and a method for manufacturing the packaging structure. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic applications (e.g., cell phones and other mobile electronic devices) are typically manufactured on a single semiconductor wafer. The die of the wafer can be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies have been developed for wafer level packaging. Summary of the invention

[0003] The present disclosure provides a packaging structure including a circuit substrate, a semiconductor package, a cover structure, and a plurality of first spacer structures. The semiconductor package is disposed on the circuit substrate and electrically connected to the circuit substrate. The cover structure is disposed on the circuit substrate and covers the semiconductor package, wherein the cover structure is attached to the circuit substrate by an adhesive material. The plurality of first spacer structures surround the semiconductor package, wherein the first spacer structure is sandwiched between the cover structure and the circuit substrate, and includes a top portion in contact with the cover structure and a bottom portion in contact with the circuit substrate.

[0004] The embodiment of the present disclosure provides a packaging structure including a circuit substrate, an interposer structure, a plurality of semiconductor dies, a cover structure, a thermal interface material, and a plurality of first spacer structures. The interposer structure is disposed on the circuit substrate and electrically connected to the circuit substrate. The plurality of semiconductor dies are disposed on the interposer structure and electrically connected to the interposer structure. The cover structure is disposed on the circuit substrate, wherein the cover structure includes a cover body portion and a side wall portion, the cover body portion is located above the plurality of semiconductor dies, the side wall portion is bonded to the cover body portion and surrounds the plurality of semiconductor dies and the interposer structure, and the side wall portion is adhered to the circuit substrate by an adhesive material. The thermal interface material is disposed between the plurality of semiconductor dies and the cover body portion of the cover structure. The plurality of first spacer structures are disposed adjacent to the adhesive material between the circuit substrate and the side wall portion of the cover structure.

[0005] The embodiment of the present disclosure provides a method for manufacturing a packaging structure. The method comprises the following steps. A circuit substrate is provided. A plurality of first spacer structures are placed on the circuit substrate, wherein the plurality of first spacer structures include a top portion and a bottom portion, and the bottom portion is in contact with the circuit substrate. A semiconductor package is set in an area on the circuit substrate surrounded by the first spacer structure. A cover structure is attached to the circuit substrate by an adhesive material, wherein the cover structure surrounds the semiconductor package, the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate, and the cover structure is in contact with the top portions of the plurality of first spacer structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A to Figure 1H are schematic cross-sectional views of various stages in a method of fabricating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0008] Figures 2A to 2F are schematic cross-sectional views and top views of various stages in a method of manufacturing a package structure according to some exemplary embodiments of the present disclosure.

[0009] FIG. 3A to FIG. 3C are various designs of spacer structures according to some exemplary embodiments of the present disclosure.

[0010] Figure 4A and Figure 4B are schematic cross-sectional views of various methods of placing a spacer structure on a wiring substrate according to some exemplary embodiments of the present disclosure.

[0011] Figure 5A and Figure 5B are various designs of spacer structures according to some other exemplary embodiments of the present disclosure.

[0012] Fig. 6A and Figure 6B are schematic cross-sectional views of various methods of placing a spacer structure on a wiring substrate according to some exemplary embodiments of the present disclosure.

[0013] FIG. 7A to FIG. 7D are schematic cross-sectional views and top views of various stages in a method of manufacturing a package structure according to some exemplary embodiments of the present disclosure.

[0014] FIG. 8A to FIG. 8Care enlarged cross-sectional views of various package structures according to some exemplary embodiments of the present disclosure.

[0015] Fig. 9 are packaging structures according to some other exemplary embodiments of the present disclosure.

[0016] Fig. 10A and Fig. 10B are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some other exemplary embodiments of the present disclosure.

[0017] Fig.11 are packaging structures according to some other exemplary embodiments of the present disclosure.

[0018] Fig.12 Detailed description of the invention is given in conjunction with some comparative embodiments of the present invention.

[0019] Fig.13 are packaging structures according to some other exemplary embodiments of the present disclosure.

[0020] [Explanation of Symbols]

[0021] 40: First spacer structure / spacer structure

[0022] 40-BS, 42-BS: Bottom part

[0023] 40C: Conductive core

[0024] 40CL: Column structure or columnar structure

[0025] 40PC: Polymer core

[0026] 40PS: polymer shell

[0027] 40S: Conductive shell

[0028] 40-TS, 42-TS: Top section

[0029] 42: Second spacer structure / spacer structure

[0030] 100: Interposer structure / interposer

[0031] 100': Intermediary layer structure

[0032] 102: Core part

[0033] 102a: First surface

[0034] 102b: Second surface

[0035] 104: Perforation

[0036] 106, 210, 220, 602B, 610: Conductive pads

[0037] 110: Electrical connector

[0038] 112. UX: Bottom Fill Structure

[0039] 114: Insulation seal

[0040] 114a, 116s: Top surface

[0041] 114b, D1-X, D2-X: dorsal surface

[0042] 116: Rewiring Structure

[0043] 116a, 604, 608B: Dielectric layer

[0044] 116b: Metallized pattern

[0045] 118: Conductive terminal

[0046] 200: Circuit substrate

[0047] 200A: First side

[0048] 200B: Second side

[0049] 230, 608A: Metallization layer

[0050] 250, 612: Conductive ball

[0051] 310: Solder paste

[0052] 320: Adhesive

[0053] 510: Thermal interface material

[0054] 520: Cover structure

[0055] 520A: Cover

[0056] 520B: Side wall

[0057] 602: Semiconductor die

[0058] 602A: Semiconductor Substrate

[0059] 602C: Passivation layer

[0060] 602D: Post passivation layer

[0061] 602E: Conductive pillars or vias

[0062] 602F: Protective layer

[0063] 606: Insulation seal

[0064] 608: Rewiring Layer

[0065] ADM, ADM1, ADM2: Adhesive materials

[0066] CM: Connecting material

[0067] CR, CX: carrier

[0068] D1: Semiconductor die

[0069] D2: Semiconductor die / die

[0070] D1A, D2A: body

[0071] D1B, D2B: connection pads

[0072] D1-S, D2-S: Effective surface

[0073] DL: Cutting Lane

[0074] Dx: distance

[0075] FR: Frame

[0076] MX: Mixture

[0077] OP1: First opening

[0078] OP2: Second opening

[0079] OP3: The third opening

[0080] OX: contact opening

[0081] OY: Open

[0082] PDX: Passive Device

[0083] PKR: Packaging Region

[0084] PK0, PK1, PK1', PK2, PK3, PK4, PK5: Package structure

[0085] SM: Semiconductor packaging / semiconductor packaging structure

[0086] SM2: Semiconductor Packaging

[0087] TP: With

[0088] Tx, Ty: thickness

[0089] W1: Width DETAILED DESCRIPTION

[0090] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a second feature is formed on or on a first feature may include an embodiment in which the second feature is formed to be in direct contact with the first feature, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature so that the second feature may not be in direct contact with the first feature. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0091] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "on," "over," "overlying," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0092] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate so that the 3D package or 3DIC can be tested, probes and / or probe cards can be used, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with a test method that includes intermediate verification of a known good die to improve yield and reduce costs.

[0093] Figure 1A to Figure 1H Schematic cross-sectional views of various stages in a method of manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure. Figure 1A, providing an interposer structure 100. In some embodiments, the interposer structure 100 includes a core portion 102, and a plurality of through holes 104 and a conductive pad 106 formed in the core portion 102. In some embodiments, the core portion 102 may be a substrate, such as a bulk semiconductor substrate, a silicon on insulator (SOI) substrate, or a multilayer semiconductor material substrate. The semiconductor material of the substrate (core portion 102) may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. In some embodiments, the core portion 102 may be doped or undoped.

[0094] In some embodiments, the conductive pad 106 is formed on the first surface 102a of the core portion 102. In some embodiments, the through hole 104 is formed in the core portion 102 and connected to the conductive pad 106. In some embodiments, the through hole 104 extends into the core portion 102 at a specific depth. In some embodiments, the through hole 104 is a substrate through hole. In some embodiments, when the core portion 102 is a silicon substrate, the through hole 104 is a silicon through hole. In some embodiments, the through hole 104 can be formed by forming a hole or a groove in the core portion 102 and then filling the groove with a conductive material. In some embodiments, the groove can be formed by, for example, etching, milling, laser drilling, etc. In some embodiments, the conductive material can be formed by an electrochemical plating process, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the conductive material can include copper, tungsten, aluminum, silver, gold, or a combination thereof. In some embodiments, the conductive pad 106 connected to the through-hole 104 can be formed as a conductive portion of a redistribution layer formed on the interposer structure 100. In some embodiments, the conductive pad 106 includes an under bump metallurgy (UBM). In some embodiments, the interposer structure 100 may also include an active device or a passive device formed in the core portion 102, such as a transistor, a capacitor, a resistor, or a diode passive device.

[0095] like Figure 1AAs shown in , the core part 102 has a plurality of package areas PKR and a cutting line DL separating each of the plurality of package areas PKR. A through hole 104 and a conductive pad 106 are formed in the core part 102 within the package area PKR. In some embodiments, the semiconductor die D1 and the semiconductor die D2 are disposed on the interposer structure 100, or on the core part 102 within the package area PKR. The semiconductor die D1 and the semiconductor die D2 are single dies singulated from a wafer. In some embodiments, the semiconductor die D1 includes the same circuit system, such as a device and a metallization pattern, or the semiconductor die D1 is the same type of die. In some embodiments, the semiconductor die D2 includes the same circuit system, or the semiconductor die D2 is the same type of die. In certain embodiments, the semiconductor die D1 and the semiconductor die D2 have different circuit systems or are different types of dies. In an alternative embodiment, the semiconductor die D1 and the semiconductor die D2 may have the same circuit system.

[0096] In some embodiments, semiconductor die D1 may be a main die, and semiconductor die D2 is an auxiliary die. In some embodiments, the main die is arranged on the core portion 102 in the center of each package area PKR, and the auxiliary die is arranged side by side and spaced apart from the main die. In some embodiments, the auxiliary die is arranged next to the main die and surrounds or surrounds the main die. In one embodiment, four or six auxiliary dies are arranged around a main die in each package area PKR. The present disclosure is not limited to this.

[0097] In some embodiments, the surface area of ​​semiconductor die D1 is greater than the surface area of ​​semiconductor die D2. In addition, in some embodiments, semiconductor die D1 and semiconductor die D2 may have different sizes, including different surface areas and / or different thicknesses. In some embodiments, semiconductor die D1 may be a logic die, including a central processing unit (CPU) die, a graphics processing unit (GPU) die, a system-on-a-chip (SoC) die, a microcontroller, etc. In some embodiments, semiconductor die D1 is a power management die, such as a power management integrated circuit (PMIC) die. In some embodiments, semiconductor die D2 may be a memory die, including a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, or a high bandwidth memory (HBM) die. The present disclosure is not limited thereto, and the number, size, and type of semiconductor dies disposed on core portion 102 may be appropriately adjusted based on product requirements.

[0098] In the illustrated embodiment, semiconductor die D1 includes a body D1A and connection pads D1B formed on an active surface D1-S of body D1A. In some embodiments, connection pads D1B may further include a pillar structure for bonding semiconductor die D1 to other structures. In some embodiments, semiconductor die D2 includes a body D2A and connection pads D2B formed on an active surface D2-S of body D2A. In other embodiments, connection pads D2B may further include a pillar structure for bonding die D2 to other structures.

[0099] In some embodiments, the semiconductor die D1 and the semiconductor die D2 are attached to the first surface 102a of the core portion 102, for example, by flip-chip bonding through an electrical connector 110. By a reflow process, the electrical connector 110 is formed between the connection pads D1B, D2B and the conductive pad 106, and the semiconductor die D2, D1 are electrically connected and physically connected to the core portion 102 of the interposer structure 100. In some embodiments, the electrical connector 110 is located between the semiconductor die D1, D2 and the interposer structure 100. In certain embodiments, the semiconductor die D1, D2 are electrically connected to the through-hole 104 and the conductive pad 106 through the electrical connector 110. In one embodiment, the electrical connector 110 is a microbump, such as a microbump with a copper metal column. In another embodiment, the electrical connector 110 is a solder bump, a lead-free solder bump, or a microbump, such as a controlled collapse chip connection (C4) bump or a microbump containing a copper column. In some embodiments, the bonding between semiconductor dies D1, D2 and core portion 102 may be solder bonding. In some embodiments, the bonding between semiconductor dies D1, D2 and core portion 102 may be direct metal-to-metal bonding, such as copper-to-copper bonding.

[0100] Reference Figure 1B In the next step, an underfill structure 112 may be formed to cover the plurality of electrical connectors 110 and fill the space between the semiconductor dies D1, D2 and the interposer structure 100. In some embodiments, the underfill structure 112 further covers the sidewalls of the semiconductor dies D1, D2 and is located within the packaging region PKR. Thereafter, an insulating sealant 114 may be formed on the interposer structure 100 (or on the core portion 102) to cover the underfill structure 112 and surround the semiconductor dies D1 and D2.

[0101] In some embodiments, the insulating sealant 114 is formed on the first surface 102a of the core part 102 in the package area PKR and on the scribe line DL. In some embodiments, the insulating sealant 114 is formed by, for example, a compression molding process or transfer molding. In one embodiment, a curing process is performed to cure the insulating sealant 114. In some embodiments, the insulating sealant 114 encapsulates the semiconductor die D1, D2 and the electrical connector 110. In some embodiments, a planarization process (including grinding or polishing) can be performed to partially remove the insulating sealant 114, thereby exposing the back side surfaces D1-X and D2-X of the semiconductor die D1 and D2. Therefore, the back side surfaces D1-X and D2-X of the semiconductor die D1 and D2 are flush with the top surface 114a of the insulating sealant 114. The top surface 114a is opposite to the back side surface 114b of the insulating sealant 114, wherein the back side surface 114b is in contact with the core part 102.

[0102] In some embodiments, the material of the insulating seal 114 includes a polymer (e.g., epoxy resin, phenolic resin, silicone resin, or other suitable resin), a dielectric material with low permittivity (Dk) and low loss tangent (Df) properties, or other suitable materials. In alternative embodiments, the insulating seal 114 may include an acceptable insulating seal material. In some embodiments, the insulating seal 114 may also include an inorganic filler or inorganic compound (e.g., silicon dioxide, clay, etc.) that can be added to the insulating seal 114 to optimize the coefficient of thermal expansion (CTE) of the insulating seal 114. The present disclosure is not limited thereto.

[0103] Reference Figure 1C ,Will Figure 1B The structure of is inverted or flipped and placed on the carrier CR, so that the carrier CR directly contacts the backside surfaces D1-X, D2-X of the semiconductor dies D1, D2 and the top surface 114a of the insulating sealing body 114. Figure 1C As shown in FIG. 1 , at this processing stage, the interposer structure 100 has not been thinned and has a thickness Tx. In other words, the through-vias 104 are not exposed and are embedded in the core portion 102 of the interposer structure 100 .

[0104] Reference Figure 1D, a thinning process is performed on the interposer 100 to partially remove or thin the core portion 102 of the interposer structure 100 until the through-hole 104 is exposed and the second surface 102b of the core portion 102 is formed. In some embodiments, the thinning process may include a backside grinding process, a polishing process, or an etching process. In some embodiments, after the thinning process, the interposer structure 100 is thinned to a thickness Ty. In some embodiments, the ratio of the thickness Ty to the thickness Tx is in a range from about 0.1 to about 0.5.

[0105] Reference Figure 1E , a rewiring structure 116 is formed on the second surface 102b of the core portion 102 in the package area PKR and above the cutting line DL. The second surface 102b of the core portion 102 is opposite to the first surface 102a of the core portion 102. In some embodiments, the rewiring structure 116, the core portion 102, the through-hole 104 and the conductive pad 106 constitute an interposer structure 100'. In some embodiments, the rewiring structure 116 electrically connects the through-hole 104 and / or electrically connects the through-hole 104 to an external device. In certain embodiments, the rewiring structure 116 includes at least one dielectric layer 116a and a metallization pattern 116b located in the dielectric layer 116a. In some embodiments, the metallization pattern 116b may include pads, vias and / or traces to interconnect the through-hole 104 and further connect the through-hole 104 to one or more external devices. Although in Figure 1E One dielectric layer 116a and one metallization pattern 116b are shown in FIG. 1 , but it should be noted that the number of layers of the dielectric layer 116a and the metallization pattern 116b is not limited thereto and can be adjusted based on requirements.

[0106] In some embodiments, the material of the dielectric layer 116a includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a low dielectric constant dielectric material (e.g., phosphosilicate glass material, fluorosilicate glass material, borophosphosilicate glass material, SiOC, spin-on glass material, spin-on polymer, or silicon carbon material). In some embodiments, the dielectric layer 116a may be formed by spin coating or deposition (including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-CVD (HDP-CVD), etc.). In some embodiments, the metallization pattern 116b includes an under-bump metallurgy (UBM). In some embodiments, forming the metallization pattern 116b may include patterning the dielectric layer using photolithography and one or more etching processes and filling the metal material into the opening of the patterned dielectric layer. Any excess conductive material on the dielectric layer may be removed, for example, by using a chemical mechanical polishing process. In some embodiments, the material of the metallization pattern 116 b includes copper, aluminum, tungsten, silver, and combinations thereof.

[0107] like Figure 1E As shown in , a plurality of conductive terminals 118 are provided on the metallization pattern 116b, and the plurality of conductive terminals 118 are electrically coupled to the through-hole 104. In some embodiments, the conductive terminal 118 is placed on the top surface 116s of the rewiring structure 116, and is electrically connected to the through-hole 104 through the metallization pattern 116b in the package area PKR. In certain embodiments, the conductive terminal 118 is positioned on the metallization pattern 116b and physically attached to the metallization pattern 116b. In some embodiments, the conductive terminal 118 includes a lead-free solder ball, a solder ball, a ball grid array (BGA) ball, a bump, a C4 bump, or a microbump. In some embodiments, the conductive terminal 118 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or a combination thereof. In some embodiments, the conductive terminal 118 is formed by forming a solder paste on the rewiring structure 116 by, for example, evaporation, electroplating, printing, or solder transfer, and then the conductive terminal 118 is reflowed into a desired bump shape. In some embodiments, the conductive terminal 118 is placed on the redistribution structure 116 by ball planting or the like. In other embodiments, the conductive terminal 118 is formed by forming a solder-free metal column (e.g., a copper column) by sputtering, printing, electroless plating, or electroplating or CVD, and then forming a lead-free cap layer by plating the metal column. The conductive terminal 118 can be used to be coupled to an external device or an additional electrical component. In some embodiments, the conductive terminal 118 is used to be coupled to a circuit substrate, a semiconductor substrate, or a packaging substrate.

[0108] Reference Figure 1F In a subsequent step, the carrier CR is peeled off. For example, the peeling process includes projecting light such as laser or UV light onto a peeling layer (e.g., a light-heat conversion release layer) attached to the carrier CR (not shown), so that the carrier CR can be easily removed together with the peeling layer. In some embodiments, the backside surfaces D1-X, D2-X of the semiconductor dies D1, D2 are exposed after the peeling process.

[0109] Reference Figure 1G After the carrier CR is peeled off, Figure 1F The structure shown in FIG. 1 is attached to a tape TP (eg, a dicing tape) supported by a frame FR. Subsequently, the tape is cut along a dicing lane DL. Figure 1F , to form a plurality of semiconductor packages SM. For example, a cutting process is performed to cut through the redistribution structure 116, the core portion 102, and the insulating seal 114, thereby removing some portions of the redistribution structure 116, some portions of the core portion 102, and some portions of the insulating seal 114 along the dicing lines DL. In some embodiments, the cutting process or the singulation process generally involves cutting using a rotating blade or a laser beam. In other words, the cutting process or the singulation process is, for example, a laser dicing process, a mechanical sawing process, or other suitable processes. After the carrier CR is peeled off, the Figure 1H The singulated semiconductor package SM shown in FIG.

[0110] Figures 2A to 2F Schematic cross-sectional views and top views of various stages in a method of manufacturing a package structure according to some exemplary embodiments of the present disclosure. Figure 2A , providing a circuit substrate 200. In some embodiments, the circuit substrate 200 is composed of a dielectric layer. In some embodiments, the circuit substrate 200 is an organic flexible substrate or a printed circuit board. In some embodiments, the circuit substrate 200 includes a conductive pad 210, a conductive pad 220, a metallization layer 230, and a through hole (not shown) embedded in the circuit substrate 200. In some embodiments, the conductive pad 210 and the conductive pad 220 are respectively distributed on two opposite sides of the circuit substrate 200, and are exposed to be electrically connected to the components / features formed later. For example, in some embodiments, the circuit substrate 200 is patterned to form a first opening OP1, a second opening OP2, and a contact opening OX that expose the conductive pad 210 located on the first side 200A of the circuit substrate 200. In addition, in some embodiments, the circuit substrate 200 is patterned to form an opening OY that exposes the conductive pad 220 located on the second side 200B of the circuit substrate 200.

[0111] In some embodiments, the metallization layer 230 and the through hole are embedded in the circuit substrate 200 and together provide a wiring function for the circuit substrate 200, wherein the metallization layer 230 and the through hole are electrically connected to the conductive pads 210 and the conductive pads 220. In other words, at least some of the conductive pads 210 are electrically connected to some of the conductive pads 220 through the metallization layer 230 and the through hole. In some embodiments, the conductive pads 210 and the conductive pads 220 may include metal pads or metal alloy pads. In some embodiments, the material of the metallization layer 230 and the material of the through hole may be substantially the same as or similar to the material of the conductive pads 210 and the material of the conductive pads 220.

[0112] Reference Figure 2B After patterning the circuit substrate 200, the solder paste 310 is disposed in the first opening OP1, the second opening OP2, and the contact opening OX of the circuit substrate 200. For example, the solder paste 310 is disposed in the first opening OP1, the second opening OP2, and the contact opening OX by printing. In the next step, a plurality of first spacer structures 40 are placed in the second opening OP2 of the circuit substrate 200 and on the solder paste 310. In an exemplary embodiment, the material of the first spacer structure 40 is not particularly limited and may be a conductive material, a polymer material, etc. This will be described in detail in a later embodiment.

[0113] Reference Figure 2C In the next step, Figure 1H The semiconductor package SM obtained in the embodiment is mounted on the circuit substrate 200 through the conductive terminal 118. For example, the semiconductor package SM is mounted on the circuit substrate 200 by providing the conductive terminal 118 in the first opening OP1 of the circuit substrate 200 and on the solder paste 310. Figure 2D , Figure 2D yes Figure 2C , the semiconductor package SM is disposed in an area surrounded by the first spacer structure 40 on the circuit substrate 200. In some embodiments, the first spacer structure 40 surrounds four sides of the semiconductor package SM. In addition, approximately 10 to 15 first spacer structures 40 may be located on each side. However, the present disclosure is not limited thereto, and the number of first spacer structures 40 surrounding the semiconductor package SM may be adjusted based on product requirements.

[0114] like Figure 2C and Figure 2DAs shown in , in some embodiments, a passive device PDX (integrated passive device or surface mounted device) may be mounted on the circuit substrate 200 next to the semiconductor package SM. For example, the passive device PDX is mounted on the circuit substrate 200 within the contact opening OX of the circuit substrate 200 and on the solder paste 310. After the first spacer structure 40, the conductive terminal 118, and the passive device PDX are placed / mounted in their respective openings, a reflow process is performed to bond the first spacer structure 40 to the conductive pad 210 of the circuit substrate 200. Similarly, a reflow process is performed to bond the conductive terminal 118 and the passive device PDX to the conductive pad 210 of the circuit substrate 200. In other words, the first spacer structure 40, the conductive terminal 118, and the passive device PDX are mounted on the conductive pad 210 of the circuit substrate 200 by a soldering process. In some embodiments, after the reflow process is performed, the semiconductor package SM and the passive device PDX may be electrically connected to the conductive pad 210 of the circuit substrate 200. In addition, the semiconductor package SM and the passive device PDX may be further electrically connected to the conductive pad 220, the metallization layer 230 and the through hole. In some embodiments, the first spacer structure 40 may or may not be electrically connected to the conductive pad 220, which will depend on the material used for the first spacer structure 40. In some embodiments, the first spacer structure 40 has a bottom portion 40-BS that is in physical contact with the conductive pad 210 of the wiring substrate 200.

[0115] like Figure 2E As shown in , in some embodiments, a bottom filling structure UX is formed to fill the space between the circuit substrate 200 and the semiconductor package SM. In some embodiments, the bottom filling structure UX fills the space between adjacent conductive terminals 118 and covers the conductive terminals 118. For example, the bottom filling structure UX surrounds the plurality of conductive terminals 118. In some embodiments, the bottom filling structure UX exposes the passive device PDX, and the passive device PDX is kept a certain distance away from the bottom filling structure UX. In other words, the bottom filling structure UX does not cover the passive device PDX. In some embodiments, the bottom filling structure UX may further cover the sidewalls of the semiconductor package SM.

[0116] Reference Figure 2F, after forming the bottom filling structure UX, the thermal interface material 510 is disposed on the back side of the semiconductor package SM. Thereafter, the cover structure 520 is bonded to the circuit substrate 200 by the adhesive material ADM. In some embodiments, the cover structure 520 is pressed onto the thermal interface material 510 so that the thermal interface material 510 is sandwiched between the semiconductor package structure SM and the cover structure 520. In some embodiments, the cover structure 520 surrounds the semiconductor package SM and the passive device PDX. For example, the cover structure 520 includes a cover body portion 520A located above the semiconductor die D1 and D2, and includes a sidewall portion 520B bonded to the cover body portion 520A. The sidewall portion 520B may surround the semiconductor die D1, D2 and the interposer structure 100', and be bonded to the circuit substrate 200 by the adhesive material ADM.

[0117] like Figure 2F As further shown in FIG. 5 , the first spacer structure 40 is sandwiched between the cap structure 520 and the wiring substrate 200. For example, the first spacer structure 40 includes a top portion 40-TS in contact with the cap structure 520 and a bottom portion 40-BS in contact with the wiring substrate 200. In some embodiments, the first spacer structure 40 is disposed between the wiring substrate 200 and the sidewall portion 520B of the cap structure 520 and is adjacent to the adhesive material ADM. In certain embodiments, the adhesive material ADM is also located between the cap structure 520 and the wiring substrate 200 and surrounds and contacts the first spacer structure 40. In addition, in some embodiments, the ratio (W1:Dx) of the width W1 of the sidewall portion 520B to the distance Dx between the wiring substrate 200 and the sidewall portion 520B is in the range of 10:1 to 30:1. For example, in an exemplary embodiment, when the width W1 is controlled in the range of 2 mm to 3 mm, the distance Dx can be controlled in the range of 100 μm to 200 μm. The distance Dx and the width W1 may be properly controlled to prevent delamination and uneven arrangement of the thermal interface material 510 and the adhesive material ADM, as well as problems of extrusion and seepage of these materials.

[0118] In an exemplary embodiment, by arranging the first spacer structure 40 between the cover structure 520 and the circuit substrate 200, the distance Dx between the circuit substrate 200 and the sidewall portion 520B can be appropriately maintained. In other words, the force applied during the bonding of the cover structure 520 to the circuit substrate 200 is controlled by maintaining the distance Dx between the cover structure 520 and the circuit substrate 200. For example, the first spacer structure 40 is used to prevent the distance Dx from being too small (excessive force applied) and to prevent the distance Dx from being too large (low force applied). In addition, the width W1 of the sidewall portion 520B is directly related to the amount of adhesive material ADM used. Therefore, the width W1 is also controlled within a certain range so that the sidewall portion 520B of the cover structure 520 is wide enough to cover the first spacer structure 40 while preventing excessive adhesive material ADM from being applied.

[0119] In certain embodiments, when the ratio of the width W1 to the distance Dx (W1:Dx) is maintained within the above range, problems caused by low applied force (thick thermal interface material 510 causing high thermal resistance) or problems caused by excessive applied force (squeezing out and seepage of adhesive material ADM) during lamination of the cover structure 520, as well as other related problems such as delamination and uneven arrangement of the thermal interface material 510 and the adhesive, can be prevented. On the other hand, when the ratio of the width W1 to the distance Dx (W1:Dx) is outside the above range, there is a risk that the thermal interface material 510 and the adhesive material ADM have uneven arrangement, thereby causing seepage and extrusion, etc.

[0120] In some embodiments, after the cap structure 520 is attached to the circuit substrate 200, a plurality of conductive balls 250 are placed in the opening OY of the circuit substrate 200, and the plurality of conductive balls 250 are electrically connected to the conductive pads 220. In some embodiments, the conductive balls 250 are, for example, solder balls or BGA balls. At this point, the package structure PK1 according to some exemplary embodiments of the present disclosure is completed.

[0121] FIG. 3A to FIG. 3C 4 are various designs of spacer structures according to some exemplary embodiments of the present disclosure. In the above embodiments, the first spacer structure 40 is shown as having a ball structure or a spherical structure. However, the present disclosure is not limited thereto, and the design of the first spacer structure 40 may be appropriately adjusted. Figure 3A As shown in FIG. 4 , the first spacer structure 40 is shown to include a ball structure having a conductive core 40C. In some embodiments, the conductive core 40C may be made of any conductive material or metal material (e.g., copper, tungsten, aluminum, silver, gold, etc.), and the present disclosure is not limited thereto. Figure 3BAs shown in FIG. 1 , in addition to having a conductive core 40C, the first spacer structure 40 may also include a conductive shell 40S coated around the conductive core 40C. In other words, the first spacer structure 40 may include a core-shell structure. In some embodiments, the material of the conductive shell 40S may be any conductive material, metal material, or metal alloy. In an exemplary embodiment, the conductive shell 40S may be a solder shell. Figure 3C As further shown in FIG. 1 , in some embodiments, the first spacer structure 40 includes a column structure or a columnar structure 40CL. For example, the column structure or the columnar structure 40CL can be made of any conductive material or metal material (such as copper, tungsten, aluminum, silver, gold, etc.), and the present disclosure is not limited thereto.

[0122] Figure 4A and Figure 4B is a schematic cross-sectional view of various methods of placing a spacer structure on a circuit substrate according to some exemplary embodiments of the present disclosure. Figure 4A In some embodiments, when the first spacer structure 40 includes a conductive material such as a conductive core 40C, the first spacer structure 40 may be placed on or attached to the conductive pad 210 of the circuit substrate 200 through a connecting material CM. For example, the connecting material CM may be the solder paste 310 used in the previous embodiment. In some embodiments, the bottom portion 40-BS of the conductive core 40C contacts the conductive pad 210, and the connecting material CM surrounds the conductive core 40C and contacts the conductive pad 210.

[0123] In an exemplary embodiment, when a conductive material such as a conductive core 40C or a conductive shell 40S is located on the outer surface of the first spacer structure 40, the first spacer structure 40 can be bonded to the circuit substrate 200 through a reflow process. For example, in such an embodiment, a first opening OP1 and a second opening OP2 are formed on the circuit substrate 200, and a solder paste 310 is disposed in the first opening OP1 and the second opening OP2 of the circuit substrate 200. The first spacer structure 40 can be placed in the second opening OP2 of the circuit substrate 200, and the conductive terminal 118 of the semiconductor package SM can be disposed in the first opening OP1 of the circuit substrate 200. Thereafter, a reflow process can be performed to bond both the first spacer structure 40 and the conductive terminal 118 to the conductive pad 210 of the circuit substrate 200.

[0124] Reference Figure 4BIn some other embodiments, when the first spacer structure 40 includes a conductive material such as a conductive core 40C, the first spacer structure 40 may be placed on or attached to the dielectric layer of the circuit substrate 200 through another connecting material CM. For example, the connecting material CM may be any adhesive 320, glue, etc. In some embodiments, the bottom portion 40-BS of the conductive core 40C contacts the dielectric layer of the circuit substrate 200, and the connecting material CM surrounds the conductive core 40C and contacts the circuit substrate 200.

[0125] Figure 5A and Figure 5B 1 and 2 are various designs of spacer structures according to some other exemplary embodiments of the present disclosure. In the previous embodiments, the first spacer structure 40 is attached to the circuit substrate 200 by a conductive material, but the present disclosure is not limited thereto, and other materials may be applied. Figure 5A In some embodiments, the first spacer structure 40 is shown to include a ball structure having a conductive core 40C, and the conductive core 40C is coated with a polymer shell 40PS. In other words, a core-shell structure having a non-conductive shell located on the outer surface of the conductive core 40C is applied to the first spacer structure 40. Figure 5B In some other embodiments, the first spacer structure 40 is shown to include a ball structure having a polymer core 40PC, and the polymer core 40PC is coated with a polymer shell 40PS. In other words, a core-shell structure having a non-conductive shell located on the outer surface of the polymer core 40PC is applied to the first spacer structure 40. In some alternative embodiments, the first spacer structure 40 may include a polymer core 40PC without any shell structure coated thereon.

[0126] Fig. 6A and Figure 6B is a schematic cross-sectional view of various methods of placing a spacer structure on a circuit substrate according to some exemplary embodiments of the present disclosure. Fig. 6A In some embodiments, when the first spacer structure 40 includes a non-conductive material (e.g., a polymer shell 40PS covering the conductive core 40C), the first spacer structure 40 can be placed on or attached to the conductive pad 210 of the circuit substrate 200 through the connecting material CM. For example, the connecting material CM can be any adhesive 320, glue, etc. In a similar manner, the bottom portion 40-BS of the polymer shell 40PS contacts the conductive pad 210, and the connecting material CM surrounds the polymer shell 40PS and contacts the conductive pad 210.

[0127] In an exemplary embodiment, when a polymer material such as the polymer core 40PC or the polymer shell 40PS is located on the outer surface of the first spacer structure 40, the first spacer structure 40 may be bonded to the circuit substrate 200 through the adhesive 320. For example, in such an embodiment, a first opening OP1 and a second opening OP2 are formed on the circuit substrate 200, and the first spacer structure 40 is placed in the second opening OP2, and the first spacer structure 40 is bonded to the conductive pad 210 of the circuit substrate 200 through the adhesive 320. In some embodiments, the solder paste 310 is disposed in the first opening OP1, and the conductive terminal 118 of the semiconductor package SM is disposed in the first opening OP1 of the circuit substrate 200. Thereafter, a reflow process may be performed to bond the conductive terminal 118 to the conductive pad 210 of the circuit substrate 200.

[0128] Reference Figure 6B In some other embodiments, when the first spacer structure 40 includes a non-conductive material (e.g., a polymer shell 40PS covering the polymer core 40PC), the first spacer structure 40 can be placed on or attached to the dielectric layer of the circuit substrate 200 through the connecting material CM. For example, the connecting material CM can be any adhesive 320, glue, etc. In some embodiments, the bottom portion 40-BS of the polymer core 40PC contacts the dielectric layer of the circuit substrate 200, and the connecting material CM surrounds the polymer core 40PC and contacts the circuit substrate 200.

[0129] FIG. 7A to FIG. 7D are schematic cross-sectional views and top views of various stages in a method of manufacturing a package structure according to some exemplary embodiments of the present disclosure. FIG. 7A to FIG. 7D The method shown in is similar to Figures 2A to 2F Therefore, the same reference numerals are used to refer to the same or similar components, and detailed descriptions thereof will be omitted herein. The difference between the embodiments is that a second spacer structure 42 is further provided.

[0130] Reference Fig. 7A , executable Figure 2A to Figure 2C The same method described in the above is used to dispose the conductive terminal 118 of the semiconductor package SM in the first opening OP1, dispose the first spacer structure 40 in the second opening OP2, and dispose the passive device PDX in the contact opening OX. Fig. 7AAs shown in , in some embodiments, a plurality of third openings OP3 are further formed in the circuit substrate 200, and a plurality of second spacer structures 42 are disposed in the third openings OP3. In some embodiments, the first spacer structure 40 and the second spacer structure 42 are attached to the conductive pad 210 of the circuit substrate 200 by using the connection material CM as described above. In an exemplary embodiment, the material and design of the second spacer structure 42 may be the same as the first spacer structure 40. In some alternative embodiments, the material and design of the second spacer structure 42 may be different from the first spacer structure 40. For example, FIG. 3A to FIG. 3C , Figure 5A and Figure 5B The various designs of the spacer structures shown in FIG. 4 are applied to the second spacer structure 42 .

[0131] like Figure 7B As shown in Figure 7B yes Fig. 7A In some embodiments, the second spacer structure 42 may be disposed on the circuit substrate 200 to surround the first spacer structure 40. For example, the second spacer structure 42 may be arranged in parallel around the four sides of the semiconductor package SM next to the first spacer structure 40. However, the present disclosure is not limited thereto, and the arrangement of the second spacer structure 42 may be adjusted based on design requirements. For example, in Figure 7C In some alternative embodiments shown in FIG. 1 , the first spacer structure 40 and the second spacer structure 42 are arranged in a zig-zag manner or staggered around the semiconductor package SM on the circuit substrate 200. For example, the first spacer structure 40 and the second spacer structure 42 may surround the interposer structure 100'.

[0132] Reference Fig.7D After the first spacer structure 40 and the second spacer structure 42 are disposed on the circuit substrate 200, the cap structure 520 is attached to the circuit substrate 200 through the adhesive material ADM. In an exemplary embodiment, the second spacer structure 42 is sandwiched between the cap structure 520 and the circuit substrate 200, and includes a top portion 42-TS in contact with the cap structure 520 and a bottom portion 42-BS in contact with the circuit substrate 200. For example, the second spacer structure 42 is disposed between the circuit substrate 200 and the sidewall portion 520B of the cap structure 520 adjacent to the adhesive material ADM.

[0133] like Fig.7DAs further shown in FIG. 5 , the adhesive material ADM is interposed between the cap structure 520 and the circuit substrate 200, and covers and contacts the first spacer structure 40 and the second spacer structure 42. In addition, in some embodiments, the ratio (W1:Dx) of the width W1 of the sidewall portion 520B to the distance Dx between the circuit substrate 200 and the sidewall portion 520B is still maintained in the range of 10:1 to 30:1. In this way, the delamination and uneven arrangement of the thermal interface material 510 and the adhesive material ADM, as well as the extrusion and seepage of these materials, can be prevented.

[0134] For example, in an exemplary embodiment, when the ratio of the width W1 to the distance Dx (W1:Dx) is maintained within the above range, problems caused by low applied force (thick thermal interface material 510 causing high thermal resistance) or problems caused by excessive applied force (extrusion and seepage of adhesive material ADM) during lamination of the cover structure 520 can be prevented, as well as other related problems such as delamination and uneven arrangement of the thermal interface material 510 and the adhesive. On the other hand, when the ratio of the width W1 to the distance Dx (W1:Dx) is outside the above range, there is a risk that the thermal interface material 510 and the adhesive material ADM have uneven arrangement, thereby causing seepage and extrusion, etc.

[0135] After the cap structure 520 is attached to the circuit substrate 200, a plurality of conductive balls 250 are placed in the openings OY of the circuit substrate 200 and electrically connected to the conductive pads 220. Thus, the package structure PK2 according to some exemplary embodiments of the present disclosure is completed.

[0136] FIG. 8A to FIG. 8C is an enlarged cross-sectional view of various packaging structures according to some exemplary embodiments of the present disclosure. For the embodiment including the first spacer structure 40 and the second spacer structure 42, their arrangement relative to the adhesive material ADM is further described. Fig. 8A In some embodiments, the sidewall portion 520B of the cap structure 520 is attached to the circuit substrate 200 through the adhesive material ADM, so that the adhesive material ADM covers and contacts both the first spacer structure 40 and the second spacer structure 42. However, the present disclosure is not limited thereto.

[0137] Reference Figure 8B In some embodiments, the sidewall portion 520B of the cap structure 520 is attached to the circuit substrate 200 through the adhesive material ADM, but the adhesive material ADM is separated from the first spacer structure 40 and the second spacer structure 42. In other words, the adhesive material ADM does not contact the first spacer structure 40 and the second spacer structure 42. In this embodiment, the first spacer structure 40 and the second spacer structure 42 are further away from each other (relative to Fig. 8AIn some embodiments, the adhesive material ADM is located in the space between the first spacer structure 40 and the second spacer structure 42 and is sandwiched between the wiring substrate 200 and the sidewall portion 520B of the cap structure 520.

[0138] Reference Figure 8C In some embodiments, the sidewall portion 520B of the cap structure 520 is attached to the circuit substrate 200 by the adhesive material ADM, whereby the adhesive material ADM covers and contacts the first spacer structure 40 and is spaced apart from the second spacer structure 42. However, the present disclosure is not limited thereto. In some alternative embodiments, the adhesive material ADM covers and contacts the second spacer structure 42 and is spaced apart from the first spacer structure 40. In other words, the adhesive material ADM may cover at least one of the plurality of first spacer structures 40 and the plurality of second spacer structures 42 while being spaced apart from the other of the plurality of first spacer structures 40 and the plurality of second spacer structures 42. Such an embodiment may be achieved by selectively disposing the adhesive material ADM on the first spacer structure 40 or the second spacer structure 42 during the bonding of the cap structure 520 to the circuit substrate 200.

[0139] Fig. 9 are packaging structures according to some other exemplary embodiments of the present disclosure. Fig. 9 The package structure PK3 shown in Fig.7D The package structure PK2 shown in FIG. 1 is a package structure PK2, so the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will be omitted herein. The difference between the embodiments is the design of the second spacer structure 42. In the previous embodiments, both the first spacer structure 40 and the second spacer structure 42 have a ball structure design in the package structure. However, the present disclosure is not limited to this. Fig. 9 In some embodiments, the first spacer structure 40 has a ball structure and the second spacer structure 42 has a column structure or a columnar structure. In the case where the first spacer structure 40 and the second spacer structure 42 have different designs, they can still have substantially the same height. Based on the above embodiments, it can be noted that the design and arrangement of the spacer structures (40 / 42) can be appropriately adjusted as long as the spacer structures (40 / 42) help control the height or distance between the circuit substrate 200 and the cover structure 520.

[0140] Fig. 10A and Fig. 10B are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some other exemplary embodiments of the present disclosure. Fig. 10A and Fig. 10B The method shown in is similar to Figures 2A to 2FTherefore, the same reference numerals are used to refer to the same or similar components, and detailed descriptions thereof will be omitted herein. The difference between the embodiments is the method of attaching the first spacer structure 40 to the circuit substrate 200.

[0141] In the previous embodiments, the first spacer structure 40 may be attached to the circuit substrate 200 (either on the dielectric layer or on the conductive pad 210) by a connecting material CM (e.g., solder paste 310 or adhesive 320, with or without a reflow process). However, the present disclosure is not limited thereto, and the connecting material CM may be omitted. For example, referring to Fig. 10A In some embodiments, the mixture MX is first formed by mixing the first spacer structure 40 with the adhesive material ADM. In some embodiments, the mixture MX is dispensed onto the circuit substrate 200. For example, the mixture MX can be dispensed onto the circuit substrate 200 so that the first spacer structure 40 is located within the second opening OP2 of the circuit substrate 200, and the adhesive material ADM covers the first spacer structure 40. In some alternative embodiments, the mixture MX can be dispensed onto the circuit substrate 200 so that the first spacer structure 40 is disposed on the dielectric layer of the circuit substrate 200.

[0142] Reference Fig. 10B , after dispensing the mixture MX on the circuit substrate 200, the cover structure 520 can be attached to the circuit substrate 200 through the adhesive material ADM, thereby sandwiching the first spacer structure 40 between the cover structure 520 and the circuit substrate 200. At this point, the package structure PK1' according to some other exemplary embodiments of the present disclosure can be completed. It should be noted that in other embodiments in which there is a second spacer structure 42, the second spacer structure 42 can also be provided on the circuit substrate 200 by forming a mixture, and the mixture can be dispensed on the circuit substrate 200 for attaching the cover structure 520.

[0143] Fig.11 are packaging structures according to some other exemplary embodiments of the present disclosure. Fig.11 The package structure PK4 shown in Figure 2F Therefore, the same reference numerals are used to refer to the same or similar components, and detailed descriptions thereof will be omitted herein. The difference between the embodiments is the design and arrangement of the first spacer structure 40 and the adhesive material ADM.

[0144] like Fig.11As shown in , in some embodiments, the adhesive material may be formed as part of the first spacer structure 40. For example, in an exemplary embodiment, the first spacer structure 40 may include a carrier CX, an adhesive material ADM1 located on one surface of the carrier CX, and another adhesive material ADM2 located on another surface of the carrier CX. For example, the first spacer structure 40 may be a double-sided tape spacer. In some embodiments, the adhesive material ADM1 is attached to the cover structure 520, and the adhesive material ADM2 is attached to the circuit substrate 200. Similar to the above embodiment, the cover structure 520 may be attached to the circuit substrate 200 by the adhesive material (ADM1 and ADM2), and the first spacer structure 40 (including ADM1, CX and ADM2) is sandwiched between the cover structure 520 and the circuit substrate 200. Similarly, in an exemplary embodiment, the ratio (W1:Dx) of the width W1 of the sidewall portion 520B to the distance Dx between the circuit substrate 200 and the sidewall portion 520B is still maintained in the range of 10:1 to 30:1. In this way, delamination and uneven arrangement of the thermal interface material 510 and the adhesive material (ADM1 / ADM2), as well as the extrusion and seepage of these materials, can be prevented.

[0145] For example, in an exemplary embodiment, when the ratio of the width W1 to the distance Dx (W1:Dx) is maintained within the above range, problems caused by low applied force (thick thermal interface material 510 causing high thermal resistance) or problems caused by excessive applied force (extrusion and seepage of the thermal interface material 510) during lamination of the cover structure 520, as well as other related problems such as delamination and uneven arrangement of the thermal interface material 510 and the adhesive can be prevented. On the other hand, when the ratio of the width W1 to the distance Dx (W1:Dx) is outside the above range, there is a risk that the thermal interface material 510 and the adhesive material have uneven arrangement, thereby causing seepage and extrusion, etc.

[0146] At this point, the package structure PK4 according to some exemplary embodiments of the present disclosure is completed.

[0147] Fig.12 Detailed description of the invention is given in conjunction with some comparative embodiments of the present invention. Fig.12 The comparative package structure PK0 shown in Figure 2F The package structure PK1 shown in FIG. 1 is a package structure PK1, and thus the same reference numerals are used to refer to the same or similar components, and detailed descriptions thereof will be omitted herein. The difference between the embodiments is that the first spacer structure 40 is omitted from the package structure PK0.

[0148] Reference Fig.12In some comparative embodiments, since there is no spacer structure between the cover structure 520 and the circuit substrate 200, it is difficult to control the force applied during the bonding of the cover structure 520 to the circuit substrate 200. As a result, the package structure PK0 may suffer from many problems, such as delamination and uneven arrangement of the thermal interface material 510 and the adhesive material ADM. For example, in some embodiments, when excessive force is applied during the bonding of the cover structure 520, the thermal interface material 510 may be squeezed out and cover the sidewalls of the semiconductor package SM, thereby causing reliability problems. Similarly, the adhesive material ADM may tend to seep toward the adjacent passive device PDX and potentially damage the passive device PDX.

[0149] Fig.13 are packaging structures according to some other exemplary embodiments of the present disclosure. Fig.13 The package structure shown in PK5 is similar to Figure 2F The package structure PK1 shown in FIG. 1 is similar to the package structure PK1 shown in FIG. 1 , and therefore the same reference numerals are used to refer to the same or similar components, and their detailed descriptions will be omitted herein. The difference between the embodiments is the design of the semiconductor package. Figure 2F As shown in , the semiconductor package SM relates to a chip-on-wafer (CoW) package. However, the present disclosure is not limited thereto. For example, referring to Fig.13 , provide semiconductor package SM2 to replace Figure 2F The semiconductor package SM shown in FIG.

[0150] In an exemplary embodiment, the semiconductor package SM2 includes a semiconductor die 602, a dielectric layer 604, an insulating seal 606, a redistribution layer 608, a conductive pad 610, and a conductive ball 612. The semiconductor die 602 is located on the dielectric layer 604. The insulating seal 606 is located on the dielectric layer 604 and surrounds the semiconductor die 602. In some embodiments, the semiconductor die 602 includes a semiconductor substrate 602A, a plurality of conductive pads 602B, a passivation layer 602C, a post-passivation layer 602D, a plurality of conductive pillars or vias 602E, and a protective layer 602F. Fig.13As shown in , the plurality of conductive pads 602B are disposed on a semiconductor substrate 602A. A passivation layer 602C is formed on the semiconductor substrate 602A and has an opening partially exposing the conductive pads 602B on the semiconductor substrate 602A. The semiconductor substrate 602A may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and further includes active components (e.g., transistors, etc.) and optional passive components (e.g., resistors, capacitors, inductors, etc.) formed therein. The conductive pads 602B may be aluminum pads, copper pads, or other suitable metal pads. The passivation layer 602C may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of any suitable dielectric material.

[0151] In addition, in some embodiments, a post passivation layer 602D is optionally formed on the passivation layer 602C. The post passivation layer 602D covers the passivation layer 602C and has a plurality of contact openings. The contact openings of the post passivation layer 602D partially expose the conductive pad 602B. The post passivation layer 602D may be a benzocyclobutene (BCB) layer, a polyimide layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed by other suitable polymers. In some embodiments, a conductive column or via 602E is formed on the conductive pad 602B by plating. In some embodiments, a protective layer 602F is formed on the post passivation layer 602D covering the conductive column or via 602E to protect the conductive column or via 602E. Although only one semiconductor die 602 is shown herein, it should be noted that the present disclosure is not limited thereto, and the number of semiconductor dies 602 in the semiconductor package SM2 may be more than one.

[0152] In addition, if Fig.13 As shown in , the redistribution layer 608 is formed on the insulating seal 606 and is electrically connected to the semiconductor die 602. In some embodiments, forming the redistribution layer 608 includes sequentially forming one or more dielectric layers 608B and one or more metallization layers 608A in an alternating manner. In certain embodiments, the metallization layer 608A is sandwiched between the dielectric layers 608B. Although only three layers of metallization layers 608A and four layers of dielectric layers 608B are shown in this article, however, the scope of the present disclosure is not limited by the embodiments of the present disclosure. In other embodiments, the number of metallization layers 608A and dielectric layers 608B can be adjusted based on product requirements. In some embodiments, the metallization layer 608A is electrically connected to the conductive pillar 602E of the semiconductor die 602.

[0153] In some embodiments, a plurality of conductive pads 610 for electrically connecting to conductive balls are disposed on the exposed top surface of the topmost layer of the metallization layer 608A. In some embodiments, the conductive pads 610 are, for example, under ball metallization (UBM) patterns for ball mounting. Fig.13 As shown in , the conductive pad 610 is formed on the redistribution layer 608 and is electrically connected to the redistribution layer 608. In some embodiments, the material of the conductive pad 610 may include copper, nickel, titanium, tungsten, or alloys thereof, and the conductive pad 610 may be formed, for example, by an electroplating process. The number of the conductive pads 610 is not limited in the present disclosure and may be selected based on the design layout. In some alternative embodiments, the conductive pad 610 may be omitted. In other words, the conductive ball 612 formed in a subsequent step may be directly disposed on the redistribution layer 608.

[0154] like Fig.13 As shown in FIG. 6 , a plurality of conductive balls 612 are disposed on the conductive pad 610 and on the redistribution layer 608. In some embodiments, the conductive balls 612 may be disposed on the conductive pad 610 by a ball implantation process or a reflow process. In some embodiments, the conductive balls 612 are, for example, solder balls or ball grid array (BGA) balls. In some embodiments, the conductive balls 612 are connected to the redistribution layer 608 through the conductive pad 610. In certain embodiments, some of the conductive balls 612 may be electrically connected to the semiconductor die 602 through the redistribution layer 608. The number of the conductive balls 612 is not limited to the present disclosure and may be specified and selected based on the number of the conductive pads 610.

[0155] In an exemplary embodiment, the semiconductor package SM2 is disposed on the circuit substrate 200 by flip chip bonding. In some embodiments, the semiconductor package SM2 is electrically connected to the conductive pad 210 of the circuit substrate 200 through the conductive ball 612. In some embodiments, the conductive ball 612 is further protected by the bottom fill structure UX. Similar to the above embodiment, since the first spacer structure 40 is located between the cover structure 520 and the circuit substrate 200, the delamination and uneven arrangement of the adhesive material ADM, as well as the extrusion and seepage of the adhesive material ADM can be prevented.

[0156] In the above-mentioned embodiment, the packaging structure includes a plurality of first spacer structures sandwiched between the cover structure and the circuit substrate. In this way, when the cover structure is bonded to the circuit substrate, the applied force can be properly controlled. For example, problems caused by low applied force (thick thermal interface material causing high thermal resistance) or problems caused by excessive applied force (extrusion and seepage of materials) during bonding of the cover structure can be prevented, as well as other related problems such as delamination and uneven arrangement of thermal interface materials and adhesives. In general, a packaging structure with better reliability can be obtained.

[0157] According to some embodiments of the present disclosure, a packaging structure includes a circuit substrate, a semiconductor package, a cover structure, and a plurality of first spacer structures. The semiconductor package is disposed on the circuit substrate and electrically connected to the circuit substrate. The cover structure is disposed on the circuit substrate and covers the semiconductor package, wherein the cover structure is attached to the circuit substrate by an adhesive material. The plurality of first spacer structures surround the semiconductor package, wherein the first spacer structure is sandwiched between the cover structure and the circuit substrate, and includes a top portion in contact with the cover structure and a bottom portion in contact with the circuit substrate.

[0158] In some embodiments, the adhesive material covers and contacts the plurality of first spacer structures and the plurality of second spacer structures. In some embodiments, the adhesive material covers one of the plurality of first spacer structures or the plurality of second spacer structures and is spaced apart from the other of the plurality of first spacer structures or the plurality of second spacer structures. In some embodiments, each of the plurality of first spacer structures is a spherical structure, a core-shell structure, or a pillar structure.

[0159] According to some other embodiments of the present disclosure, a packaging structure includes a circuit substrate, an interposer structure, a plurality of semiconductor dies, a cover structure, a thermal interface material, and a plurality of first spacer structures. The interposer structure is disposed on the circuit substrate and electrically connected to the circuit substrate. The plurality of semiconductor dies are disposed on the interposer structure and electrically connected to the interposer structure. The cover structure is disposed on the circuit substrate, wherein the cover structure includes a cover body portion and a side wall portion, the cover body portion is located above the plurality of semiconductor dies, the side wall portion is bonded to the cover body portion and surrounds the plurality of semiconductor dies and the interposer structure, and the side wall portion is adhered to the circuit substrate by an adhesive material. The thermal interface material is disposed between the plurality of semiconductor dies and the cover body portion of the cover structure. The plurality of first spacer structures are disposed adjacent to the adhesive material between the circuit substrate and the side wall portion of the cover structure.

[0160] In some embodiments, the circuit substrate includes a plurality of openings, the plurality of openings exposing the conductive pads of the circuit substrate, and the plurality of first spacer structures are disposed within the plurality of openings and connected to the conductive pads. In some embodiments, the plurality of first spacer structures are attached to the dielectric layer of the circuit substrate. In some embodiments, the adhesive material is located between the plurality of first spacer structures and the plurality of second spacer structures, and is spaced apart from the plurality of first spacer structures and the plurality of second spacer structures. In some embodiments, the adhesive material covers at least one of the plurality of first spacer structures and the plurality of second spacer structures.

[0161] According to another embodiment of the present disclosure, a method for manufacturing a packaging structure is described. The method includes the following steps. A circuit substrate is provided. A plurality of first spacer structures are placed on the circuit substrate, wherein the plurality of first spacer structures include a top portion and a bottom portion, and the bottom portion is in contact with the circuit substrate. A semiconductor package is disposed in an area on the circuit substrate surrounded by the first spacer structure. A cover structure is attached to the circuit substrate by an adhesive material, wherein the cover structure surrounds the semiconductor package, the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate, and the cover structure is in contact with the top portions of the plurality of first spacer structures.

[0162] In some embodiments, the method further includes: forming a plurality of first openings and a plurality of second openings on the circuit substrate; placing the plurality of first spacer structures within the plurality of second openings of the circuit substrate, and bonding the plurality of first spacer structures to the circuit substrate using an adhesive; disposing solder paste within the plurality of first openings; and disposing the semiconductor package onto the circuit substrate by disposing a plurality of conductive terminals of the semiconductor package within the plurality of first openings of the circuit substrate, and performing a reflow process to bond the plurality of conductive terminals to the circuit substrate.

[0163] In some embodiments, placing the plurality of first spacer structures on the circuit substrate includes: forming a mixture by mixing the plurality of first spacer structures with the adhesive material and distributing the mixture on the circuit substrate; bonding the cover structure to the circuit substrate by pressing the cover structure onto the mixture so that the cover structure is bonded to the circuit substrate through the adhesive material, and wherein the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate.

[0164] In some embodiments, the method further includes: placing a plurality of second spacer structures on the circuit substrate so that they surround the plurality of first spacer structures; and bonding the cover structure to the circuit substrate through the adhesive material so that the plurality of second spacer structures are sandwiched between the cover structure and the circuit substrate.

[0165] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, comprising: Circuit substrate; A semiconductor package, disposed on the circuit substrate and electrically connected to the circuit substrate; a cover structure, disposed on the circuit substrate and covering the semiconductor package, wherein the cover structure is attached to the circuit substrate by an adhesive material; as well as A plurality of first spacer structures surround the semiconductor package, wherein the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate and include a top portion in contact with the cover structure and a bottom portion in contact with the circuit substrate, wherein the height of each of the plurality of first spacer structures is smaller than the height of the cover structure and smaller than the height of the semiconductor package. 2 . The package structure according to claim 1 , wherein the circuit substrate comprises a plurality of openings, the plurality of openings exposing conductive pads of the circuit substrate, and the plurality of first spacer structures are disposed in the plurality of openings and connected to the conductive pads.

3. The packaging structure according to claim 1 further includes a plurality of second spacer structures surrounding the plurality of first spacer structures, wherein the plurality of second spacer structures are sandwiched between the cover structure and the circuit substrate and include a top portion in contact with the cover structure and a bottom portion in contact with the circuit substrate. 4 . The package structure according to claim 3 , wherein the adhesive material is located between the plurality of first spacer structures and the plurality of second spacer structures, and is spaced apart from the plurality of first spacer structures and the plurality of second spacer structures. 5 . The package structure according to claim 3 , wherein the adhesive material covers and contacts the plurality of first spacer structures and the plurality of second spacer structures. 6 . The package structure according to claim 3 , wherein the adhesive material covers one of the plurality of first spacer structures or the plurality of second spacer structures and is spaced apart from the other of the plurality of first spacer structures or the plurality of second spacer structures. 7 . The package structure according to claim 1 , wherein each of the plurality of first spacer structures is a sphere structure, a core-shell structure or a pillar structure.

8. A packaging structure, comprising: Circuit substrate; an interposer structure, disposed on the circuit substrate and electrically connected to the circuit substrate; a plurality of semiconductor dies disposed on and electrically connected to the interposer structure; a cover structure disposed on the circuit substrate, wherein the cover structure comprises a cover body portion and a side wall portion, the cover body portion is located above the plurality of semiconductor dies, the side wall portion is bonded to the cover body portion and surrounds the plurality of semiconductor dies and the interposer structure, and the side wall portion is attached to the circuit substrate through an adhesive material, wherein a ratio W1:Dx of a width W1 of the side wall portion to a distance Dx between the circuit substrate and the side wall portion is in a range of 10:1 to 30:1; a thermal interface material disposed between the plurality of semiconductor dies and the cover portion of the cover structure; as well as A plurality of first spacer structures are disposed between the circuit substrate and the sidewall portion of the cap structure adjacent to the adhesive material. 9 . The package structure according to claim 8 , wherein the circuit substrate comprises a plurality of openings, the plurality of openings exposing conductive pads of the circuit substrate, and the plurality of first spacer structures are disposed in the plurality of openings and connected to the conductive pads. 10 . The package structure according to claim 8 , wherein the plurality of first spacer structures are attached to a dielectric layer of the circuit substrate. 11 . The package structure of claim 8 , further comprising a plurality of second spacer structures surrounding the plurality of first spacer structures, wherein the plurality of second spacer structures are disposed between the wiring substrate and the sidewall portion of the cap structure adjacent to the adhesive material. 12 . The package structure according to claim 11 , wherein the adhesive material is located between the plurality of first spacer structures and the plurality of second spacer structures, and is spaced apart from the plurality of first spacer structures and the plurality of second spacer structures. 13 . The package structure according to claim 11 , wherein the adhesive material covers at least one of the plurality of first spacer structures and the plurality of second spacer structures. 14 . The package structure according to claim 11 , wherein the plurality of first spacer structures and the plurality of second spacer structures are arranged in a zigzag manner around the interposer structure on the circuit substrate.

15. A method for manufacturing a packaging structure, comprising: Providing a circuit substrate; placing a plurality of first spacer structures on the circuit substrate, wherein the plurality of first spacer structures include a top portion and a bottom portion, and the bottom portion is in contact with the circuit substrate; Disposing a semiconductor package on the circuit substrate in an area surrounded by the plurality of first spacer structures; as well as The cover structure is adhered to the circuit substrate by an adhesive material, wherein the cover structure surrounds the semiconductor package, the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate, and the cover structure is in contact with the top portions of the plurality of first spacer structures, wherein the height of each of the plurality of first spacer structures is smaller than the height of the cover structure and smaller than the height of the semiconductor package.

16. The method according to claim 15, further comprising: forming a plurality of first openings and a plurality of second openings on the circuit substrate; disposing solder paste in the plurality of first openings and the plurality of second openings; placing the plurality of first spacer structures within the plurality of second openings of the wiring substrate; disposing the semiconductor package on the circuit substrate by disposing a plurality of conductive terminals of the semiconductor package in the plurality of first openings of the circuit substrate; as well as A reflow process is performed to bond the plurality of first spacer structures to the circuit substrate and to bond the plurality of conductive terminals to the circuit substrate.

17. The method according to claim 15, further comprising: forming a plurality of first openings and a plurality of second openings on the circuit substrate; placing the plurality of first spacer structures in the plurality of second openings of the circuit substrate, and bonding the plurality of first spacer structures to the circuit substrate using an adhesive; disposing solder paste within the plurality of first openings; as well as The semiconductor package is disposed on the circuit substrate by disposing a plurality of conductive terminals of the semiconductor package in the plurality of first openings of the circuit substrate, and a reflow process is performed to bond the plurality of conductive terminals to the circuit substrate.

18. The method of claim 15, wherein placing the plurality of first spacer structures on the wiring substrate comprises: forming a mixture by mixing the plurality of first spacer structures with the adhesive material and dispensing the mixture on the circuit substrate; The cover structure is attached to the circuit substrate by pressing the cover structure onto the mixture so that the cover structure is attached to the circuit substrate through the adhesive material, and wherein the plurality of first spacer structures are interposed between the cover structure and the circuit substrate.

19. The method according to claim 15, further comprising: placing a plurality of second spacer structures on the circuit substrate so as to surround the plurality of first spacer structures; as well as The cover structure is attached to the circuit substrate through the adhesive material so that the plurality of second spacer structures are sandwiched between the cover structure and the circuit substrate.

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