Nonvolatile memory device with ferroelectric layer

Abstract

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface and a gate structure disposed above the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulating layer pattern alternately laminated along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first direction and the second direction. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer and a source electrode structure and a drain electrode structure disposed in contact with the channel layer and spaced apart from each other in the second direction.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0163139, filed on December 9, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to a non-volatile memory device, and more specifically, to a non-volatile memory device having a ferroelectric layer. Background Technology

[0004] As design rules become more restrictive and integration density increases, research continues on semiconductor device structures that can simultaneously guarantee structural stability and signal storage reliability. Currently, flash memory devices employing a three-layer stacked structure of charge tunneling layer, charge trapping layer, and charge blocking layer are widely used for charge storage.

[0005] Recently, various non-volatile memory devices with structures different from existing flash memory devices have been proposed. An example of a non-volatile memory device is a ferroelectric memory device with a transistor structure. Ferroelectric memory devices can non-volatilely store any residual polarization of different sizes and orientations as signal information in the gate ferroelectric layer. Furthermore, the signal information can be read out by utilizing the characteristic that the magnitude of the operating current flowing through the channel layer between the source and drain electrodes changes according to the stored residual polarization. Summary of the Invention

[0006] A non-volatile memory device according to one aspect of this disclosure includes a substrate having an upper surface and a gate structure disposed above the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulating layer pattern alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. Additionally, the non-volatile memory device includes a ferroelectric layer disposed above the substrate on at least a portion of a sidewall surface of the gate structure. The sidewall surface of the gate structure is a plane defined by the first and second directions. The non-volatile memory device includes: a channel layer disposed above the substrate and on the ferroelectric layer; and a source electrode structure and a drain electrode structure, each disposed above the substrate and configured to contact the channel layer. The source electrode structure and the drain electrode structure are spaced apart from each other in the second direction.

[0007] A nonvolatile memory device according to another aspect of the present disclosure includes a substrate having an upper surface and a gate structure disposed above the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulating layer pattern alternately laminated along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure above the substrate. The one sidewall surface of the gate structure forms a plane substantially parallel to the first direction and the second direction. The nonvolatile memory device includes source and drain electrode structures disposed on the ferroelectric layer and spaced apart from each other in the second direction, and a channel structure disposed above the substrate and disposed between the source and drain electrode structures. Each of the source and drain electrode structures is disposed on the ferroelectric layer.

[0008] A nonvolatile memory device according to another aspect of the present disclosure includes a substrate and a gate structure disposed above the substrate having an upper surface. The gate structure includes at least one gate functional layer pattern and at least one gate insulating layer pattern alternately laminated along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes an interface insulating layer and a channel layer sequentially disposed on one sidewall surface of the gate structure. The one sidewall surface of the gate structure is a plane defined by the first direction and the second direction. The nonvolatile memory device includes source and drain electrode structures spaced apart from each other in the second direction. Each of the source and drain electrode structures contacts the channel layer. The gate functional layer pattern includes a floating electrode layer portion disposed on the interface insulating layer and the gate insulating layer pattern, a ferroelectric layer portion disposed on the floating electrode layer portion and the interface insulating layer, and a gate electrode layer portion disposed in contact with the ferroelectric layer portion. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a perspective view schematically showing a nonvolatile memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is Figure 1 a plan view of the nonvolatile memory device of

[0011] Figure 3 is a cross-sectional view taken along line A-A' of the nonvolatile memory device of Figure 1

[0012] Figures 4A-4E is a view schematically showing an operation of the nonvolatile memory device according to an embodiment of the present disclosure.

[0013] Figure 5 ​is a perspective view schematically showing a nonvolatile storage device according to another embodiment of the present disclosure.

[0014] Figure 6A is a circuit diagram schematically showing Figure 5 the nonvolatile storage device.

[0015] Figure 6B is a partial plan view of the nonvolatile storage device corresponding to the circuit of Figure 6A .

[0016] Figure 6C is a sectional view taken along line C-C' of Figure 6B .

[0017] Figure 7 is a perspective view schematically showing a nonvolatile storage device according to another embodiment of the present disclosure.

[0018] Figure 8 is a plan view of the nonvolatile storage device of Figure 7 .

[0019] Figure 9 is a sectional view taken along line D-D' of the nonvolatile storage device of Figure 7 .

[0020] Figure 10 is a perspective view schematically showing a nonvolatile storage device according to yet another embodiment of the present disclosure.

[0021] Figure 11 is a plan view of the nonvolatile storage device of Figure 10 .

[0022] Figure 12 is a sectional view taken along line E-E' of the nonvolatile storage device of Figure 10 .

[0023] Figure 13 is a perspective view schematically showing a nonvolatile storage device according to yet another embodiment of the present disclosure.

[0024] Figure 14 is a plan view of the nonvolatile storage device of Figure 13 .

[0025] Figure 15 is a sectional view taken along line F-F' of the nonvolatile storage device of Figure 13 .

[0026] Figure 16 is a perspective view schematically showing a nonvolatile storage device according to yet another embodiment of the present disclosure.

[0027] Figure 17 isFigure 16 a plan view of the nonvolatile storage device of FIG. 1.

[0028] Figure 18 is a cross-sectional view taken along line G-G' of the nonvolatile storage device of FIG. 1. Figure 16

[0029] Figure 19 is a perspective view schematically illustrating the nonvolatile storage device according to a further embodiment of the present disclosure.

[0030] Figure 20 is a plan view of the nonvolatile storage device of FIG. 1. Figure 19

[0031] Figure 21 is a cross-sectional view taken along line H-H' of the nonvolatile storage device of FIG. 1. Figure 19

[0032] Figure 22 is a perspective view schematically illustrating the nonvolatile storage device according to a further embodiment of the present disclosure.

[0033] Figure 23 is a plan view of the nonvolatile storage device of FIG. 1. Figure 22

[0034] Figure 24 is a cross-sectional view taken along line I-I' of the nonvolatile storage device of FIG. 1. Figure 22 DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the size of components such as the width and thickness of components are exaggerated for the sake of clarity in illustration of each device. The terms used herein can correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms can be interpreted differently by those of ordinary skill in the art to which the embodiments pertain. If explicitly defined in detail, the terms can be interpreted according to the definition. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meanings as those generally understood by those of ordinary skill in the art to which the embodiments pertain.

[0036] In addition, unless explicitly defined in the context, the expression of the singular form of the word is understood to include the plural form of the word. It will be understood that the term "include" or "have" is intended to designate the presence of characteristics, numbers, steps, operations, components, elements, parts, or combinations thereof, and is not used to exclude the presence or addition of one or more other characteristics, numbers, steps, operations, components, elements, parts, or combinations thereof.

[0037] ​​​​​In the present specification, the term "predetermined direction" can mean one direction determined in a coordinate system and a direction opposite to the one direction. As an example, in an x-y-z coordinate system, the z direction can refer to a direction in which the absolute value of the z axis increases in the positive direction of the z axis from the origin 0 and a direction in which the absolute value of the z axis increases in the negative direction of the z axis from the origin 0. In the x-y-z coordinate system, the x direction and the y direction can each be explained in substantially the same manner.

[0038] Figure 1 is a perspective view schematically showing a nonvolatile memory device 1 according to an embodiment of the present disclosure. Figure 2 is Figure 1 is a plan view of the nonvolatile memory device of Figure 3 is a cross-sectional view taken along line A-A' of the nonvolatile memory device of Figure 1

[0039] Referring to Figures 1-3 The nonvolatile memory device 1 can include a substrate 101, first and second gate structures 12 and 14, a source electrode structure 22, a drain electrode structure 24, first and second ferroelectric layers 312 and 314, and first and second channel layers 322 and 324. In addition, the nonvolatile memory device 1 can further include a base insulating layer 110 disposed on the substrate 101 and an insulating structure 26 extending in a first direction (i.e., a z direction) perpendicular to the substrate 101. The memory device structure including the first gate structure 12, the first ferroelectric layer 312, and the first channel layer 322 can share the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26 with the memory device structure including the second gate structure 14, the second ferroelectric layer 314, and the second channel layer 324.

[0040] The substrate 101 can include a semiconductor material. Specifically, the semiconductor material can include silicon (Si), germanium (Ge), and gallium arsenide (GaAs), etc. The substrate 101 can be doped with an n-type dopant or a p-type dopant. As an example, the substrate 101 can include a well region doped with an n-type dopant or a p-type dopant.

[0041] The base insulating layer 110 can be disposed on the substrate 101. The base insulating layer 110 can electrically insulate the first and second gate structures 12 and 14, the first and second ferroelectric layers 312 and 314, the first and second channel layers 322 and 324, the source electrode structure 22, and the drain electrode structure 24 from the substrate 101, respectively.

[0042] Although not shown in Figure 1 ​At least one conductive layer and at least one insulating layer can be provided between the substrate 101 and the base insulating layer 110, although not shown. The conductive layer and the insulating layer can form various circuit patterns. That is, as non-limiting examples, the conductive layer and the insulating layer can form a plurality of wirings, or can constitute a passive element such as a capacitor or a resistor, or an active element such as a diode or a transistor.

[0043] Referring to Figure 1 The first gate electrode structure 12 can be provided on the base insulating layer 110. The first gate electrode structure 12 can include first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d and first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, and 132e, which are alternately stacked in a first direction (i.e., a z direction) perpendicular to the substrate 101 on the base insulating layer 110. The first gate insulating layer pattern 132a can be disposed in contact with the base insulating layer 110. The fifth gate insulating layer pattern 132e can be disposed as an uppermost layer of the first gate electrode structure 12.

[0044] The first gate electrode structure 12 can extend in a second direction (i.e., a y direction) perpendicular to the first direction. The first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d can be electrically insulated from each other by the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, and 132e. The first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d can be conductive lines extending in the second direction (i.e., the y direction). The first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d can each maintain a predetermined electric potential.

[0045] In one embodiment, the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d can each include a conductive material. For example, the conductive material can include a doped semiconductor material, a metal, a conductive metal silicide, a conductive metal nitride, or a conductive metal oxide. For example, the conductive material can include n-type doped silicon, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. The first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, and 132e can each include an insulating material. For example, the insulating material can include an oxide, a nitride, and an oxynitride, etc.

[0046] In some other embodiments, the number of the gate electrode layer patterns of the first gate electrode structure 12 can not necessarily be limited to four. The gate electrode layer patterns can be provided in various different numbers, and the gate insulating layer pattern can insulate various numbers of the source electrode layer patterns in the first direction (i.e., the z direction).

[0047] Referring to Figures 1-3 The first ferroelectric layer 312 can be disposed on the base insulating layer 110 and on one sidewall surface S1 of the first gate structure 12. Here, the one sidewall surface S1 can form a plane (i.e., a y-z plane parallel to the z direction and the y direction) substantially parallel to the first direction and the second direction. The first ferroelectric layer 312 can have a predetermined thickness t1 in a third direction (i.e., the x direction) perpendicular to the first direction and the second direction. For example, the thickness t1 can be 1 nanometer (nm) to 50 nanometers (nm) inclusive of both end values.

[0048] The first ferroelectric layer 312 can include a ferroelectric material. In a state in which no external electric field is applied, the ferroelectric material can have an electric remanent polarization. In addition, in the ferroelectric material, when an external electric field is applied, the electric polarization can exhibit a hysteresis behavior. By controlling the external electric field, one of a plurality of stable polarization states on a polarization hysteresis curve can be written into the ferroelectric material. After the external electric field is removed from the ferroelectric material, the written polarization can be stored in the ferroelectric material in the form of a remanent polarization. The remanent polarization can be used for non-volatile storage of a plurality of pieces of signal information. For example, the first ferroelectric layer 312 can include hafnium oxide, zirconium oxide, and hafnium zirconium oxide, etc. The first ferroelectric layer 312 can have a crystal structure of an orthorhombic system.

[0049] The first channel layer 322 can be disposed on the base insulating layer 110 and contact the first ferroelectric layer 312. Specifically, the first channel layer 322 can be disposed on one surface S2 of the first ferroelectric layer 312 defined by the first direction and the second direction (i.e., the z direction and the y direction). The first channel layer 322 can have a predetermined thickness t2 in the third direction (i.e., the x direction). For example, the thickness t2 can be 1 nanometer (nm) to 50 nanometers (nm) inclusive of both end values. Although the thickness of the first ferroelectric layer 312 is shown to be greater than the thickness of the first channel layer 322 in Figure 3 In the embodiment of FIG. 1, the thickness of the first ferroelectric layer 312 is not limited to this, and in other embodiments, the thickness of the first ferroelectric layer 312 can be less than or equal to the thickness of the first channel layer 322.

[0050] The first channel layer 322 can provide a path for electric carriers such as electrons or holes to move between the source electrode structure 22 and the drain electrode structure 24. As described later, when a conductive channel is formed in the first channel layer 322, the electrical resistance of the first channel layer 322 can decrease. However, the electrical resistance of the conductive channel can also vary depending on the magnitude and direction of the remanent polarization stored in the first ferroelectric layer 312.

[0051] The first channel layer 322 can include, for example, a doped semiconductor material or a metal oxide. For example, the semiconductor material can include silicon (Si), germanium (Ge), and gallium arsenide (GaAs), etc. The metal oxide can include indium-gallium-zinc (In-Ga-Zn) oxide. In one embodiment, the first channel layer 322 can include silicon (Si) doped with an n-type dopant. Alternatively, the first channel layer 322 can include c-axis aligned indium-gallium-zinc (In-Ga-Zn) oxide. The first channel layer 322 can have a single-crystal structure or a polycrystal structure.

[0052] Referring again to Figures 1-3 , the source electrode structure 22 and the drain electrode structure 24 can each be disposed on the base insulating layer 110 to be in contact with the surface S3 of the first channel layer 322 while being spaced apart from each other in the second direction (i.e., the y direction). The source electrode structure 22 and the drain electrode structure 24 can each have a columnar shape extending along the first direction (i.e., the z direction). The source electrode structure 22 and the drain electrode structure 24 can each be disposed to be in contact with the first channel layer 322 and the second channel layer 324.

[0053] The insulating structure 26 can be disposed between the source electrode structure 22 and the drain electrode structure 24. The insulating structure 26 can be disposed to be in contact with the first channel layer 322 and the second channel layer 324. The insulating structure 26 can have a columnar shape extending from the base insulating layer 110 in the first direction (i.e., the z direction). The insulating structure 26 can function to inhibit movement of electric carriers between the source electrode structure 22 and the drain electrode structure 24 via a path other than the first channel layer 322 or the second channel layer 324.

[0054] The source electrode structure 22 and the drain electrode structure 24 can each maintain a predetermined electric potential. The electric potential of each of the source electrode structure 22 and the drain electrode structure 24 can be the same as or different from each other. In one embodiment, during operation of the nonvolatile memory device, if a conductive channel is formed in the first channel layer 322 or the second channel layer 324 and a predetermined potential difference occurs between the source electrode structure 22 and the drain electrode structure 24, electric carriers can move via the conductive channel.

[0055] The source electrode structure 22 and the drain electrode structure 24 can each include an electrically conductive material. For example, the electrically conductive material can include a doped semiconductor material, a metal, an electrically conductive metal nitride, an electrically conductive metal oxide, an electrically conductive metal carbide, and an electrically conductive metal silicide, etc. For example, the electrically conductive material can include doped silicon, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. The insulating structure 26 can include an oxide, a nitride, or an oxynitride. As an example, the insulating structure 26 can include silicon oxide, silicon nitride, or silicon oxynitride.

[0056] Referring to Figures 1-3 The second channel layer 324 can be disposed on the base insulating layer 110 and can be in contact with the sidewalls of the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26. The sidewalls of the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26 can be located on the same plane S4. The plane S4 can form a plane substantially parallel to the first direction and the second direction (i.e., a y-z plane parallel to the z direction and the y direction). The second channel layer 324 can have a predetermined thickness t2 along the third direction (i.e., the x direction). The configuration of the second channel layer 324 can be substantially the same as that of the first channel layer 322.

[0057] The second ferroelectric layer 314 can be disposed on the base insulating layer 110 and on one surface S5 of the second channel layer 324. The one surface S5 can be a plane defined by the first direction and the second direction (i.e., a y-z plane parallel to the z direction and the y direction). The second ferroelectric layer 314 can have a predetermined thickness t1 along the third direction (i.e., the x direction). The configuration of the second ferroelectric layer 314 can be substantially the same as that of the first ferroelectric layer 312.

[0058] The second gate structure 14 can be provided on the base insulating layer 110 and in contact with one surface S6 of the second ferroelectric layer 314. The plane S6 can form a plane substantially parallel to the first direction and the second direction (i.e., a y-z plane parallel to the z direction and the y direction). The second gate structure 14 can include the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d and the first to fifth gate insulating layer patterns 134a, 134b, 134c, 134d, and 134e alternately stacked along the first direction (i.e., the z direction). The first gate insulating layer pattern 134a can be provided to contact the base insulating layer 110. The fifth gate insulating layer pattern 134e can be provided as the uppermost layer of the second gate structure 14. The second gate structure 14 can extend in the second direction (i.e., the y direction). The configurations of the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d and the first to fifth gate insulating layer patterns 134a, 134b, 134c, 134d, and 134e of the second gate structure 14 can be substantially the same as the configurations of the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d and the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, and 132e of the first gate structure 12.

[0059] As described above, in the nonvolatile memory device 1 according to the embodiment of the present disclosure, the first gate structure 12 and the second gate structure 14 can be symmetrically provided with respect to each other on both sides of the y-z plane centered on the source electrode structure 22, the insulating structure 26, and the drain electrode structure 24. Similarly, the first ferroelectric layer 312 and the second ferroelectric layer 314 can be symmetrically provided with respect to each other, and the first channel layer 322 and the second channel layer 324 can be symmetrically provided with respect to each other.

[0060] In one embodiment, the first gate structure 12, the first ferroelectric layer 312, the first channel layer 322, the source electrode structure 22, and the drain electrode structure 24 can constitute one operation unit of the nonvolatile memory device 1, and the second gate structure 14, the second ferroelectric layer 314, the second channel layer 324, the source electrode structure 22, and the drain electrode structure 24 can constitute another operation unit of the nonvolatile memory device 1. The source electrode structure 22 and the drain electrode structure 24 can be shared by different operation units. That is, the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12, the first ferroelectric layer 312, and the first channel layer 322 can work together with the source electrode structure 22 and the drain electrode structure 24. Further, the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d of the second gate structure 14, the second ferroelectric layer 314, and the second channel layer 324 can work together with the source electrode structure 22 and the drain electrode structure 24.

[0061] Figures 4A-4E is a view schematically showing an operation of a nonvolatile memory device according to an embodiment of the present disclosure. Figure 4A is a circuit diagram of a nonvolatile memory device according to an embodiment of the present disclosure. Figure 4B is a plan view of a portion of a nonvolatile memory device corresponding to the circuit diagram of Figure 4A Figure 4C and Figure 4D are views schematically showing different remanent polarizations stored in a ferroelectric layer of a nonvolatile memory device according to an embodiment of the present disclosure. Figure 4E is a cross-sectional view taken along line B-B' of Figure 4B

[0062] In particular, Figure 4B is a plan view schematically showing one operation unit 1a of the nonvolatile memory device 1 described above with reference to Figures 1-3 One operation unit 1a may, for example, include the first gate structure 12, the first ferroelectric layer 312, the first channel layer 322, the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26. In order to facilitate a related description of the operation of one operation unit 1a, the uppermost gate insulating layer pattern 132e of the first gate structure 12 is omitted in Figure 4B

[0063] With reference to Figure 4A , first to fourth memory cells MC1, MC2, MC3, and MC4 are disclosed. The first to fourth memory cells MC1, MC2, MC3, and MC4 can each have the form of a transistor, and can respectively include first to fourth ferroelectric layers FD1, FD2, FD3, and FD4 serving as storage layers.

[0064] The source and the drain of each of the first to fourth memory cells MC1, MC2, MC3, and MC4 can be electrically connected to a global source line (GSL) and a global drain line (GDL). The gate electrodes of the first to fourth memory cells MC1, MC2, MC3, and MC4 can be electrically connected to first to fourth word lines GL1, GL2, GL3, and GL4, respectively.

[0065] ​​​With respect to a write operation to at least one of the first to fourth memory cells MC1, MC2, MC3, and MC4, at least one of the first to fourth word lines GL1, GL2, GL3, and GL4 can be selected. A polarization switching voltage having a magnitude greater than or equal to a predetermined threshold voltage can be applied across each of the first to fourth ferroelectric layers FD1, FD2, FD3, and FD4 of the corresponding first to fourth memory cells MC1, MC2, MC3, and MC4 through the at least one selected word line. At this time, the global source line GSL and the global drain line GDL can be grounded. By applying the polarization switching voltage, the polarizations of the first to fourth ferroelectric layers FD1, FD2, FD3, and FD4 can be switched and then aligned in a predetermined direction. After the polarization switching voltage is removed, the switched polarizations can be stored in the corresponding first to fourth ferroelectric layers FD1, FD2, FD3, and FD4 in the form of remnant polarizations. As a result, as described above, by applying the polarization switching voltage through at least one of the first to fourth word lines GL1, GL2, GL3, and GL4, a write operation can be performed on at least one of the first to fourth memory cells MC1, MC2, MC3, and MC4. After the write operation is completed, a predetermined signal can be stored in the corresponding memory cell in a non-volatile manner.

[0066] Meanwhile, an operation of reading a signal non-volatile stored in the first to fourth memory cells MC1, MC2, MC3, and MC4 can be performed. As an exemplary example, a process of reading a signal stored in the fourth memory cell MC4 will be described. First, the fourth word line GL4 corresponding to the fourth memory cell MC4 is selected. Subsequently, a read voltage greater than or equal to a predetermined threshold voltage can be applied to the gate electrode of the fourth memory cell MC4 through the fourth word line GL4. The absolute value of the read voltage can be smaller than the absolute value of the polarization switching voltage. That is, the polarization inside the fourth ferroelectric layer FD4 can not be switched by the read voltage. The transistor of the fourth memory cell MC4 is turned on by the read voltage, and a conductive channel can be formed in the channel layer of the transistor. As a result, when a source-drain potential difference is formed between the global source line GSL and the global drain line GDL, a source-drain current can flow through the conductive channel.

[0067] The source-drain current can vary depending on the orientation and magnitude of the remnant polarization stored in the fourth ferroelectric layer FD4. As an example, when the remnant polarization is oriented from the gate electrode toward the channel layer (corresponding to a case where the fourth memory cell MC4 stores a logic "0"), the source-drain current can be greater than or equal to a predetermined threshold current. When the remnant polarization is oriented from the channel layer toward the gate electrode (corresponding to a case where the fourth memory cell MC4 stores a logic "1"), the source-drain current can be less than the predetermined threshold current. Figure 4Cthe fourth ferroelectric layer FD4 adjacent to the channel layer, thereby increasing the electron density of the conductive channel. As a result, the magnitude of the current flowing along the conductive channel can increase. As another example, when the remanent polarization is oriented from the channel layer toward the gate electrode (corresponding to the second polarization DP2 in Figure 4D the fourth ferroelectric layer FD4 adjacent to the channel layer, thereby decreasing the electron density of the conductive channel. As a result, the magnitude of the current flowing along the conductive channel can decrease. As described above, by turning on the transistor of the memory cell to be read and measuring the current flowing through the channel layer, the signal stored in the memory cell can be read.

[0068] In other embodiments, the number of memory cells disposed between the global source line GSL and the global drain line GDL need not be limited to four and can be other various numbers. Similarly, the number of word lines need not be limited to four and can be other various numbers.

[0069] Reference is made to Figure 4B , the global source line GSL described above with reference to Figure 4A may correspond to the source electrode structure 22, while the global drain line GDL can correspond to the drain electrode structure 24. In addition, the first to fourth word lines GL1, GL2, GL3, and GL4 can correspond to the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12 in Figures 1-3 , the fourth word line GL4 and the fourth ferroelectric layer FD4 of the fourth memory cell MC4 shown in Figure 4A may correspond to the fourth gate electrode layer pattern 122d and the region of the first ferroelectric layer 312 covered by the fourth gate electrode layer pattern 122d shown in Figure 4B , the fourth memory cell MC4 shown in Figure 4B and Figure 4E , Figure 4A the channel layer of the fourth memory cell MC4 shown in can correspond to the eighth region 322-h of the first channel layer 322 covered by the fourth gate electrode layer pattern 122d between the source electrode structure 22 and the drain electrode structure 24. Reference is made to Figures 1-3 and Figure 4E , the first channel layer 322 can include the first to ninth regions 322-a, 322-b, 322-c, 322-d, 322-e, 322-f, 322-g, 322-h, and 322-i, which correspond to the regions between the source electrode structure 22 and the drain electrode structure 24 that overlap the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d and the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, and 132e along the third direction (i.e., the x-direction). As an example, Figure 4AThe channel layers of the first to third memory cells MC1, MC2 and MC3 shown can correspond to Figure 4E The second region 322-b, the fourth region 322-d, and the sixth region 322-f of the first channel layer 322.

[0070] In the following text, as an example, a description will be given for including Figures 4B-4E The write and read operations of the memory cell structure shown are for the fourth gate electrode layer pattern 122d, the first ferroelectric layer 312, and the eighth part 322-h of the first channel layer 322. The memory cell structure corresponds to... Figure 4A The fourth memory cell MC4 of the non-volatile memory device is shown. It can correspond to the first to third memory cells MC1, MC2, and MC3. Figures 4B-4E The storage cell structure applies essentially the same write and read operations.

[0071] Can be used Figures 4B-4D This describes the write operation to the fourth memory cell, MC4. (See reference...) Figure 4B The fourth gate electrode layer pattern 122d is selected from the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12. Subsequently, the source electrode structure 22 and the drain electrode structure 24 are grounded, and a first polarization switching voltage with positive polarity is applied to the fourth gate electrode layer pattern 122d. The first polarization switching voltage can be a voltage with an absolute value equal to or greater than a predetermined threshold voltage, enabling the switching of the polarization orientation of the first ferroelectric layer 312. When the first polarization switching voltage is applied, as... Figure 4C As shown, a first polarization DP1 can be formed in the region of the first ferroelectric layer 312 that is covered by or shares the region with the fourth gate electrode layer pattern 122d. The first polarization DP1 can be oriented from the interface region of the first ferroelectric layer 312 that contacts the fourth gate electrode layer pattern 122d toward the interface region of the first ferroelectric layer 312 that contacts the first channel layer 322. Subsequently, the first polarization switching voltage is removed. Even after the first polarization switching voltage is removed, the first polarization DP1 can be stored in the form of residual polarization. In addition, the formation of the first polarization DP1 allows positive charge CP and negative charge CN to be generated in the internal region of the first ferroelectric layer 312. Even after the first polarization switching voltage is removed, the positive charge CP can be distributed in the interface region of the first ferroelectric layer 312 that contacts the first channel layer 322, while the negative charge CN can be distributed in the interface region of the first ferroelectric layer 312 that contacts the fourth gate electrode layer pattern 122d.

[0072] As another embodiment, in Figure 4BIn this process, the fourth gate electrode layer pattern 122d is selected from the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d. Subsequently, after grounding the source electrode structure 22 and the drain electrode structure 24, a second polarization switching voltage with negative polarity is applied to the fourth gate electrode layer pattern 122d. The second polarization switching voltage can be a voltage whose absolute value is equal to or greater than a predetermined threshold voltage to switch the polarization orientation of the first ferroelectric layer 312. When the second polarization switching voltage is applied, as... Figure 4D As shown, a second polarization DP2 can be formed in the internal region of the first ferroelectric layer 312 covered by the fourth gate electrode layer pattern 122d. The second polarization DP2 can be oriented from the interface region of the first ferroelectric layer 312 contacting the first channel layer 322 toward the interface region of the first ferroelectric layer 312 contacting the fourth gate electrode layer pattern 122d. Subsequently, the second polarization switching voltage is removed. Even after the second polarization switching voltage is removed, the second polarization DP2 can be stored in the form of residual polarization. Furthermore, the formation of the second polarization DP2 allows positive charges CP and negative charges CN to be generated in the internal region of the first ferroelectric layer 312. Even after the second polarization switching voltage is removed, the positive charge CP can be distributed in the interface region of the first ferroelectric layer 312 contacting the fourth gate electrode layer pattern 122d, while the negative charge CN can be distributed in the interface region of the first ferroelectric layer 312 contacting the first channel layer 322. As described above, it is possible to achieve this through the above reference. Figures 4B-4D The polarization orientation switching operation of the first ferroelectric layer 312 is described to perform the write operation. As an example, with Figure 4C The formation operation of the first polarization DP1 can be called a programming operation, and is related to... Figure 4D The formation operation of the second polarization DP2 can be referred to as the erasure operation.

[0073] At the same time, will refer to Figure 4B and Figure 4E The following describes the operation of reading signal information stored in the fourth memory cell MC4. First, a read voltage with an absolute value equal to or greater than a predetermined threshold voltage is applied to the fourth gate electrode layer pattern 122d. The absolute value of the read voltage can be less than the absolute values ​​of the first polarization switching voltage and the second polarization switching voltage. That is, the polarization of the first ferroelectric layer 312 covered by the fourth gate electrode layer pattern 122d may not be switched due to the read voltage.

[0074] Conversely, a conductive channel CH4 can be formed in the eighth region 322-h of the first channel layer 322 adjacent to the first ferroelectric layer 312 by reading the voltage. (Reference) Figure 4EThe conductive channel CH4may electrically connect the source electrode structure 22 to the drain electrode structure 24. The electron density inside the conductive channel CH4may be higher than the electron density of the first channel layer 322 outside the conductive channel CH4.

[0075] After the conductive channel CH4is formed, a source-drain potential difference is formed between the source electrode structure 22 and the drain electrode structure 24. As an example, after the source electrode structure 22 is grounded, a drain voltage having a positive polarity can be applied to the drain electrode structure 24. Thus, electrons can flow from the source electrode structure 22 to the drain electrode structure 24 through the conductive channel CH4. At this time, the current density generated by the flow of the electrons can be affected by the orientation of the remanent polarization stored in the adjacent first ferroelectric layer 312. When the orientation of the remanent polarization is the same as the orientation of the first polarization DP1of Figure 4C , the electron density inside the conductive channel CH4increases, so that the current density flowing along the conductive channel CH4may increase. In contrast, when the orientation of the remanent polarization is the same as the orientation of the second polarization DP2of Figure 4D , the electron density inside the conductive channel CH4decreases, so that the current density flowing along the conductive channel CH4may decrease. As described above, by forming a conductive channel in the channel layer of the memory cell to be read and by measuring the current flowing through the conductive channel, the signal stored in the memory cell can be read.

[0076] According to one embodiment of the present disclosure, a nonvolatile memory device can include a gate structure, a source electrode structure, and a drain electrode structure disposed in a direction perpendicular to a substrate. In addition, the nonvolatile memory device can include a ferroelectric layer and a channel layer disposed adjacent to the gate structure, the source electrode structure, and the drain electrode structure. In the nonvolatile memory device, a plurality of memory cells can be randomly accessed by a pattern of independently selectable gate electrodes. Thereby, the nonvolatile memory device can independently perform a write operation and a read operation on the accessed memory cell.

[0077] Figure 5 is a perspective view schematically showing a nonvolatile memory device 2 according to another embodiment of the present disclosure. Figure 6A is a circuit diagram schematically showing Figure 5 the nonvolatile memory device. Figure 6B is a partial plan view of the nonvolatile memory device corresponding to the circuit diagram of Figure 6A , and Figure 6C is a cross-sectional view taken along line C-C' of Figure 6B . Figure 6A and Figure 6B may be a view schematically showing one operation unit 2a of the nonvolatile memory device 2 of Figure 5 .

[0078] Referring to Figure 5 , as compared to the non-volatile memory device 1 described above with reference to Figures 1-3 , the non-volatile memory device 2 can include a plurality of source electrode structures 22a and 22b, a plurality of drain electrode structures 24a and 24b, and insulating structures 26a, 26b, and 27 disposed on the base insulating layer 110 along the second direction (i.e., the y-direction). As one example, as shown, the first source electrode structure 22a, the first insulating structure 26a, the first drain electrode structure 24a, the inter-element insulating structure 27, the second source electrode structure 22b, the second insulating structure 26b, and the second drain electrode structure 24b can be sequentially disposed along the second direction (i.e., the y-direction). Although the number of source electrode structures, drain electrode structures, and insulating structures are shown as two in Figure 5 , the devices contemplated by the present disclosure need not be limited thereto. In other embodiments, the number of source electrode structures, drain electrode structures, and insulating structures can vary along the second direction (i.e., the y-direction).

[0079] Meanwhile, referring to Figure 5 , the first gate structure 12 and the second gate structure 14, the first ferroelectric layer 312 and the second ferroelectric layer 314, and the first channel layer 322 and the second channel layer 324 can extend along the second direction (i.e., the y-direction) on the base insulating layer 110 and cover the plurality of source electrode structures 22a and 22b, the plurality of drain electrode structures 24a and 24b, and the insulating structures 26a, 26b, and 27. Figure 6B and Figure 6C , the first operating unit 2a can correspond to a portion of the non-volatile memory device 2 of Figure 5 . As an example, the first operating unit 2a can include the first gate structure 12, the first ferroelectric layer 312, the first channel layer 322, the first source electrode structure 22a and the second source electrode structure 22b, the first drain electrode structure 24a and the second drain electrode structure 24b, and the insulating structures 26a, 26b, and 27. Referring to Figure 5 , the second operating unit 2b can correspond to another portion of the non-volatile memory device 2. As an example, the second operating unit 2b can include the second gate structure 14, the second ferroelectric layer 314, the second channel layer 324, the first source electrode structure 22a and the second source electrode structure 22b, the first drain electrode structure 24a and the second drain electrode structure 24b, and the insulating structures 26a, 26b, and 27. Hereinafter, the method of operation of the non-volatile memory device 2 will be described using the first operating unit 2a as an example, but the method can be substantially equally applied to the second operating unit 2b as well as operating units in other embodiments.

[0080] Referring to Figure 5 , Figures 6A-6C , Figure 6AThe first global source line GSL1 and the first global drain line GDL1 can correspond to the first source electrode structure 22a and the first drain electrode structure 24a of the first operation unit 2a shown in Figure 5 , Figure 6B and Figure 6C . Figure 6A The second global source line GSL2 and the second global drain line GDL2 can correspond to the second source electrode structure 22b and the second drain electrode structure 24b of the first operation unit 2a shown in Figure 5 , Figure 6B and Figure 6C . Figure 6A The first global gate line GGL1 can correspond to the first gate electrode layer pattern 122a of the first operation unit 2a shown in Figure 5 , Figure 6B and Figure 6C . Likewise, Figure 6A The second to fourth global gate lines GGL2, GGL3 and GGL4 can correspond to the second to fourth gate electrode layer patterns 122b, 122c and 122d of the first operation unit 2a shown in Figure 5 , Figure 6B and Figure 6C .

[0081] With reference to Figure 6A , the first to fourth memory cells MC1, MC2, MC3 and MC4 can each be connected to the first global source line GSL1 and the first global drain line GDL1. Likewise, the fifth to eighth memory cells MC5, MC6, MC7 and MC8 can each be connected to the second global source line GSL2 and the second global drain line GDL2. The first memory cell MC1 and the fifth memory cell MC5 can each be connected to the first global gate line GGL1 and can each have a first ferroelectric layer FD1 and a fifth ferroelectric layer FD5, respectively. Likewise, the second memory cell MC2 and the sixth memory cell MC6 can each be connected to the second global gate line GGL2 and can each have a second ferroelectric layer FD2 and a sixth ferroelectric layer FD6, respectively. The third memory cell MC3 and the seventh memory cell MC7 can each be connected to the third global gate line GGL3 and can each have a third ferroelectric layer FD3 and a seventh ferroelectric layer FD7, respectively. The fourth memory cell MC4 and the eighth memory cell MC8 can each be connected to the fourth global gate line GGL4 and can each have a fourth ferroelectric layer FD4 and an eighth ferroelectric layer FD8, respectively.

[0082] In the following, as an example of an embodiment, a description will be made for a memory cell array 1 including Figure 5 , Figure 6B and Figure 6CWrite and read operations of the memory cell structure of the fourth gate electrode layer pattern 122d, the first ferroelectric layer 312, and the eighth portion 322a-8 of the first channel portion 322a of the first operation unit 2a shown. These structures correspond to Figure 6A The components of the fourth memory cell MC4 of the nonvolatile memory device shown in FIG. 6B. Similarly, substantially the same write and read operations can be performed with structures corresponding to the first to third memory cells and the fifth to eighth memory cells MC1, MC2, MC3, MC5, MC6, MC7, and MC8.

[0083] Reference is made to Figure 6C In the second direction (i.e., the y direction), the first channel layer 322 can include: a first channel portion 322a disposed between the first source electrode structure 22a and the first drain electrode structure 24a; a second channel portion 322b disposed between the second source electrode structure 22b and the second drain electrode structure 24b; and a third channel portion 322c disposed between the first drain electrode structure 24a and the second source electrode structure 22b. The first to third channel portions 322a, 322b, and 322c can include: second portions 322a-2, 322b-2, and 322c-2 that overlap the first gate electrode layer pattern 122a; fourth portions 322a-4, 322b-4, and 322c-4 that overlap the second gate electrode layer pattern 122b; sixth portions 322a-6, 322b-6, and 322c-6 that overlap the third gate electrode layer pattern 122c; and eighth portions 322a-8, 322b-8, and 322c-8 that overlap the fourth gate electrode layer pattern 122d. Similarly, the first to third channel portions 322a, 322b, and 322c can include: first portions 322a-1, 322b-1, and 322c-1 that overlap the first gate insulating layer pattern 132a; third portions 322a-3, 322b-3, and 322c-3 that overlap the second gate insulating layer pattern 132b; fifth portions 322a-5, 322b-5, and 322c-5 that overlap the third gate insulating layer pattern 132c; and seventh portions 322a-7, 322b-7, and 322c-7 that overlap the fourth gate insulating layer pattern 132d; and ninth portions 322a-9, 322b-9, and 322c-9 that overlap the fifth gate insulating layer pattern 132e.

[0084] Meanwhile, with respect to the write and read operations of the memory cell structure of the fourth gate electrode layer pattern 122d, the first ferroelectric layer 312, and the eighth portion 322a-8 of the first channel portion 322a shown in FIG. 6B, the same operations can be performed with respect to the first to third memory cells and the fifth to eighth memory cells MC1, MC2, MC3, MC5, MC6, MC7, and MC8. Figure 6AThe write operation related to the fourth memory cell MC4 is selected from the first to fourth global word lines GGL1, GGL2, GGL3, and GGL4. A polarization switching voltage Vs having an absolute value equal to or greater than a predetermined threshold voltage can be applied to the fourth global word line GGL4, and the polarization switching voltage Vs can be applied to the gate electrodes of the fourth memory cell MC4 and the eighth memory cell MC8. The polarization switching voltage Vs is a voltage capable of switching the polarization of the fourth ferroelectric layer FD4 of the fourth memory cell MC4 and the eighth ferroelectric layer FD8 of the eighth memory cell MC8. However, in order to perform the write operation only on the fourth memory cell MC4, the first global source line GSL1 and the first global drain line GDL1 can be grounded, and a predetermined voltage Vp having an absolute value smaller than that of the polarization switching voltage Vs can be applied to the second global source line GSL2 and the second global drain line GDL2, respectively. In this way, the polarization switching voltage Vs is applied only to the fourth ferroelectric layer FD4 of the fourth memory cell MC4, and a voltage corresponding to the difference between the polarization switching voltage Vs and the predetermined voltage Vp can be applied to the eighth ferroelectric layer FD8 of the eighth memory cell MC8. Accordingly, when the polarization switching voltage Vs is applied to the global gate line GGL4, the polarization of the fourth ferroelectric layer FD4 of the fourth memory cell MC4 is switched, and the polarization of the eighth ferroelectric layer FD8 of the eighth memory cell MC8 is not switched.

[0085] The write operation for storing the switched polarization in the form of a residual polarization in the fourth ferroelectric layer FD4 is substantially the same as the above with reference to Figures 4A-4D The write operation of the first ferroelectric layer 312 described above is substantially the same, and will not be repeated here, but by this similar method, the write operation can be performed on the fourth memory cell MC4.

[0086] The write operation described above for the fourth memory cell MC4 can also use Figure 5 and Figure 6Bcorresponding structures 2 and 2a shown in FIG. 2. First, a polarization switching voltage Vs is applied to the fourth gate electrode layer pattern 122d corresponding to the fourth global word line GGL4. At this time, the first source electrode structure 22a and the first drain electrode structure 24a corresponding to the first global source line GSL1 and the first global drain line GDL1, respectively, can be grounded. On the other hand, a predetermined voltage Vp having an amplitude smaller than the polarization switching voltage Vs can be applied to the second source electrode structure 22b and the second drain electrode structure 24b corresponding to the second global source line GSL2 and the second global drain line GDL2, respectively. By doing so, the polarization in a first region of the first ferroelectric layer 312 located between the first source electrode structure 22a and the first drain electrode structure 24a along the second direction and in contact with the fourth gate electrode layer pattern 122d can be switched. Meanwhile, a voltage substantially smaller than the polarization switching voltage Vs is applied to a second region of the first ferroelectric layer 312 located between the second source electrode structure 22b and the second drain electrode structure 24b along the second direction and in contact with the fourth gate electrode layer pattern 122d. Accordingly, the polarization in the second region of the first ferroelectric layer 312 is not switched.

[0087] After the polarization switching voltage Vs is removed, the switched polarization can be stored in the form of a residual polarization. The first region of the first ferroelectric layer 312 having the switched polarization can be a region overlapping with the eighth portion 322a-8 of the first channel portion 322a of Figure 6C the first ferroelectric layer 312. The second region of the first ferroelectric layer 312 not having the switched polarization can be a region overlapping with the eighth portion 322b-8 of the second channel portion 322b of Figure 6C the first ferroelectric layer 312.

[0088] Meanwhile, a read operation for the residual polarization stored in the fourth memory cell MC4 will be explained. First, in the state shown in FIG. 2, the polarization switching voltage Vs is applied to the fourth gate electrode layer pattern 122d corresponding to the fourth global word line GGL4. At this time, the first source electrode structure 22a and the first drain electrode structure 24a corresponding to the first global source line GSL1 and the first global drain line GDL1, respectively, can be grounded. On the other hand, a predetermined voltage Vp having an amplitude smaller than the polarization switching voltage Vs can be applied to the second source electrode structure 22b and the second drain electrode structure 24b corresponding to the second global source line GSL2 and the second global drain line GDL2, respectively. By doing so, the polarization in a first region of the first ferroelectric layer 312 located between the first source electrode structure 22a and the first drain electrode structure 24a along the second direction and in contact with the fourth gate electrode layer pattern 122d can be switched. Meanwhile, a voltage substantially smaller than the polarization switching voltage Vs is applied to a second region of the first ferroelectric layer 312 located between the second source electrode structure 22b and the second drain electrode structure 24b along the second direction and in contact with the fourth gate electrode layer pattern 122d. Accordingly, the polarization in the second region of the first ferroelectric layer 312 is not switched. Figure 6AIn the above, the fourth global word line GGL4 is selected. Subsequently, a read voltage Vr equal to or greater than the predetermined threshold voltage can be applied to the gate electrodes of the fourth storage unit MC4 and the eighth storage unit MC8 through the fourth global word line GGL4. The absolute value of the read voltage Vr can be smaller than the absolute value of the polarization switching voltage Vs. That is, the polarization inside the fourth ferroelectric layer FD4 and the eighth ferroelectric layer FD8 can not be switched by the read voltage Vr. The transistors of the fourth storage unit MC4 and the eighth storage unit MC8 are turned on by the read voltage Vr, and a conductive channel can be formed in the channel layer of the transistor. When a source-drain potential difference is formed between the first global source line GSL1 and the first global drain line GDL1, a source-drain current can flow only through the conductive channel of the fourth storage unit MC4. Because the magnitude of the source-drain current changes according to the orientation of the remanent polarization stored in the fourth ferroelectric layer FD4 of the fourth storage unit MC4, it is possible to read the signal information of the remanent polarization stored in the fourth storage unit MC4 by measuring the magnitude of the source-drain current. On the other hand, when no potential difference is formed between the second global source line GSL2 and the second global drain line GDL2, an operation current can not flow through the conductive channel of the eighth storage unit MC8.

[0089] The above-described read operation for the fourth storage unit MC4 can also be explained in the same manner with reference to Figure 5 、 Figure 6B and Figure 6C . First, a read voltage Vr is applied to the fourth gate electrode layer pattern 122d corresponding to the fourth global word line GGL4. A conductive channel CH100 can be formed in the channel layer 322 overlapping the fourth gate electrode layer pattern 122d by the read voltage Vr. Subsequently, a source-drain voltage is applied between the first source electrode structure 22a and the first drain electrode structure 24a corresponding to the first global source line GSL1 and the first global drain line GDL1, respectively, to form a potential difference. No potential difference is formed between the second global source line GSL2 and the second global drain line GDL2. As a result, a source-drain current can flow only through the conductive channel CH100 between the first source electrode structure 22a and the first drain electrode structure 24a. The read operation for the fourth storage unit MC4 can be performed by measuring the source-drain current.

[0090] By the above-described method, a write operation and a read operation can be performed by randomly accessing Figure 5 、 Figure 6B and Figure 6C the storage units of the first operation unit 2a of the nonvolatile memory device 2. The write operation and the read operation can be performed for Figure 5 、 Figure 6B and Figure 6CThe write operation and the read operation of the first operation unit 2a of the nonvolatile storage device 2 can be identically applied to the second operation unit 2b of the nonvolatile storage device 2.

[0091] Figure 7 is a perspective view schematically showing a nonvolatile storage device 3 according to another embodiment of the present disclosure. Figure 8 is Figure 7 is a plan view of the nonvolatile storage device. Figure 9 is a cross-sectional view taken along the line D-D' of the nonvolatile storage device. Figure 7

[0092] Referring to Figures 7-9 , compared with the nonvolatile storage device 1, Figures 1-3 The nonvolatile storage device 3 can further include a first interface insulating layer 332 and a second interface insulating layer 334.

[0093] The first interface insulating layer 332 can be disposed between the first ferroelectric layer 312 and the first channel layer 322. One surface of the first interface insulating layer 322 can contact the first ferroelectric layer 312, and the other surface of the first interface insulating layer 332 can contact the first channel layer 322. In one embodiment, the first interface insulating layer 332 can be disposed on a plane formed substantially parallel to the first direction and the second direction (i.e., a y-z plane parallel to the z direction and the y direction). The first interface insulating layer 332 can have a predetermined thickness t3 along the third direction (i.e., the x direction). In one embodiment, the thickness t3 of the first interface insulating layer 332 can be less than the thickness t1 of the first ferroelectric layer 312.

[0094] The first interface insulating layer 332 can prevent the first ferroelectric layer from directly contacting the first channel layer 322. That is, the first interface insulating layer 332 can prevent a defect site such as an oxygen vacancy from being generated at an interface between the first ferroelectric layer 312 and the first channel layer 322. The first interface insulating layer 332 can have an amorphous structure. The first interface insulating layer 332 can have a lower dielectric constant than the first ferroelectric layer 312. The first interface insulating layer 332 can be non-ferroelectric. For example, the first interface insulating layer 332 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.

[0095] The second interface insulating layer 334 can be disposed between the second ferroelectric layer 314 and the second channel layer 324. One surface of the second interface insulating layer 334 can contact the second ferroelectric layer 314, and the other surface of the second interface insulating layer 334 can contact the second channel layer 324. The second interface insulating layer 334 can prevent the second ferroelectric layer 314 from directly contacting the second channel layer 324.

[0096] ​The second interface insulating layer 334 can have substantially the same configuration as the first interface insulating layer 332. The second interface insulating layer 334 can have a predetermined thickness t3 in the third direction (i.e., the x direction).

[0097] Figure 10 is a perspective view schematically showing a nonvolatile memory device 4 according to still another embodiment of the present disclosure. Figure 11 is Figure 10 a plan view of the nonvolatile memory device. Figure 12 is a cross-sectional view taken along the line E-E' of the nonvolatile memory device. Figure 10

[0098] Referring to Figures 10-12 , compared to the nonvolatile memory device 3 of Figures 7-9 The nonvolatile memory device 4 can further include a first floating electrode layer 342 and a second floating electrode layer 344. The first floating electrode layer 342 and the second floating electrode layer 344 can be formed of an electrically conductive material.

[0099] The first floating electrode layer 342 can be disposed between the ferroelectric layer 312 and the first interface insulating layer 332. One surface of the first floating electrode layer 342 can contact the first ferroelectric layer 312, and the other surface of the first floating electrode layer 342 can contact the first interface insulating layer 332. In one embodiment, the first floating electrode layer 342 can be disposed on a plane defined by the first direction and the second direction (i.e., the z direction and the y direction). The first floating electrode layer 342 can have a predetermined thickness t4 in the third direction (i.e., the x direction).

[0100] The first floating electrode layer 342 can remain in an electrically floating state. As an example, the first floating electrode layer 342 is not electrically connected to the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12 and the first channel layer 322. The first floating electrode layer 342 can be charged with a positive charge or a negative charge therein depending on the polarity of the voltage applied to the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d. The charged positive charge or negative charge can function to stabilize the remanent polarization stored in the first ferroelectric layer 312. Thus, the presence of the floating electrode layer improves the durability and stability of the remanent polarization of the nonvolatile memory device 4.

[0101] ​In addition, in one embodiment, the structure of the nonvolatile storage device includes a first ferroelectric layer 312 having a relatively high dielectric constant, which is electrically connected in series with a first interface insulating layer 332 having a relatively low dielectric constant. When a polarization switching voltage or a read voltage is applied to this series connection structure, if the first floating electrode layer 342 is not present, a relatively high voltage can be applied to the first interface insulating layer 332 having a relatively low dielectric constant. Due to the thinness of the first ferroelectric layer 312 and the first interface insulating layer 332, the first interface insulating layer 332 can actually be electrically destroyed. In contrast, when the first floating electrode layer 342 is interposed between the first ferroelectric layer 312 and the first interface insulating layer 332, the first floating electrode layer 342 can suppress the relatively high voltage from being applied to the first interface insulating layer 332, thereby improving the durability and reliability of the nonvolatile storage device 4.

[0102] Likewise, a second floating electrode layer 344 can be provided between the second ferroelectric layer 314 and the second interface insulating layer 334. As an example, the second floating electrode layer 344 is not electrically connected to the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d of the second gate structure 14 and the second channel layer 324. One surface of the second floating electrode layer 344 can contact the second ferroelectric layer 314, and the other surface of the second floating electrode layer 344 can contact the second interface insulating layer 334. In one embodiment, the second floating electrode layer 344 can be disposed on a plane formed substantially parallel to the first direction and the second direction (i.e., a y-z plane parallel to the z direction and the y direction). The second floating electrode layer 344 can have a predetermined thickness t4 along the third direction (i.e., the x direction). The configuration and function of the second floating electrode layer 344 can be substantially the same as those of the first floating electrode layer 342. That is, the second floating electrode layer 344 is capable of improving the retention of the remanent polarization stored in the second floating electrode layer 344 and the durability of the second interface insulating layer 334.

[0103] Figure 13 is a perspective view schematically showing a nonvolatile storage device 5 according to yet another embodiment of the present disclosure. Figure 14 is Figure 13 a plan view of the nonvolatile storage device of Figure 15 is a cross-sectional view taken along the line F-F' of the nonvolatile storage device of Figure 13

[0104] Referring to Figures 13-15 , in comparison with the nonvolatile storage device 3 of Figures 7-9 , the nonvolatile storage device 5 can further include a third interface insulating layer 352 and a fourth interface insulating layer 354.

[0105] ​A third interface insulating layer 352 can be disposed between the first gate structure 12 and the first ferroelectric layer 312. As an example, one surface of the third interface insulating layer 352 can contact the first gate structure 12, and another surface of the third interface insulating layer 352 can contact the first ferroelectric layer 312. In one embodiment, the third interface insulating layer 352 can be disposed on a plane formed substantially parallel to the first direction and the second direction (i.e., a y-z plane parallel to the z direction and the y direction). The third interface insulating layer 352 can have a predetermined thickness t5 along the third direction (i.e., the x direction). In one embodiment, the thickness t5 of the third interface insulating layer 352 can be smaller than the thickness t1 of the first ferroelectric layer 312.

[0106] The third interface insulating layer 352 can prevent the first ferroelectric layer 312 from directly contacting the first gate structure 12. The third interface insulating layer 352 can prevent the generation of defect points at the interface between the first ferroelectric layer 312 and the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12. The third interface insulating layer 352 can have an amorphous structure. The third interface insulating layer 352 can have a lower dielectric constant than the first ferroelectric layer 312. The third interface insulating layer 352 can be non-ferroelectric. As an example, the third interface insulating layer 352 can have paraelectric characteristics. For example, the third interface insulating layer 352 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like.

[0107] The third interface insulating layer 352 can be formed of substantially the same material as the first interface insulating layer 332. The thickness t5 of the third interface insulating layer 352 can be substantially the same as the thickness t3 of the first interface insulating layer 332.

[0108] Likewise, a fourth interface insulating layer 354 can be disposed between the second gate structure 14 and the second ferroelectric layer 314. As an example, one surface of the fourth interface insulating layer 354 can contact the second gate structure 14, and another surface of the fourth interface insulating layer 354 can contact the second ferroelectric layer 314. In one embodiment, the fourth interface insulating layer 354 can be disposed on a plane formed substantially parallel to the first direction and the second direction (i.e., a y-z plane parallel to the z direction and the y direction). The fourth interface insulating layer 354 can have a thickness t5 along the third direction (i.e., the x direction). In one embodiment, the thickness t5 of the fourth interface insulating layer 354 can be smaller than the thickness t1 of the second ferroelectric layer 314.

[0109] The fourth interface insulating layer 354 can prevent the second ferroelectric layer 314 from directly contacting the second gate structure 14. The fourth interface insulating layer 354 can prevent defect points from being generated at interfaces between the second ferroelectric layer 314 and the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d of the second gate structure 14. The fourth interface insulating layer 354 can have an amorphous structure. The fourth interface insulating layer 354 can have a lower dielectric constant than the second ferroelectric layer 314. The fourth interface insulating layer 354 can be non-ferroelectric. As an example, the fourth interface insulating layer 354 can have paraelectric characteristics. For example, the fourth interface insulating layer 354 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like.

[0110] The fourth interface insulating layer 354 can be formed of substantially the same material as the second interface insulating layer 334. The thickness t5 of the fourth interface insulating layer 354 can be substantially the same as the thickness t3 of the second interface insulating layer 334.

[0111] Figure 16 is a perspective view schematically showing a nonvolatile memory device 6 according to still another embodiment of the present disclosure. Figure 17 is Figure 16 a plan view of the nonvolatile memory device of Figure 18 is a cross-sectional view taken along the line G-G' of the nonvolatile memory device of Figure 16

[0112] Referring to Figures 16-18 , compared with the nonvolatile memory device 3 of Figures 7-9 The nonvolatile memory device 6 can differ in configuration of the first gate structure 1012 and the second gate structure 1014 from the nonvolatile memory device 3 of

[0113] In this embodiment, the first gate structure 1012 can include the first to fourth gate electrode layer patterns 1122a, 1122b, 1122c, and 1122d and the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e alternately stacked in the first direction (i.e., the z direction). The second gate structure 1014 can include the first to fourth gate electrode layer patterns 1124a, 1124b, 1124c, and 1124d and the first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e alternately stacked in the first direction (i.e., the z direction).

[0114] Referring to Figure 16 and Figures 7-9 ​The first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e of the first gate structure 1012 can separate the first ferroelectric layer 1312, the first interface insulating layer 1332, and the first channel layer 1322 relative to a second direction and a third direction (i.e., the y-direction and the x-direction). Therefore, the first ferroelectric layer 1312, the first interface insulating layer 1332, and the first channel layer 1322 can be discontinuously disposed in the first direction. (Referring to the above reference...) Figures 16-18 Compared to the described embodiments, the first ferroelectric layer 1312 in this embodiment can be configured to contact a portion of a sidewall surface of the first gate structure 1012 in the lateral direction (i.e., the x-direction), specifically, only the sidewall surfaces of the first to fourth gate electrode layer patterns 1122a, 1122b, 1122c, and 1122d. In other words, the first ferroelectric layer 1312 does not contact the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e in the lateral direction (i.e., the x-direction). Furthermore, the first interface insulating layer 1332 and the first channel layer 1322 can be sequentially arranged in the lateral direction starting from the first ferroelectric layer 1312, and can be arranged between the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e.

[0115] refer to Figures 7-9 , and the above reference Figure 16 Compared to the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 132d, and 1132e in the described embodiments, the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e can be configured to directly contact the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26. In this embodiment, the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e can more effectively achieve electrical insulation between the first to fourth gate electrode layer patterns 1122a, 1122b, 1122c, and 1122d in the first direction (i.e., the z-direction).

[0116] Similarly, refer to Figure 18 and Figures 7-9 The first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e of the second gate structure 1014 can separate the second ferroelectric layer 1314, the second interface insulating layer 1334, and the second channel layer 1324 from each other with respect to the second direction and the third direction (i.e., the y-direction and the x-direction). Therefore, the second ferroelectric layer 1314, the second interface insulating layer 1334, and the second channel layer 1324 can be discontinuously disposed in the first direction (i.e., the z-direction). Therefore, in conjunction with the above reference...Figure 16 Compared to the described embodiments, the second ferroelectric layer 1314 in this embodiment can be configured to contact a portion of a sidewall surface of the second gate structure 1014 in the lateral direction (i.e., the x-direction), specifically, only the sidewall surfaces of the first to fourth gate electrode layer patterns 1124a, 1124b, 1124c, and 1124d. In other words, the second ferroelectric layer 1314 does not contact the first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e in the lateral direction (i.e., the x-direction).

[0117] refer to Figure 18 and Figures 7-9 , and the above reference Figure 19 Compared to the first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 134d, and 1134e in the described embodiment, the first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e can be configured to directly contact the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26. In this embodiment, the first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e can more effectively achieve electrical insulation between the first to fourth gate electrode layer patterns 1124a, 1124b, 1124c, and 1124d in the first direction (i.e., the z-direction).

[0118] Simultaneously, the first to fourth gate electrode layer patterns 1122a, 1122b, 1122c, 1122d, 1124a, 1124b, 1124c, and 1124d of the first gate structure 1012 and the second gate structure 1014, the first ferroelectric layer 1312 and the second ferroelectric layer 1314, the first interface insulating layer 1332 and the second interface insulating layer 1334, the first channel layer 1322 and the second channel layer 1324, and the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, 1132e, 1134a, 1134b, 1134c, 1134d, and 1124d are also present. The material properties and functions of 134e are substantially the same as those of the first to fourth gate electrode layer patterns 122a, 122b, 122c, 122d, 124a, 124b, 124c and 124d of the first gate structure 12 and the second gate structure 14, the first ferroelectric layer 312 and the second ferroelectric layer 314, the first interface insulating layer 332 and the second interface insulating layer 334, the first channel layer 322 and the second channel layer 324, and the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, 132e, 134a, 134b, 134c, 134d and 134e.

[0119] Figure 20This is a perspective view schematically illustrating a non-volatile storage device 7 according to a further embodiment of the present disclosure. Figure 19 yes Figure 21 A plan view of a non-volatile storage device. Figure 19 It is along Figures 19-21 A cross-sectional view of line HH′ of a non-volatile storage device.

[0120] refer to Figures 10-12 ,and Figure 21 Compared to the non-volatile memory device 4, the non-volatile memory device 7 may differ in the configuration of the first ferroelectric layer portion 2312 and the second ferroelectric layer portion 2314, the first floating electrode layer portion 2342 and the second floating electrode layer portion 2344, and the first gate structure 2012 and the second gate structure 2014.

[0121] The first gate structure 2012 may include first to fourth gate functional layer patterns 2112a, 2112b, 2112c, and 2112d and first to fifth gate insulating layer patterns 2132a, 2132b, 2132c, 2132d, and 2132e alternately stacked on the substrate insulating layer 110 along a first direction (i.e., the z-direction). The first gate structure 2012 may extend in a second direction (i.e., the y-direction).

[0122] The first interface insulating layer 332 may be disposed on a sidewall surface S7 of the first gate structure 2012. That is, the first interface insulating layer 332 may be configured to cover a sidewall surface S7 of the first gate structure 2012. A sidewall surface S7 is a plane formed substantially parallel to the first and second directions (i.e., a yz plane parallel to the z and y directions). In a particular embodiment, the first interface insulating layer 332 may be configured to contact the first to fifth gate insulating layer patterns 2132a, 2132b, 2132c, 2132d, and 2132e, and the first floating electrode layer portion 2342.

[0123] Additionally, the first channel layer 322 can be configured to contact the first interface insulating layer 332. The first channel layer 322 can be disposed on a plane substantially parallel to the first direction and the second direction (i.e., a yz plane parallel to the z and y directions).

[0124] refer to Figures 19-21, the first to fourth gate functional layer patterns 2112a, 2112b, 2112c, and 2112d of the first gate structure 2012 can each have a first floating electrode layer portion 2342, a first ferroelectric layer portion 2312, and a first gate electrode layer portion 2122. As an example, in the first gate functional layer pattern 2112a, the first floating electrode layer portion 2342 can be disposed on the first interface insulating layer 332, the first gate insulating layer pattern 2132a, and the second gate insulating layer pattern 2132b. The first floating electrode layer portion 2342 can each have a predetermined thickness t6 from the first interface insulating layer 332 in the x-direction, and from the first gate insulating layer pattern 2132a and the second gate insulating layer pattern 2132b in the z-direction. The first ferroelectric layer portion 2312 can be disposed on the first floating electrode layer portion 2342, the first gate insulating layer pattern 2132a, and the second gate insulating layer pattern 2132b. The first ferroelectric layer portion 2312 can have a predetermined thickness t7 from the first floating electrode layer portion 2342. The first gate electrode layer portion 2122 can be disposed to contact or cover the first ferroelectric layer portion 2312 between the first gate insulating layer pattern 2132a and the second gate insulating layer pattern 2132b.

[0125] As for the second gate functional layer pattern 2112b, the first floating electrode layer portion 2342, the first ferroelectric layer portion 2312, and the first gate electrode layer portion 2122 can be disposed between the second gate insulating layer pattern 2132b and the third gate insulating layer pattern 2312c and contact the first interface insulating layer 332 in substantially the same manner. As another example, for the third gate functional layer pattern 2112c, the first floating electrode layer portion 2342, the first ferroelectric layer portion 2312, and the first gate electrode layer portion 2122 can be disposed between the third gate insulating layer pattern 2132c and the fourth gate insulating layer pattern 2132d and contact the first interface insulating layer 332 in substantially the same manner. As for the fourth gate functional layer pattern 2112d, the first floating electrode layer portion 2342, the first ferroelectric layer portion 2312, and the first gate electrode layer portion 2122 can be disposed between the fourth gate insulating layer pattern 2132d and the fifth gate insulating layer pattern 2132e and contact the first interface insulating layer 332 in substantially the same manner.

[0126] Referring to Figures 10-12 , the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26 can be disposed on the base insulating layer 110 to contact the first channel layer 322. Further, the second channel layer 324 can be disposed on the base insulating layer 110 to contact one sidewall surface of each of the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26. In addition, the second interface insulating layer 334 can be disposed to contact the second channel layer 324.

[0127] On the base insulating layer 110, a second gate structure 2014 can be provided in contact with the second interface insulating layer 334. The second gate structure 2014 can include first to fourth gate functional layer patterns 2114a, 2114b, 2114c, and 2114d and first to fifth gate insulating layer patterns 2134a, 2134b, 2134c, 2134d, and 2134e which are alternately stacked on the base insulating layer 110 along a first direction (i.e., the z direction). The second gate structure 2014 can extend in a second direction (i.e., the y direction).

[0128] The first to fourth gate functional layer patterns 2114a, 2114b, 2114c, and 2114d of the second gate structure 2014 can each have a second floating electrode layer portion 2344, a second ferroelectric layer portion 2314, and a second gate electrode layer portion 2124. The configurations of the second floating electrode layer portion 2344, the second ferroelectric layer portion 2314, and the second gate electrode layer portion 2124 of the second gate structure 2014 can be substantially the same as those of the first floating electrode layer portion 2342, the first ferroelectric layer portion 2312, and the first gate electrode layer portion 2122 of the first gate structure 2012.

[0129] When the nonvolatile memory device 7 according to the above-described embodiment is compared with the nonvolatile memory device 4 of Figures 10-12 In the first to fourth gate functional layer patterns 2112a, 2112b, 2112c, and 2112d of the first gate structure 2012 and the first to fourth gate functional layer patterns 2114a, 2114b, 2114c, and 2114d of the second gate structure 2014, the areas of the first ferroelectric layer portion 2312 and the second ferroelectric layer portion 2314 in contact with the first gate electrode layer portion 2122 and the second gate electrode layer portion 2124, respectively, can be increased. In addition, the areas of the first floating electrode layer portion 2342 and the second floating electrode layer portion 2344 in contact with the first ferroelectric layer portion 2312 and the second ferroelectric layer portion 2314 can be increased. As a result, by increasing the areas of the first ferroelectric layer portion 2312 and the second ferroelectric layer portion 2314 serving as storage layers, the density of the remanent polarization stored in the ferroelectric layer portions 2313 and 2314 can be increased. As a result, the reliability of the storage operation can be improved.

[0130] Meanwhile, the material properties and functions of the first and second gate electrode layer portions 2122 and 2124 of the first and second gate structures 2012 and 2014, the first and second ferroelectric layer portions 2312 and 2314, the first and second floating electrode layer portions 2342 and 2344, and the first to fifth gate insulating layer patterns 2132a, 2132b, 2132c, 2132d, 2132e, 2134a, 2134b, 2134c, 2134d, and 2134e are respectively the same as those of the first to fourth gate electrode layer patterns 122a, 122b, 122c, 122d, 124a, 124b, 124c, and 124d, the first and second ferroelectric layer 312 and 314, the first and second floating electrode layer 342 and 344, and the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, 132e, 134a, 134b, 134c, 134d, and 134e of the non-volatile memory device 1 described above with reference to FIGS. 1A to 1C. Figure 22 The material properties and functions of the first to fourth gate electrode layer patterns 122a, 122b, 122c, 122d, 124a, 124b, 124c, and 124d, the first and second ferroelectric layer 312 and 314, the first and second floating electrode layer 342 and 344, and the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, 132e, 134a, 134b, 134c, 134d, and 134e of the first and second gate structures 12 and 14 of the described embodiments are substantially the same.

[0131] Figure 23 is a perspective view schematically showing a non-volatile memory device 8 according to a further embodiment of the present disclosure. Figure 22 is a plan view of the non-volatile memory device of Figure 24 Figure 22 is a cross-sectional view taken along line I-I' of the non-volatile memory device of Figures 22-24

[0132] Referring to Figures 1-3 , compared to the non-volatile memory device 1 of Figures 1-3 , the non-volatile memory device 8 differs in the configuration of the channel structure 28.

[0133] In this embodiment, the channel structure 28 replaces the insulating structure 26 in the non-volatile memory device 1 of Figures 1-3 . That is, the channel structure 28 can be disposed to be in contact with the source electrode structure 22 and the drain electrode structure 24 in the second direction (i.e., the y direction). Further, the channel structure 28 can be disposed to be in contact with the first and second ferroelectric layers 312 and 314 in the third direction (i.e., the x direction). Thus, the first and second channel layers 322 and 324 of the non-volatile memory device 1 of Figures 1-3 are omitted from the non-volatile memory device 8 of this embodiment.

[0134] ​​The channel structure 28 can have a columnar shape extending in the first direction (i.e., the z direction) from the base insulating layer 110. When a read voltage is applied to at least one of the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12, a conductive channel can be formed in a region of the channel structure 28 that overlaps the at least one gate electrode layer pattern. Likewise, when a read voltage is applied to at least one of the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d of the second gate structure 14, a conductive channel can be formed in a region of the channel structure 28 that overlaps the at least one gate electrode layer pattern.

[0135] For example, the channel structure 28 can include a doped semiconductor material or a metal oxide. For example, the semiconductor material can include silicon (Si), germanium (Ge), and gallium arsenide (GaAs), etc. The metal oxide can include indium-gallium-zinc (In-Ga-Zn) oxide. In one embodiment, the channel structure 28 can include silicon (Si) doped with an n-type dopant. Alternatively, the channel structure 28 can include c-axis aligned indium-gallium-zinc (In-Ga-Zn) oxide. The channel structure 28 can have a single-crystal structure or a polycrystal structure.

[0136] As described above, the non-volatile memory device 8 of the present embodiment can include a channel structure 28 having a columnar shape. By using the channel structure 28 instead of the insulating structure 26 of the non-volatile memory device 1 of Figure 5 the present embodiment in the same position, it is possible to simplify the device structure and the manufacturing process.

[0137] In other embodiments, in the non-volatile memory device 2 of Figures 7-9 the present embodiment, a non-volatile memory device in which the insulating structures 26a and 26b are replaced with the channel structure 28 of the present embodiment can be implemented, while omitting the first channel layer 322 and the second channel layer 324. Likewise, in the non-volatile memory device 3 of Figures 10-12 the present embodiment, Figures 13-15 the non-volatile memory device 4 of Figures 19-21 the present embodiment, Figures 16-18 the non-volatile memory device 5 of the present embodiment, and the non-volatile memory device 7 of the present embodiment, a non-volatile memory device in which the insulating structure 26 is replaced with the channel structure 28 of the present embodiment can be implemented. In these embodiments, the first channel layer 322 and the second channel layer 324 can be omitted. In addition, in the non-volatile memory device 6 of Figures 16-18 the present embodiment, a non-volatile memory device in which the insulating structure 26 is replaced with the channel structure 28 of the present embodiment can be implemented, while omitting ​ the first channel layer 1322 and the second channel layer 1324 of the non-volatile memory device 6 of the present embodiment.

[0138] Embodiments of the inventive concept have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept as disclosed in the following claims.

Claims

1. A non-volatile storage device, comprising: A substrate having an upper surface; A gate structure disposed above the substrate, the gate structure comprising at least one gate electrode layer pattern and at least one gate insulating layer pattern alternately stacked along a first direction perpendicular to the upper surface, wherein the gate structure extends in a second direction perpendicular to the first direction; A ferroelectric layer is disposed above the substrate and on at least a portion of a sidewall surface of the gate structure, wherein the sidewall surface of the gate structure forms a plane substantially parallel to the first direction and the second direction; A channel layer disposed above the substrate and on the ferroelectric layer; and The source electrode structure and the drain electrode structure are spaced apart from each other in the second direction, each disposed above the substrate and configured to contact the channel layer. The non-volatile memory device further includes conductive channels formed in some portions of the channel layer. The conductive channel extends along the second direction to electrically connect the source electrode structure and the drain electrode structure over the substrate. Wherein, the ferroelectric layer and the channel layer are separated in the first direction by the gate insulating layer pattern, and The ferroelectric layer and the channel layer are discontinuously disposed along the sidewall surface of the gate structure in the first direction.

2. The non-volatile storage device according to claim 1, further comprising: A substrate insulating layer is disposed on the substrate to contact the gate structure, the ferroelectric layer, the channel layer, the source electrode structure, and the drain electrode structure.

3. The non-volatile storage device according to claim 1, wherein, The ferroelectric layer has a predetermined thickness in a third direction perpendicular to the first and second directions.

4. The non-volatile storage device according to claim 1, wherein, The channel layer comprises a doped semiconductor material or a metal oxide.

5. The non-volatile storage device according to claim 1, wherein, Each of the source electrode structure and the drain electrode structure has a column shape extending in the first direction.

6. The non-volatile storage device according to claim 1, further comprising: An insulating structure is disposed between the source electrode structure and the drain electrode structure.

7. The non-volatile storage device according to claim 3, wherein, The gate electrode layer pattern is configured to contact the ferroelectric layer in the third direction, and The gate insulating layer pattern is configured to contact the source electrode structure and the drain electrode structure in the third direction.

8. The non-volatile storage device according to claim 1, further comprising: A non-ferroelectric first interface insulating layer is disposed between the ferroelectric layer and the channel layer.

9. The non-volatile storage device according to claim 8, further comprising: A non-ferroelectric second interface insulating layer is disposed between the gate structure and the ferroelectric layer.

10. The non-volatile storage device according to claim 8, further comprising: A floating electrode layer is disposed between the ferroelectric layer and the first interface insulating layer.

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