Pulse control circuit and method, pulse generator, and deep brain stimulation system

Abstract

The present invention discloses a pulse control circuit and method, a pulse generator, and a deep brain stimulation system. Different from the prior art, a pulse opening device and a pulse closing device are used to control the pulses output by a pulse generation circuit. The number of circuit components is greatly reduced, reducing the power consumption and failure rate of the circuit itself, improving the stability of the pulse control circuit, and at the same time, the lower power consumption can extend the battery life of the implantable device. It is possible to achieve the same stimulation accuracy and pulse width control accuracy as that of using an integrated operational amplifier only by using six field effect transistors, and the circuit principle design is transformed from a complex design to a cleverly conceived simplified design. In addition, the internal resistance of the field effect transistor in the prior art is less than 100 ohms, and the present invention uses a field effect transistor with an internal resistance of 1 KΩ to improve the control resolution and linearity, and can achieve precise control of the pulse width and period of the stimulation pulse under the same accuracy requirements.

Description

Technical Field

[0001] The present invention belongs to the technical field of implantable medical instruments, and in particular relates to a pulse control circuit and method, a pulse generator, and a deep brain stimulation system. Background Art

[0002] With the development of brain surgery technology and neuroelectronics technology, deep brain stimulation (DBS) has become the preferred treatment for advanced Parkinson's disease worldwide due to its better clinical effects than lesion surgery, enabling a non-destructive neurointerventional surgical process and a reversible treatment plan. The existing deep brain stimulation system mainly consists of an implantable pulse generator (IPG) in the body, a stimulating electrode (Lead), an in-body extension wire (Extension), an external programming device (Programer&Remoter), and related surgical tools (Surgical tool), etc. In this system, the precise pulse stimulation of the implantable pulse generator (IPG) in the body is the basis for better treatment effects and higher reliability. Enterprises that have obtained the sales qualification of deep brain stimulation devices at home and abroad have spared no effort in developing products related to pulse generators.

[0003] Most of the pulse current sources of the existing IPGs are implemented using operational amplifiers, and the internal circuit requires dozens of field effect transistors. As Figure 1 shown, it is the internal circuit structure diagram of an IPG in the prior art, with a complex circuit structure, numerous devices, and high power consumption.

[0004] To meet the precise control requirements of the existing pulse width and period, high-speed logic circuits are required, resulting in relatively high power consumption. However, if power consumption is to be reduced, control accuracy needs to be sacrificed, and linearity will also decrease, making it impossible to achieve precise pulse stimulation of the IPG. Therefore, a simple-structured and low-power IPG control circuit solution needs to be proposed. Summary of the Invention

[0005] The purpose of the present invention is to provide a pulse control circuit and method, a pulse generator, and a deep brain stimulation system, which are used to solve the problems of complex internal circuit structure, numerous devices, and high power consumption of the IPG in the prior art.

[0006] To solve the above technical problems, a first aspect of the present invention proposes a pulse control circuit, including a first power supply, a pulse turn-on device, a pulse turn-off device, a mirror current source, and a pulse generation circuit;

[0007] The mirror current source has a first output terminal and a second output terminal;

[0008] The input terminal of the mirror current source is connected to the positive electrode of the first power supply, the first output terminal is connected to one end of the pulse turn-on device, the second output terminal is connected to one end of the pulse turn-off device and the pulse generation circuit, and the pulse generation circuit is connected to the positive and negative electrodes of the first power supply;

[0009] The other end of the pulse turn-on device and the other end of the pulse turn-off device are both connected to the negative electrode of the first power supply;

[0010] The pulse generation circuit is used to output a third pulse signal. The pulse turn-on device controls the turn-on of the third pulse signal through a first pulse signal, and the pulse turn-off device controls the turn-off of the third pulse signal through a second pulse signal;

[0011] The first pulse signal and the second pulse signal cooperate to control the pulse width of the third pulse signal.

[0012] Optionally, the pulse turn-on device is a first field-effect transistor, and the pulse turn-off device is a second field-effect transistor;

[0013] The gate of the first field-effect transistor is used to receive the first pulse signal, the drain of the first field-effect transistor is connected to the first output terminal, and the source of the first field-effect transistor is connected to the negative electrode of the first power supply;

[0014] The gate of the second field-effect transistor is used to receive the second pulse signal, the drain of the second field-effect transistor is connected to the second output terminal, and the source of the second field-effect transistor is connected to the negative electrode of the first power supply.

[0015] Optionally, the mirror current source includes a third field-effect transistor and a fourth field-effect transistor;

[0016] The gate of the third field-effect transistor is respectively connected to the gate of the fourth field-effect transistor and the drain of the third field-effect transistor. The source of the third field-effect transistor is connected to the positive electrode of the first power supply, and the drain of the third field-effect transistor serves as the first output terminal and is connected to the drain of the first field-effect transistor;

[0017] The source of the fourth field-effect transistor is connected to the positive electrode of the first power supply, and the drain of the fourth field-effect transistor serves as the second output terminal and is connected to the drain of the second field-effect transistor and the pulse generation circuit.

[0018] Optionally, the pulse generation circuit includes a fifth field-effect transistor, a sixth field-effect transistor, a first capacitor, and a voltage regulator tube;

[0019] One end of the first capacitor is connected to the cathode of the voltage stabilizing diode and the drain of the fourth field effect transistor, and the other end of the first capacitor and the source of the sixth field effect transistor are both connected to the negative pole of the first power supply;

[0020] The source of the fifth field effect transistor is connected to the positive pole of the first power supply, the gates of the fifth field effect transistor and the sixth field effect transistor are both connected to the anode of the voltage stabilizing diode, and the drain of the fifth field effect transistor is connected to the drain of the sixth field effect transistor and is used to output the third pulse signal.

[0021] Optionally, the period of the third pulse signal is T, where T = C * R * 10, C is the capacitance value of the first capacitor, and R is the channel resistance value of the fourth field effect transistor.

[0022] Optionally, the channel resistance value of the fourth field effect transistor is 1 KΩ.

[0023] Optionally, the first field effect transistor, the second field effect transistor, and the sixth field effect transistor are all N-channel field effect transistors.

[0024] Optionally, the third field effect transistor, the fourth field effect transistor, and the fifth field effect transistor are all P-channel field effect transistors.

[0025] Optionally, the frequency of the first pulse signal is 100 Hz.

[0026] Optionally, the frequency of the second pulse signal is 100 Hz.

[0027] Optionally, the first power supply is a 10 V DC power supply.

[0028] In a second aspect of the present invention, a pulse control method is proposed, which uses any one of the pulse control circuits described in the above feature descriptions.

[0029] Optionally, the pulse control method includes:

[0030] S1: Applying the first pulse signal to the pulse opening device and applying the second pulse signal to the pulse closing device, and the pulse generating circuit outputs the third pulse signal;

[0031] S2: Adjusting the time interval between the first pulse signal and the second pulse signal to control the pulse width of the third pulse signal.

[0032] In a third aspect of the present invention, a pulse generator is proposed, which includes any one of the pulse control circuits described in the above feature descriptions.

[0033] In a fourth aspect of the present invention, a deep brain stimulation system is proposed, which includes the pulse generator.

[0034] The present invention provides a pulse control circuit and method, a pulse generator, and a deep brain stimulation system. Different from the prior art, a pulse turn-on device and a pulse turn-off device are used to control the pulses output by a pulse generation circuit. The number of circuit components is greatly reduced, the power consumption and failure rate of the circuit itself are lowered, the stability of the pulse control circuit is improved, and at the same time, the lower power consumption can extend the battery life of the implantable device.

[0035] In addition, in the control circuit provided by the present invention, only six field effect transistors can be used to achieve the same output stimulation accuracy and pulse width control accuracy as that using an integrated operational amplifier, and the circuit principle design is transformed from a complicated design to an ingenious and streamlined design.

[0036] Furthermore, the internal resistance of the field effect transistors in the prior art is less than 100 ohms, while the present invention uses field effect transistors with an internal resistance of 1 KΩ, which can improve the control resolution and linearity, and can achieve precise control of the pulse width and period of the stimulation pulses under the same accuracy requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic diagram of the internal circuit of the IPG in the prior art;

[0038] Figure 2 is a schematic diagram of a pulse control circuit provided by an embodiment of the present invention;

[0039] Figure 3 is a schematic diagram of the flow of a pulse control method provided by another embodiment of the present invention;

[0040] 100 - mirror current source, 200 - pulse generation circuit, T1 - first field effect transistor, T2 - second field effect transistor, T3 - third field effect transistor, T4 - fourth field effect transistor, T5 - fifth field effect transistor, T6 - sixth field effect transistor, D - voltage stabilizing diode, C1 - first capacitor, DC - first power supply. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The following will describe the specific embodiments of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0043] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0044] As Figure 2 shown, a first aspect of the present invention provides a pulse control circuit, including a first power supply DC, a pulse turn-on device, a pulse turn-off device, a mirror current source 100, and a pulse generation circuit 200. The mirror current source 100 has a first output terminal and a second output terminal. The input terminal of the mirror current source 100 is connected to the positive electrode of the first power supply DC. The first output terminal is connected to one end of the pulse turn-on device. The second output terminal is connected to one end of the pulse turn-off device and the pulse generation circuit 200. The other ends of the pulse turn-on device and the pulse turn-off device are both connected to the negative electrode of the first power supply DC. The pulse turn-on device is used to control a first pulse signal, and the pulse turn-off device is used to control a second pulse signal. The pulse generation circuit 200 is used to output a third pulse signal. The first pulse signal and the second pulse signal cooperate to control the pulse width of the third pulse signal.

[0045] Different from the prior art, a pulse output by the pulse generation circuit 200 is controlled by using the pulse turn-on device and the pulse turn-off device. The number of circuit components is greatly reduced, the power consumption and failure rate of the circuit itself are reduced, the stability of the pulse control circuit is improved, and at the same time, the lower power consumption can extend the battery life of the implantable device.

[0046] Preferably, the pulse turn-on device is a first field effect transistor T1, and the pulse turn-off device is a second field effect transistor T2. The gate of the first field effect transistor T1 is used to receive the first pulse signal. The drain of the first field effect transistor T1 is connected to the first output terminal. The source of the first field effect transistor T1 is connected to the negative electrode of the first power supply DC. The gate of the second field effect transistor T2 is used to receive the second pulse signal. The drain of the second field effect transistor T2 is connected to the second output terminal. The source of the second field effect transistor T2 is connected to the negative electrode of the first power supply DC.

[0047] Both the pulse-on device and the pulse-off device can be selected as field effect transistors. There are many types of field effect transistors. For the convenience of description, in the embodiments of the present invention, the first field effect transistor T1 and the second field effect transistor T2 can both be selected as N-channel field effect transistors, and the specific model can be AO3400 N-channel field effect transistors. However, it is not limited to this type, and other types of field effect transistors can also be realized, which are not limited here.

[0048] The first pulse signal for controlling the first field effect transistor T1 can be regarded as a pulse-on signal, and the second pulse signal for controlling the second field effect transistor T2 can be regarded as a pulse-off signal. When the first pulse signal gives a low level to the gate of the first field effect transistor T1, the first field effect transistor T1 is in the off state. At this time, the circuit at the first output terminal is in an open circuit state, and no current flows through. According to the principle of the mirror current circuit, it can be known that the circuit at the second output terminal also has no current flowing through. At this time, the pulse generation circuit 200 is in an open circuit state and cannot emit the third pulse signal. When the first pulse signal gives a high level to the gate of the first field effect transistor T1, the first field effect transistor T1 is in the on state. At this time, the circuit at the first output terminal is in a conducting state, and current flows through. According to the principle of the mirror current circuit, it can be known that the same current as that at the first output terminal also flows through the second output terminal. At this time, power can be supplied to the pulse generation circuit 200 to enable it to generate the third pulse signal. However, since the second field effect transistor T2 and the pulse generation circuit 200 are connected in parallel, if a high level is given to the gate of the second field effect transistor T2 at this time, the second field effect transistor T2 is in the on state, and the current at the second output terminal will not or only partially flow through the pulse generation circuit 200, resulting in the inability to generate the third pulse signal; if a low level is given to the gate of the second field effect transistor T2 at this time, the second field effect transistor T2 is in the off state, and the current at the second output terminal will all flow into the pulse generation circuit 200, and the pulse generation circuit 200 can generate the third pulse signal. Therefore, it is possible to control the pulse width of the third pulse signal by the time interval between the first pulse signal and the second pulse signal.

[0049] Specifically, the mirror current source 100 may include a third field effect transistor T3 and a fourth field effect transistor T4. The gate of the third field effect transistor T3 is connected to the gate of the fourth field effect transistor T4 and the drain of the third field effect transistor T3 respectively. The source of the third field effect transistor T3 is connected to the positive pole of the first power supply DC. The drain of the third field effect transistor T3 serves as the first output end and is connected to the drain of the first field effect transistor T1. The source of the fourth field effect transistor T4 is connected to the positive pole of the first power supply DC. The drain of the fourth field effect transistor T4 serves as the second output end and is connected to the drain of the second field effect transistor T2 and the pulse generation circuit 200. Generally, the mirror current source 100 can be implemented by two field effect transistors. Of course, this is not limited to this case. Other circuits or devices that can achieve the same function as the mirror current source 100 can also be used for replacement or deformation.

[0050] For the convenience of description, in the embodiments of the present invention, both the third field effect transistor T3 and the fourth field effect transistor T4 can be selected as P-channel field effect transistors, and the specific model can be AO6800 P-channel field effect transistors. However, this is not limited to this type, and other types of field effect transistors can also be implemented, which is not limited here.

[0051] Further, the pulse generation circuit 200 includes a fifth field effect transistor T5, a sixth field effect transistor T6, a first capacitor C1 and a voltage stabilizing diode D. One end of the first capacitor C1 is connected to the cathode of the voltage stabilizing diode D and the drain of the fourth field effect transistor T4. The other end of the first capacitor C1 and the source of the sixth field effect transistor T6 are both connected to the negative pole of the first power supply DC. The source of the fifth field effect transistor T5 is connected to the positive pole of the first power supply DC. The gate of the fifth field effect transistor T5 and the gate of the sixth field effect transistor T6 are both connected to the anode of the voltage stabilizing diode D. The drain of the fifth field effect transistor T5 is connected to the drain of the sixth field effect transistor T6 and is used to output the third pulse signal.

[0052] When the first pulse signal gives a low level to the gate of the first field effect transistor T1, the first field effect transistor T1 is in the off state. At this time, the circuit of the first output end is in an open circuit state and no current flows through. According to the principle of the mirror current circuit, the circuit of the second output end also has no current flowing through. At this time, the pulse generation circuit 200 is in an open circuit state and cannot emit the third pulse signal.

[0053] When the first pulse signal gives a high level to the gate of the first field-effect transistor T1, the first field-effect transistor T1 is in the conducting state. At this time, the circuit at the first output terminal is in the conducting state and there is current flowing through. According to the principle of the mirror current circuit, the same current as that at the first output terminal also flows through the second output terminal. At this time, power can be supplied to the pulse generation circuit 200 to enable it to generate the third pulse signal. However, since the second field-effect transistor T2 and the pulse generation circuit 200 are in a parallel connection relationship, if a high level is given to the gate of the second field-effect transistor T2 at this time, the second field-effect transistor T2 is in the conducting state, and the current at the second output terminal will not or only partially flow through the pulse generation circuit 200, resulting in the inability to generate the third pulse signal; if a low level is given to the gate of the second field-effect transistor T2 at this time, the second field-effect transistor T2 is in the cut-off state, and the current at the second output terminal will charge the first capacitor C1, and the first capacitor C1 enters the charging process. When the charging process of the first capacitor C1 is completed, if a high level is given to the gate of the second field-effect transistor T2 at this time, the second field-effect transistor T2 is in the conducting state, the voltage across the first capacitor C1 will be less than its charged voltage, and the first capacitor C1 enters the discharging process and outputs a pulse voltage. When the discharging voltage of the first capacitor C1 is greater than the reverse breakdown voltage of the zener diode D, the zener diode D conducts in the reverse direction, and at the same time, a high level is applied to the gates of the fifth field-effect transistor T5 and the sixth field-effect transistor T6. The fifth field-effect transistor T5 and the sixth field-effect transistor T6 are in the conducting state and output a pulse signal, that is, the third pulse signal.

[0054] For the convenience of description, in the embodiment of the present invention, the fifth field-effect transistor T5 can be selected as a P-channel field-effect transistor, and the sixth field-effect transistor T6 can be selected as an N-channel field-effect transistor. The specific models can be the AO6800 P-channel field-effect transistor and the AO3400 N-channel field-effect transistor. However, it is not limited to this type, and other types of field-effect transistors can also be realized, which are not limited here. It should be noted that in the embodiment of the present invention, the parameters of the N-channel field-effect transistor and the P-channel field-effect transistor should be symmetrically complementary, which can be specifically manifested as similar absolute values of the turn-on voltage, similar absolute values of the conduction current, and similar conduction resistance and other parameters.

[0055] The period of the third pulse signal is T, where T = C * R * 10, C is the capacitance value of the first capacitor C1, and R is the channel resistance value of the fourth field-effect transistor T4. The period of the third pulse signal can be controlled by adjusting the capacitance value of the first capacitor C1 and the channel resistance value of the fourth field-effect transistor T4.

[0056] Optionally, the channel resistance of the fourth field effect transistor T4 is 1 KΩ. Compared with the internal resistance of the field effect transistor in the prior art being less than 100 Ω, the present invention uses a field effect transistor with an internal resistance of 1 KΩ to improve the control resolution and linearity, and can achieve precise control of the pulse width and period of the stimulation pulse under the same precision requirements.

[0057] To facilitate the description of the technical solution of the present invention, the IPG control circuit of the present invention will be described in detail through more specific embodiments below. In this embodiment, the first field effect transistor T1, the second field effect transistor T2, and the sixth field effect transistor T6 can all be selected as AO3400 N-channel field effect transistors, and the third field effect transistor T3, the fourth field effect transistor T4, and the fifth field effect transistor T5 can all be selected as AO6800 P-channel field effect transistors. The frequencies of the first pulse signal and the second pulse signal can be selected as 100 Hz, and the first power supply DC can be selected as a 10 V DC power supply. As Figure 2 shown, the specific connection relationship of the circuit is as follows:

[0058] The positive pole of the 12 V DC power supply DC is connected to the source electrodes of the AO6800 P-channel field effect transistors T3, T4, and T5; the negative pole of the 12 V DC power supply DC is connected to the source electrodes of the AO3400 N-channel field effect transistors T1, T2, and T6 and one end of the 1 μF capacitor C1 and grounded; the periodic 100 Hz pulse turn-on signal Vg is connected to the gate electrode of the AO3400 N-channel field effect transistor T1; the periodic 100 Hz pulse turn-off signal Voff is connected to the gate electrode of the AO3400 N-channel field effect transistor T2; the gate electrodes of the AO6800 P-channel field effect transistors T3 and T4 are connected and connected to the drain electrode of the AO6800 P-channel field effect transistor T3 and the drain electrode of the AO3400 N-channel field effect transistor T1; the drain electrode of the AO6800 P-channel field effect transistor T4 and the drain electrode of the AO3400 N-channel field effect transistor T2 are connected and connected to the other end of the 1 μF capacitor C1 and the cathode of the 1N4743 voltage stabilizing diode D; the anode of the 1N4743 voltage stabilizing diode D is connected to the gate electrodes of the AO6800 P-channel field effect transistor T5 and the AO3400 N-channel field effect transistor T6; the drain electrodes of the AO6800 P-channel field effect transistor T5 and the AO3400 N-channel field effect transistor T6 are connected and connected to the periodic 100 Hz output pulse Vo.

[0059] Another embodiment of the present invention proposes a pulse control method using any one of the pulse control circuits described in the above characteristic description.

[0060] Optionally, as Figure 3 shown, the pulse control method includes:

[0061] S1: Apply the first pulse signal to the pulse-on device and the second pulse signal to the pulse-off device, and the pulse generation circuit 200 outputs the third pulse signal;

[0062] S2: Adjust the time interval between the first pulse signal and the second pulse signal to control the pulse width of the third pulse signal.

[0063] An embodiment of the present invention further provides a pulse generator, including the pulse control circuit described in any one of the above feature descriptions.

[0064] An embodiment of the present invention further provides a deep brain stimulation system, including the pulse generator.

[0065] In summary, the present invention provides a pulse control circuit and method, a pulse generator, and a deep brain stimulation system. Different from the prior art, a pulse-on device and a pulse-off device are used to control the pulse output by the pulse generation circuit. The number of circuit components is greatly reduced, the power consumption and failure rate of the circuit itself are reduced, the stability of the pulse control circuit is improved, and at the same time, the lower power consumption can extend the battery life of the implantable device.

[0066] In addition, in the control circuit provided by the present invention, only six field effect transistors can be used to achieve the same output stimulation accuracy and pulse width control accuracy as that of using an integrated operational amplifier, realizing the transformation from a complex design to a cleverly conceived streamlined design in the circuit principle design.

[0067] In addition, the internal resistance of the field effect transistor in the prior art is less than 100 ohms. The present invention uses a field effect transistor with an internal resistance of 1 KΩ, which can improve the control resolution and linearity, and can accurately control the pulse width and period of the stimulation pulse under the same accuracy requirements.

[0068] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example" or "specific example" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0069] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art, within the scope of the technical solution of the present invention, makes any form of equivalent substitution or modification and other changes to the technical solution and technical content disclosed by the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A pulse control circuit, characterized in that, It includes a first power supply, a pulse turn-on device, a pulse turn-off device, a mirror current source, and a pulse generation circuit; The mirror current source has a first output terminal and a second output terminal; The input terminal of the mirror current source is connected to the positive pole of the first power supply, the first output terminal is connected to one end of the pulse turn-on device, the second output terminal is connected to one end of the pulse turn-off device and the pulse generation circuit, and the pulse generation circuit is connected to the positive and negative poles of the first power supply; The other ends of the pulse turn-on device and the pulse turn-off device are both connected to the negative pole of the first power supply; The pulse generation circuit is used to output a third pulse signal. The pulse turn-on device controls the turn-on of the third pulse signal through a first pulse signal, and the pulse turn-off device controls the turn-off of the third pulse signal through a second pulse signal; The first pulse signal and the second pulse signal cooperate to control the pulse width of the third pulse signal; The pulse turn-on device is a first field-effect transistor, and the pulse turn-off device is a second field-effect transistor; The mirror current source includes a third field-effect transistor and a fourth field-effect transistor; The pulse generation circuit includes a fifth field-effect transistor, a sixth field-effect transistor, a first capacitor, and a voltage regulator tube.

2. The pulse control circuit according to claim 1, wherein The gate of the first field-effect transistor is used to receive the first pulse signal. The drain of the first field-effect transistor is connected to the first output terminal, and the source of the first field-effect transistor is connected to the negative pole of the first power supply; The gate of the second field-effect transistor is used to receive the second pulse signal. The drain of the second field-effect transistor is connected to the second output terminal, and the source of the second field-effect transistor is connected to the negative pole of the first power supply.

3. The pulse control circuit according to claim 2, wherein, The gate of the third field-effect transistor is respectively connected to the gate of the fourth field-effect transistor and the drain of the third field-effect transistor. The source of the third field-effect transistor is connected to the positive pole of the first power supply. The drain of the third field-effect transistor serves as the first output terminal and is connected to the drain of the first field-effect transistor; The source of the fourth field-effect transistor is connected to the positive pole of the first power supply. The drain of the fourth field-effect transistor serves as the second output terminal and is connected to the drain of the second field-effect transistor and the pulse generation circuit.

4. The pulse control circuit according to claim 3, wherein One end of the first capacitor is connected to the cathode of the voltage regulator tube and the drain of the fourth field-effect transistor. The other end of the first capacitor and the source of the sixth field-effect transistor are both connected to the negative pole of the first power supply; The source of the fifth field-effect transistor is connected to the positive pole of the first power supply. The gate of the fifth field-effect transistor and the gate of the sixth field-effect transistor are both connected to the anode of the voltage regulator tube. The drain of the fifth field-effect transistor is connected to the drain of the sixth field-effect transistor and is used to output the third pulse signal.

5. A pulse control circuit according to claim 4, characterized in that, The period of the third pulse signal is T, where T = C * R * 10, C is the capacitance value of the first capacitor, and R is the channel resistance value of the fourth field-effect transistor.

6. The pulse control circuit according to claim 5, characterized in that, The channel resistance value of the fourth field-effect transistor is 1 KΩ.

7. The pulse control circuit according to claim 4, characterized in that, The first field-effect transistor, the second field-effect transistor, and the sixth field-effect transistor are all N-channel field-effect transistors.

8. The pulse control circuit according to claim 4, characterized in that, The third field effect transistor, the fourth field effect transistor, and the fifth field effect transistor are all P-channel field effect transistors.

9. The pulse control circuit according to any one of claims 1-8, characterized in that, The frequency of the first pulse signal is 100 Hz.

10. The pulse control circuit according to any one of claims 1-8, characterized in that, The frequency of the second pulse signal is 100 Hz.

11. The pulse control circuit according to any one of claims 1-8, characterized in that, The first power supply is a 10V DC power supply.

12. A pulse control method, characterized in that, Use the pulse control circuit according to any one of claims 1-11.

13. A pulse control method according to claim 12, characterized in that, The pulse control method includes: S1: Apply the first pulse signal to the pulse turn-on device, apply the second pulse signal to the pulse turn-off device, and the pulse generation circuit outputs the third pulse signal; S2: Adjust the time interval between the first pulse signal and the second pulse signal to control the pulse width of the third pulse signal.

14. A pulse generator, characterized in that, Include the pulse control circuit according to any one of claims 1-11.

15. A deep brain stimulation system, characterized in that, Include the pulse generator according to claim 14.

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