Method of generating multiple levels of protection data and storage device

Abstract

The application provides a method and a storage device for generating multiple protection level data, comprising the following steps: obtaining a data protection level M of a page strip and a data processing capacity N of a media interface controller; when M is greater than N+1, performing the following steps: providing N pieces of user data to the media interface controller, so that the media interface controller generates intermediate check data for the N pieces of user data; writing the N pieces of data into the page strip; providing N-1 pieces of user data and the intermediate check data to the media interface controller, and generating check data DY according to the N-1 pieces of user data and the intermediate check data; judging whether the sum of the user data and the intermediate check data provided to the media interface controller has reached M-1 pieces of data; if yes, instructing the media interface controller to write the generated check data DY into the page strip.

Description

TECHNICAL FIELD

[0001] The present application relates to storage devices, and in particular, to a method of generating data with multiple protection levels and a storage device. BACKGROUND

[0002] Figure 1 A block diagram of a solid state storage device is shown. The solid state storage device 102 is coupled to a host for providing storage capability to the host. The host and the solid state storage device 102 can be coupled in various ways, including but not limited to connecting the host and the solid state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication network, etc. The host can be an information processing device capable of communicating with the storage device in the above manners, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc. are common NVMs.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is configured to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and is also configured to perform storage management, host logical address to flash physical address mapping, wear leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data of the DRAM 110. The DRAM can store the FTL table and / or buffered IO command data.

[0006] The control component 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive results of command execution output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] A memory target is one or more logical units (LUNs) of a shared CE (Chip Enable) signal within a NAND flash package. A NAND flash package can include one or more dies. Typically, a logical unit corresponds to a single die. A logical unit can include multiple planes. Multiple planes within a logical unit can be accessed in parallel, while multiple logical units within a NAND flash chip can execute commands and report status independently of one another.

[0008] Data is typically stored and read from a storage medium in pages. Data is erased in blocks. A block (also referred to as a physical block) contains multiple pages. A block contains multiple pages. A page (referred to as a physical page) on a storage medium has a fixed size, such as 17664 bytes. Physical pages can also have other sizes.

[0009] In a solid state storage device, a FTL (Flash Translation Layer) is utilized to maintain mapping information from logical addresses to physical addresses. Logical addresses constitute a storage space of the solid state storage device as perceived by upper layer software such as an operating system. Physical addresses are addresses used to access physical storage units of the solid state storage device. In the related art, address mapping can also be implemented in an intermediate address form. For example, a logical address is mapped to an intermediate address, and the intermediate address is further mapped to a physical address.

[0010] A table structure storing mapping information from logical addresses to physical addresses is referred to as an FTL table. The FTL table is important metadata in the solid state storage device. Typically, data items of the FTL table record address mapping relationships in the solid state storage device in units of data pages.

[0011] The FTL table includes a plurality of FTL table entries (or table items). In one case, a corresponding relationship between one logical page address and one physical page is recorded in each FTL table entry. In another case, a corresponding relationship between a plurality of continuous logical page addresses and a plurality of continuous physical pages is recorded in each FTL table entry. In still another case, a corresponding relationship between a logical block address and a physical block address is recorded in each FTL table entry. In yet another case, a mapping relationship between logical block addresses and physical block addresses, and / or a mapping relationship between logical page addresses and physical page addresses is recorded in the FTL table. The solid state storage device includes a plurality of NVM chips. Each NVM chip includes one or more dies (DIEs) or logical units (LUNs). The dies or logical units can respond to read and write operations in parallel. A plurality of read, write or erase operations on the same die or logical unit are executed sequentially.

[0012] A large block includes physical blocks from each of a plurality of logical units (LUNs), also referred to as a logical unit group. Each logical unit can provide one physical block for a large block. For example, in Figure 2 In the schematic diagram of the large block shown, a large block is constructed on every 16 logical units (LUNs). Each large block includes 16 physical blocks from 16 logical units (LUNs) respectively. In Figure 2 In the example of FIG. 2, large block 0 includes physical block 0 from each of the 16 logical units (LUNs), and large block 1 includes physical block 1 from each of the logical units (LUNs). Large blocks can also be constructed in a variety of other ways. Chinese patent application No. 201710752321.0 discloses variable length large blocks, which is incorporated herein by reference in its entirety.

[0013] As an optional way, a page stripe is constructed in a large block, and physical pages of the same physical address within each logical unit (LUN) constitute a “page stripe”. Figure 2In the example, physical pages P0-0, P0-1,..., and P0-x of large block 0 form a page stripe 0, where physical pages P0-0, P0-1,..., and P0-6 are used to store user data, and physical page P0-x is used to store the parity data calculated from all user data in the stripe. Similarly, Figure 2 In the example, physical pages P2-0, P2-1,..., and P2-x of large block 0 form a page stripe 2. Optionally, the physical page used to store the parity data can be located at any position in the page stripe.

[0014] To write data to a page stripe, the control component (104) of the storage device (also see Figure 1 ) provides a parity data calculator. As an example of calculating the parity data using XOR operation, for a page stripe including N+1 physical pages, XOR is calculated for the user data of N physical pages (e.g., (P0-0) XOR (P0-1) XOR (P0-2) XOR... XOR (P0-(N-1))), and the result is written to the physical page (e.g., P0-N) of the page stripe storing the parity data. Optionally, multiple parity data calculators (e.g., M) are provided in the control component (104) to write data to M page stripes simultaneously. The parity data calculators use a cache (e.g., XOR cache) to record the intermediate results of the parity data.

[0015] The parity data of a page stripe is used to protect the user data of the page stripe. The way the parity data is generated defines the data protection level. For example, in RAID (Redundant Arrays of Independent Drives) technology, there are data protection levels including RAID 1-5, RAID 10, RAID 11, etc.

[0016] Figure 3 A diagram showing the storage device generating parity data for a page stripe is shown.

[0017] Data to be written to the NVM is cached in the DRAM Figure 3 As an example, the data protection level of the storage device is "3+1", one parity data is generated for every three data, and the three data and its parity data are recorded in a page stripe.

[0018] The CPU of the control component provides data D1 in the DRAM to the media interface controller. The media interface controller writes the data D1 to the NVM. The media interface controller also generates intermediate check data DX for the data D1 and records in the XOR cache. As an example, the data D1 is the first portion of data of a page stripe, the XOR cache is initialized to 0, and the data stored in the XOR cache is XORed with the data D1 and the XOR cache is updated with the result of the calculation.

[0019] Next, the CPU also provides data D2 in the DRAM to the media interface controller. The media interface controller writes the data D2 to the NVM. The media interface controller also generates new intermediate check data DX by XORing the data stored in the XOR cache with the data D2 and updates the XOR cache with the result of the calculation. Next, the CPU also provides data D3 in the DRAM to the media interface controller. The media interface controller writes the data D3 to the NVM. The media interface controller also generates new check data DX by XORing the data stored in the XOR cache with the data D3 and updates the XOR cache with the result of the calculation.

[0020] The CPU also instructs the media interface controller to write the data DX in the XOR cache to the NVM, and the data D1, D2, D3 and DX of the NVM are located in the same page stripe.

[0021] Optionally, the CPU also instructs the media interface controller to move the data of the XOR cache to the DRAM.

[0022] Generally, a storage device has a determined data protection level, and the storage device is formatted according to the determined data protection level. To change the data protection level of the storage device, the storage device also needs to be reformatted. Under the control of the CPU, the media interface controller is able to generate check data according to multiple data protection levels. Figure 3

[0023] The namespace NS is also defined in the NVMe protocol. A namespace with size n is a set of logical pages with logical page addresses from 0 to n-1. The namespace can be uniquely identified by the namespace ID. SUMMARY

[0024] ​A namespace (NS) presents a plurality of virtual storage devices to a host coupled to a storage device, although these virtual storage devices can be provided by the same storage device, each NS is treated as an independent virtual storage device by the host. Thus the host wishes to format independently for one or more NSs, and wishes to provide differentiated functions or performance for each NS, for example, wishes to have different data protection levels for each NS, and can adjust the data protection level of one or more NSs without affecting the use of other NSs belonging to the same storage device as the one or more NSs.

[0025] Multiple data protection levels coexisting in a storage device require multiple ways of generating check data. The process of generating check data for each piece of user data using the CPU to control the media interface controller provides the greatest flexibility, but also introduces the greatest workload for the CPU. Using the hardware of the media interface controller to calculate the check data provides better performance, but lacks flexibility, and generally the hardware circuit is designed and provided to calculate the check data for a certain data protection level, and the hardware is difficult to adapt to changes in the data protection level. Thus it is necessary to obtain a reasonable balance between performance and flexibility for providing multiple data protection levels.

[0026] According to a first aspect of the present application, a method for generating write data according to the first aspect of the present application is provided, comprising the following steps: obtaining a data protection level M of a page stripe and a data processing capability N of a media interface controller; when M is greater than N+1, performing the following steps: providing N pieces of user data to the media interface controller, so that the media interface controller generates intermediate check data for the N pieces of user data; writing the N pieces of data to the page stripe; providing N-1 pieces of user data and the intermediate check data to the media interface controller, generating check data DY according to the N-1 pieces of user data and the intermediate check data; judging whether the sum of the user data and the intermediate check data provided to the media interface controller has reached M-1 pieces of data; if so, instructing the media interface controller to write the generated check data DY to the page stripe.

[0027] According to the first method of the first aspect of the present application, if the sum of the user data and the intermediate check data provided to the media interface controller has not reached M-1 pieces of data, the step of providing N-1 pieces of user data and the intermediate check data to the media interface controller, and the subsequent steps, are continued to be performed.

[0028] According to the first or second method of the first aspect of the present application, if the user data provided to the media interface controller is less than N-1 pieces, designated data is further obtained so that the sum of the designated data and the user data provided to the media interface controller satisfies N-1 pieces.

[0029] The third method according to the first aspect of the present application, wherein the specified data is all-zero data or random data.

[0030] The first to fourth methods according to the first aspect of the present application, wherein the intermediate check data DX is indicated to the media interface controller to have a placeholder mark, and in response, the media interface controller does not write the data having the placeholder mark into the page stripe when writing data into the page stripe.

[0031] The first to fifth methods according to the first aspect of the present application, wherein the intermediate check data DX is indicated to the media interface controller to have a placeholder mark with the specified data, and in response, the media interface controller does not write the data having the placeholder mark into the page stripe when writing data into the page stripe.

[0032] The first to sixth methods according to the first aspect of the present application, wherein a placeholder mark is marked for the specified data, and the data having the placeholder mark is not written into the page stripe when writing data into the page stripe.

[0033] The first to seventh methods according to the first aspect of the present application, wherein M and N satisfy the following relationship: M=N+m+1, wherein M, N and m are positive integers, and N>1.

[0034] The first to eighth methods according to the first aspect of the present application, wherein if M is less than N, the following steps are performed: providing M-1 portions of user data to the media interface controller; obtaining specified data such that the obtained specified data and the M-1 portions of user data satisfy N portions; generating check data DX for the M-1 portions of user data and the specified data; and writing the M-1 portions of user data and the check data DX into the page stripe.

[0035] The ninth method according to the first aspect of the present application, wherein when the M-1 portions of user data are provided to the media interface controller, if the user data is less than M-1 portions, a second specified data is further obtained such that the obtained user data and the second specified data satisfy M-1 portions.

[0036] According to the second aspect of the present application, a storage device according to the second aspect of the present application is provided, comprising a control component, which performs the method as described above.

[0037] According to a third aspect of the present application, a storage device according to the third aspect of the present application is provided, comprising a CPU, a media interface controller, a DRAM and a page stripe, wherein: the DRAM buffers user data to be written into the NVM; the CPU provides N portions of data buffered in the DRAM to the media interface controller according to a data processing capability N of the media interface controller; the media interface controller, when determining that M is greater than N, executes the following steps: buffers N portions of user data, generates intermediate check data DX for the N portions of user data, and writes the N portions of data into the page stripe; the media interface controller buffers N-1 portions of user data, generates check data DY according to the N-1 portions of user data and the intermediate check data DX; and determines whether final check data has been generated for M-1 portions of data.

[0038] According to a fourth aspect of the present application, a method for generating data of multiple protection levels according to the fourth aspect of the present application is provided, comprising the following steps: in response to a write command for writing data into a namespace, obtaining the namespace to which the write command is to write data; querying a namespace table to obtain namespace configuration information of the namespace indicated by the write command; obtaining, from the namespace configuration information, a data protection level M and a physical address space of the namespace indicated by the write command; allocating a large block constructed according to the data protection level from the physical address space; allocating a page stripe capable of carrying data from the large block; and if M is greater than N+1, wherein N is a data processing capability of a media interface controller, executing the following steps: providing N portions of user data to the media interface controller, so that the media interface controller generates intermediate check data for the N portions of user data; writing the N portions of data into the page stripe; providing N-1 portions of user data and the intermediate check data to the media interface controller, and generating check data DY according to the N-1 portions of user data and the intermediate check data; and if the sum of the user data and the intermediate check data provided to the media interface controller has reached M-1 portions of data, instructing the media interface controller to write the generated check data DY into the page stripe.

[0039] According to the first method of the fourth aspect of the present application, further comprising the step of: recording, in a corresponding part of an FTL table corresponding to the namespace indicated by the write command, an address to be accessed by the write command and a physical address in a page stripe allocated for the namespace carrying the written data.

[0040] According to the second method of the fourth aspect of the present application, if the sum of the user data and the intermediate check data provided to the media interface controller has not reached M-1 portions of data, continuing to execute the step of providing N-1 portions of user data and the intermediate check data to the media interface controller, and subsequent steps.

[0041] According to the first to the eighth methods of the fourth aspect of the present application, if the user data provided to the media interface controller is less than N-1, designated data is obtained so that the sum of the obtained designated data and the user data provided to the media interface controller satisfies N-1.

[0042] According to the fifth method of the fourth aspect of the present application, the designated data is all-zero data or random data.

[0043] According to the first to the ninth methods of the fourth aspect of the present application, the intermediate check data DX is indicated to the media interface controller to have a placeholder mark, and in response, the media interface controller does not write the data having the placeholder mark into the page stripe when writing data into the page stripe.

[0044] According to the first to the ninth methods of the fourth aspect of the present application, the intermediate check data DX is indicated to the media interface controller to have a placeholder mark, and in response, the media interface controller does not write the data having the placeholder mark into the page stripe when writing data into the page stripe.

[0045] According to the first to the ninth methods of the fourth aspect of the present application, the intermediate check data DX is indicated to the media interface controller to have a placeholder mark, and in response, the media interface controller does not write the data having the placeholder mark into the page stripe when writing data into the page stripe.

[0046] According to the first to the ninth methods of the fourth aspect of the present application, M and N satisfy the following relationship: M=N+m+1; where M, N and m are positive integers, and N>1.

[0047] According to the first to the tenth methods of the fourth aspect of the present application, if M is less than N, the following steps are performed: M-1 portions of user data are provided to the media interface controller; designated data is obtained so that the sum of the obtained designated data and the M-1 portions of user data satisfies N; check data DX is generated for the M-1 portions of user data and the designated data; and the M-1 portions of user data and the check data DX are written into the page stripe.

[0048] According to the eleventh method of the fourth aspect of the present application, when the M-1 portions of user data are provided to the media interface controller, if the user data is less than M-1, second designated data is obtained so that the sum of the obtained user data and the second designated data is M-1.

[0049] According to a fifth aspect of the present application, a method for generating data of multiple protection levels according to the fifth aspect of the present application is provided, comprising the following steps: obtaining a namespace to which a write command indicates to write data in response to the write command; querying a namespace table to obtain namespace configuration information of the namespace indicated by the write command; and obtaining a data protection level of the namespace from the namespace configuration information.

[0050] According to the first method of the fifth aspect of the present application, a physical address space is further obtained from the namespace configuration information; a large block is allocated from the physical address space according to the data protection level; and a page stripe capable of carrying data is allocated from the large block.

[0051] According to a sixth aspect of the present application, a method for writing data into a namespace according to the sixth aspect of the present application is provided, comprising the following steps: obtaining a namespace to which a write command indicates to write data in response to the write command; querying a namespace table to obtain namespace configuration information of the namespace indicated by the write command; obtaining a data protection level and a physical address space of the namespace from the namespace configuration information; allocating a large block from the physical address space according to the data protection level; allocating a page stripe capable of carrying data from the large block; and writing user data indicated by the write command into the allocated page stripe.

[0052] According to the first method of the sixth aspect of the present application, the media interface controller generates check data for the user data according to the data protection level of the namespace indicated by the write command, and writes the check data into the page stripe.

[0053] According to the first and second methods of the sixth aspect of the present application, further comprising the step of: recording an address accessed by the write command and a physical address carrying the written data in the page stripe allocated for the namespace in a corresponding part of an FTL table corresponding to the namespace indicated by the write command.

[0054] According to the second and third methods of the sixth aspect of the present application, if a number of user data flowing through the media interface controller is less than a number of user data for which check data is generated recorded in the namespace configuration information, the stored check data is an intermediate result.

[0055] According to the fourth method of the sixth aspect of the present application, check data is generated using the intermediate result and newly written data into the namespace.

[0056] According to the first to fifth methods of the sixth aspect of the present application, when the number of user data flowing through the media interface controller equals the number of user data recorded in the namespace configuration information for generating the check data, the check data of the page stripe corresponding to the namespace is generated, and the check data is written into the physical storage space corresponding to the namespace and occupies the check data page of the page stripe.

[0057] According to the seventh aspect of the present application, a storage device for providing different data protection levels for multiple namespaces is provided, and the storage device comprises a control component, an FTL table, and one or more NVM chips, wherein the control component performs the method as described above.

[0058] According to the first device of the seventh aspect of the present application, the namespace table comprises at least one entry, and each entry records the configuration information of one of the namespaces provided by the storage device.

[0059] According to the first device of the seventh aspect of the present application, the configuration information comprises one or more of the storage capacity of the namespace, the data protection level of the command space, the used FTL table, and the physical address range.

[0060] According to the first device of the seventh aspect of the present application, the storage device further comprises a DRAM.

[0061] According to the first to fourth devices of the seventh aspect of the present application, the FTL table comprises multiple parts, and each part provides the conversion from the logical address to the physical address for one of the namespaces provided by the storage device.

[0062] According to the first to fifth devices of the seventh aspect of the present application, the entry of the namespace table records the part of the FTL table used by the namespace corresponding to the entry.

[0063] According to the first to sixth devices of the seventh aspect of the present application, the NVM chip provides the physical address space of the storage device.

[0064] According to the first to seventh devices of the seventh aspect of the present application, the physical address space is divided into multiple parts, and each part corresponds to one namespace.

[0065] According to the first to eighth devices of the seventh aspect of the present application, when the namespace is created, the size of the physical address space allocated for the namespace is determined according to the storage space size and the data protection level of the namespace.

[0066] The first to ninth devices according to the seventh aspect of the application, wherein the chunks are constructed in the NVM chip according to the size of the storage space of the namespace and the data protection level.

[0067] The tenth device according to the seventh aspect of the application, wherein the data protection level indicates the error checking method used.

[0068] The eighth and ninth devices according to the seventh aspect of the application, wherein one or more of the following are recorded in the configuration information of the namespace: the number of chunks, the construction method of the chunks, and the correspondence between the chunk number and the physical address.

[0069] The first to tenth devices according to the seventh aspect of the application, wherein the physical address space allocated for the namespace is greater than, equal to, or less than the storage space required by the namespace.

[0070] The eleventh device according to the seventh aspect of the application, wherein when the physical address space allocated for the namespace is greater than the storage space required by the namespace, the extra storage space is used to provide available chunks for garbage collection of the physical address space allocated for the namespace and / or provide additional storage space for the namespace to write more data.

[0071] The eleventh and twelfth devices according to the seventh aspect of the application, wherein when the physical address space allocated for the namespace is less than the storage space required by the namespace, the size of the storage space allocated is dynamically adjusted according to the amount of data written to the physical address space allocated for the namespace, and the configuration information of the namespace is updated according to the adjustment result.

[0072] According to the eighth aspect of the application, a method for creating a namespace is provided, characterized by comprising the following steps: in response to a command for creating a namespace, obtaining the size of the namespace to be created from the command space; and allocating physical storage space for the command space.

[0073] The first method according to the eighth aspect of the application, wherein the physical storage space is allocated for the namespace according to the size of the namespace to be created and the data protection level.

[0074] The first method according to the eighth aspect of the application, wherein the data protection level is obtained from the command, or a predetermined data protection level is used.

[0075] The first method according to the eighth aspect of the application, wherein the physical address space is allocated for the command space from the unused physical address space of the storage device.

[0076] According to the fourth method of the eighth aspect of the present application, the physical address space allocated for the namespace is equal to, less than or greater than the physical address space requested by the command space according to the size of the namespace to be created and the data protection level.

[0077] According to the fifth method of the eighth aspect of the present application, the command indicates the additional storage space required by the namespace to be created.

[0078] According to the sixth method of the eighth aspect of the present application, all namespaces share the unallocated physical address space.

[0079] According to the seventh method of the eighth aspect of the present application, the large blocks allocated to the namespace are recorded in the configuration information of the namespace.

[0080] According to the eighth method of the eighth aspect of the present application, one or more large blocks are constructed in the physical storage space, each large block having the data protection level of the namespace to which it is allocated.

[0081] According to the ninth method of the eighth aspect of the present application, a large block table is created to record one or more large blocks allocated to a specified namespace.

[0082] According to the ninth method of the eighth aspect of the present application, the physical address of the large block, the location of the physical block storing the check data and one or more of the bad block flags are recorded in the entry of the large block table.

[0083] According to the ninth method of the eighth aspect of the present application, an entry is added to the namespace table to record the configuration information of the created namespace.

[0084] According to the ninth method of the eighth aspect of the present application, the configuration information of the namespace includes the storage space size of the namespace, the data protection level, the allocated physical address space, the additional storage space size or proportion, and / or the large block table of the physical address space.

[0085] According to the ninth aspect of the present application, a method for deleting a namespace according to the ninth aspect of the present application is provided, comprising the steps of: in response to a command for deleting a namespace, obtaining the namespace identifier from the command; obtaining the entry corresponding to the command space identifier from the namespace table according to the namespace identifier; obtaining the physical address space and large blocks allocated to the namespace from the entry; deleting the entry; and marking the large blocks as unused.

[0086] According to the first method of the ninth aspect of the present application, in response to the large blocks being marked as unused, the data recorded in the large blocks is erased. BRIEF DESCRIPTION OF DRAWINGS

[0087] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only represent some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained based on these drawings.

[0088] Figure 1 is a block diagram of a solid-state storage device in the related art;

[0089] Figure 2 is a schematic diagram of a large block in the related art;

[0090] Figure 3 shows a block diagram of a host and a storage device according to an embodiment of the present application;

[0091] Figure 4 shows a block diagram of a host and a storage device according to another embodiment of the present application

[0092] Figure 5 shows a schematic diagram of a flow of writing data to an NS according to an embodiment of the present application;

[0093] Figure 6 shows a flowchart of processing a write command according to an embodiment of the present application;

[0094] Figure 7 shows a flowchart of creating an NS according to an embodiment of the present application;

[0095] Figure 8 shows a schematic diagram of a storage device generating check data for a page stripe;

[0096] Figure 9A 、 Figure 9B 、 Figure 9C shows a schematic diagram of a storage device generating check data for a page stripe according to an embodiment of the present application;

[0097] Figure 10 shows a flowchart of writing data to a page stripe according to an embodiment of the present application;

[0098] Figure 11 shows a flowchart of writing data to a page stripe according to another embodiment of the present application. DETAILED DESCRIPTION

[0099] With reference to the drawings and embodiments disclosed herein, it is understood that the application is not limited in scope to the particular embodiments described herein. It is also understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting as the scope of the present application will be apparent from this detailed description to those of ordinary skill in the art.

[0100] Figure 4 A block diagram of a host and a storage device according to embodiments of the present application is shown.

[0101] Referring to Figure 4 , a host is coupled to a storage device. The host accesses the storage device by accessing a plurality of namespaces (e.g., NS0, NS 1, NS 2, and NS 3) provided by the storage device. The namespaces are provided according to, for example, the NVMe protocol.

[0102] According to embodiments of the present application, the namespaces provided by the storage device have the same or different namespace configurations. The namespace configurations include, for example, the size of the storage capacity of the namespace, the level of data protection of the namespace, the FTL table used, the range of physical addresses, etc.

[0103] The storage device includes a control component, one or more NVM chips, and optionally a DRAM. In some embodiments, the control component internally integrates a memory without the need for additionally providing a DRAM in the storage device. In other embodiments, the control component uses a DRAM provided by the host. The DRAM is used to store the check data generated for the user data.

[0104] According to embodiments of the present application, the control component further includes a namespace table (abbreviated as NS table). The NS table includes a plurality of entries, each entry of the NS table records the configuration information of one of the namespaces provided by the storage device.

[0105] Optionally, the FTL table includes a plurality of portions, each portion is used to provide the conversion from logical addresses to physical addresses for one of the NSs provided by the storage device. For example, the entry of the NS table records the portion of the FTL table used by the NS (e.g., the start address of the FTL table in the DRAM). As another example, according to the number of the NS and the size of the storage space, the portion of the FTL table used by the NS is calculated.

[0106] Optionally, one or more NVM chips of the storage device provide the physical address space of the storage device. The physical address space is divided into a plurality of portions (each portion is abbreviated as NVM space, e.g., NVM space 0, NVM space 1, NVM space 2, and NVM space 3, the physical address space also includes an unassigned NVM space). The assigned NVM spaces correspond one-to-one to the NSs.

[0107] When the NS is created, the size of the NVM space allocated for the created NS is determined according to the size of the storage space of the NS and the data protection level. For example, the storage space of the NS is 100GB, and the data protection level is "5+1", then the allocated NVM space needs 100GB to store user data, and needs additional 20GB to store check data, so the allocated NVM space needs at least 120GB storage space. The physical address range of the allocated 120GB storage space is recorded in the NS configuration information.

[0108] The data protection level also corresponds to the construction scheme of the large block of the NVM space. The large block is constructed in the NVM space according to the data protection level. For example, the data protection level of the created NS is "2+1", then the constructed large block includes 3 physical blocks, of which 2 physical blocks store user data and 1 physical block stores check data. As another example, the data protection level of the created NS is "a+b", then the constructed large block includes a+b physical blocks, of which a physical blocks store user data and b physical blocks store check data, where a and b are positive integers. Further optionally, each physical block belonging to the same large block is provided by a different logical unit (LUN) to ensure the parallelism of data access of the large block.

[0109] Optionally, the data protection level also indicates the error check method adopted. For example, the check data is calculated by exclusive or of the user data, or the user data is subjected to RS encoding to obtain the check data.

[0110] The NS configuration information also records, for example, the number of large blocks of the NVM space, the construction method of the large block, and the correspondence between the large block number and the physical address, etc.

[0111] Further optionally, the allocated NVM space is larger than the storage space required to store the user data and the check data of the NS, and the additional storage space is used to provide available large blocks when garbage collection is performed for the NVM space. Some NSs also have the requirement of the amount of written data. Since the NVM chip has a limited number of erasing and writing times, by providing more additional storage space for the NVM space allocated for the NS, more amount of written data can also be carried.

[0112] Optionally, the allocated NVM space is less than the storage space required to store the user data and the check data of the NS. At the initial stage of the use of the NS, the user writes less data into the NS or has not written data into the NS. At this time, less NVM space is allocated to the NS, so that the storage device can provide more large blocks to other NSs, thereby improving the utilization of the physical storage resources of the storage device. When the user writes more data into the NS, more large blocks are allocated to the NVM space corresponding to the NS to increase the allocated NVM space. And the NS configuration information is updated to record the large blocks allocated to the NVM space of the NS. Further optionally, when the user deletes the data in the NS or identifies that there is less valid data recorded in the NS, the large blocks allocated to the corresponding NVM space are also released, and the NS configuration information is also updated to record the large blocks allocated to the NVM space of the NS.

[0113] The media interface controller generates the check data according to the user data to be written into the NVM space and buffers the generated check data in the DRAM. For example, the data protection level is a+b, and a pages of user data are required to generate b pages of check data. Before all a pages of user data are received, the check data calculated for each page of user data is buffered in the DRAM. Figure 3 The figure shows the check data generated and buffered in the DRAM for NS0-NS3. It can be understood that, in response to b pages of check data being finally generated, the media interface controller writes the b pages of check data into the large block in which a pages of user data are stored. And the DRAM storage space occupied by the b pages of check data is also released.

[0114] Figure 5 The figure shows the flowchart of writing data into the NS according to the embodiments of the present application.

[0115] For example, the host writes data into NS0 (indicated by (1) in the figure). The command of writing data (referred to as write command for short) is sent to the control component of the storage device (indicated by (2) in the figure). The write command indicates the address to be accessed and the NS. The control component queries the NS table according to the NS indicated by the write command (indicated by (3) in the figure) to obtain the NS configuration information of the NS. The data protection level (for example, “2+1”) and the NVM space (for example, NVM space0) of the NS are obtained from the NS configuration information. A large block constructed according to the data protection level “2+1” is allocated from the NVM space0, and a page stripe capable of carrying data is allocated from the large block. The media interface controller writes the user data indicated by the write command into the allocated page stripe (indicated by (4) in the figure). Figure 5 Figure 5 Figure 5 Figure 5 ​​​In the middle, as indicated by (5). As the user data indicated by the write command flows through the media interface controller, the media interface controller also generates check data for it according to the data protection level of NS0 "2+1", and the generated check is stored in DRAM ( Figure 5 (4) indicates.

[0116] The FTL table corresponding to NS0 also records the address accessed by the write command and the physical address of the allocated page strip carrying the written data. This allows the host to retrieve the physical address from the FTL table corresponding to NS0 when accessing the written data via a read command, and then read the previously written data from that physical address. The read command indicates the NS. The NS table is accessed using the NS indicated by the read command to obtain the NS configuration information, which indicates the FTL corresponding to that NS. Optionally, the FTL table can be queried based on the NS number and address accessed by the read command, without needing to look up the NS table. For example, the NS number and address can be concatenated bit by bit as an index to access the FTL table.

[0117] If the user data flowing through the media interface controller is less than the required "2" pages for the page stripe, the checksum data recorded in DRAM is an intermediate result of the checksum data. When the user writes data to NS0 again, the media interface controller uses the intermediate result of the checksum data cached in DRAM and the newly written data to NS0 to continue generating checksum data. Figure 5 (Not shown in the image). In response to the user data flowing through the media interface controller filling the required "2" pages of the page stripe, the check data for that page stripe is also generated by the media interface controller, and then the check data in DRAM is also written to NVM space 0, occupying the required "1" pages of check data for that page stripe.

[0118] As an example again, the host writes data to NS2. Figure 5 In the middle, as indicated by (6). The write command is sent to the control unit of the storage device ( Figure 5 In the middle, as indicated by (7). The write command indicates the address to be accessed and NS. The control unit queries the NS table based on the NS indicated by the write command ( Figure 4 In the process, as instructed by (8), the NS configuration information of NS 2 is obtained. From the NS configuration information, the data protection level (e.g., "15+1") and NVM space (e.g., NVM space 2) of the NS are obtained. A block constructed according to the data protection level "15+1" is allocated from NVM space 2, and a page strip capable of carrying data is allocated from this block. The media interface controller writes the user data indicated by the write command into the allocated page strip ( Figure 5The media interface controller also generates the check data for the user data flowing through the media interface controller according to the data protection level "15+1" of NS 2 (indicated by (10)) as the user data indicated by the write command flows through the media interface controller. The generated check data is stored in the DRAM Figure 5 The media interface controller also generates the check data for the user data flowing through the media interface controller according to the data protection level "15+1" of NS 2 (indicated by (10)) as the user data indicated by the write command flows through the media interface controller. The generated check data is stored in the DRAM

[0119] If the user data flowing through the media interface controller to be written into NS 2 does not yet fill the "15" pages required by the page stripe, the check data recorded in the DRAM is an intermediate result of the check data. When the user next writes data into NS 2, the media interface controller continues to generate the check data using the intermediate result of the check data cached in the DRAM and the new data written by the user into NS 2 Figure 5 The check data for the page stripe is also generated by the media interface controller in response to the user data flowing through the media interface controller to be written into NS 2 filling the "15" pages required by the page stripe, and then the check data in the DRAM is also written into the NVM space 2 and occupies the "1" page of check data required by the page stripe.

[0120] Figure 6 A flowchart of processing a write command according to an embodiment of the present application is shown.

[0121] According to an embodiment of the present application, a host issues a write command to a storage device to write data in the storage device.

[0122] Referring to Figure 6 , the control component of the storage device receives the write command, obtains the NS configuration information of the namespace (NS) to be accessed from the NS table according to the namespace (NS) to be accessed by the write command, allocates a physical address and obtains the data protection level of the namespace (NS) to be accessed according to the obtained NS configuration information; and calculates the check data according to the obtained data protection level, so as to write the data into the NVM.

[0123] Figure 7 A flowchart of creating a namespace according to an embodiment of the present application is shown.

[0124] The storage device according to an embodiment of the present application provides a command of creating a namespace. A host issues a command of creating a namespace to the storage device to create a namespace in the storage device. The command of creating a namespace indicates the size of the namespace to be created and optionally the data protection level. Optionally, the command of creating a namespace can not indicate the data protection level, and the storage device creates the namespace using a default data protection level.

[0125] Referring to Figure 7 , the control component receives the command of creating a namespace, and extracts the storage space size of the namespace to be created and optionally the data protection level from the command of creating a namespace.

[0126] In response, the control component allocates NVM space for the NS to be created. The size of the NVM space to be allocated is determined based on the storage size indicated by the NS command and the data protection level. The NVM space is allocated for the NS from the unused NVM space of the storage device. For example, the storage size of the NS to be created is 200GB and the data protection level is "15+1", then the size of the NVM space to be allocated is at least 200GB+13.4GB+the size of the additional storage space. Alternatively, the size of the NVM space to be allocated is less than 200GB, and when the data written by the user to the NS reaches or approaches 200GB, the NVM space is allocated with an additional large block.

[0127] Alternatively, the NS command also indicates the additional storage space required by the NS to be created. For example, the created NS is provided with additional storage space equivalent to 10-20% of the storage size of the NS, and the NS command can indicate other amounts of additional storage space. Still alternatively, no additional storage space is allocated for the NS, and the unused NVM space of the storage device is shared by the NSs. For example, in response to the fact that NS 0 needs to receive the data generated by garbage collection from the additional large block, a large block C is allocated from the unused NVM space, and it is recorded in the NS configuration table of NS 0 that large block C has been allocated to NS 0.

[0128] Alternatively, the control component also constructs one or more large blocks in the NVM space, and the constructed large blocks meet the data protection level indicated by the NS creation command. Further alternatively, a large block table is created to record one or more large blocks allocated to a specified NVM space, and the entries of the large block table record the physical address of the large block, the location of the physical block storing the check data, the bad block flag, etc.

[0129] The control component also adds an entry in the NS table to record the configuration information of the created NS. The NS configuration information includes the storage size of the NS, the data protection level, the allocated NVM space, the size or proportion of the additional storage space, and / or the large block table of the NVM space, etc.

[0130] According to yet another embodiment of the present application, the storage device provides a command to delete an NS. The host issues a delete NS command to the storage device to delete an NS in the storage device. The delete NS command indicates the number or identifier of the NS to be created.

[0131] The control unit receives a delete NS command and extracts, for example, the number of the NS to be deleted from the delete NS command. It accesses the NS table using the NS number to retrieve and delete the entry corresponding to that NS number. Furthermore, based on the retrieved entries in the NS table, it obtains the NVM space allocated to that NS and its blocks, marking these blocks as unused so that they can be allocated to other NSs. Optionally, in response to marking these blocks as unused, it also erases the data recorded in these blocks.

[0132] Different data protection levels correspond to different methods of generating verification data. Under the control of the control unit, through... Figures 3-5 The media interface controller can generate verification data according to various data protection levels.

[0133] Figure 3 In the example, the CPU is required to move each piece of data from DRAM to the NVM, thus introducing a significant load on the CPU. The goal is to reduce the CPU load during the process of generating checksum data and writing it to the NVM chip.

[0134] Figure 8 This diagram illustrates how another storage device generates checksum data for page stripes.

[0135] Figure 8 In this example, the CPU provides all the user data required to write the page stripe to the media interface controller at once, thereby reducing the number of times the CPU is involved in writing data to the page stripe, in order to... Figure 3 The technical solution reduces the CPU load. For example, the CPU writes N data packets to the NVM chip at once via the media interface controller. The media interface controller processes the continuously received N data packets at once. Figure 8 In the example, N=3, and the data (D1, D2, and D3) are used to calculate checksum data. The generated checksum data is stored in the XOR buffer (denoted as data DX). The media interface controller also writes the N consecutively received data as user data into the page stripe of the NVM. The media interface controller also writes the XOR buffered data DX into the NVM as checksum data for the page stripe. Furthermore, data D1, D2, and D3, along with the checksum data DX, are stored in the same page stripe.

[0136] The following description uses a storage device with a data protection level of "3+1" as an example. Figure 8 In this embodiment, a verification data is generated for every three data sets, and the three data sets and their verification data are recorded in the page stripe of the NVM chip.

[0137] See Figure 8 The data to be written to NVM (data D1, D2, and D3) is cached in DRAM. Figure 8The CPU of the control component moves the N pieces (N=3) of data (D1, D2 and D3) in the DRAM from the DRAM to the control component (1) according to the specified data protection level, and provides the data to the media interface controller (2). The media interface controller writes the data D1, D2 and D3 into the page stripe (3) in the NVM chip. The media interface controller also generates the check data DX for the data D1, D2 and D3 and records in the XOR cache (4). It is understood that, Figure 8 The operation indicated by (3) and the operation indicated by (4) can be performed simultaneously. The media interface controller also writes the check data DX generated in the XOR cache into the NVM chip (5), in which the data D1, D2, D3 and the check data DX are located in the same page stripe. Figure 8 Figure 8 As an example, the XOR cache is initialized to 0, and the media interface controller operates the data D1, D2 and D3 to XOR with the data stored in the XOR cache in sequence, and updates the XOR cache with the calculation result. After the data D1, D2 and D3 are all XORed with the data stored in the XOR cache, the data DX in the XOR cache is the check data DX corresponding to the data D1, D2 and D3. Figure 8 Figure 8 Alternatively, the media interface controller initializes the XOR cache to the data D1, and operates the data D2 and D3 to XOR with the data stored in the XOR cache in sequence, and updates the XOR cache with the calculation result. After the data D2 and D3 are all XORed with the data stored in the XOR cache, the data DX in the XOR cache is the check data DX corresponding to the data D1, D2 and D3. Figure 8 According to an embodiment of the application, the media interface controller calculates the check data for the determined N pieces of data, N corresponding to the data protection level. Thus, the command indicated by the CPU to the media interface controller to write the data into the NVM chip and generate the check data also indicates the determined data protection level, for example "N+1". Thus, for the process of generating a group of page stripes of data, the CPU only intervenes once, generating a command to the media interface controller, which indicates the N pieces of data and the physical address of the page stripe. In another example, the CPU also separately indicates to the media interface controller to write the data in the XOR cache into the page stripe.

[0138] Alternatively, the CPU also indicates to the media interface controller to move the data of the XOR cache to the DRAM.

[0139]

[0140] Figure 8

[0141] Alternatively, the CPU also indicates to the media interface controller to move the data of the XOR cache to the DRAM. ​​​​​

[0142] Figure 8 In this embodiment, the media interface controller writes data to the page stripe only for a specified data protection level. When the storage device needs to provide multiple different data protection levels, it needs to... Figure 9A The embodiments are improved.

[0143] Figure 9B , Figure 9C and Figure 9A A schematic diagram illustrating the generation of checksum data for page stripes using a storage device according to an embodiment of this application is shown. Figure 9A In one embodiment, the CPU operates the media controller to write data to page stripes with multiple different data protection levels.

[0144] Figure 9A In this example, the media interface controller's processing capability lies in calculating checksums for N data samples (N=3 for example), and the generated checksums are stored in the XOR cache. The media interface controller also writes the N data samples as user data into the page stripes of the NVM. Furthermore, the media interface controller writes the XOR cached data DX into the NVM as checksums for the page stripes.

[0145] The required data protection level is, for example, N+m+1 (for example, N=3, m=2), generating one checksum for every 5 data entries, with the 5 data entries and their checksum recorded on the same page strip.

[0146] See Figure 9A The data to be written to NVM (data D1, D2, and D3) is cached in DRAM. Figure 9A (Not shown in the image). The CPU of the control unit moves N copies (N=3) of data (D1, D2, and D3) from the DRAM to the control unit according to the specified data protection level. Figure 9A (1) indicates), and provides to the media interface controller ( Figure 9A (2) indicates). The media interface controller writes data D1, D2, and D3 into the page stripe in the NVM chip ( Figure 9A (3) indicates). The media interface controller also generates check data DX for data D1, D2 and D3 and records it in the XOR cache. Figure 9A (4) indicates). The media interface controller also moves the parity data DX generated in the XOR cache to the DRAM. Figure 9B (5) Instructions.

[0147] Continue reading Figure 9B Other data to be written to NVM (data D4 and D5) is also cached in DRAM. Figure 9B(Not shown in the image). Because the media interface controller accepts a data protection level of N (N=3), the CPU moves the checksum DX and data (D4 and D5) from DRAM to the control unit (…). Figure 9A (Indicated by (6) and (7)). The verification data DX is in Figure 9B In the processing demonstrated, data is generated by the control unit and then transferred to the DRAM. Figure 9B In the example, the CPU combines the check data DX in DRAM with the data D4 and D5 to be written to NVM to form N copies of data (N=3) acceptable for the media interface controller to generate check data. Therefore, from the perspective of the media interface controller, it still only needs to process the operation of generating check data for N copies of data.

[0148] according to Figure 9B In an embodiment, when the CPU instructs the media interface controller to write the parity number DX and data (D4 and D5) to the NVM, it also provides a "placeholder" mark for the parity data DX. Figure 9B (Indicated by the shaded line of data DX). Because the check data DX has a "placeholder" marker, the media interface controller uses the data with the "placeholder" marker to calculate the check data, but does not write the data with the "placeholder" marker to the NVM. See details. Figure 9B The media interface controller writes data D4 and D5 into the page stripe of the NVM chip. Figure 9B (8) indicates that (data DX was not written to the NVM chip because it had a placeholder mark). The media interface controller also generates check data DY for data D4, D5 and DX and records it in the XOR cache. Figure 9B (9) indicates). The media interface controller also moves the parity data DY generated in the XOR cache to the DRAM. Figure 9A (10) indicates). At this point, data D1-D5 and check data DY have been written into the NVM chip, and these data and check data together form a complete page strip.

[0149] Optionally, the media interface controller can also move the parity data DY generated in the XOR cache to DRAM.

[0150] As an example, before the CPU provides data D4, D5, and DX to the media interface controller to generate parity data DY, the XOR cache is initialized to 0. The media interface controller performs XOR operations on the data DX, D4, and D5 sequentially with the data stored in the XOR cache, and updates the XOR cache with the calculation results. After the data DX, D4, and D5 have all undergone XOR operations with the data stored in the XOR cache, the data DY in the XOR cache is the parity data DY corresponding to the data DX, D4, and D5.

[0151] Optionally, in response to the CPU providing the media interface controller with data D4, D5 and DX to generate the check data DY, the media interface controller initializes the XOR cache with the first of the received set of N (N=3) portions of data (e.g., data DX), and operates data D4 and D5 in turn with the data stored in the XOR cache to perform XOR operations, and updates the XOR cache with the results of the operations. After data D4 and D5 have both been XORed with the data stored in the XOR cache, the data DY in the XOR cache is the check data DY corresponding to data D4, D5 and DX. Further, since the XOR cache was initialized with data DX, and the data stored in the XOR cache after Figure 9B processing is also DX, in step (6) of Figure 9A , the media interface controller can be provided with only data D4 and D5, without having to move data DX from the DRAM. However, this requires that the media interface controller be modified to accept a command indicating N-1 portions of data, with the implication that the other portion of data is the data stored in the XOR cache, in response to a command indicating a different number of portions of data (N=3).

[0152] By combining the operations of Figure 9B and Figure 9A , a page stripe with a write data protection level of "3+2+1" is implemented using a media interface controller that only accepts a data protection level of "N+1" (N=3).

[0153] And by combining the operations of Figure 9C and Figure 9C , a page stripe with a write data protection level of "3+1+1" is implemented using a media interface controller that only accepts a data protection level of "N+1" (N=3).

[0154] Referring to Figure 9A , the required data protection level is, for example, N+m+1 (as an example, N=3, m=1), and 1 portion of check data is generated for every 4 portions of data, and the 4 portions of data and its check data are recorded in the same page stripe. After the processing according to Figure 9C generates the (intermediate) check data DX for N portions of data, the combination of the remaining m portions of data and the intermediate check data X is not N portions of data, Figure 9C the embodiments handle this situation.

[0155] Continuing to refer to Figure 9B , other data (data D4) to be written to the NVM is also cached in the DRAM Figure 9C (not shown). Since the media interface controller accepts a data protection level of N (N=3), the CPU moves the check data DX and data D4, as well as all-0 data (denoted as D0') from the DRAM to the control unit Figure 9AThe check data DX is moved to the DRAM (indicated by (6) and (7) in Figure 9C In the process shown, the check data DX is generated by the control component and moved to the DRAM. In Figure 9C In the example, the CPU provides the check data DX in the DRAM to the media interface controller along with the data D4 to be written to the NVM and the all-0 data D0' to make up N pieces of data (N=3) acceptable to the media interface controller for generating the check data, so that the media interface controller still only needs to handle the operation of generating the check for N pieces of data.

[0156] According to Figure 9C In the example, the CPU provides the check data DX in the DRAM to the media interface controller along with the data D4 to be written to the NVM and the all-0 data D0' to make up N pieces of data (N=3) acceptable to the media interface controller for generating the check data, so that the media interface controller still only needs to handle the operation of generating the check for N pieces of data. Figure 9C In the example, the CPU provides the check data DX in the DRAM to the media interface controller along with the data D4 to be written to the NVM and the all-0 data D0' to make up N pieces of data (N=3) acceptable to the media interface controller for generating the check data, so that the media interface controller still only needs to handle the operation of generating the check for N pieces of data. Figure 9C In the example, the CPU provides the check data DX in the DRAM to the media interface controller along with the data D4 to be written to the NVM and the all-0 data D0' to make up N pieces of data (N=3) acceptable to the media interface controller for generating the check data, so that the media interface controller still only needs to handle the operation of generating the check for N pieces of data. Figure 9C In the example, the CPU provides the check data DX in the DRAM to the media interface controller along with the data D4 to be written to the NVM and the all-0 data D0' to make up N pieces of data (N=3) acceptable to the media interface controller for generating the check data, so that the media interface controller still only needs to handle the operation of generating the check for N pieces of data. Figure 9C In the example, the CPU provides the check data DX in the DRAM to the media interface controller along with the data D4 to be written to the NVM and the all-0 data D0' to make up N pieces of data (N=3) acceptable to the media interface controller for generating the check data, so that the media interface controller still only needs to handle the operation of generating the check for N pieces of data. Figure 10 In the example, the CPU provides the check data DX in the DRAM to the media interface controller along with the data D4 to be written to the NVM and the all-0 data D0' to make up N pieces of data (N=3) acceptable to the media interface controller for generating the check data, so that the media interface controller still only needs to handle the operation of generating the check for N pieces of data.

[0157] In the example, the CPU provides the check data DX in the DRAM to the media interface controller along with the data D4 to be written to the NVM and the all-0 data D0' to make up N pieces of data (N=3) acceptable to the media interface controller for generating the check data, so that the media interface controller still only needs to handle the operation of generating the check for N pieces of data.

[0158] In the example, the CPU provides the check data DX in the DRAM to the media interface controller along with the data D4 to be written to the NVM and the all-0 data D0' to make up N pieces of data (N=3) acceptable to the media interface controller for generating the check data, so that the media interface controller still only needs to handle the operation of generating the check for N pieces of data.

[0159] Figure 10 A flowchart of writing data to a page stripe according to an embodiment of the application is shown.

[0160] Figure 11Embodiments of the application are applicable to a case where a media interface controller is used to generate check data for N pieces of data and write the N pieces of data to NVM, and the data protection level of a page stripe is "N+m+1", where m and N are positive integers, and N>1.

[0161] To write data to a page stripe, the CPU obtains N pieces of data. The N pieces of data are stored in, for example, a DRAM.

[0162] The CPU provides the obtained N pieces of data to the media interface controller, instructs the media interface controller to write the N pieces of data to a page stripe of the NVM, and the media interface controller also generates first check data based on the N pieces of data. The CPU instructs the media interface controller whether each of the N pieces of data provided to the media interface controller is "placeholder" data. The media interface controller writes non-"placeholder" data to the page stripe, and does not write "placeholder" data to the page stripe.

[0163] The CPU further obtains N-1 pieces of data to be written to the page stripe from, for example, a DRAM, provides the N-1 pieces of data to the media interface controller together with the previously generated first check data, and instructs the media interface controller that the N-1 pieces of data obtained from the DRAM are non-"placeholder" data, and the first check data is "placeholder" data. In response, the media interface controller writes the N-1 pieces of non-"placeholder" data to the page stripe, and does not write "placeholder" data to the page stripe. The media interface controller also generates second check data based on the received N pieces of data.

[0164] As an example, m=N-1, all user data of the page stripe has been written to the page stripe so far, and the second check data is the check data of the page stripe. The CPU further instructs the media interface controller to write the second check data to the page stripe. The N pieces of data written the first time, the N-1 pieces of data written the second time, and the second check data are written to the same page stripe.

[0165] Figure 11 A flowchart of writing data to a page stripe according to yet another embodiment of the application is shown.

[0166] ​ Embodiments of the application are applicable to a case where a media interface controller is used to generate check data for N pieces of data and write the N pieces of data to NVM, and the data protection level of a page stripe is "N+m+1", where m and N are positive integers, and N>1.

[0167] To write data to a page stripe, the CPU first obtains the data protection level of the data to be written currently. As an example, the data protection level is M (M=N+m+1).

[0168] The CPU obtains N pieces of data (each piece of data is, for example, 1 page of a page stripe). The N pieces of data are stored in, for example, a DRAM. The CPU provides the obtained N pieces of data to the media interface controller, instructs the media interface controller to write the N pieces of data to a page stripe of the NVM, and the media interface controller also generates intermediate check data according to the N pieces of data. The CPU instructs the media interface controller whether each piece of the N pieces of data provided to the media interface controller is "placeholder" data. The media interface controller writes non-"placeholder" data to the page stripe, and "placeholder" data is not written to the page stripe. Optionally, the CPU also instructs the media interface controller to move the XOR cache data to the DRAM.

[0169] To generate check data for a page stripe with a data protection level of "N+m+1", check data needs to be calculated for N+m pieces of data. The CPU identifies whether check data has been generated for M-1 (=N+m) pieces of data (1130). If check data has been generated for M-1 pieces of data, the CPU instructs the media interface controller to write the generated check data (denoted as final check data) to the same page stripe of the NVM as the M-1 pieces of data were written to previously. If check data has not been generated for M-1 pieces of data, the CPU obtains N-1 pieces of data from the DRAM. If the data provided by the user to be written to the NVM is not enough for N-1 pieces of data, one or more pieces of specified data (for example, all-0 data) or random data are additionally obtained, so that the combination of the data provided by the user to be written to the NVM and the specified data is N-1 pieces of data. The CPU provides the combination of the N-1 pieces of data and the intermediate check data generated by the media interface controller previously to the media interface controller as N pieces of data, and the CPU also marks the intermediate check data as "placeholder". If there is additional specified data, the CPU also marks the additional specified data as "placeholder".

[0170] The media interface controller calculates new intermediate check data from the N-1 pieces of data obtained by the CPU and the intermediate check data, and the new intermediate check data is saved in the XOR cache. The media interface controller also writes data that is not marked as "placeholder" from the obtained N pieces of data to the NVM. Optionally, the CPU also instructs the media interface controller to move the XOR cache data to the DRAM.

[0171] And turning to step 1130, the CPU identifies whether check data has been generated for M-1 (=N+m) pieces of data (1130), and continues the subsequent steps.

[0172] According to an embodiment of the present application, a solid-state storage device is also provided, which includes a controller and a non-volatile memory chip, wherein the controller performs any one of the methods provided by the embodiments of the present application.

[0173] According to the embodiments of the present application, a program stored on a readable medium, when executed by a controller of a solid state storage device, causes the solid state storage device to perform any of the methods provided by the embodiments of the present application.

[0174] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the preferred embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to encompass within their scope all possible variations and modifications of the preferred embodiments. It is apparent that those skilled in the art can, without departing from the spirit or scope of the application, make various changes and modifications of the application. Thus, the application is intended to encompass all such changes and modifications as fall within the scope of the claims, together with all equivalents thereof.

Claims

1. A method for generating write data, comprising the following steps: Obtain the data protection level M of the page stripe and the data processing capability N of the media interface controller; When M is greater than N+1, perform the following steps: The CPU provides N copies of user data to the media interface controller at once through a single command, enabling the media interface controller to generate intermediate verification data for the N copies of user data. Write the N sets of user data into the page strip; The CPU provides N-1 copies of user data and intermediate verification data to the media interface controller in one command, and generates verification data DY based on the N-1 copies of user data and intermediate verification data. Determine whether the sum of the user data and intermediate verification data provided to the media interface controller has reached M-1 data entries; If so, the media interface controller is instructed to write the generated verification data DY into the page strip.

2. The method as described in claim 1, wherein if the sum of the user data and intermediate verification data provided to the media interface controller does not reach M-1 data sets, the step of providing N-1 data sets and the intermediate verification data to the media interface controller, and subsequent steps, shall continue.

3. The method as described in claim 1 or 2, wherein if the user data provided to the media interface controller is less than N-1 copies, specified data is also acquired, such that the sum of the acquired specified data and the user data provided to the media interface controller satisfies N-1 copies.

4. The method of claim 1 or 2, wherein the intermediate check data DX is indicated to the media interface controller to have a placeholder mark, and in response, the media interface controller does not write the data with the placeholder mark to the page strip when writing data to the page strip.

5. The method of claim 1 or 2, wherein the intermediate check data DX and the specified data are indicated to the media interface controller to have placeholder marks, and in response, the media interface controller does not write the data with placeholder marks into the page strip when writing data into the page strip.

6. The method of claim 1 or 2, wherein if M is less than N, the following steps are performed: Provide M-1 copies of user data to the media interface controller; Obtain specified data such that the sum of the obtained specified data and the M-1 copies of user data satisfies N copies; Generate verification data DX for the M-1 copies of user data and the specified data; Write M-1 copies of user data and verification data DX into the page strip.

7. A storage device, including a control component, performing the method as claimed in any one of claims 1-6.

8. A storage device comprising a CPU, a media interface controller, DRAM, and page stripes, wherein: DRAM is used to cache user data to be written to NVM. The CPU, based on the data processing capability N of the media interface controller, provides N copies of data cached in DRAM to the media interface controller at once through a single command. When the media interface controller determines that M is greater than N, it performs the following steps: Cache N copies of user data, generate intermediate verification data DX for the N copies of user data, and write the N copies of user data into the page stripe; The media interface controller caches N-1 copies of user data and generates verification data DY based on the N-1 copies of user data and intermediate verification data DX; Determine whether final verification data has been generated for M-1 data sets.

9. A method for generating data with multiple protection levels, comprising the following steps: In response to a write command that writes data to a namespace, the namespace to which the write command is to be written is obtained; Query the namespace table to obtain the namespace configuration information of the namespace indicated by the write command; Obtain the data protection level M and physical address space of the namespace indicated by the write command from the namespace configuration information; Allocate large blocks from the physical address space, constructed according to the data protection level; Allocate data-carrying page strips from the large block; If M is greater than N+1, perform the following steps, where N is the data processing capability of the media interface controller: The CPU provides N copies of user data to the media interface controller at once through a single command, enabling the media interface controller to generate intermediate verification data for the N copies of user data. Write the N sets of user data into the page strip; The CPU provides N-1 copies of user data and intermediate verification data to the media interface controller in one command, and generates verification data DY based on the N-1 copies of user data and intermediate verification data. If the sum of the user data and intermediate verification data provided to the media interface controller reaches M-1 data units, the media interface controller is instructed to write the generated verification data DY into the page strip.

10. The method of claim 9, further comprising the step of: recording in a corresponding portion of the FTL table corresponding to the namespace indicated by the write command the address to be accessed by the write command and the physical address of the page stripe allocated to the namespace carrying the written data.

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