Integrated circuit, semiconductor structure and method for forming trench capacitor

Abstract

Various embodiments of the present disclosure relate to an integrated circuit (IC) comprising a pillar structure adjacent to a trench capacitor. A substrate has a plurality of sidewalls defining a trench. The trench extends into a front surface of the substrate. The trench capacitor comprises a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers, the plurality of capacitor electrode layers and the plurality of capacitor dielectric layers respectively lining the trench and defining a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front surface of the substrate, and the second width is aligned with a first point disposed below the front surface.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an integrated circuit, a semiconductor structure, and a method for forming a trench capacitor. Background Art

[0002] Trench capacitors exhibit high power density relative to some other capacitor types within semiconductor integrated circuits (ICs). As a result, trench capacitors are used in applications such as dynamic random-access memory (DRAM) memory cells, among other applications. Some examples of trench capacitors include high-density deep trench capacitors (DTCs) for advanced technology node processes. Summary of the invention

[0003] According to an embodiment of the present disclosure, an integrated circuit includes a substrate, a trench capacitor, and a pillar structure. The substrate includes a plurality of sidewalls defining a trench, wherein the trench extends into the front surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers, wherein the plurality of capacitor electrode layers and the plurality of capacitor dielectric layers are respectively lined with the trench and define a cavity within the substrate. A pillar structure is disposed within the substrate and adjacent to the trench, wherein the pillar structure has a first width and a second width less than the first width, wherein the first width is aligned with the front surface of the substrate and the second width is aligned with a first point disposed below the front surface.

[0004] According to an embodiment of the present disclosure, a semiconductor structure includes a substrate, a trench capacitor, and a pillar structure. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers overlying the front side surface of the substrate, wherein the plurality of capacitor electrode layers and the plurality of capacitor dielectric layers define a first trench segment and a second trench segment protruding into the substrate, and further define a first cavity and a second cavity, wherein the first cavity and the second cavity are respectively recessed into the substrate at the first trench segment and the second trench segment. The pillar structure is laterally disposed between the first trench segment and the second trench segment, wherein the width of the pillar structure continuously decreases in a first direction, and the first direction is from the front side surface toward the bottom surface of the first trench segment and the second trench segment.

[0005] According to an embodiment of the present disclosure, a method for forming a trench capacitor includes: performing a first patterning process on a front side surface of a substrate to define an upper portion of a trench and an upper portion of a pillar structure, wherein the first patterning process is performed to reduce a width of the pillar structure from the front side surface to a first point below the front side surface; performing a second patterning process on the substrate to expand the trench and increase a height of the pillar structure; and forming a plurality of capacitor dielectric layers and a plurality of capacitor electrode layers in the trench so that a cavity is defined between a plurality of side walls of an uppermost capacitor dielectric layer, wherein the cavity is disposed in the trench, and wherein the uppermost capacitor dielectric layer seals the cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated circuit (IC) including a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench are shown.

[0008] Figures 2 to 4 Show Figure 1 Cross-sectional views of some alternative embodiments of an IC.

[0009] Figure 5 , Fig. 6A as well as Figure 6B Cross-sectional views of some embodiments of an IC including a plurality of pillar structures disposed within a substrate and a trench capacitor adjacent to each pillar structure are shown.

[0010] Figures 7 to 14 Cross-sectional views of some embodiments of methods of forming an integrated chip (IC) having a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench are shown.

[0011] Fig.15 A flow chart illustrating some embodiments of a method for forming an IC having a trench capacitor disposed within a trench and laterally adjacent to a cavity within the trench.

[0012] Description of Figure Numbers

[0013] 100, 200, 300, 400, 500, 600a, 600b: integrated circuits;

[0014] 101: Column structure;

[0015] 101us: upper surface;

[0016] 102: semiconductor substrate;

[0017] 102f: anterior surface;

[0018] 102ls: lower surface;

[0019] 102t: groove;

[0020] 103: cavity;

[0021] 104: doping region;

[0022] 106: Trench capacitor;

[0023] 106ts: groove section;

[0024] 108: insulator layer;

[0025] 110a, 110b, 110c, 110d: capacitor electrode layers;

[0026] 112a, 112b, 112c, 112d: capacitor dielectric layers;

[0027] 114: top cover dielectric layer;

[0028] 116: etching stop layer;

[0029] 117: Internal connection structure;

[0030] 118: via hole;

[0031] 120: conductive wire;

[0032] 122: Inner connection dielectric structure;

[0033] 202: First point;

[0034] 204: Second point;

[0035] 206: Third point;

[0036] 402, 404: dielectric layer;

[0037] 406: interlayer dielectric layer;

[0038] 408: dielectric protection layer;

[0039] 700, 800, 900, 1000, 1100, 1200, 1300, 1400: cross-sectional views;

[0040] 702: Mask layer stacking;

[0041] 704, 706: hard mask layer;

[0042] 708: upper dielectric layer;

[0043] 710: Anti-reflective coating;

[0044] 712: Photoresist;

[0045] 715, 904: horizontal line;

[0046] 716, 718, 902: angle;

[0047] 802: side wall protection layer;

[0048] 1202: contact opening;

[0049] 1500: Methods;

[0050] 1502, 1504, 1506, 1508, 1510, 1512, 1514: action;

[0051] h1, h2, h3: height;

[0052] L1, L2, L3: length;

[0053] t1, t2, t3: thickness;

[0054] w1, w2: width. DETAILED DESCRIPTION

[0055] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the present disclosure may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0056] Additionally, for ease of description herein, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted likewise accordingly.

[0057] The integrated circuit may include a plurality of semiconductor devices, such as trench capacitors disposed in and / or above a semiconductor substrate. For example, the substrate may include a plurality of sidewalls defining a plurality of trenches. The semiconductor substrate further includes a plurality of substrate pillars, such that the plurality of substrate pillars laterally separate adjacent trenches from each other. The trench capacitor includes a plurality of electrodes and one or more dielectric layers, wherein the plurality of electrodes and the dielectric layers are alternately stacked in the plurality of trenches. Each electrode extends continuously across each trench in the plurality of trenches and extends continuously along the plurality of sidewalls of the substrate pillars. The capacitance density of the trench capacitor may be increased by increasing the number of trenches disposed in the substrate. This is because the surface area between adjacent electrodes increases as the number of trenches increases.

[0058] One difficulty of trench capacitors is the physical stress in the semiconductor substrate as the number of trenches increases. For example, during the manufacture of trench capacitors, an etching process is performed on the semiconductor substrate to define a plurality of substrate pillars and a plurality of trenches. The etching process is configured so that the plurality of substrate pillars respectively include substantially vertical opposing sidewalls. A deposition process is performed to define a plurality of electrodes and dielectric layers within the trenches so that the electrodes and dielectric layers completely fill each trench. This is partly due to the conformity of the electrodes and dielectric layers to the substantially vertical opposing sidewalls of the substrate pillars. However, during the manufacturing process and / or during operation of the trench capacitors, the electrodes and dielectric layers are exposed to heat (e.g., due to a baking process and / or heat generated by high voltage and / or current). The heat causes the dielectric layer and / or the electrodes to undergo thermal expansion. Since the trenches are completely filled, the expansion of the above-mentioned layers exerts forces on the surface of the substrate defining the trenches. This may cause the semiconductor substrate to warp, break and / or crack, thereby causing device failure. As the trench density increases (e.g., due to smaller process nodes), it is expected that the aforementioned problems will become more prominent.

[0059] Accordingly, various embodiments of the present disclosure relate to a trench capacitor having high capacitance density and low substrate warpage and an associated method for forming the trench capacitor. For example, the method for forming the trench capacitor includes performing an etching process on the front side surface of a semiconductor substrate to define a plurality of substrate pillars and a plurality of grooves. The etching process is configured so that the width of each substrate pillar continuously decreases from the front side surface of the semiconductor substrate to a first point below the front side surface. In addition, the width of each substrate pillar may continuously increase from the first point to a second point, the second point being vertically located below the first point. Subsequently, multiple deposition processes (e.g., atomic layer deposition (ALD) processes) are performed to define multiple electrodes and dielectric layers along multiple sidewalls of the substrate pillar structure and within multiple grooves. With the aid of the profile of the substrate pillar, after performing the multiple deposition processes, a cavity may exist within each groove. This is because the electrode and the dielectric layer are conformal to the sidewalls of the substrate pillar. The presence of the voids within each groove provides space for the electrode and the dielectric layer to expand when exposed to heat. This alleviates the forces applied to the semiconductor substrate due to the above-mentioned layers undergoing thermal expansion, thereby reducing warping, cracking and / or splitting of the semiconductor substrate.

[0060] Figure 1 A cross-sectional view of some embodiments of an integrated circuit (IC) 100 having a trench capacitor 106 disposed within a semiconductor substrate 102 is shown.

[0061] In some embodiments, the IC 100 has an interconnect structure 117 overlying a semiconductor substrate 102. The semiconductor substrate 102 includes a doped region 104. In some embodiments, the doped region 104 may be, for example, of a first doping type (e.g., p-type) or include the first doping type. A trench capacitor 106 overlies the semiconductor substrate 102 and has a plurality of trench segments 106ts that fill a plurality of trenches 102t defined by a plurality of sidewalls of the semiconductor substrate 102. The trench segments 106ts may be deposited within the doped region 104 such that the doped region 104 is configured to electrically isolate the trench capacitor 106 from other devices disposed within and / or on the semiconductor substrate 102. The semiconductor substrate 102 includes a pillar structure 101 that is laterally defined between the plurality of trench segments 106ts of the trench capacitor 106. The insulator layer 108 extends along the front side surface 102 f of the semiconductor substrate 102 and along a plurality of sidewalls of the semiconductor substrate 102 that define the plurality of trenches 102 t and the pillar structures 101 .

[0062] In some embodiments, the interconnect structure 117 includes a plurality of vias 118 and a plurality of conductive lines 120 disposed within the interconnect dielectric structure 122. The vias 118 and the conductive lines 120 are configured to electrically couple a plurality of semiconductor devices disposed within the IC 100 together. In addition, an etch stop layer 116 is disposed along the upper surface of the trench capacitor 106. A top dielectric layer 114 is disposed between the trench capacitor 106 and the etch stop layer 116.

[0063] In some embodiments, the trench capacitor 106 includes a plurality of capacitor electrode layers (capacitor electrode layers 110a to capacitor electrode layers 110d) and a plurality of capacitor dielectric layers (capacitor dielectric layers 112a to capacitor dielectric layers 112d) alternately disposed between the capacitor electrode layers 110a to capacitor electrode layers 110d. In some embodiments, the capacitor electrode layer 110a and the capacitor electrode layer 110c are directly electrically coupled together through the overlying conductive lines 120 and vias 118, thereby defining a first capacitor electrode. In other embodiments, the capacitor electrode layer 110b and the capacitor electrode layer 110d are directly electrically coupled together through the overlying conductive lines 120 and vias 118, thereby defining a second capacitor electrode. By means of a first electrode and a second electrode each having more than one capacitor electrode layer, the capacitance density of the trench capacitor 106 can be increased. For example, the capacitance (C) (in farads) of the trench capacitor 106 is defined as: where A is the overlapping area between the first electrode and the second electrode; ε i is the relative static permittivity of the capacitor dielectric layers 112a to 112d between the first electrode and the second electrode; ε0 is the electric constant (ε0 ≈ 8.854×10 -12 F m -1 ); and d is the distance separating the first electrode and the second electrode. Thus, in some embodiments, by increasing the overlapping area (A) between the first electrode and the second electrode, the capacitance (C) of the trench capacitor 106 can be increased. In other embodiments, in order to increase the overlapping area (A) between the first electrode and the second electrode, the number of trench segments 106ts can be increased.

[0064] In some embodiments, the pillar structure 101 has a first width w1 aligned with the front side surface 102f of the semiconductor substrate 102, and further has a second width w2 vertically disposed at a first point (position), the first point being below the front side surface 102f. The first width w1 is greater than the second width w2. In other embodiments, the width of the pillar structure 101 continuously decreases from the front side surface 102f of the semiconductor substrate 102 to the first point. This in part ensures that the cavity 103 will exist in each of the plurality of trenches 102t. For example, during the manufacture of the trench capacitor 106, the capacitor electrode layers 110a to 110d and the capacitor dielectric layers 112a to 112d (e.g., by one or more ALD processes) are deposited so that they will conform to the shape of the pillar structure 101. Since the first width w1 of the pillar structure 101 is greater than the second width w2 of the pillar structure 101 , the cavity 103 will exist in each trench 102 t after depositing the capacitor electrode layers 110 a to 110 d and the capacitor dielectric layers 112 a to 112 d .

[0065] In some embodiments, during operation and / or manufacturing of the IC 100, multiple layers of the trench capacitor 106 are exposed to high heat. The high heat causes the capacitor electrode layers 110a to 110d and the capacitor dielectric layers 112a to 112d to thermally expand, so that the layers may expand into the cavity 103. This partially alleviates the forces applied to the semiconductor substrate 102 due to the expansion of the capacitor electrode layers 110a to 110d and the capacitor dielectric layers 112a to 112d. For example, in various embodiments, the capacitor electrode layers 110a to 110d and the capacitor dielectric layers 112a to 112d completely fill each trench 102t, so that the cavity 103 (not shown) is omitted. In such embodiments, the expansion of the layers of the trench capacitor 106 applies forces to the surface of the semiconductor substrate 102, which may cause the semiconductor substrate 102 to warp and / or crack. Therefore, in some embodiments according to the present disclosure, capacitor electrode layers 110a to 110d and capacitor dielectric layers 112a to 112d may be formed in such a manner that a cavity 103 exists in each trench 102t by virtue of the profile of the pillar structure 101. The capacitor electrode layers 110a to 110d and the capacitor dielectric layers 112a to 112d may expand into the cavity 103 when undergoing thermal expansion, thereby alleviating warping, cracking, and / or fracturing of the semiconductor substrate 102. This partially increases the number of trenches 102t that may be formed within the semiconductor substrate 102, thereby increasing the capacitor density of the trench capacitor 106 while reducing substrate warping.

[0066] In some embodiments, the first width w1 of the pillar structure 101 is in the range of about 0.1 microns to 0.2 microns. In other embodiments, if the first width w1 is less than about 0.1 microns, the pillar structure 101 is too thin so that it may be destroyed by the force applied by the multiple layers of the trench capacitor 106. In still other embodiments, if the first width w1 is greater than about 0.2 microns, the number of trenches 102t that can be formed in the semiconductor substrate 102 is reduced and / or the opening of each trench 102t is too small to facilitate the proper deposition of the multiple layers of the trench capacitor 106 in the trench 102t. In various embodiments, the second width w2 of the pillar structure 101 is in the range of about 0.07 microns to 0.17 microns. In other embodiments, if the second width w2 is less than about 0.07, the pillar structure 101 is too thin so that it may be destroyed by the force applied by the multiple layers of the trench capacitor 106. In still other embodiments, if the second width w2 is greater than about 0.17, the size of the cavity 103 may be reduced. In such embodiments, the reduction in the size of the cavity 103 will increase the stress applied to the semiconductor substrate 102 due to the expansion of the capacitor electrode layer 110a to the capacitor electrode layer 110d and the capacitor dielectric layer 112a to the capacitor dielectric layer 112d, thereby causing warping and / or cracking of the semiconductor substrate 102. In various embodiments, the first width w1 is greater than the second width w2. In other embodiments, the difference between the first width w1 and the second width w2 (e.g., w1-w2) is greater than about 30 nanometers. In some embodiments, if the difference between the first width w1 and the second width w2 is less than about 30 nanometers, the size of the cavity 103 may be reduced, thereby causing warping and / or cracking of the semiconductor substrate 102.

[0067] Figure 2 Show according to Figure 1 Some embodiments of a cross-sectional view of an integrated circuit (IC) 200 of some alternative embodiments of the IC 100 are shown.

[0068] The IC 100 includes an interconnect structure 117 overlying a front side surface 102f of a semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 may be, for example, or include a bulk substrate (e.g., bulk silicon), a silicon-on-insulator (SOI) substrate, or other suitable substrate, and / or may include a first doping type (e.g., p-type). The doped region 104 is disposed in the semiconductor substrate 102 and may include the first doping type having a higher doping concentration than the semiconductor substrate 102. The interconnect structure 117 includes an interconnect dielectric structure 122, a plurality of vias 118, and a plurality of conductive lines 120. The interconnect dielectric structure 122 may, for example, include one or more inter-level dielectric (ILD) layers. The one or more ILD layers may, for example, be or include an oxide such as silicon dioxide, a low dielectric constant (k) dielectric material, an ultra-low k dielectric material, any combination of the foregoing, or other suitable dielectric materials. The plurality of vias 118 and the plurality of conductive lines 120 are configured to electrically couple a plurality of semiconductor devices disposed above and / or within the semiconductor substrate 102. In other embodiments, the vias 118 and the conductive lines 120 may be or include, for example, tungsten, copper, aluminum, titanium nitride, tantalum nitride, any combination of the foregoing, or the like.

[0069] The semiconductor substrate 102 includes a plurality of sidewalls defining one or more trenches 102t. The trenches 102t extend continuously from the front side surface 102f of the semiconductor substrate 102 to a point below the front side surface 102f. In another embodiment, a trench capacitor 106 is disposed above the front side surface 102f and at least partially fills the trench 102t. In some embodiments, the trench capacitor 106 includes a plurality of capacitor electrode layers (capacitor electrode layer 110a to capacitor electrode layer 110d) and a plurality of capacitor dielectric layers (capacitor dielectric layer 112a to capacitor dielectric layer 112d). An insulator layer 108 is disposed between the semiconductor substrate 102 and the first capacitor electrode layer 110a, such that the insulator layer 108 can electrically isolate the trench capacitor from the semiconductor substrate 102 and / or devices disposed in / above the semiconductor substrate 102. In some embodiments, the insulator layer 108 can be, for example, or include an oxide such as silicon dioxide or other suitable dielectric material. In some embodiments, the capacitor dielectric layers 112a to 112d are alternately stacked between the capacitor electrode layers 110a to 110d, so that adjacent capacitor electrode layers 110a to 110d are separated from each other by one of the capacitor dielectric layers 112a to 112d. In other embodiments, the thickness of each of the capacitor dielectric layers 112a to 112d is greater than the thickness of each of the capacitor electrode layers 110a to 110d. In some embodiments, the capacitor electrode layers 110a to 110d may, for example, be or include titanium nitride, tantalum nitride, or the like, respectively. In other embodiments, the capacitor dielectric layers 112a to 112d may, for example, be or include a high-k dielectric material or some other suitable dielectric material, respectively. The high-k dielectric material may, for example, be or include hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, titanium oxide, or some other suitable high-k dielectric material, or any combination of the foregoing. In yet other embodiments, the capacitor electrode layers 110a to 110d and / or the capacitor dielectric layers 112a to 112d may extend into the trenches 102t along the front surface 102f, respectively, such that the above layers line each trench 102t.

[0070] The trench capacitor 106 has a plurality of trench segments 106ts filling the corresponding trenches 102t. The trench segments 106ts of the trench capacitor 106 are conformal to the plurality of sidewalls of the semiconductor substrate 102 defining the pillar structure 101. In further embodiments, the capping dielectric layer 114 extends continuously along the upper surface of the uppermost capacitor dielectric layer 112d. The capping dielectric layer 114 may, for example, be configured to seal each cavity 103 within the corresponding trench 102t to a first gas pressure such that the cavity 103 is defined between the plurality of inner sidewalls of the capping dielectric layer 114. In some embodiments, the capping dielectric layer 114 may, for example, be or include an oxide such as silicon dioxide, silicon oxynitride, silicon oxycarbide, or other suitable dielectric material. In further embodiments, an etch stop layer 116 is disposed along the upper surface of the trench capacitor 106. In some embodiments, the etch stop layer 116 may be, for example, or include, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, any combination thereof, or other suitable dielectric materials.

[0071] The pillar structure 101 has a first width w1 vertically aligned with the front side surface 102f of the semiconductor substrate 102, and further has a second width w2, which is disposed at a first point 202 vertically offset from the front side surface 102f. In some embodiments, the first width w1 is greater than the second width w2. In addition, the width of the pillar structure 101 may be continuously reduced from the front side surface 102f of the semiconductor substrate 102 to the first point 202. In other embodiments, the first height h1 of the pillar structure 101 is defined as from the front side surface 102f of the semiconductor substrate 102 to the first point 202. In yet other embodiments, the first height h1 is, for example, greater than 0.05 microns or in the range of about 0.05 microns to 4 microns. In other embodiments, if, for example, the first height h1 is less than 0.05 microns, the size of the cavity 103 may be reduced, which may increase the amount of stress induced on the semiconductor substrate 102. In yet other embodiments, the width of the pillar structure 101 decreases continuously across the first height h1 in a direction away from the front side surface 102f of the semiconductor substrate 102. In some embodiments, the first width w1 of the pillar structure 101 is in a range of about 0.1 microns to 0.2 microns. In various embodiments, the second width w2 of the pillar structure 101 is in a range of about 0.07 microns to 0.17 microns. In some embodiments, the first length L1 of the trench 102t is in a range of about 0.3 microns to 0.4 microns. The first length L1 is aligned with the front side surface 102f of the semiconductor substrate 102 and may define an opening of the trench 102t. In some embodiments, if the first length L1 is less than about 0.3 microns, the opening of the trench 102t is too small so that multiple layers of the trench capacitor 106 may be improperly deposited in the trench 102t. In other embodiments, if the first length L1 is greater than about 0.4 microns, the number of trenches 102t that may be formed in the semiconductor substrate 102 is reduced and / or the first width w1 is reduced, so that the pillar structure 101 is too thin and may be destroyed by the force applied by the multiple layers of the trench capacitor 106. In some embodiments, the trench pitch of the plurality of trenches 102t is equal to the sum of the first width w1 of the pillar structure 101 and the first length L1 of the trench 102t (e.g., w1+L1). In some embodiments, the trench pitch is in the range of about 0.4 microns to 0.6 microns. In other embodiments, if the trench pitch is less than about 0.4 microns, the opening of the trench 102t may be too small so that the multiple layers of the trench capacitor may not properly fill the trench 102t. In yet other embodiments, if the trench pitch is greater than about 0.6 microns, the capacitance density of the trench capacitor 106 may be reduced.

[0072] The second height h2 of the pillar structure 101 is defined from the front side surface 102f of the semiconductor substrate 102 to the second point 204. The second point 204 is vertically disposed below the first point 202 in a direction away from the front side surface 102f. In some embodiments, the second height h2 is, for example, about 6 microns, or is in a range of about 0.595 microns to 7.65 microns. In some embodiments, the width of the pillar structure 101 continuously increases from the first point 202 to the second point 204. The third height h3 of the pillar structure 101 is defined from the front side surface 102f of the semiconductor substrate 102 to the third point 206. The third point 206 may be aligned with the lower surface 102ls of the semiconductor substrate 102. In some embodiments, the lower surface 102ls of the semiconductor substrate 102 defines the bottom surface of the trench 102t and / or is aligned with the bottom surface of the trench segment 106ts. In some embodiments, the third height h3 may be about 7 microns, about 8.5 microns, or in a range of about 6.5 microns to 8.5 microns. The second length L2 of the trench 102t is aligned with the second point 204. In some embodiments, the second length L2 is in the range of about 0.21 microns to 0.36 microns. In other embodiments, the second length L2 is in the range of about 70% to 90% of the first length L1 (e.g., in the range of about 0.7×L1 to 0.9×L1). The third length L3 of the trench 102t is aligned with the third point 206 and / or with the lower surface 102ls of the semiconductor substrate 102. In some embodiments, the third length L3 is in the range of about 0.3 microns to 0.4 microns or in the range of about 0.24 microns to 0.4 microns. In other embodiments, the third length L3 is in the range of about 80% to 100% of the first length L1 (e.g., in the range of about 0.8×L1 to L1). Therefore, in some embodiments, the third length L3 is substantially equal to the first length L1. In some embodiments, if the third length L3 is less than about 0.8×L1, the size of the cavity 103 is reduced, which may increase the amount of stress induced on the semiconductor substrate 102. In other embodiments, if the third length L3 is greater than the length L1, the multiple layers of the trench capacitor 106 may not be properly disposed along the corner of the trench 102t. This may, in part, cause delamination between the capacitor dielectric layer 112a to the capacitor dielectric layer 112d and / or the capacitor electrode layer 110a to the capacitor electrode layer 110d.

[0073] Figure 3 A cross-sectional view of some embodiments of an IC 300 including a trench capacitor 106 disposed within a semiconductor substrate 102 is shown.

[0074] The IC 300 includes an interconnect structure 117 overlying a front side surface 102f of a semiconductor substrate 102. The semiconductor substrate 102 includes a plurality of sidewalls defining trenches 102t. In addition, the semiconductor substrate 102 includes a plurality of pillar structures 101 disposed between the trenches 102t. The pillar structures 101 have a first width w1 aligned with the front side surface 102f of the semiconductor substrate 102 and a second width w2 disposed at a first point 202. The first point 202 is vertically offset from the front side surface 102f by a non-zero distance in a direction away from the front side surface 102f. In some embodiments, the pillar structures 101 have a curved sidewall section that extends continuously from the front side surface 102f to the first point 202. In other embodiments, the width of the pillar structures 101 continuously decreases from the front side surface 102f to the first point 202. In some embodiments, capacitor dielectric layers 112a-112b and capacitor electrode layers 110a-110b conform to the curved sidewall segments of pillar structures 101. In still other embodiments, a lower surface 1021s of semiconductor substrate 102 defining a bottom surface of trench 102t is curved.

[0075] Figure 4 Show according to Figure 2 Cross-sectional views of some embodiments of IC 400 to some alternative embodiments of IC 200 .

[0076] The first dielectric layer 402 extends over the upper surface of the trench capacitor 106 and the etch stop layer 116. The second dielectric layer 404 overlies the first dielectric layer 402. In some embodiments, the first dielectric layer 402 and / or the second dielectric layer 404 may be, for example, each or include an oxide such as silicon dioxide, undoped silicon glass, any combination of the foregoing, or other suitable dielectric materials. In some embodiments, the interconnect dielectric structure 122 includes a plurality of interlayer dielectric (ILD) layers 406 and a plurality of dielectric cap layers 408. The plurality of dielectric cap layers 408 are alternately stacked between adjacent layers of the plurality of ILD layers 406. In other embodiments, the ILD layers 406 may be, for example, each or include silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, any combination of the foregoing, or other suitable dielectric materials. In yet other embodiments, the dielectric protection layer 408 may be or include, for example, silicon nitride, silicon carbide, silicon oxynitride or other suitable dielectric materials, and / or may be configured as an etch stop layer when forming the interconnect structure 117 .

[0077] Figure 5 Shown corresponding to Figure 2 Cross-sectional views of some embodiments of IC 500 to some alternative embodiments of IC 200 .

[0078] like Figure 5As shown in FIG. 1 , the semiconductor substrate 102 includes a plurality of five trenches 102t, wherein the trench capacitor 106 includes a plurality of five trench segments 106ts filling the corresponding trenches 102t. It should be understood that Figure 5 This is merely an example of a semiconductor substrate 102 that may include any number of trenches 102t. By increasing the number of trenches 102t disposed within the semiconductor substrate 102, the capacitor density of the trench capacitors 106 increases.

[0079] Fig. 6A Shown corresponding to Figure 2 Cross-sectional views of some embodiments of some alternative embodiments of IC 200 and IC 600a.

[0080] like Fig. 6A As shown in , the insulator layer 108 extends continuously along the front side surface 102f of the semiconductor substrate 102 and along multiple side walls of the semiconductor substrate 102 defining the trench 102t. Therefore, the insulator layer 108 is disposed between the trench capacitor 106 and the semiconductor substrate 102, and can be configured to electrically isolate the trench capacitor 106 from other devices disposed in and / or above the semiconductor substrate 102. In addition, the insulator layer 108 extends continuously along multiple side walls and the upper surface of each pillar structure 101. The first width w1 of the pillar structure 101 is aligned with the front side surface 102f of the semiconductor substrate 102 and is greater than the second width w2 of the pillar structure 101. The second width w2 is aligned with the first point 202, which is vertically disposed below the front side surface 102f. In some embodiments, the width of the pillar structure 101 continuously decreases from the front side surface 102f to the first point 202. In addition, by virtue of the profile of the pillar structure 101, the first thickness t1 of the insulator layer 108 is less than the second thickness t2 of the insulator layer 108. In further embodiments, the first thickness t1 may be, for example, about 250 angstroms, or in the range of about 250 angstroms to 500 angstroms. In some embodiments, the second thickness t2 is disposed below the first point 202, and may be, for example, about 450 angstroms, or in the range of about 450 angstroms to 900 angstroms. In further embodiments, the thickness of the insulator layer 108 may continuously increase from the front side surface 102f of the semiconductor substrate 102 to the first point 202. This facilitates, in part, the formation of the cavity 103 within each trench 102t, so that the cavity 103 abuts against multiple layers of the trench capacitor 106. In some embodiments, the upper surface 101us of the pillar structure 101 is curved. In further embodiments, the third thickness t3 of the insulator layer 108 is disposed along the upper surface 101us of the pillar structure 101. In some embodiments, the third thickness t3 is less than the second thickness t2.

[0081] Figure 6B Shown corresponding to Fig. 6ACross-sectional views of some embodiments of some alternative embodiments of IC 600a and some embodiments of IC 600b.

[0082] like Figure 6B As shown in , the cap dielectric layer 114 extends continuously along the upper surface of the uppermost capacitor dielectric layer 112 d. Therefore, in some embodiments, the cap dielectric layer 114 can seal each cavity 103 within the corresponding trench 102 t to the first gas pressure, so that the cavity 103 is defined between multiple inner sidewalls of the cap dielectric layer 114.

[0083] Figures 7 to 14 Cross-sectional views 700 through 1400 illustrate some embodiments of a method of forming an integrated circuit (IC) having a trench capacitor disposed in a trench and having a plurality of sidewalls defining a cavity according to the present disclosure. Figures 7 to 14 700 to 1400, but it should be understood that Figures 7 to 14 The structure shown in is not limited to the method and can actually be independent of the method. Figures 7 to 14 Described as a series of actions, it should be understood that these actions are not limited to the order of actions, can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be completely or partially omitted.

[0084] like Figure 7As shown in the cross-sectional view 700 of FIG. 1 , a semiconductor substrate 102 is provided and then patterned to define at least a portion of a trench 102t and a pillar structure 101 within the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or other suitable substrate materials. Before performing the patterning process, a mask layer stack 702 is formed over a front side surface 102f of the semiconductor substrate 102. In some embodiments, the mask layer stack 702 includes a first hard mask layer 704, a second hard mask layer 706, an upper dielectric layer 708, an anti-reflection coating (ARC) layer 710, and a photoresist 712. In some embodiments, the first hard mask layer 704 may be deposited along the front side surface 102f of the semiconductor substrate 102 (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). Subsequently, after the first hard mask layer 704 is deposited, an ion implantation process may be performed on the semiconductor substrate 102 through the first hard mask layer 704, so that the semiconductor substrate 102 includes a first doping type (e.g., p-type). In yet other embodiments, other ion implantation processes may be performed to define other doped regions (not shown) within the semiconductor substrate 102 (e.g., Figure 1 After performing the ion implantation process, a second hard mask layer 706, an upper dielectric layer 708, an ARC layer 710, and a photoresist 712 are deposited (e.g., by CVD, PVD, ALD, etc., respectively) over the first hard mask layer 704. In some embodiments, the pillar structure 101 may be or include, for example, silicon, intrinsic silicon, doped silicon, or other suitable materials.

[0085] In addition, if Figure 7As shown in , the mask layer stack 702 is patterned to define an opening within the mask layer stack 702 and expose the front side surface 102f of the semiconductor substrate 102. Subsequently, the semiconductor substrate 102 is patterned according to the mask layer stack 702 to define at least a portion of the trench 102t within the semiconductor substrate 102. In some embodiments, the patterning process includes performing one or more dry etching processes. In addition, the power, time, pressure, and angle of the one or more dry etching processes are configured to define the first width w1, the second width w2, the first height h1, and the second height h2 of the column structure 101. In some embodiments, the first width w1 of the column structure 101 is in the range of about 0.1 microns to 0.2 microns. In various embodiments, the second width w2 of the column structure 101 is in the range of about 0.07 microns to 0.17 microns. In yet other embodiments, the first height h1 is, for example, greater than 0.05 microns or in the range of about 0.05 microns to 4 microns. In some embodiments, the second height h2 is, for example, about 6 microns, or in a range of about 0.595 microns to 7.65 microns. In yet other embodiments, one or more dry etching processes are performed to define a second length L2 of the first length L1 of each trench 102t. In some embodiments, the first length L1 of the trench 102t is in a range of about 0.3 microns to 0.4 microns. In some embodiments, the second length L2 is in a range of about 0.21 microns to 0.36 microns. In other embodiments, the second length L2 is in a range of about 70% to 90% of the first length L1 (e.g., in a range of about 0.7×L1 to 0.9×L1).

[0086] A first angle 716 is defined by a horizontal line aligned with the front side surface 102f of the semiconductor substrate 102 and the first sidewall of the pillar structure 101. In various embodiments, the first angle 716 is in a range of about 92° to 95° or other suitable values. A second angle 718 is defined by a horizontal line 715 aligned with the first point 202 and the second sidewall of the pillar structure 101. In some embodiments, the second angle 718 is in a range of about 88° to 90° or other suitable values. The first point 202 is disposed below the front side surface 102f of the semiconductor substrate 102. In some embodiments, the first height h1 and the second height h2 correspond to the heights of the trench 102t.

[0087] In some embodiments, the first hard mask layer 704 may be, for example, or include an oxide such as silicon dioxide or other suitable dielectric materials. The second hard mask layer 706 may be, for example, or include amorphous carbon or other suitable dielectric materials. The upper dielectric layer 708 may be, for example, or include silicon oxynitride, silicon oxycarbide, or the like.

[0088] like Figure 8As shown in the cross-sectional view 800 of FIG. 1 , a sidewall protection layer 802 is formed along a plurality of sidewalls of the semiconductor substrate 102 defining the trench 102t. In some embodiments, the sidewall protection layer 802 may be deposited or grown, for example, by thermal oxidation, CVD, PVD, or other suitable deposition or growth processes. In other embodiments, the sidewall protection layer 802 may be, for example, or include an oxide such as silicon dioxide or other suitable dielectric material.

[0089] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , the semiconductor substrate 102 is patterned to expand the trench 102t and further define the pillar structure 101. In some embodiments, the patterning process may include a mask layer stack ( Figure 8 The mask layer stack 702 of FIG. 1 exposes the semiconductor substrate 102 to one or more etchants. In another embodiment, Fig. 9 The patterning process can be included in the Figure 7 In addition, when performing one or more dry etchings, the one or more dry etchings are performed at a lower pressure. Fig. 9 After the patterning process, a removal process is performed to remove the mask layer stack ( Figure 8 In addition, Fig. 9 The power, time, pressure, and angle of one or more dry etching processes are configured to define a third length L3 of the trench 102t and a third height h3 of the pillar structure 101 and / or the trench 102t. In some embodiments, the third length L3 is in a range of about 0.3 microns to 0.4 microns or in a range of about 0.24 microns to 0.4 microns. In other embodiments, the third length L3 is in a range of about 80% to 100% of the first length L1 (for example, in a range of about 0.8×L1 to L1). Therefore, in some embodiments, the third length L3 is substantially equal to the first length L1. In other embodiments, the third length L3 is aligned with the lower surface 102ls of the semiconductor substrate 102. In some embodiments, the width of the pillar structure 101 continuously decreases from the second point 204 to the third point 206.

[0090] The third angle 902 is defined between the sidewall of the pillar structure 101 and the substantially horizontal line 904. In some embodiments, the substantially horizontal line 904 is vertically aligned with the second point 204 and is parallel to the front side surface 102f of the semiconductor substrate 102. In some embodiments, the third angle 902 is in the range of about 90° to 93°. The third height h3 of the pillar structure 101 is defined from the front side surface 102f of the semiconductor substrate 102 to the third point 206. The third point 206 may be aligned with the lower surface 102ls of the semiconductor substrate 102. In some embodiments, the third height h3 may be about 7 microns, about 8.5 microns, or in the range of about 6.5 microns to 8.5 microns. In yet other embodiments, when performing Fig. 9 After one or more dry etchings, a removal process (such as wet etching) may be performed to remove the sidewall protection layer 802. In another embodiment, the sidewall protection layer 802 may be Fig. 9 The sidewall protection layer 802 can be retained in place during the patterning process, so that the sidewalls of the semiconductor substrate 102 defining the trench 102t and / or the upper portion of the pillar structure 101 (e.g., the area between the front side surface 102f and the second point 204) can be prevented from being damaged. Figure 7 The dimensions defined by the patterning process (eg, the first width w1, the second width w2, the first length L1, the first height h1, the second height h2 and / or the second length L2) are Fig. 9 In another embodiment, the patterning process of Figure 7 and Fig. 9 The patterning process is performed so that the trenches 102t each have a high aspect ratio (eg, an aspect ratio greater than about 20:1).

[0091] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , an insulator layer 108 is formed along the front side surface 102f of the semiconductor substrate 102 and the sidewalls of the semiconductor substrate 102 defining the trench 102t. In some embodiments, the insulator layer 108 may be, for example, or include an oxide such as silicon dioxide or other suitable dielectric material, and / or may be formed to have a thickness greater than 250 angstroms or in the range of about 250 angstroms to 900 angstroms or other suitable values. In other embodiments, the insulator layer 108 may be, for example, deposited by, for example, sputtering, CVD, PVD, thermal oxidation or other suitable growth or deposition processes. In some embodiments, the insulator layer 108 may be formed only by thermal oxidation. Subsequently, a plurality of capacitor electrode layers 110a to 110d and a plurality of capacitor dielectric layers 112a to 112d are formed in the trench 102t of the semiconductor substrate 102. The above-mentioned layers are formed so that they conform to the sidewalls of the pillar structure 101 and the sidewalls of the semiconductor substrate 102 that define the trench 102t, thereby defining a cavity 103 within each trench 102t. The cavity 103 is defined between the sidewalls of the uppermost capacitor dielectric layer 112d. In addition, a cap dielectric layer 114 is formed above the uppermost capacitor dielectric layer 112d. In some embodiments, the capacitor electrode layer 110a to the capacitor electrode layer 110d and the capacitor dielectric layer 112a to the capacitor dielectric layer 112d can be formed, for example, by ALD, CVD, PVD or other suitable deposition or growth processes, respectively. In other embodiments, the above-mentioned layers can be deposited only by ALD, so an ALD process can be performed to deposit each layer. In other embodiments, the cap dielectric layer 114 can be formed, for example, by ALD, CVD or other suitable deposition or growth processes.

[0092] During subsequent processing steps, the capacitor electrode layers 110a to 110d and / or the capacitor dielectric layers 112a to 112d may be exposed to high heat (e.g., by a thermal annealing process). The high heat may cause the capacitor electrode layers 110a to 110d and the capacitor dielectric layers 112a to 112d to thermally expand, so that the layers may expand into the cavity 103. This partially relieves the force applied to the semiconductor substrate 102 and / or the pillar structure 101 when the capacitor electrode layers 110a to 110d and the capacitor dielectric layers 112a to 112d expand. Therefore, cracking, deformation, and / or breakage of the semiconductor substrate 102 and / or the pillar structure 101 may be reduced.

[0093] In other embodiments, the capping dielectric layer 114 is formed such that it extends within each trench 102t, thereby sealing the cavity 103 with the first gas pressure, for example, see Figure 2 and Figure 6B Thus, the capping dielectric layer 104 may extend continuously along the upper surface of the uppermost capacitor dielectric layer 112 d . In such embodiments, each cavity 103 is defined between a plurality of inner sidewalls of the capping dielectric layer 114 .

[0094] like Fig.11 As shown in the cross-sectional view 1100 of , the capacitor electrode layers 110a to 110d and / or the capacitor dielectric layers 112a to 112d are patterned, thereby defining the trench capacitor 106. In some embodiments, a process for patterning each capacitor electrode layer 110a to 110d and / or the capacitor dielectric layer 112a to 112d includes: forming a mask layer (not shown) over a target capacitor dielectric layer and / or capacitor dielectric layer; exposing an unmasked area of ​​the target capacitor dielectric layer and / or capacitor dielectric layer to one or more etchants, thereby reducing a width of the target layer; and performing a removal process (e.g., a wet etching process) to remove the mask layer. For example, a first patterning process according to a first mask layer (not shown) may be performed on the first capacitor electrode layer 110a, a second patterning process according to a second mask layer (not shown) may be performed on the second capacitor electrode layer 110b and the first capacitor dielectric layer 112a, and additional patterning processes may be performed for the remaining capacitor layers. In addition, an etch stop layer 116 is formed over the upper surface of the trench capacitor 106. In some embodiments, the etch stop layer 116 may be deposited by CVD, PVD, ALD, or other suitable growth or deposition processes. In some embodiments, the etch stop layer 116 may be, for example, or include silicon nitride, silicon carbide, or other suitable dielectric materials.

[0095] like Fig.12As shown in the cross-sectional view 1200 of , the first dielectric layer 402 is formed over the semiconductor substrate 102 and the second dielectric layer 404 is formed over the first dielectric layer 402. In some embodiments, the first dielectric layer 402 and / or the second dielectric layer 404 may be, for example, respectively or include an oxide such as silicon dioxide, undoped silicon glass, any combination of the foregoing, or other suitable dielectric materials. In addition, an interlayer dielectric (ILD) layer 406 is formed over the second dielectric layer 404. In some embodiments, the ILD layer 406, the first dielectric layer 402, and the second dielectric layer 404 may be, for example, respectively formed by CVD, PVD, thermal oxidation, or other suitable deposition or growth processes. In some embodiments, the ILD layer 406 may be, for example, or include silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, or other suitable dielectric materials. Additionally, the ILD layer 406 , the first dielectric layer 402 , and the second dielectric layer 404 are patterned to define a plurality of contact openings 1202 over the trench capacitors 106 and expose the upper surface of each of the capacitor electrode layers 110 a to 110 d .

[0096] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , the via 118 is formed above the capacitor electrode layer 110 a to the capacitor electrode layer 110 d. In some embodiments, the process for forming the via 118 may include: depositing a conductive material (e.g., copper, aluminum, tungsten, titanium nitride, tantalum nitride, etc.) above the semiconductor substrate 102 (e.g., by CVD, PVD, sputtering, electroplating, electroless plating, etc.), thereby filling the contact opening ( Fig.12 and performing a planarization process (eg, a chemical mechanical planarization (CMP) process) on the conductive material until the upper surface of the ILD layer 406 is reached, thereby defining the via 118.

[0097] If Fig.14 1400 shows that the remaining layers of the interconnect structure 117 are formed above the trench capacitor 106. The interconnect structure 117 includes an interconnect dielectric structure 122, a plurality of conductive lines 120, and a plurality of vias 118. In some embodiments, the interconnect structure 117 includes an ILD layer 406 and a plurality of dielectric protection layers 408. In some embodiments, the ILD layer 406 and / or the dielectric protection layer 408 may be deposited, for example, by CVD, PVD, thermal oxidation, or other suitable deposition or growth processes, respectively. In addition, the conductive line 120 and / or the via 118 may be formed by a single damascene process or a dual damascene process. In yet other embodiments, the conductive line 120 may be, for example, or include tungsten, copper, aluminum, titanium nitride, tantalum nitride, or other suitable conductive materials.

[0098] Fig.15 A method 1500 of forming an integrated circuit (IC) including a trench capacitor disposed in a trench and laterally adjacent to a cavity in the trench according to the present disclosure is shown. Although method 1500 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in a different order than shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0099] At act 1502, a mask layer stack is formed over a frontside surface of a semiconductor substrate. Figure 7 A cross-sectional view 700 corresponding to some embodiments of act 1502 is shown.

[0100] At action 1504, a first patterning process is performed on the semiconductor substrate according to the mask layer stack, thereby defining an upper portion of the pillar structure and an upper portion of an adjacent trench. The pillar structure is laterally disposed between the plurality of trenches. In addition, the width of the pillar structure continuously decreases from the front side surface of the semiconductor substrate to a first point, the first point being disposed below the front side surface. Figure 7 A cross-sectional view 700 corresponding to some embodiments of act 1504 is shown.

[0101] At act 1506 , a sidewall protection layer is formed along sidewalls of the semiconductor substrate defining the post structure and the trench. Figure 8 A cross-sectional view 800 is shown corresponding to some embodiments of act 1506 .

[0102] At act 1508 , a second patterning process is performed on the semiconductor substrate according to the mask layer stack, thereby enlarging the trenches and increasing the height of the pillar structures. Fig. 9 A cross-sectional view 900 corresponding to some embodiments of act 1508 is shown.

[0103] At act 1510, an insulator layer, a plurality of capacitor electrode layers, and a plurality of capacitor dielectric layers are formed over the frontside surface of the semiconductor substrate and within the trenches. Thus, the layers conform to the sidewalls of the pillar structures, thereby defining a cavity in each trench. Fig.10 A cross-sectional diagram 1000 is shown corresponding to some embodiments of act 1510 .

[0104] At act 1512, a patterning process is performed on the capacitor electrode layer and the capacitor dielectric layer, thereby defining a trench capacitor. Fig.11 A cross-sectional view 1100 is shown corresponding to some embodiments of act 1512 .

[0105] At activity 1514, an interconnect structure is formed over the trench capacitor and the frontside surface of the semiconductor substrate. Figure 12 to Figure 14 Cross-sectional views 1200 - 1400 are shown corresponding to some embodiments of act 1514 .

[0106] Accordingly, in some embodiments, the present disclosure relates to an integrated circuit (IC) comprising a pillar structure disposed within a substrate and having a width that continuously decreases from a front side surface of the substrate to a point below the front side surface. A trench capacitor includes a first trench segment and a second trench segment, the first trench segment and the second trench segment being recessed into the substrate and defining a first cavity and a second cavity disposed on opposite sides of the pillar structure.

[0107] In some embodiments, the present application provides an integrated circuit (IC) comprising: a substrate having a plurality of sidewalls defining a trench, wherein the trench extends into a front side surface of the substrate; a trench capacitor comprising a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers, wherein the plurality of capacitor electrode layers and the plurality of capacitor dielectric layers are respectively lined with the trench and define a cavity within the substrate; and a pillar structure disposed within the substrate and adjacent to the trench, wherein the pillar structure has a first width and a second width less than the first width, wherein the first width is aligned with the front side surface of the substrate and the second width is aligned with a first point disposed below the front side surface. In an embodiment, the width of the pillar structure increases continuously from the first point to a second point, wherein the second point is disposed below the first point. In an embodiment, the width of the pillar structure decreases continuously from the second point to a third point, wherein the third point is disposed below the second point, and wherein the third point is aligned with a lower surface of the substrate, wherein the lower surface defines a bottom of the trench. In an embodiment, the pillar structure comprises a first curved sidewall section disposed between the front side surface of the substrate and the first point, wherein the pillar structure comprises a vertical sidewall section disposed below the first curved sidewall section. In an embodiment, the pillar structure includes a second curved sidewall section disposed below the vertical sidewall section. In an embodiment, the plurality of capacitor dielectric layers include an uppermost capacitor dielectric layer, the uppermost capacitor dielectric layer continuously lining the groove and sealing the cavity within the groove. In an embodiment, the integrated circuit further includes an insulator layer, the insulator layer continuously extending from the front side surface of the substrate to the plurality of sidewalls of the substrate defining the groove, wherein the insulator layer is disposed between the trench capacitor and the substrate, wherein the thickness of the insulator layer is respectively greater than the thickness of the plurality of capacitor electrode layers and the plurality of capacitor dielectric layers. In an embodiment, the insulator layer extends continuously along the plurality of sidewalls and the upper surface of the pillar structure. In an embodiment, the insulator layer includes a first dielectric material, and the capacitor dielectric layer includes a second dielectric material different from the first dielectric material.

[0108] In some embodiments, the present application provides a semiconductor structure, comprising: a substrate; a trench capacitor, comprising a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers overlying a front side surface of the substrate, wherein the plurality of capacitor electrode layers and the plurality of capacitor dielectric layers define a first trench section and a second trench section protruding into the substrate, and further define a first cavity and a second cavity, the first cavity and the second cavity being respectively recessed into the substrate at the first trench section and the second trench section; and a pillar structure, laterally disposed between the first trench section and the second trench section, wherein a width of the pillar structure continuously decreases in a first direction, the first direction being from the front side surface toward the bottom surface of the first trench section and the second trench section. In an embodiment, the pillar structure comprises a first inclined sidewall section, a second inclined sidewall section, and a third inclined sidewall section, wherein the second inclined sidewall section is vertically disposed between the first inclined sidewall section and the third inclined sidewall section, wherein the first inclined sidewall section and the third inclined sidewall section are inclined in the same direction, the same direction being opposite to the direction of the angle of the second inclined sidewall section. In an embodiment, the widths of the first cavity and the second cavity continuously increase in the first direction. In an embodiment, the column structure continuously decreases along a first vertical distance in the first direction, wherein a first width of the column structure is greater than the first vertical distance, and wherein the first width is aligned with the front side surface of the substrate. In an embodiment, the semiconductor structure further includes an insulator layer disposed between the substrate and the first trench segment and the second trench segment, wherein the insulator layer extends continuously along a plurality of sidewalls and an upper surface of the column structure, wherein a thickness of the insulator layer continuously increases in the first direction. In an embodiment, the insulator layer includes silicon dioxide, and the plurality of capacitor dielectric layers respectively include high dielectric constant dielectric materials. In an embodiment, a first thickness of the insulator layer disposed along the upper surface of the column structure is less than a second thickness of the insulator layer disposed along the plurality of sidewalls of the column structure. In an embodiment, the column structure has a curved upper surface.

[0109] In some embodiments, the present application provides a method for forming a trench capacitor, the method comprising: performing a first patterning process on a front side surface of a substrate to define an upper portion of a trench and an upper portion of a pillar structure, wherein the first patterning process is performed so that the width of the pillar structure decreases from the front side surface to a first point below the front side surface; performing a second patterning process on the substrate to expand the trench and increase the height of the pillar structure; and forming a plurality of capacitor dielectric layers and a plurality of capacitor electrode layers in the trench so that a cavity is defined between a plurality of sidewalls of the uppermost capacitor dielectric layer, wherein the cavity is disposed in the trench, and wherein the uppermost capacitor dielectric layer seals the cavity. In an embodiment, the method further comprises: forming a sidewall protection layer along a plurality of sidewalls of the substrate defining the trench, wherein the sidewall protection layer is formed after the first patterning process and before the second patterning process. In an embodiment, the second patterning process is performed so that the width of the pillar structure continuously decreases from a second point to a lower surface of the substrate, wherein the second point is disposed vertically below the first point, and the lower surface of the substrate defines a bottom surface of the trench.

[0110] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, comprising: a substrate comprising a plurality of sidewalls defining a trench, wherein the trench extends into a front side surface of the substrate; A trench capacitor comprising a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers, the plurality of capacitor electrode layers and the plurality of capacitor dielectric layers respectively lining the trench and defining a cavity within the substrate; as well as a pillar structure disposed in the substrate and adjacent to the trench, wherein the pillar structure has a first width and a second width less than the first width, wherein the first width is aligned with the front side surface of the substrate and the second width is aligned with a first point disposed below the front side surface, The plurality of capacitor electrode layers and the plurality of capacitor dielectric layers are conformal to sidewalls of the pillar structure. 2 . The integrated circuit of claim 1 , wherein a width of the pillar structure increases continuously from the first point to a second point, wherein the second point is disposed below the first point.

3. The integrated circuit of claim 2, wherein the width of the pillar structure continuously decreases from the second point to a third point, wherein the third point is disposed below the second point, and wherein the third point is aligned with a lower surface of the substrate, the lower surface defining a bottom of the trench. 4 . The integrated circuit of claim 1 , wherein the pillar structure comprises a first curved sidewall segment disposed between the frontside surface of the substrate and the first point, wherein the pillar structure comprises a vertical sidewall segment disposed below the first curved sidewall segment. 5 . The integrated circuit of claim 4 , wherein the pillar structure comprises a second curved sidewall segment disposed below the vertical sidewall segment.

6. The integrated circuit of claim 1, wherein the plurality of capacitor dielectric layers includes an uppermost capacitor dielectric layer that continuously lines the trench and seals the cavity within the trench.

7. The integrated circuit of claim 1 , further comprising: an insulator layer extending continuously from the front side surface of the substrate to the plurality of sidewalls of the substrate defining the trench, wherein the insulator layer is disposed between the trench capacitor and the substrate, wherein a thickness of the insulator layer is greater than a thickness of the plurality of capacitor electrode layers and the plurality of capacitor dielectric layers, respectively. 8 . The integrated circuit of claim 7 , wherein the insulator layer extends continuously along a plurality of sidewalls and an upper surface of the pillar structure.

9. The integrated circuit of claim 7, wherein the insulator layer comprises a first dielectric material and the capacitor dielectric layer comprises a second dielectric material different from the first dielectric material.

10. A semiconductor structure comprising: substrate; A trench capacitor comprising a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers overlying a front side surface of the substrate, wherein the plurality of capacitor electrode layers and the plurality of capacitor dielectric layers define a first trench segment and a second trench segment protruding into the substrate, and define a first cavity and a second cavity, the first cavity and the second cavity being recessed into the substrate at the first trench segment and the second trench segment, respectively; as well as a column structure disposed laterally between the first groove segment and the second groove segment, wherein a width of the column structure continuously decreases in a first direction, the first direction being from the front side surface toward the bottom surfaces of the first groove segment and the second groove segment, The plurality of capacitor electrode layers and the plurality of capacitor dielectric layers are conformal to sidewalls of the pillar structure.

11. A semiconductor structure according to claim 10, wherein the column structure includes a first inclined sidewall segment, a second inclined sidewall segment and a third inclined sidewall segment, wherein the second inclined sidewall segment is vertically arranged between the first inclined sidewall segment and the third inclined sidewall segment, wherein the first inclined sidewall segment and the third inclined sidewall segment are inclined in the same direction, and the same direction is opposite to the direction of the angle of the second inclined sidewall segment. 12 . The semiconductor structure of claim 10 , wherein widths of the first cavity and the second cavity continuously increase in the first direction.

13. The semiconductor structure of claim 10, wherein the pillar structure continuously decreases along a first vertical distance in the first direction, wherein a first width of the pillar structure is greater than the first vertical distance, and wherein the first width is aligned with the front side surface of the substrate.

14. A semiconductor structure according to claim 10, wherein the semiconductor structure further comprises an insulator layer disposed between the substrate and the first trench segment and the second trench segment, wherein the insulator layer extends continuously along multiple sidewalls and an upper surface of the pillar structure, wherein a thickness of the insulator layer continuously increases in the first direction.

15. The semiconductor structure of claim 14, wherein the insulator layer comprises silicon dioxide, and the plurality of capacitor dielectric layers each comprises a high-k dielectric material. 16 . The semiconductor structure of claim 14 , wherein a first thickness of the insulator layer disposed along the upper surface of the pillar structure is smaller than a second thickness of the insulator layer disposed along the plurality of sidewalls of the pillar structure. The semiconductor structure of claim 10 , wherein the pillar structure has a curved upper surface.

18. A method for forming a trench capacitor, the method comprising: performing a first patterning process on the front side surface of the substrate to define an upper portion of the trench and an upper portion of the pillar structure, wherein the first patterning process is performed to reduce a width of the pillar structure from the front side surface to a first point below the front side surface; performing a second patterning process on the substrate to enlarge the trench and increase the height of the pillar structure; as well as A plurality of capacitor dielectric layers and a plurality of capacitor electrode layers are formed within the trench such that a cavity is defined between a plurality of sidewalls of an uppermost capacitor dielectric layer, wherein the cavity is disposed within the trench, and wherein the uppermost capacitor dielectric layer seals the cavity.

19. The method for forming a trench capacitor according to claim 18, further comprising: A sidewall protection layer is formed along a plurality of sidewalls of the substrate defining the trench, wherein the sidewall protection layer is formed after the first patterning process and before the second patterning process.

20. A method for forming a trench capacitor according to claim 18, wherein the second patterning process is performed so that the width of the pillar structure continuously decreases from a second point to a lower surface of the substrate, wherein the second point is vertically disposed below the first point, and the lower surface of the substrate defines a bottom surface of the trench.

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