Image sensor and method of manufacturing the same

Abstract

An image sensor includes a first pixel row and a second pixel row, each of the first pixel row and the second pixel row including pixels arranged in a first direction, the first pixel row and the second pixel row being adjacent to each other in a second direction crossing the first direction. The image sensor further includes: a device isolation pattern disposed between the first pixel row and the second pixel row and spaced apart from each other in the first direction; and a support pattern disposed between the first pixel row and the second pixel row and interposed between the device isolation pattern. Each of the support pattern is connected to a corresponding one of the pixels.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2019-0175615, filed with the Korean Intellectual Property Office on December 26, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The devices, apparatus, and methods disclosed herein relate to image sensors and methods of manufacturing the same, and more particularly, to complementary metal-oxide-semiconductor (CMOS) image sensors and methods of manufacturing the same. Background Technology

[0004] An image sensor is a semiconductor device that converts optical images into electrical signals. With recent advancements in the computer and communications industries, the demand for high-performance image sensors is constantly growing in various applications such as digital cameras, camcorders, personal communication systems, game consoles, security cameras, medical miniature cameras, and / or robots. Image sensors can be classified into two types: charge-coupled device (CCD) and complementary metal-oxide-semiconductor (CMOS). Typically, CMOS image sensors are referred to as "CIS." A CIS comprises multiple pixels arranged in a two-dimensional pattern. Each of these pixels includes a photodiode (PD) that converts incident light into an electrical signal. Recently, to improve the resolution of CIS, pixels have been configured with increased aspect ratios. Summary of the Invention

[0005] On the one hand, a method for manufacturing an image sensor with reduced process failures is provided, as well as an image sensor manufactured by the method.

[0006] On the other hand, an image sensor with improved resolution and sensitivity characteristics and a method for manufacturing the same are provided.

[0007] According to one aspect of the embodiments, an image sensor is provided, the image sensor comprising: a first pixel row and a second pixel row, each pixel row including a plurality of pixels arranged in a first direction, the first pixel row and the second pixel row being adjacent to each other in a second direction intersecting the first direction; a plurality of device isolation patterns disposed between the first pixel row and the second pixel row, the plurality of device isolation patterns being spaced apart from each other in the first direction; and a plurality of support patterns disposed between the first pixel row and the second pixel row, each of the plurality of support patterns being located between two adjacent device isolation patterns of the plurality of device isolation patterns, wherein each of the plurality of support patterns is connected to a corresponding pixel of the plurality of pixels.

[0008] According to another aspect of embodiments, there is provided an image sensor, the image sensor comprising: a first pixel row and a second pixel row, each of the first pixel row and the second pixel row comprising a plurality of pixels arranged in a first direction, the first pixel row and the second pixel row being adjacent to each other in a second direction crossing the first direction; a plurality of first device isolation patterns disposed between the first pixel row and the second pixel row, the plurality of first device isolation patterns being spaced apart from each other in the first direction; and a plurality of second device isolation patterns disposed between the plurality of first device isolation patterns, wherein each of the plurality of second device isolation patterns comprises an isolation pattern disposed between corresponding first device isolation patterns of the plurality of first device isolation patterns; and an insulating pattern between the isolation pattern and each of the corresponding first device isolation patterns of the plurality of first device isolation patterns.

[0009] According to still another aspect of embodiments, there is provided a method of manufacturing an image sensor, the method comprising: forming a plurality of trenches in a substrate to define a plurality of pixel regions and a plurality of support patterns between the plurality of pixel regions; doping side surfaces of the plurality of pixel regions and the plurality of support patterns exposed by the plurality of trenches with an impurity; and forming a plurality of first device isolation patterns to fill the plurality of trenches, wherein each of the plurality of support patterns is connected to a corresponding pixel region of the plurality of pixel regions.

[0010] According to still another aspect of embodiments, there is provided a method of manufacturing an image sensor, the method comprising: forming a plurality of first trenches in a substrate, the plurality of first trenches extending in a first direction and being spaced apart from each other in a second direction crossing the first direction; forming a plurality of preliminary device isolation patterns to fill the plurality of first trenches; forming a plurality of second trenches in the substrate to cross the plurality of first trenches; and forming a plurality of second device isolation patterns to fill the plurality of second trenches, wherein each of the plurality of preliminary device isolation patterns is divided into a plurality of first device isolation patterns by the plurality of second trenches. BRIEF DESCRIPTION OF DRAWINGS

[0011] The example embodiments will be more clearly understood from the following brief description, taken in conjunction with the accompanying drawings, in which:

[0012] FIG. 1 is a circuit diagram illustrating a pixel of an image sensor according to an embodiment;

[0013] FIG. 2 is a plan view illustrating an image sensor according to an embodiment;

[0014] FIG. 3 is an enlarged view illustrating a portion P1 of the image sensor according to an embodiment; FIG. 2

[0015] FIG. 4A and​FIG. 4B They are respectively along FIG. 2 The cross-sectional views taken by lines A-A' and B-B';

[0016] FIG. 5 This is a plan view illustrating a method for manufacturing an image sensor according to an embodiment;

[0017] FIG. 6A and FIG. 6B They are respectively along FIG. 5 The cross-sectional views taken by lines A-A' and B-B';

[0018] FIG. 7A , FIG. 7B , FIG. 8B and FIG. 7A This is a cross-sectional view illustrating a method for manufacturing an image sensor according to an embodiment, wherein... FIG. 8A and FIG. 2 It is along FIG. 7B The line A-A' is intercepted, and FIG. 8B and FIG. 2 It is along FIG. 2 The line B-B' is the intercept;

[0019] FIG. 3 This is a plan view of an image sensor according to an embodiment;

[0020] FIG. 4A It is along FIG. 4B A cross-sectional view taken from line B-B';

[0021] FIG. 5 This is a plan view illustrating a method for manufacturing an image sensor according to an embodiment;

[0022] FIG. 6A and FIG. 6B They are respectively along FIG. 5 The cross-sectional views taken by lines A-A' and B-B';

[0023] FIG. 2 and FIG. 7A They are respectively along FIG. 7B The cross-sectional views taken along lines A-A' and B-B' are used to illustrate the method of manufacturing an image sensor according to an embodiment;

[0024] FIG. 2 This is a plan view of an image sensor according to an embodiment;

[0025] FIG. 8A It is along FIG. 8B A cross-sectional view taken from line B-B';

[0026] FIG. 14 and FIG. 15is a plan view showing a method of manufacturing an image sensor according to an embodiment;

[0027] FIG. 14 and FIG. 14 are cross-sectional views taken along lines A-A' and B-B' of FIG. 4A respectively, and FIG. 2 and FIG. 3 are cross-sectional views taken along lines A-A' and B-B' of FIG. 4A respectively;

[0028] FIG. 4B and FIG. 2 are cross-sectional views taken along lines A-A' and B-B' of FIG. 3 respectively to illustrate a method of manufacturing an image sensor according to an embodiment;

[0029] FIG. 4A is a plan view showing an image sensor according to an embodiment;

[0030] FIG. 4B is an enlarged view showing a portion P2 of the image sensor of FIG. 4A ;

[0031] FIG. 14 is a cross-sectional view taken along line B-B' of FIG. 15 ;

[0032] FIG. 16 , FIG. 18 and FIG. 17A are plan views showing a method of manufacturing an image sensor according to an embodiment;

[0033] FIG. 17B are cross-sectional views taken along lines A-A', B-B' and C-C' of FIG. 16 respectively, FIG. 19A are cross-sectional views taken along lines A-A', B-B' and C-C' of FIG. 19B respectively, and FIG. 18 are cross-sectional views taken along lines A-A', B-B' and C-C' of FIG. 20A respectively;

[0034] FIG. 20B are cross-sectional views taken along lines A-A', B-B' and C-C' of FIG. 14 respectively to illustrate a method of manufacturing an image sensor according to an embodiment;

[0035] FIG. 5 is a plan view showing an image sensor according to an embodiment;

[0036] FIG. 6A to FIG. 8B is a cross-sectional view taken along line B-B' of FIG. 5 ;

[0037] FIG. 6A to FIG. 8B is a plan view showing a method of manufacturing an image sensor according to an embodiment;

[0038] FIG. 16 are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 17A , respectively, to explain a method of manufacturing an image sensor according to an embodiment.

[0039] FIG. 17B are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 5 , respectively, to explain a method of manufacturing an image sensor according to an embodiment. DETAILED DESCRIPTION

[0040] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings.

[0041] It should be noted that the drawings are intended to illustrate the general characteristics of methods, structures and / or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings, which are not to scale, are merely meant to aid in understanding example embodiments and are not intended to limit the scope of example embodiments in any way. For example, relative thicknesses and positions of molecular, layer, regional, and / or structural elements can be reduced or exaggerated for clarity. The use of similar or identical reference numerals in various drawings is intended to indicate like or similar elements or features.

[0042] FIG. 6A is a circuit diagram showing a pixel of an image sensor according to an embodiment.

[0043] Referring to FIG. 6B , a unit pixel PX of an image sensor can include a photoelectric conversion device PD, a transfer transistor Tx, a source follower transistor Sx, a reset transistor Rx, and a selection transistor Ax. The transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, and the selection transistor Ax can include a transfer gate TG, a source follower gate SG, a reset gate RG, and a selection gate AG, respectively.

[0044] The photoelectric conversion device PD can be a photodiode including a p-type impurity region and an n-type impurity region. A floating diffusion region FD can be disposed between the transfer transistor Tx and the reset transistor Rx to function as a drain of the transfer transistor Tx. The floating diffusion region FD can also function as a source electrode of the reset transistor Rx. The floating diffusion region FD can be electrically connected to the source follower gate SG of the source follower transistor Sx. The source follower transistor Sx can be connected to the selection transistor Ax.

[0045] Hereinafter, reference will be made to FIG. 16The operation of the image sensor according to the embodiment will be described. First, if external light is incident into the photoelectric conversion device PD, an electron-hole pair can be generated in the photoelectric conversion device PD. The hole can move into and accumulate in the p-type impurity region of the photoelectric conversion device PD, and the electron can move into and accumulate in the n-type impurity region of the photoelectric conversion device PD. By turning on the reset transistor Rx and applying a power supply voltage VDD to the drain of the reset transistor Rx and the source follower transistor Sx, the charge can be released from the floating diffusion region FD while preventing the electron from entering the floating diffusion region FD. Thereafter, by turning on the transfer transistor Tx, the generated charge (e.g., the electron and the hole) can be transferred into and accumulated in the floating diffusion region FD. A change in the amount of the accumulated charge can cause a change in the gate bias of the source follower transistor Sx, and this can cause a change in the source potential of the source follower transistor Sx. Thus, if the selection transistor Ax is turned on, a signal associated with the charge can be read out through the column line.

[0046] FIG. 18 An example of a pixel in which a single photoelectric conversion device PD and four transistors (i.e., Tx, Rx, Ax, and Sx) are provided is shown, but example embodiments are not limited to this example. For example, the image sensor can include a plurality of pixels PX, and in certain embodiments, the reset transistor Rx, the source follower transistor Sx, or the selection transistor Ax can be shared by adjacent pixels in the pixels PX. In this case, the integration density of the image sensor can be increased.

[0047] FIG. 19A is a plan view showing the image sensor according to the embodiment, and FIG. 19B is a plan view showing FIG. 2 is an enlarged view of the portion P1 of the image sensor of FIG. 7A and FIG. 7B are cross-sectional views taken along lines A-A’ and B-B’ of FIG. 14 , respectively.

[0048] Referring to FIG. 20A , FIG. 20B and FIG. 2 , a substrate 100 including a plurality of pixel regions PXR can be provided. The substrate 100 can be a semiconductor substrate (e.g., a silicon wafer, a germanium wafer, a silicon-germanium wafer, a II-VI compound semiconductor wafer, or a III-V compound semiconductor wafer) or a silicon-on-insulator (SOI) wafer. The substrate 100 can have a first surface 100a and a second surface 100b opposite to each other.

[0049] The pixel regions PXR can be two-dimensionally arranged in a first direction D1 and a second direction D2 parallel to the first surface 100a of the substrate 100 (see, for example, FIG. 7A The first direction D1 and the second direction D2 can not be parallel to each other (for example, in some embodiments, the first direction D1 and the second direction D2 can intersect). The pixel regions PXR arranged in the first direction D1 among the pixel regions PXR can constitute a row (hereinafter, a pixel row). As an example, the substrate 100 can include a first pixel row RO1 and a second pixel row RO2 adjacent to each other in the second direction D2, and each of the first pixel row RO1 and the second pixel row RO2 includes a plurality of pixel regions PXR arranged in the first direction D1.

[0050] The device isolation pattern 130 can be provided in the substrate 100 and between the pixel regions PXR. The device isolation pattern 130 can include first device isolation patterns 130a separated from each other in the first direction D1 and second device isolation patterns 130b separated from each other in the second direction D2. The first device isolation patterns 130a can be provided between the first pixel row RO1 and the second pixel row RO2 and can be spaced apart from each other in the first direction D1. The second device isolation patterns 130b can be provided between the pixel regions PXR in the first pixel row RO1 and between the pixel regions PXR in the second pixel row RO2.

[0051] Each of the device isolation patterns 130 can be provided to penetrate at least a portion of the substrate 100. Each of the device isolation patterns 130 can extend from the first surface 100a of the substrate 100 toward an internal portion of the substrate 100 in a third direction D3 perpendicular to the first surface 100a. As an example, in some embodiments, a bottom surface 130B of each of the device isolation patterns 130 can be spaced apart from the second surface 100b of the substrate 100. In other embodiments, differently from what is shown in the drawings, the bottom surface 130B of each of the device isolation patterns 130 can be substantially coplanar with the second surface 100b of the substrate 100. Each of the device isolation patterns 130 can be provided between adjacent pixel regions PXR among the pixel regions PXR to suppress or prevent a crosstalk problem between the adjacent pixel regions PXR among the pixel regions PXR.

[0052] Each of the device isolation patterns 130 can include the isolation pattern 110 disposed to penetrate at least a portion of the substrate 100 and the insulating pattern 120 interposed between the isolation pattern 110 and the substrate 100. The isolation pattern 110 can be disposed between adjacent ones of the pixel regions PXR in the pixel region PXR, and the insulating pattern 120 can be interposed between the isolation pattern 110 and each of the adjacent ones of the pixel regions PXR in the pixel region PXR. In some embodiments, a bottom surface 110B of the isolation pattern 110 can be spaced apart from the second surface 100b of the substrate 100, and the insulating pattern 120 can extend into a region between the bottom surface 110B of the isolation pattern 110 and the second surface 100b of the substrate 100. The isolation pattern 110 can be formed of or include at least one of a semiconductor material (e.g., doped polysilicon) or a metallic material (e.g., tungsten or aluminum). The insulating pattern 120 can be formed of or include at least one of, for example, silicon nitride, silicon oxide, silicon oxynitride, or a high-k dielectric material (e.g., hafnium oxide and / or aluminum oxide).

[0053] In this specification, the isolation pattern 110 and the insulating pattern 120 of each of the first device isolation patterns 130a can be referred to as a first isolation pattern 110 and a first insulating pattern 120, respectively, and the isolation pattern 110 and the insulating pattern 120 of each of the second device isolation patterns 130b can be referred to as a second isolation pattern 110 and a second insulating pattern 120, respectively.

[0054] The support pattern 140 can be disposed in the substrate 100 and between the pixel regions PXR. The support pattern 140 can be disposed between the first pixel row RO1 and the second pixel row RO2 and can be interposed between the first device isolation patterns 130a. The first device isolation patterns 130a and the support pattern 140 can be alternately and repeatedly arranged in the first direction D1 between the first pixel row RO1 and the second pixel row RO2. Each of the support patterns 140 can be interposed between a corresponding pair of the second device isolation patterns 130b among the second device isolation patterns 130b. The support pattern 140 can be a protruding portion of the substrate 100 extending into a region between the device isolation patterns 130. Each of the support patterns 140 can extend in the third direction D3 to be placed between adjacent ones of the device isolation patterns 130. The device isolation patterns 130 can be spaced apart from each other with the support pattern 140 interposed therebetween.

[0055] Reference FIG. 7B and FIG. 2Each of the support patterns 140 can be between directly adjacent ones of the first device isolation patterns 130a and between directly adjacent ones of the second device isolation patterns 130b. Each of the support patterns 140 can be connected to a corresponding one of the pixel regions PXR. As an example, each of the support patterns 140 can be disposed between and connected to four directly adjacent ones of the pixel regions PXR. Thus, the support patterns 140 can be used to support the pixel regions PXR during a process of forming the device isolation patterns 130.

[0056] Referring back to FIG. 4A , FIG. 4B and FIG. 8A , the isolation pattern 110 of each of the device isolation patterns 130 can be disposed between adjacent ones of the support patterns 140. The insulating pattern 120 of each of the device isolation patterns 130 can extend into a region between the isolation pattern 110 and each of the adjacent ones of the support patterns 140.

[0057] The first doped region 150 can be disposed in each of the support patterns 140 and can extend along a side surface of each of the support patterns 140, as best shown in FIG. 8B In some embodiments, the first doped region 150 can extend into a portion of the substrate 100 adjacent to the bottom surface 130B of each of the device isolation patterns 130. The insulating pattern 120 of each of the device isolation patterns 130 can be between the isolation pattern 110 of each of the device isolation patterns 130 and the first doped region 150 and can be in contact with the first doped region 150. The isolation pattern 110 can be spaced apart from the first doped region 150 with the insulating pattern 120 between the isolation pattern 110 and the first doped region 150.

[0058] The second doped region 152 can be provided in each of the pixel regions PXR and can extend along a side surface of each of the pixel regions PXR. In some embodiments, the second doped region 152 can extend into a portion of the substrate 100 adjacent to the bottom surface 130B of each of the device isolation patterns 130. The insulating pattern 120 of each of the device isolation patterns 130 can be interposed between the isolation pattern 110 of each of the device isolation patterns 130 and the second doped region 152, and can be in contact with the second doped region 152. The isolation pattern 110 can be spaced apart from the second doped region 152 with the insulating pattern 120 interposed therebetween. The first doped region 150 and the second doped region 152 can have the same conductivity type, and can be connected to each other.

[0059] The photoelectric conversion region PD can be provided in each of the pixel regions PXR. The photoelectric conversion region PD can be provided in the substrate 100 and between adjacent ones of the device isolation patterns 130. The photoelectric conversion region PD can include a first impurity region 160 and a second impurity region 170. The second impurity region 170 can be disposed closer to the first surface 100a of the substrate 100 than the first impurity region 160. The first impurity region 160 can be a region doped with an impurity of a first conductivity type, and the second impurity region 170 can be a region doped with an impurity of a second conductivity type different from the first conductivity type. In one embodiment, the first conductivity type and the second conductivity type can be n-type and p-type, respectively. In this case, the impurity of the first conductivity type can include an n-type impurity such as phosphorus, arsenic, bismuth, and / or antimony, and the impurity of the second conductivity type can include a p-type impurity such as boron.

[0060] The second doped region 152 can be provided between the photoelectric conversion region PD and each of the adjacent ones of the device isolation patterns 130. The second doped region 152 can be doped with an impurity of the second conductivity type. The second doped region 152 can prevent electrons trapped in a dangling bond from entering the photoelectric conversion region PD, where the dangling bond can exist on a side surface of each of the pixel regions PXR, and thus the second doped region 152 can enable the dark current or white spot problem to be suppressed or prevented from occurring in the image sensor. The first doped region 150 can be doped with an impurity of the second conductivity type, and can contain the same impurity as the second doped region 152.

[0061] A floating diffusion region FD can be provided in each of the pixel regions PXR. The floating diffusion region FD can be provided adjacent to the first surface 100a of the substrate 100 and can be spaced apart from the first impurity region 160 by the second impurity region 170. The floating diffusion region FD can be doped with impurities of the first conductivity type. A transfer gate TG can be provided on each of the pixel regions PXR and can be provided on the first surface 100a of the substrate 100. The transfer gate TG can be provided adjacent to the floating diffusion region FD.

[0062] An interconnection structure 180 can be provided on the first surface 100a of the substrate 100. The interconnection structure 180 can include an interlayer insulating layer 186 provided on the first surface 100a of the substrate 100 to cover the transfer gate TG, and an interconnection line 182 and a via 184 provided in the interlayer insulating layer 186. The floating diffusion region FD can be connected to a corresponding one of the vias 184, and each of the vias 184 can be connected to a corresponding one of the interconnection lines 182. The interlayer insulating layer 186 can be formed of or include at least one of silicon oxide, silicon oxynitride, or silicon nitride. The interconnection line 182 and the via 184 can be formed of or include at least one of a conductive material.

[0063] A color filter 200 can be provided on the second surface 100b of the substrate 100. The color filter 200 can be provided to overlap the pixel regions PXR, respectively, when viewed in a plan view. A grid pattern 210 can be provided on the second surface 100b of the substrate 100 and between the color filters 200. As an example, the grid pattern 210 can be provided on the device isolation pattern 130 and the support pattern 140. In an embodiment, the grid pattern 210 can be formed of or include at least one of a metal material. A microlens 220 can be provided on the color filter 200. The microlens 220 can be provided to overlap the pixel regions PXR, respectively, when viewed in a plan view. The microlens 220 can change a propagation path of external light so that the external light is incident into the pixel regions PXR.

[0064] According to an embodiment, each of the support patterns 140 can be provided between adjacent ones of the pixel regions PXR and between adjacent ones of the device isolation patterns 130. Each of the support patterns 140 can be connected to adjacent ones of the pixel regions PXR. Accordingly, the support patterns 140 can support the pixel regions PXR during a process of forming the device isolation patterns 130.

[0065] FIG. 21 is a plan view illustrating a method of manufacturing an image sensor according to an embodiment, andFIG. 22 and FIG. 21 are cross-sectional views taken along lines A-A' and B-B' of FIG. 23 , respectively. FIG. 21 , FIG. 21 , FIG. gA and FIG. 4A are cross-sectional views to illustrate a method of manufacturing an image sensor according to an embodiment, in which FIG. 2 and FIG. 3 are taken along a line A-A' of FIG. 4A , while FIG. 4B and FIG. 2 are taken along a line B-B' of FIG. 3 . For the sake of conciseness, elements previously described with reference to FIG. 4A , FIG. 4B , FIG. 4A and FIG. 21 may be identified by the same reference numerals without repeating the description thereof in detail.

[0066] Referring to FIG. 22 , FIG. 23 and FIG. 24 , a plurality of trenches 130T can be formed in the substrate 100 to define a plurality of pixel regions PXR and a plurality of support patterns 140. Forming the trenches 130T can include forming a mask pattern (not shown) on the first surface 100a of the substrate 100 and etching the substrate 100 using the mask pattern as an etching mask. The mask pattern can have openings defining the positions and shapes of the trenches 130T. The substrate 100 can include the pixel regions PXR and the support patterns 140 defined by the trenches 130T.

[0067] The pixel regions PXR can be two-dimensionally arranged in a first direction D1 and a second direction D2 parallel to the first surface 100a of the substrate 100 (see FIG. 26 ). As an example, the substrate 100 can include a first pixel row RO1 and a second pixel row RO2 adjacent to each other in the second direction D2, and each of the first and second pixel rows RO1 and RO2 includes a plurality of pixel regions PXR arranged in the first direction D1. The trenches 130T can include first trenches 130Ta spaced apart from each other in the first direction D1 and second trenches 130Tb spaced apart from each other in the second direction D2. The first trenches 130Ta can be spaced apart from each other in the first direction D1 between the first and second pixel rows RO1 and RO2. The second trenches 130Tb can be formed between the pixel regions PXR in the first pixel row RO1 and between the pixel regions PXR in the second pixel row RO2.

[0068] The support patterns 140 can be formed between the pixel regions PXR. The support patterns 140 can be formed between the first pixel row RO1 and the second pixel row RO2 to be spaced apart from each other in the first direction D1. Each of the support patterns 140 can be interposed between adjacent first trenches 130Ta among the first trenches 130Ta and between adjacent second trenches 130Tb among the second trenches 130Tb. Each of the support patterns 140 can be connected to a corresponding pixel region PXR among the pixel regions PXR. As an example, each of the support patterns 140 can be disposed between and connected to four directly adjacent pixel regions PXR among the pixel regions PXR.

[0069] The first impurity region 160 can be formed in each of the pixel regions PXR. Forming the first impurity region 160 can include implanting an impurity of a first conductivity type (e.g., an n-type impurity) into each of the pixel regions PXR.

[0070] The first doped region 150 can be formed on a side surface of the support pattern 140 exposed by the trench 130T and in a portion of the substrate 100 adjacent to a bottom surface of the trench 130T. The second doped region 152 can be formed on a side surface of the pixel region PXR exposed by the trench 130T and in a portion of the substrate 100 adjacent to a bottom surface of the trench 130T. Forming the first doped region 150 and the second doped region 152 can include implanting an impurity of a second conductivity type (e.g., a p-type impurity) into the side surface of the support pattern 140 exposed by the trench 130T, the side surface of the pixel region PXR exposed by the trench 130T, and the portion of the substrate 100 adjacent to the bottom surface of the trench 130T. In an embodiment, the first doped region 150 and the second doped region 152 can be formed simultaneously by a plasma doping process.

[0071] Reference FIG. 28 , FIG. 25A to FIG. 25C and FIG. 24The device isolation pattern 130 can be formed to fill the trench 130T, respectively. Forming the device isolation pattern 130 can include forming an insulating layer on the first surface 100a of the substrate 100 to partially fill each of the trenches 130T, forming an isolation layer on the insulating layer to fill a remaining portion of each of the trenches 130T, and planarizing the isolation layer and the insulating layer to expose the first surface 100a of the substrate 100. As a result of the planarization process, the insulating pattern 120 and the isolation pattern 110 can be locally formed in each of the trenches 130T. Each of the device isolation patterns 130 can include the isolation pattern 110 disposed in each of the trenches 130T and the insulating pattern 120 interposed between an inner surface of each of the trenches 130T and the isolation pattern 110. The device isolation patterns 130 can include a first device isolation pattern 130a filling a first trench 130Ta and a second device isolation pattern 130b filling a second trench 130Tb.

[0072] Referring to FIG. 27A to FIG. 27C , FIG. 26 and FIG. 29A to FIG. 29C , a second impurity region 170 can be formed in each of the pixel regions PXR. Forming the second impurity region 170 can include implanting an impurity of a second conductivity type (e.g., a p-type impurity) into each of the pixel regions PXR. The second impurity region 170 can be formed closer to the first surface 100a of the substrate 100 than the first impurity region 160. A transfer gate TG can be formed on the first surface 100a of the substrate 100, and a floating diffusion region FD can be formed in a portion of the substrate 100 located on one side of the transfer gate TG. Forming the floating diffusion region FD can include implanting an impurity of a first conductivity type (e.g., an n-type impurity) into the substrate 100.

[0073] An interconnection structure 180 can be formed on the first surface 100a of the substrate 100. Forming the interconnection structure 180 can include forming an interlayer insulating layer 186 to cover the transfer gate TG, and forming an interconnection line 182 and a via 184 in the interlayer insulating layer 186. The floating diffusion region FD can be connected to a corresponding one of the vias 184, and each of the vias 184 can be connected to a corresponding one of the interconnection lines 182. Next, a chemical mechanical polishing (CMP) or a lapping process can be performed on the second surface 100b of the substrate 100 to thin the substrate 100.

[0074] Referring again to FIG. 28 , FIG. 30A to FIG. 30C and FIG. 21The color filter 200 can be formed on the second surface 100b of the substrate 100, and in an embodiment, can overlap with the pixel regions PXR, respectively, when viewed in a plan view. The grid pattern 210 can be formed on the second surface 100b of the substrate 100 and between the color filters 200, and in an embodiment, can overlap with the device isolation pattern 130 and the support pattern 140 when viewed in a plan view. The microlens 220 can be formed on the second surface 100b of the substrate 100, and in an embodiment, can overlap with the pixel regions PXR, respectively, when viewed in a plan view.

[0075] As the demand for image sensors having improved resolution and sensitivity increases, the aspect ratio of each of the pixel regions PXR increases, and thus the aspect ratio of each of the trenches 130T defining the pixel regions PXR also increases. However, in this case, a tilting problem of the pixel regions PXR can occur during an etching process of forming the trenches 130T or during a subsequent cleaning process.

[0076] According to an embodiment, each of the support patterns 140 can be formed between adjacent ones of the pixel regions PXR and connected to the adjacent ones of the pixel regions PXR. In this case, the support patterns 140 can support the pixel regions PXR during the etching process of forming the trenches 130T or during the subsequent cleaning process. Thus, the tilting problem of the pixel regions PXR can be prevented. Accordingly, process failures in a process of manufacturing the image sensor can be reduced. In addition, as the pixel regions PXR are supported by the support patterns 140, the aspect ratio of the pixel regions PXR can be easily increased. The increased aspect ratio of the pixel regions PXR can facilitate improvement of resolution and sensitivity characteristics of the image sensor.

[0077] FIG. 5 is a plan view illustrating an image sensor according to an embodiment, and FIG. 6A to FIG. 8B is a cross-sectional view taken along line B-B' of FIG. 5 is a cross-sectional view taken along line A-A' of FIG. 6A to FIG. 8B may be substantially the same as the cross-sectional view of FIG. 24 , and thus repeated description thereof is omitted for the sake of brevity. For the sake of conciseness, repeated description of features identical to those of FIG. 25A to FIG. 25C , FIG. 5 , FIG. 6A and FIG. 6B is omitted, and features different from those of the image sensor of FIG. 26 , FIG. 27A to FIG. 27C , FIG. 2 and FIG. 7A will mainly be described below.

[0078] In conjunction with FIG. 7B reference to FIG. 28 and FIG. 29A to FIG. 29C , the device isolation pattern 130 can be disposed in the substrate 100 and between the pixel regions PXR. As an example, the device isolation pattern 130 can be disposed between the first pixel row ROl and the second pixel row RO2, which are adjacent to each other in the second direction D2. The device isolation pattern 130 can be spaced apart from each other in the first direction Dl between the first pixel row ROl and the second pixel row RO2. Each of the device isolation pattern 130 can extend into the region between adjacent pixel regions PXR in the first pixel row ROl and the region between adjacent pixel regions PXR in the second pixel row RO2. Each of the device isolation pattern 130 can be a cross-shaped pattern when viewed in a plan view, as FIG. 28 best shown. Each of the device isolation pattern 130 can be disposed between adjacent pixel regions PXR in the pixel regions PXR (e.g., between adjacent four pixel regions PXR in the pixel regions PXR).

[0079] Each of the device isolation pattern 130 can include the isolation pattern 110 disposed to penetrate at least a portion of the substrate 100 and the insulating pattern 120 interposed between the isolation pattern 110 and the substrate 100. As an example, the isolation pattern 110 can be spaced apart from each other in the first direction Dl between the first pixel row ROl and the second pixel row RO2. The isolation pattern 110 can extend into the region between adjacent pixel regions PXR in the first pixel row ROl and the region between adjacent pixel regions PXR in the second pixel row RO2, and can be a cross-shaped pattern when viewed in a plan view. The isolation pattern 110 can be disposed between adjacent pixel regions PXR in the pixel regions PXR (e.g., between adjacent four pixel regions PXR in the pixel regions PXR). The insulating pattern 120 can be interposed between the isolation pattern 110 and each of the adjacent pixel regions PXR in the pixel regions PXR.

[0080] The support pattern 140 can be disposed in the substrate 100 and between the pixel regions PXR, and can be interposed between the device isolation patterns 130. As an example, the support pattern 140 can be interposed between the device isolation patterns 130 between the first pixel row RO1 and the second pixel row RO2. The device isolation patterns 130 and the support patterns 140 can be alternately and repeatedly arranged in the first direction D1 between the first pixel row RO1 and the second pixel row RO2. Each of the support patterns 140 can be interposed between corresponding ones of the pixel regions PXR in the first pixel row RO1 and the pixel regions PXR in the second pixel row RO2, and can be connected to the corresponding ones of the pixel regions PXR. The support patterns 140 can be interposed between adjacent ones of the pixel regions PXR in the first pixel row RO1 and the pixel regions PXR in the second pixel row RO2, and can be connected to the adjacent ones of the pixel regions PXR. Thus, the support patterns 140 can serve to support the pixel regions PXR during a process of forming the device isolation patterns 130.

[0081] The isolation pattern 110 of each of the device isolation patterns 130 can be disposed between adjacent ones of the support patterns 140. The insulating pattern 120 of each of the device isolation patterns 130 can extend into a region between the isolation pattern 110 and each of the adjacent ones of the support patterns 140.

[0082] FIG. 5 are plan views illustrating a method of manufacturing an image sensor according to an embodiment, and FIG. 6A and FIG. 6B are cross-sectional views taken along lines A-A' and B-B' of FIG. 21 , respectively. FIG. 30A to FIG. 30C and FIG. 2 are cross-sectional views taken along lines A-A' and B-B' of FIG. 7A , respectively, to explain a method of manufacturing an image sensor according to an embodiment. For the sake of brevity, repeated description of features identical to those of FIG. 7B and FIG. 2 will be omitted, and features different from the method of FIG. 4A and FIG. 4B will mainly be described below.

[0083] Referring to FIG. 8A , FIG. 8B and FIG. 31 , a plurality of trenches 130T can be formed in the substrate 100 to define a plurality of pixel regions PXR and a plurality of support patterns 140. The trenches 130T can be formed by a process identical to that of FIG. 32 , FIG. 31 andFIG. 31 The method described can be substantially the same as the method for forming the trenches 130T. As an example, the trenches 130T can be spaced apart from each other in the first direction D1 between the first pixel row RO1 and the second pixel row RO2 adjacent to each other in the second direction D2. Each of the trenches 130T can extend into a region between adjacent pixel regions PXR in the pixel regions PXR in the first pixel row RO1 and a region between adjacent pixel regions PXR in the pixel regions PXR in the second pixel row RO2, and each of the trenches 130T can be a cross-shaped pattern when viewed in a plan view.

[0084] The support patterns 140 can be formed between the pixel regions PXR. The support patterns 140 can be formed to be spaced apart from each other in the first direction D1 between the first pixel row RO1 and the second pixel row RO2. Each of the support patterns 140 can be interposed between adjacent ones of the trenches 130T. Each of the support patterns 140 can be interposed between a corresponding one of the pixel regions PXR in the first pixel row RO1 and a corresponding one of the pixel regions PXR in the second pixel row RO2, and can be connected to the corresponding pixel regions PXR. The support patterns 140 can be interposed between adjacent ones of the pixel regions PXR in the first pixel row RO1 and between adjacent ones of the pixel regions PXR in the second pixel row RO2, and can be connected to the adjacent pixel regions PXR.

[0085] The first and second doped regions 150 and 152 can be formed in side portions of the support patterns 140 exposed by the trenches 130T, side portions of the pixel regions PXR exposed by the trenches 130T, and portions of the substrate 100 adjacent to bottom surfaces of the trenches 130T.

[0086] Reference is made to FIG. 21 , FIG. 2 and FIG. 3 The device isolation patterns 130 can be formed to fill the trenches 130T, respectively. The device isolation patterns 130 can be formed by substantially the same method as the method described with reference to FIG. 4A , FIG. 4B and FIG. 2 The device isolation patterns 130 can be formed by substantially the same method as the method described with reference to FIG. 3 , FIG. 4A , FIG. 4B , FIG. 4A and FIG. 31 Subsequent processes can be performed in substantially the same manner as described with reference to

[0087] FIG. 32This is a plan view of an image sensor according to an embodiment, and FIG. 33 It is along FIG. 34A to FIG. 34C A cross-sectional view taken along line B-B'. FIG. 33 The cross-sectional view taken by line A-A' can be compared with FIG. 35A to FIG. 35C The cross-sectional views are basically the same, so for the sake of brevity, repeated descriptions have been omitted. For the sake of simplicity, details regarding the cross-sectional views will be omitted. FIG. 31 , FIG. 5 , FIG. 6A to FIG. 8B and FIG. 5 Repeated descriptions of features that are identical to those of the previous ones, and the following will mainly describe features that are identical to those of the previous ones. FIG. 6A to FIG. 8B , FIG. 33 , ​ and ​ The characteristics of image sensors differ.

[0088] Combination ​ For reference ​ and ​ Device isolation patterns 130 may be disposed in the substrate 100 and between pixel regions PXR. Device isolation patterns 130 may include a first device isolation pattern 130a separated from each other in a first direction D1 and a second device isolation pattern 130b separated from each other in a second direction D2. The first device isolation pattern 130a may be disposed between the first pixel row RO1 and the second pixel row RO2, and may be spaced apart from each other in the first direction D1. The second device isolation pattern 130b may be disposed between pixel regions PXR in the first pixel row RO1 and between pixel regions PXR in the second pixel row RO2.

[0089] The device isolation pattern 130 may further include a third device isolation pattern 130c, which is disposed between the first pixel row RO1 and the second pixel row RO2 and between the first device isolation patterns 130a. The first device isolation patterns 130a and the third device isolation patterns 130c may be arranged alternately and repeatedly in the first direction D1 between the first pixel row RO1 and the second pixel row RO2. Each of the third device isolation patterns 130c may be located between a pair of corresponding second device isolation patterns 130b. Each of the third device isolation patterns 130c may be located between directly adjacent first device isolation patterns 130a in the first device isolation patterns 130a and between directly adjacent second device isolation patterns 130b in the second device isolation patterns 130b.

[0090] Each of the device isolation patterns 130 can include the isolation pattern 110 disposed to penetrate at least a portion of the substrate 100 and the insulating pattern 120 interposed between the isolation pattern 110 and the substrate 100. The isolation pattern 110 can be disposed between adjacent ones of the pixel regions PXR in the pixel region PXR, and the insulating pattern 120 can be interposed between the isolation pattern 110 and each of the adjacent ones of the pixel regions PXR in the pixel region PXR. The isolation pattern 110 of each of the first and second device isolation patterns 130a and 130b can be disposed between adjacent ones of the third device isolation patterns 130c. The insulating pattern 120 of each of the first and second device isolation patterns 130a and 130b can extend into a region between the isolation pattern 110 and each of the adjacent ones of the third device isolation patterns 130c. The isolation pattern 110 of each of the third device isolation patterns 130c can be disposed between adjacent ones of the first device isolation patterns 130a and between adjacent ones of the second device isolation patterns 130b. The insulating pattern 120 of each of the third device isolation patterns 130c can extend into a region between the isolation pattern 110 and each of the adjacent ones of the first and second device isolation patterns 130a and 130b.

[0091] In this specification, the isolation pattern 110 and the insulating pattern 120 of each of the first device isolation patterns 130a can be respectively referred to as a first isolation pattern 110 and a first insulating pattern 120, and the isolation pattern 110 and the insulating pattern 120 of each of the second device isolation patterns 130b can be respectively referred to as a second isolation pattern 110 and a second insulating pattern 120. In addition, the isolation pattern 110 and the insulating pattern 120 of each of the third device isolation patterns 130c can be respectively referred to as a third isolation pattern 110 and a third insulating pattern 120.

[0092] In some embodiments, the first doped region 150 can be disposed in a portion of the substrate 100 adjacent to the bottom surface 130B of the device isolation pattern 130. The second doped region 152 can be disposed in each of the pixel regions PXR and can extend along a side surface of each of the pixel regions PXR. In some embodiments, the second doped region 152 can extend into a portion of the substrate 100 adjacent to the bottom surface 130B of each of the device isolation patterns 130 and can be connected to the first doped region 150.

[0093] ​ and ​is a plan view showing a method of manufacturing an image sensor according to an embodiment. ​ and ​ are cross-sectional views taken along lines A-A' and B-B' of ​ , respectively, and ​ and ​ are cross-sectional views taken along lines A-A' and B-B' of ​ , respectively. ​ and ​ are cross-sectional views taken along lines A-A' and B-B' of ​ , respectively, to illustrate a method of manufacturing an image sensor according to an embodiment. For the sake of brevity, repeated description of features identical to those of ​ and ​ will be omitted, and features different from the method of ​ and ​ will mainly be described below.

[0094] Referring to ​ , ​ and ​ , a plurality of trenches 130T can be formed in the substrate 100 to define a plurality of pixel regions PXR and a plurality of support patterns 140. The trenches 130T can be formed by substantially the same method as described with reference to ​ , ​ and ​ . The trenches 130T can include first trenches 130Ta spaced apart from each other in the first direction D1 and second trenches 130Tb spaced apart from each other in the second direction D2. The first trenches 130Ta can be spaced apart from each other in the first direction D1 between the first pixel row RO1 and the second pixel row RO2. The second trenches 130Tb can be formed between the pixel regions PXR in the first pixel row RO1 and between the pixel regions PXR in the second pixel row RO2.

[0095] The support patterns 140 can be formed between the pixel regions PXR. The support patterns 140 can be formed between the first pixel row RO1 and the second pixel row RO2 to be spaced apart from each other in the first direction D1. Each of the support patterns 140 can be interposed between adjacent ones of the first trenches 130Ta and between adjacent ones of the second trenches 130Tb. Each of the support patterns 140 can be connected to a corresponding one of the pixel regions PXR. As an example, each of the support patterns 140 can be disposed between and connected to four directly adjacent ones of the pixel regions PXR, as best shown in ​ .

[0096] The first doped region 150 can be formed on the side surfaces of the support pattern 140 exposed by the trench 130T and in the portion of the substrate 100 adjacent to the bottom surface of the trench 130T. The second doped region 152 can be formed on the side surfaces of the pixel region PXR exposed by the trench 130T and in the portion of the substrate 100 adjacent to the bottom surface of the trench 130T.

[0097] Referring to ​ , ​ and ​ , the device isolation pattern 130 can be formed to fill the trench 130T, respectively. The device isolation pattern 130 can be formed by substantially the same method as the method described with reference to ​ , ​ and ​ , and thus a repeated description thereof will be omitted for the sake of brevity. Each of the device isolation patterns 130 can include the isolation pattern 110 disposed in each of the trenches 130T and the insulating pattern 120 interposed between the inner surface of each of the trenches 130T and the isolation pattern 110. The device isolation patterns 130 can include a first device isolation pattern 130a filling the first trench 130Ta and a second device isolation pattern 130b filling the second trench 130Tb.

[0098] After the first device isolation pattern 130a and the second device isolation pattern 130b are formed, the support pattern 140 can be removed. In an embodiment, removing the support pattern 140 can include forming a mask pattern (not shown) on the first surface 100a of the substrate 100 to have an opening exposing the support pattern 140 and etching the support pattern 140 using the mask pattern as an etching mask. During etching the support pattern 140, the insulating pattern 120 of each of the device isolation patterns 130 can serve as an etching stop layer. As a result of etching the support pattern 140, a plurality of holes 140H can be formed between the pixel regions PXR and between the device isolation patterns 130. Each of the holes 140H can be formed between adjacent ones of the first device isolation patterns 130a in the first device isolation pattern 130a and between adjacent ones of the second device isolation patterns 130b in the second device isolation pattern 130b.

[0099] Referring to ​ , ​ and ​ , the third device isolation pattern 130c can be formed to fill the hole 140H, respectively. The third device isolation pattern 130c can be formed by substantially the same method as the method described with reference to ​ , ​ and ​The method described forms the third device isolation pattern 130c substantially in the same manner as the method described above, and therefore repetitive description thereof will be omitted for the sake of brevity. Each of the third device isolation patterns 130c can include the isolation pattern 110 disposed in each of the holes 140H and the insulating pattern 120 interposed between the isolation pattern 110 and the inner surface of each of the holes 140H. In some embodiments, an additional doped region can be formed in the portion of the substrate 100 exposed by the hole 140H prior to forming the third device isolation pattern 130c. Thus, the first doped region 150 can extend along the bottom surface 130B of the first through third device isolation patterns 130a, 130b, and 130c. The subsequent processes can be performed substantially in the same manner as described with reference to ​ 、 ​ 、 ​ 、 ​ and ​ and therefore repetitive description thereof will be omitted for the sake of brevity.

[0100] ​ is a plan view illustrating an image sensor according to an embodiment, and ​ is an enlarged view illustrating a portion P2 of the image sensor of ​ . ​ is a cross-sectional view taken along the line B-B’ of ​ . The cross-sectional views taken along the lines A-A’ and C-C’ of ​ may be substantially the same as the cross-sectional view of ​ and therefore repetitive description thereof will be omitted for the sake of brevity. For the sake of conciseness, repetitive description of features identical to those of ​ 、 ​ 、 ​ and ​ will be omitted and features different from those of the image sensor of ​ 、 ​ 、 ​ and ​ will mainly be described below.

[0101] Reference is made to ​ in conjunction with ​ 、 ​ and ​The device isolation pattern 130 can be provided in the substrate 100 and between the pixel regions PXR. The device isolation pattern 130 can include first device isolation patterns 130a spaced apart from each other in the first direction D1 and second device isolation patterns 130b interposed between the first device isolation patterns 130a and extending in the second direction D2. The first device isolation patterns 130a can be provided between the first pixel row RO1 and the second pixel row RO2 and can be spaced apart from each other in the first direction D1. Each of the second device isolation patterns 130b can be interposed between adjacent ones of the first device isolation patterns 130a and can extend parallel to the second direction D2 into regions between adjacent ones of the pixel regions PXR in the first pixel row RO1 and regions between adjacent ones of the pixel regions PXR in the second pixel row RO2.

[0102] Each of the device isolation patterns 130 can include the isolation pattern 110 provided to penetrate at least a portion of the substrate 100 and the insulating pattern 120 interposed between the isolation pattern 110 and the substrate 100. The isolation pattern 110 can be provided between adjacent ones of the pixel regions PXR and the insulating pattern 120 can be interposed between the isolation pattern 110 and each of the adjacent ones of the pixel regions PXR. The isolation pattern 110 and the insulating pattern 120 of each of the first device isolation patterns 130a can be provided between adjacent ones of the second device isolation patterns 130b.

[0103] The isolation pattern 110 of each of the second device isolation patterns 130b can be interposed between adjacent ones of the first device isolation patterns 130a and can extend parallel to the second direction D2 into regions between adjacent ones of the pixel regions PXR in the first pixel row RO1 and regions between adjacent ones of the pixel regions PXR in the second pixel row RO2. The insulating pattern 120 of each of the second device isolation patterns 130b can be interposed between the isolation pattern 110 and each of the adjacent ones of the first device isolation patterns 130a and can extend parallel to the second direction D2 into regions between the isolation pattern 110 and each of the adjacent ones of the pixel regions PXR.

[0104] The doped region 152 can be provided in each of the pixel regions PXR and can extend along a side surface of each of the pixel regions PXR. In some embodiments, the doped region 152 can extend into a portion of the substrate 100 adjacent to the bottom surface 130B of each of the device isolation patterns 130. The doped region 152 can extend in the second direction D2 along a side surface of each of the second device isolation patterns 130b, and thus the doped region 152 can be provided in the isolation pattern 110 of each of the first device isolation patterns 130a. The doped region 152 can be interposed between the insulating pattern 120 of each of the second device isolation patterns 130b and the pixel region PXR adjacent to the insulating pattern 120 and between the insulating pattern 120 of each of the second device isolation patterns 130b and the isolation pattern 110 of the first device isolation pattern 130a adjacent to the insulating pattern 120.

[0105] ​ 、 ​ and ​ is a plan view illustrating a method of manufacturing an image sensor according to an embodiment. ​ is a cross-sectional view taken along line A-A', B-B', and C-C' of ​ is a cross-sectional view taken along line A-A', B-B', and C-C' of ​ is a cross-sectional view taken along line A-A', B-B', and C-C' of ​ is a cross-sectional view taken along line A-A', B-B', and C-C' of ​ is a cross-sectional view taken along line A-A', B-B', and C-C' of ​ is a cross-sectional view taken along line A-A', B-B', and C-C' of ​ is a cross-sectional view taken along line A-A', B-B', and C-C' of ​ to illustrate a method of manufacturing an image sensor according to an embodiment. For the sake of brevity, repeated description of features identical to those of ​ and ​ will be omitted, and features different from those of ​ and ​ will mainly be described below.

[0106] Referring to ​ and ​ , a first trench 130Ta can be formed in the substrate 100. The first trench 130Ta can extend in the first direction D1 and can be spaced apart from each other in the second direction D2. Forming the first trench 130Ta can include forming a first mask pattern (not shown) on the first surface 100a of the substrate 100 to have openings exposing regions in which the first trench 130Ta is to be formed, and etching the substrate 100 using the first mask pattern as an etching mask.

[0107] The first impurity region 160 can be formed in portions of the substrate 100 between the first trenches 130Ta, and the doped region 152 can be formed in side surfaces and a bottom surface of the substrate 100 exposed by the first trenches 130Ta. The doped region 152 can be formed in portions of the substrate 100 adjacent to inner side surfaces and a bottom surface of the first trenches 130Ta. The first impurity region 160 and the doped region 152 can be formed by substantially the same methods as described with reference to ​ 、 ​ and ​ . Repetitive description thereof will be omitted for brevity.

[0108] With reference to ​ and ​ , the preliminary device isolation patterns 130P can be formed to fill the first trenches 130Ta, respectively. The preliminary device isolation patterns 130P can be formed by substantially the same methods as described with reference to ​ 、 ​ and ​ . Repetitive description thereof will be omitted for brevity. Each of the preliminary device isolation patterns 130P can include the isolation pattern 110 disposed in each of the first trenches 130Ta and the insulating pattern 120 interposed between an inner surface of each of the first trenches 130Ta and the isolation pattern 110.

[0109] With reference to ​ and ​ , the second trenches 130Tb can be formed in the substrate 100. The second trenches 130Tb can be formed to cross the first trenches 130Ta. As an example, the second trenches 130Tb can extend in the second direction D2 and can be spaced apart from each other in the first direction D1. Forming the second trenches 130Tb can include forming a second mask pattern (not shown) on the first surface 100a of the substrate 100 to have openings of an exposure region in which the second trenches 130Tb are to be formed, and etching the substrate 100 and the preliminary device isolation patterns 130P using the second mask pattern as an etching mask.

[0110] Each of the preliminary device isolation patterns 130P can be divided by the second trenches 130Tb into first device isolation patterns 130a spaced apart from each other in the first direction D1. The substrate 100 can include a plurality of pixel regions PXR defined by the first trenches 130Ta and the second trenches 130Tb. The pixel regions PXR can be arranged two-dimensionally in the first direction D1 and the second direction D2, as ​ best shown.

[0111] The additional doped region 152 can be formed in the side surface of each of the pixel regions PXR exposed by the second trench 130Tb, the side surface of the isolation pattern 110 of each of the first device isolation patterns 130a exposed by the second trench 130Tb, and the portion of the substrate 100 adjacent to the bottom surface of the trench 130Tb. The additional doped region 152 can be formed by substantially the same method as that described with reference to ​ 、 ​ and ​ The additional doped region 152 can be formed by substantially the same method as that described with reference to

[0112] With reference to ​ and ​ The second device isolation patterns 130b can be formed to fill the second trenches 130Tb, respectively. The second device isolation patterns 130b can be formed by substantially the same method as that described with reference to ​ 、 ​ and ​ The second device isolation patterns 130b can be formed by substantially the same method as that described with reference to ​ 、 ​ 、 ​ 、 ​ and ​ The subsequent processes can be performed in substantially the same manner as that described with reference to

[0113] According to an embodiment, after the first trenches 130Ta are formed, the second trenches 130Tb can be formed to cross the first trenches 130Ta. The pixel regions PXR can be defined by the first trenches 130Ta and the second trenches 130Tb. In this case, since the first trenches 130Ta and the second trenches 130Tb are formed by separate etching processes, it is possible to prevent the inclination problem of the pixel regions PXR. Accordingly, it is possible to reduce the process failure in the process of manufacturing the image sensor. In addition, since the first trenches 130Ta and the second trenches 130Tb are formed by separate etching processes, it is possible to easily increase the aspect ratio of the pixel regions PXR. This can contribute to the improvement of the resolution and the sensitivity characteristics of the image sensor.

[0114] ​ is a plan view showing an image sensor according to an embodiment, and ​ is a cross-sectional view taken along ​ line B-B' of ​ cross-sectional views taken along lines A-A' and C-C' of ​ may be substantially the same as the cross-sectional view of ​ , ​ , ​ and ​ repetitive description of features which are the same as those of ​ , ​ , ​ and ​ will be mainly described below.

[0115] Referring to ​ in conjunction with ​ and ​ , a device isolation layer 130 can be disposed in the substrate 100 and between the pixel regions PXR. The device isolation layer 130 can extend in the first direction D1 between the first pixel row RO1 and the second pixel row RO2, and can extend in the second direction D2 to intervene between adjacent ones of the pixel regions PXR in the first pixel row RO1 and between adjacent ones of the pixel regions PXR in the second pixel row RO2. Portions of the device isolation layer 130 extending in the first direction D1 and the second direction D2 can be connected to form a single object. The device isolation layer 130 can include an isolation pattern 110 disposed to penetrate at least a portion of the substrate 100 and an insulating pattern 120 intervening between the isolation pattern 110 and the substrate 100.

[0116] A doped region 152 can be disposed in each of the pixel regions PXR and can extend along a side surface of each of the pixel regions PXR. In some embodiments, the doped region 152 can extend into a portion of the substrate 100 adjacent to a bottom surface 130B of the device isolation layer 130. The insulating pattern 120 can intervene between the isolation pattern 110 and the doped region 152 and can be in contact with the doped region 152.

[0117] ​ is a plan view showing a method of manufacturing an image sensor according to an embodiment, and ​ are cross-sectional views taken along lines A-A', B-B' and C-C' of ​ respectively. ​ are cross-sectional views taken along lines A-A', B-B' and C-C' of ​cross-sectional views taken along lines A-A', B-B', and C-C' to illustrate a method of manufacturing an image sensor according to an embodiment. For the sake of simplicity, repeated description of features identical to those of ​ and ​ will be omitted for brevity, and features different from those of ​ and ​ will mainly be described below.

[0118] Referring to ​ and Figures 34A to 34C , a first trench 130Ta can be formed in the substrate 100. The first trench 130Ta can extend in the first direction D1 and can be spaced apart from each other in the second direction D2. Forming the first trench 130Ta can include forming a first mask pattern (not shown) on the first surface 100a of the substrate 100 to have openings of exposed regions in which the first trench 130Ta is to be formed, and etching the substrate 100 using the first mask pattern as an etching mask. After forming the first trench 130Ta, the first mask pattern can be removed.

[0119] A mask layer ML can be formed on the first surface 100a of the substrate 100 to fill the first trench 130Ta. Thereafter, a second trench 130Tb can be formed in the substrate 100. The second trench 130Tb can be formed to cross the first trench 130Ta. As an example, the second trench 130Tb can extend in the second direction D2 and can be spaced apart from each other in the first direction D1. Forming the second trench 130Tb can include forming a second mask pattern (not shown) on the mask layer ML to have openings of exposed regions in which the second trench 130Tb is to be formed, and etching the substrate 100 and the mask layer ML using the second mask pattern as an etching mask.

[0120] The substrate 100 can include a plurality of pixel regions PXR defined by the first trench 130Ta and the second trench 130Tb. The pixel regions PXR can be two-dimensionally arranged in the first direction D1 and the second direction D2.

[0121] Referring to Figure 31 and Figures 35A to 35C , the mask layer ML can be removed after forming the first trench 130Ta and the second trench 130Tb. A first impurity region 160 can be formed in each of the pixel regions PXR, and a doped region 152 can be formed in side surfaces and a bottom surface of the substrate 100 exposed by the first trench 130Ta and the second trench 130Tb. The doped region 152 can be formed in a portion of the substrate 100 adjacent to inner surfaces and a bottom surface of the first trench 130Ta and the second trench 130Tb. The doped region 152 can be formed by the same method as that described with reference to Figure 5 ,Figure 6A and Figure 6B The first impurity region 160 and the doped region 152 are formed in substantially the same manner as described above, and thus repetitive description thereof will be omitted for brevity.

[0122] The device isolation layer 130 can be formed to fill the first trench 130Ta and the second trench 130Tb, respectively. The device isolation layer 130 can be formed in substantially the same manner as described above with reference to Figure 2 , Figure 7A and Figure 7B The device isolation layer 130 can be formed in substantially the same manner as described above, and thus repetitive description thereof will be omitted for brevity. The device isolation layer 130 can include the isolation pattern 110 disposed in the first trench 130Ta and the second trench 130Tb, and the insulating pattern 120 interposed between the isolation pattern 110 and the inner surface of each of the first trench 130Ta and the second trench 130Tb. Subsequent processes can be performed in substantially the same manner as described above with reference to Figure 2 , Figure 4A , Figure 4B , Figure 8A and Figure 8B Subsequent processes can be performed in substantially the same manner as described above, and thus repetitive description thereof will be omitted for brevity.

[0123] According to an embodiment, a tilt problem of the pixel region PXR can be prevented, and an aspect ratio of the pixel region PXR can be easily increased. Thus, process failure in a process of manufacturing the image sensor can be reduced, and optical characteristics (e.g., resolution and sensitivity) of the image sensor can be easily improved.

[0124] According to the various example embodiments described above, a tilt problem of the pixel region can be prevented, and an aspect ratio of the pixel region can be easily increased. Thus, process failure in a process of manufacturing the image sensor can be reduced, and optical characteristics (e.g., resolution and sensitivity) of the image sensor can be easily improved.

[0125] While example embodiments have been particularly shown and described, it will be understood by those of ordinary skill in the art that changes can be made to form and details without departing from the spirits and scopes of the appended claims.

Claims

1. An image sensor, comprising: The first pixel row includes the first pixels arranged in the first direction; The second pixel row includes a second pixel arranged in the first direction, and the first pixel row and the second pixel row are adjacent to each other in a second direction that intersects the first direction; A first support pattern is disposed between the first pixels and spaced apart from each other in the first direction; The second support pattern is disposed between the second pixels and spaced apart from each other in the first direction; The third support pattern and the device isolation pattern are disposed between the first pixel row and the second pixel row, and are arranged alternately and repeatedly in the first direction. Wherein, the first support pattern is connected to the first pixel. The second support pattern is connected to the second pixel. Each of the third support patterns is located between a first pixel in the first pixel and a second pixel in the second pixel, and is connected to the first pixel and the second pixel, wherein the first pixel and the second pixel are arranged in the second direction. In the first direction, each device isolation pattern extends between a pair of third support patterns to contact the pair of third support patterns, extends between a pair of first pixels to contact a corresponding first support pattern in the first support pattern, and extends between a pair of second pixels to contact a corresponding second support pattern in the second support pattern.

2. The image sensor according to claim 1, wherein, Each of the first support pattern, the second support pattern, and the third support pattern includes a first doped region extending along the side surface of the support pattern.

3. The image sensor according to claim 2, wherein, Each of the first pixel and the second pixel includes a second doped region extending along the side surface of the pixel, and The first doped region and the second doped region have the same conductivity type.

4. The image sensor according to claim 3, wherein, Each of the first pixel and the second pixel includes a photoelectric conversion region, and The second doped region is disposed between the photoelectric conversion region and the corresponding device isolation pattern in the device isolation pattern.

5. The image sensor according to claim 3, wherein, The first doped region and the second doped region contain the same impurities.

6. The image sensor according to claim 1, wherein, Each of the device isolation patterns has a cross-shaped pattern when viewed in a plan view.

7. The image sensor according to claim 6, wherein, Each of the device isolation patterns includes: An isolation pattern, situated between the pair of third support patterns, and extending between the pair of first pixels and between the pair of second pixels; and An insulating pattern is located between the isolation pattern and each of the pair of third support patterns, between the isolation pattern and the corresponding first support pattern, and between the isolation pattern and the corresponding second support pattern, and extends between the isolation pattern and the pair of first pixels and between the isolation pattern and the pair of second pixels.

8. The image sensor according to claim 7, wherein, The isolation pattern includes semiconductor materials or metallic materials.

9. The image sensor according to claim 1, further comprising: The substrate includes the first pixel and the second pixel. Each of the first pixel and the second pixel includes: A portion of the substrate; and A photoelectric conversion region is disposed in said portion of the substrate, and Each of the first support pattern, the second support pattern, and the third support pattern is another part of the substrate.

10. The image sensor according to claim 9, wherein, Each of the device isolation patterns is disposed in the substrate, and the substrate extends along the bottom surface of the device isolation pattern to connect the first pixel and the second pixel to the first support pattern, the second support pattern and the third support pattern.

Images