Channel Design Based on Transform Domain Analysis

Abstract

The present application discloses a channel design based on transform domain analysis. A system and method for improving data channel design by applying transform domain analysis to more reliably extract user data from a signal is disclosed. In some embodiments, a device may include a channel circuit configured to receive an analog signal at an input of the channel circuit and sample the analog signal to obtain a signal sample set. The channel circuit may further apply a filter configured to perform transform domain analysis on the signal sample set to generate a first subset of samples, the first subset including fewer transitions than the signal sample set and having a higher signal-to-noise ratio (SNR) than the signal sample set. The channel circuit may detect a first bit transform domain representation value from the first subset, and determine a channel bit value encoded in the analog signal based on the signal sample set and using the first bit transform domain representation value detected from the first subset as auxiliary information.

Description

Summary of the invention

[0001] In certain embodiments, an apparatus includes an analog-to-digital converter (ADC) configured to convert an analog signal into a digital sampling sequence; and a circuit configured to perform a transform domain analysis on the digital sampling sequence. The circuit may include a first transform domain analysis filter configured to apply a transform analysis signal to a received sampling sequence to produce a first transformed sampling sequence having a higher signal-to-noise ratio (SNR) than the received sampling sequence. The circuit may further include a first detector configured to detect a bit sequence transform domain representation from the first transformed sampling sequence; and a second detector configured to determine a sequence of user bits corresponding to the analog signal based on the digital sampling sequence and the bit sequence transform domain representation.

[0002] In certain embodiments, a method includes improving bit detection from a received analog signal at a data channel circuit, including converting the analog signal into a set of digital samples; and decomposing the set of digital samples by applying a transform domain analysis filter using N sequence transform domain nodes of the data channel circuit, starting from a first transform domain node and ending at an Nth transform domain node. For a current transform domain node n=N, the method may include detecting an Nth transform domain bit sequence representation having a higher signal-to-noise ratio (SNR) than the digital sample set based on a decomposed sample set received from an N-1th transform domain node. The method may include decrementing the current transform domain by one so that n is set to n-1. For a current transform domain node n, the method may include detecting an nth transform domain bit sequence representation based on a decomposed sample set received from an n-1th transform domain node and a transform domain bit sequence representation received from an n+1th transform domain node. The method may include detecting a user data bit sequence based on the digital sample set and the transform domain bit sequence representation received from an n=1 transform domain node.

[0003] In some embodiments, an apparatus may include a channel circuit configured to receive an analog signal at an input of the channel circuit and sample the analog signal to obtain a signal sample set. The channel circuit may further apply a filter configured to perform a transform domain analysis on the signal sample set to generate a first subset of samples, the first subset including fewer transitions and a higher signal-to-noise ratio (SNR) than the signal sample set; detect a first bit transform domain representation value from the first subset; and determine a channel bit value encoded in the analog signal based on the signal sample set and the first bit transform domain representation value detected from the first subset. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1is a diagram of a system implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0005] Figure 2 is a diagram of a system implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0006] Figure 3 is a diagram of a system implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0007] Figure 4 is a diagram of a system implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0008] Figure 5 is a diagram of example results from an implementation of transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0009] Figure 6 is a diagram of example results from an implementation of transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0010] Figure 7 is a diagram of a system implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0011] Figure 8 A flowchart depicting an example method of transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0012] Fig. 9 is a diagram of a system implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0013] Fig.10 is a graph of equalized signal-to-noise ratio (SNR) distribution at different domain nodes in a transform domain analysis-based channel implementation according to certain embodiments of the present disclosure;

[0014] Fig.11 is a set of graphs of SNR distribution at different domain nodes in a channel implementation based on transform domain analysis according to certain embodiments of the present disclosure;

[0015] Fig.12 is a flow chart of an example method of transform domain analysis based channel design and application according to certain embodiments of the present disclosure;

[0016] Fig.13 is a diagram of a system implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure;

[0017] Fig.14A flowchart depicting an example method of transform domain analysis based channel design and application according to certain embodiments of the present disclosure;

[0018] Figure 15(a) and 15(b) are multiple groups of graphs of channel bit combinations from different channels in a transform domain analysis-based channel implementation according to certain embodiments of the present disclosure;

[0019] Fig.16 is a set of graphs of bit combinations with reduction of redundant bits in a channel implementation based on transform domain analysis according to certain embodiments of the present disclosure;

[0020] Fig.17 A flowchart depicting an example method of transform domain analysis based channel design and application according to certain embodiments of the present disclosure;

[0021] Fig.18 A flowchart depicting an example method of transform domain analysis based channel design and application according to certain embodiments of the present disclosure;

[0022] Fig.19 is a diagram of a system implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure; and

[0023] Fig. 20 is a diagram of a system implemented using transform domain analysis based channel design in accordance with certain embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] In the following detailed description of certain embodiments, reference is made to the accompanying drawings, which form a part of the embodiments and are shown in these drawings by way of illustration of example embodiments. It should also be understood that features of the embodiments and examples herein may be combined, exchanged or removed, other embodiments may be utilized or created, and structural changes may be made without departing from the scope of the present disclosure.

[0025] According to various embodiments, the methods and functions described herein may be implemented as one or more software programs running on a computer processor or controller. Special hardware implementations include, but are not limited to, application specific integrated circuits, programmable logic arrays, and other hardware devices, which may also be constructed to implement the methods and functions described herein. The methods and functions may be performed by modules or nodes, which may include one or more physical components (e.g., logic, circuits, processors, etc.) of a computing device configured to perform a specific task or job, or may include instructions that may cause a processor to perform a specific task or job when executed, or any combination thereof. In addition, the methods described herein may be implemented as a computer-readable storage medium or memory device, which includes instructions that cause a processor to perform these methods when executed.

[0026] Figure 1 is a diagram of a system (generally referred to as 100) implemented using transform domain analysis-based channel design according to certain embodiments of the present disclosure. Specifically, Figure 1 A design flow for an example data channel architecture, such as a read channel for a hard disk drive (HDD) application, is shown. Although many examples and descriptions of data channels for data storage devices are provided herein, the principles of channel design based on transform domain analysis can be applied to other signal processing channels, such as channels for processing wireless communication signals in telephones, radios, or similar devices. For example, references to writing data can apply to transmitting information, while references to reading data can apply to receiving transmitted signals.

[0027] like Figure 1As shown, data to be written to the storage medium can be received as user bits in chunks of fixed-length blocks, such as having a size corresponding to a data storage sector (e.g., having a length of 512 bytes, 1 kilobyte (kB), 4kB, etc.). The user bits can be encoded using an error correction code (ECC) encoder 102, which adds redundant data to protect the sector in the event of a bit error. If some bits are not successfully detected during a read operation, the ECC data can be used to recover the lost bits. The encoded bits (sometimes referred to as channel bits) can then be written to the surface of a magnetic storage medium (e.g., a hard disk) using a magnetic writer (referred to as a write head) and read back using a magnetic reader (referred to as a read head) when data from the sector is needed. In system 100, the read and write heads and the storage medium are depicted as transmitter / receiver / medium 104. In non-HDD applications, transmitter / receiver / medium 104 may refer to an antenna for sending and receiving wireless signals over an air medium, a system for reading and writing data to a solid-state data storage medium, or other applications for data channels as described herein.

[0028] The output from the read head 104 (sometimes referred to as the readback signal) then passes through (multiple) analog front end (AFE) filters 106 to shape the signal in the analog domain and also filter out signals outside the Nyquist band. The filtered signal is provided to an analog-to-digital converter (ADC) 108, which periodically samples the analog signal to generate a sequence of digital sample values ​​(sometimes referred to as a baud rate sampled readback signal or baud_rate_rb). The sample values ​​can then be equalized to a target response at an equalizer 110 and passed through a detector 112, which is designed to match the target response and detect bit values ​​from the sample sequence. Finally, the detected bits can be sent to an ECC decoder 114 to eliminate any bit errors to extract user bits. In some embodiments, the same channel can be used to write and read data (or send and receive data), and the ECC encoder 102 and the ECC decoder 114 can be a single ECC encoder / decoder unit that encodes and decodes data.

[0029] Magnetic recording channels can be described in terms of normalized density (ND), which can be defined as PW50 / T, where (pulse width) PW50 is a measure of the resolution of the along-track reader and T defines the width of the bit. Therefore, ND can be used as a measure of the system resolution. The noise sources of the magnetic recording channel can also be characterized by various metrics, two examples of which are provided herein for illustrative purposes. One example is the electronic signal-to-noise ratio (eSNR), which can define the amount of noise independent of the data, with one major source being the noise from the reader element. On the other hand, jitter noise is the main source of noise in magnetic recording, which can be used as a measure of data-dependent noise and can be observed at bit transitions (e.g., a change in the recorded data symbol represents a change in the bit from 1 to 0 and vice versa). The amount of jitter can show how much the position of the transition is offset from the expected position, and head field gradients (together with the thermal gradients generated by the laser in heat-assisted magnetic recording (HAMR) systems) and grain size can be the main sources of jitter noise.

[0030] The digitized readback signal (baud rate_rb, output from ADC 108) can be equalized to a target response at an equalizer 110. Intersymbol interference (ISI) can be a form of distortion in a signal where one symbol interferes with the detection of subsequent symbols, and the target response can refer to a form of estimated ISI that the system uses to compensate for the actual ISI during reading. The equalizer 110 and the target response can be designed together, and for a given sufficiently long equalizer length (e.g., the length of the equalizer refers to a number of filter coefficients or "taps" of the equalizer), the length of the target response can define the equalized SNR (Eql_SNR) input to the detector 112 and the complexity of the detector 112. The longer the target response, the higher the equalized SNR can be, but the complexity of the detector 112 can increase exponentially. For example, the detector 112 can be a data-dependent noise prediction (DDNP) detector, which can have filters at the branches of the detector to estimate data-dependent noise, which can become very complex.

[0031] This information provides some key observations. First, the system resolution defined by ND can cause the magnetic recording channel to filter out bit transitions from signal components, thereby acting as a low-pass filter for the signal. Second, jitter (the main noise source in channel 100) can be the result of bit transitions. In the noise-free digitized readback signal (baud rate_rb), high signal volume and very small jitter noise can be observed in the absence of bit transitions, and high jitter noise and low signal can be observed in the presence of bit transitions.

[0032] The equalizer 110 and the target response can be designed to take into account all of the signal and bit spectra present in the sector to optimize Eql_SNR. Signal components corresponding to many transitions can be a challenge because they have less signal energy and more noise to equalize. These signal components can define the bit error rate (BER) at the output of the detector 112, which in turn can define the amount of ECC redundancy required to reliably read the data, thereby defining the format efficiency (the amount of user data that can be accommodated on the storage medium). Therefore, signal components with many transitions can ultimately define the areal density capability (ADC) of the HDD. Processing these components together with other signal components, rather than processing different components differently, can limit the system's ability to reliably read back data without a large amount of ECC, and therefore can limit the drive's ADC.

[0033] Therefore, the channel 100 may be configured to include a transform domain analysis module (TDAM) 130. Applying transform domain analysis in the data channel may improve the channel's ability to manage bit transitions and improve the BER at the output of the detector 112 and the functionality of the data channel. Figure 2 Transform domain analysis is described in more detail.

[0034] Figure 2 is a diagram of a system (generally referred to as 200) implemented using transform domain analysis-based channel design according to certain embodiments of the present disclosure. Specifically, Figure 2 The application of transform domain analysis of a signal via multiple analysis filters and synthesis filters is shown to illustrate how the signal can be decomposed and recovered without losing information. Figure 2 The system 200 can be used in a data channel (such as Figure 1 is implemented in channel 100).

[0035] The concept of wavelet transform is used as an example to better explain the proposed design options. The concept of wavelet transform is based on a wavelet kernel, which can be of many types and can be designed for a given application. Here, the Haar (Daubechies 1) wavelet kernel is used as an example.

[0036] Figure 2 It is shown that an input signal 202 having 256 samples is decomposed into 2 orthogonal signal sets 204 and 206, each with 128 samples, using 2 orthogonal wavelet analysis signals (corresponding to the Haar kernel). Using those orthogonal signal sets 204 and 206, the input signal 202 can be perfectly synthesized into an output signal 226.

[0037] The input signal 202 may correspond to an example channel bit sequence of known values. The two orthogonal wavelet analysis signals may be implemented as two analysis filters 208 and 210 and two downsamplers 212. Analysis Filter A L 208 may represent a low pass filter with low frequency focus, while the analysis filter A H 210 may represent a high pass analysis filter with high frequency focus. To avoid increasing the total number of samples from the input signal 202 to the orthogonal signal sets 204, 206, the signal output from each analysis filter 208, 210 may be passed through a downsampler 212. The downsampler 212 may be configured to discard every other sample from the signal so that each of the orthogonal signal sets 204 and 206 has half the samples of the input signal 202. The process of applying transform domain analysis (e.g., analyzing the signal via an orthogonal wavelet) and downsampling the input signal may be referred to as transforming or decomposing the signal.

[0038] To reconstruct the input signal 202 at the output 226, each of the orthogonal signal sets 204, 206 may be passed through an upsampler 214, which may add zero samples, each of which is discarded by the downsampler 212. L The low-pass signal 208 can then be synthesized by a low-pass synthesis filter S L 220 processing, and from A H The high-pass signal 210 can be synthesized by a high-pass synthesis filter S H 222. The outputs of the two synthesis filters 220, 222 may be combined at a summing node 224 to output a synthesized signal 226. The analysis filters 208, 210, the synthesis filters 220, 222, the downsampler 212, and the upsampler 214 may be referred to as nodes or modules and may be implemented via circuits, executable code, or a combination thereof. In some examples, the combination of the analysis filter and the corresponding downsampler may be collectively referred to as a transform domain analysis node or module. Figure 3 discuss Figure 2 extension of the design.

[0039] Figure 3 is a diagram of a system (generally referred to as 300) implemented using transform domain analysis-based channel design according to certain embodiments of the present disclosure. Specifically, Figure 3 Shows how to Figure 2 Additional analysis filters are applied after the first group shown, resulting in multiple nested filters and branching paths. System 300 can be used on data channels such as Figure 1 is implemented in channel 100).

[0040] By adding a further branched transform domain analysis path after the initial set of analysis filters 308, 310, it is possible to obtain Figure 3 . Each branch of the signal may be referred to as a separate branch, path, or channel. In some embodiments, the path may be indicated by the corresponding high-pass and low-pass analysis filters through which the signal passes. For example, Figure 3 The top path has a first low pass filter A L 308 passes through and then passes through the second low pass filter A L The signal transmitted by 312 can therefore be referred to as branch A LL .at the same time, Figure 3 The second path has a first low-pass filter A L 308 passes through and then passes through a high pass filter AH 314 transmits the signal, so it can be called branch A LH Since each additional branch includes another analysis filter and downsampler, after two branches, the number of samples in each signal set can be further reduced to 1 / 4 of the original size of the input signal 302 (or for this example, from 256 samples to 64 samples).

[0041] Figure 2 The example input signal 202 corresponds to an example channel bit sequence. Figure 3 , the input signal 302 may instead include an example digitized sample sequence received from an ADC (such as from Figure 1 The baud rate received by the ADC 108 is _rb) to show how the readback signal corresponding to the channel bits shown earlier looks on those domains. Figure 3 In the depicted example, the readback signal may correspond to a system with ND=2, eSNR=20 dB, and a jitter of 20%.

[0042] Using the described wavelet transform, the readback signal samples corresponding to bits that have no transitions (eg, have more signal and less noise) can be represented primarily by A L On the other hand, samples corresponding to bits with transitions (e.g., with less signal and more noise) may be transmitted primarily through A H This behavior becomes more apparent after two nested transform domain nodes, where the readback sample domain representation 316 is in A LL The path is close to the channel bit domain representation (e.g., has a very strong signal), and the sample domain representation 318 is at A HLThe path deviates from the channel bit domain representation in the opposite situation (e.g., has very low signal and is mainly noise). In the sample domain representation depicted, the vertical line represents a single sample value (e.g., the channel bit domain representation), while the plotted line represents the signal amplitude (e.g., the channel response domain representation). The plotted signal amplitude line has a higher absolute value relative to the x-axis, indicating a stronger signal amplitude than where the line has a lower absolute value. It can be seen that A LL The plotted line of the sampling domain 316 shows high signal amplitudes, while A HL The 318 sample domain shows very low signal amplitudes. It can be noted here that an actual bit can have two values ​​(e.g., 0 and 1, or -1 and 1), while various domain representations can have a larger range of potential values. Transform domain representations as discussed herein can correspond to bit values ​​in the underlying user data, but those representations can be expressed via more than two values ​​per sample or representation.

[0043] The Equalized SNR (Eql SNR) values ​​also show this trend, with the Eql SNR value at A LL The highest point is at node 312, while at A HL The signal level is lowest at node 320. For example, the input signal 302 in this example may have an Eql SNR of 8.11 dB (decibels), where a higher dB value indicates a stronger signal amplitude. L At node 308, Eq1 SNR increases to 8.25 dB, while at A H At node 310, Eql SNR decreases to 3.29, reflecting that the signal samples with fewer transitions are mainly along A L path, while signal samples with more transitions are mainly along A H The highest signal amplitude can be found at A in the next transform domain. LL Found at node 312, it is 8.69dB, while the lowest signal amplitude can be found at A HL Found at node 320, it is 1.28dB.

[0044] At some domain nodes, it can also be observed that the target length is reduced from the equalization target (EqlTarget) [0.83 0.55 0.09] of the input signal 302. For example, in this example, A LH The target at node 314 may be equal to [0.99 0.01 0.05], which may be practically implemented using a tap filter (e.g., a threshold detector or a peak detector instead of a Viterbi detector). HL [0.99-0.11-0.01] at node 320 can be reliably achieved using 2 taps instead of 3 taps, and can still be achieved with high confidence using a single tap filter.

[0045] To detect bit values ​​from the signal samples, an equalizer 322 and a detector 324 may be added at one or more points along the path(s). For example, the equalizer 322 and the detector 324 are depicted as being included after the transform domain node after the second branch. In some embodiments, the equalizer 322 and the detector 324 may be added only along certain branches other than the high SNR branch and the low SNR branch (such as the high SNR branch A). LL , or low SNR branch A HL ) to add the equalizer 322 and detector 324. The equalizer 322 and detector 324 may also be included at an intermediate point along the branch path, such as at A L After node 308 but before A LL Node 312 or A LH Node 314. The required complexity of the equalizer and detector may be different at different points along the channel. For example, the equalizer and detector for the low signal amplitude path may need to be more complex than the equalizer and detector along the high signal amplitude path to obtain useful information. In another example, the equalizer and detector included after a single transform domain analysis node may need to be more complex than the equalizer and detector included after a three nested domain node. Figure 4 Further expanded Figure 3 Transform domain analysis channel implementation.

[0046] Figure 4 4 is a diagram of a system (generally referred to as 400) implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure. Specifically, Figure 4 shows that another additional layer of branching paths is added to Figure 3 , and shows the SNR distribution associated with each node at this layer. It can be seen that along the A including nodes 408, 412 and 415 LLL The Eql SNR of the path has increased to 10.20dB, while the path A with the lowest performance HLL The signal amplitude of the input signal is only 1.01dB. At very low signal amplitudes, it is unlikely that the path will provide any useful information about the input signal.

[0047] Figure 4 Also shown is a method for referencing the sample domain representation derived at each node of the branching path. Following the low pass filter branch may add "a" to the representation, while following the high pass filter branch may add "d" to the representation. For example, in A L The baud rate readback signal at the node can be represented by baud rate_rb a, while in A LHThe representation of the baud rate readback at the node can be baud rate_rb ad. Similarly, if the input is a channel bit sequence instead of a baud rate readback signal, then A HL The representation at the node may be the channel bit da. The branches themselves may also be referred to according to the "a" and "d" nomenclature, such as by referring to the channels or branches aa, ad, etc.

[0048] Now transfer to Figure 5 , a diagram showing example results from an implementation of a transform domain analysis-based channel design according to certain embodiments of the present disclosure. Specifically, Figure 5 The electronic SNR (eSNR) versus the equalized SNR (Eql SNR) at the signal domain and at the low pass filter branch of the transform domain analysis channel are plotted for ND = 2, 2.5 and 3 when jitter = 20% of the bit length. The signal domain results for ND 2.0, 2.5 and 3.0 are represented by the graph lines with small hash marks, generally showing the lowest Eql SNR relative to the eSNR. The results for the AL nodes, e.g., DWT (Discrete Wavelet Transform) a, are represented by the graph lines identified with squares. A LL The results for a node, e.g., DWT aa, are represented by graphical lines marked with triangles. LLL Results for nodes, eg, DWT aaa, are represented by graphical lines identified by diamond shapes.

[0049] As shown in the figure, it can be observed that the deeper nested transform domain (A L →A LL →A LLL ) increases because more noise is averaged. Additionally, the figure shows that the impact of ND is smaller at the nested transform domain because blocks of 2, 4 or 8 bits are detected instead of every bit in the signal domain. Figure 6 It is shown that the same results hold when jitter = 30% of bit length.The following figures provide example architectures and methods for applying transform domain analysis in a read channel.

[0050] Figure 7 is a diagram of a system (generally referred to as 700) implemented using transform domain analysis-based channel design according to certain embodiments of the present disclosure. Specifically, Figure 7 It is shown how to use transform domain analysis to extract auxiliary information for channel detection. Figure 1 An example transform domain analysis module (TDAM) 730 of the TDAM 130 can be added to a standard channel architecture with minimal changes. The TDAM 730 can improve channel performance by providing additional auxiliary information for improving detector performance.

[0051] System 700 may include segments of a data channel (such as a read channel) corresponding to Figure 1 The system 700 may include an AFE filter 706 that may receive an analog signal, such as a readback signal from a read head element. The AFE filter 706 may pass the processed analog signal to an ADC 708, which may periodically sample the analog signal to output a sequence of digital samples, such as a baud_rate_rb signal. An equalizer 710 may receive and equalize the baud_rate_rb signal, which may be passed to a detector 712 to detect a bit sequence corresponding to channel bits recorded to a storage medium.

[0052] In the example of system 700, additional transform domain analysis nodes may be added to determine additional auxiliary information that may be provided to the detector 712 to improve its ability to detect the correct bit sequence from the equalized sample sequence. For example, the baud_rate_rb signal may be provided from the ADC to a first discrete wavelet transform (DWT) node 716, which may correspond to a first low pass analysis filter (and may include an associated down sampler), such as Figure 4 408 of the embodiment of the present invention. Therefore, DWT 716 can output a baud_rate_rb_a sample set, which should produce a higher SNR than the basic baud_rate_rb sample set. In a first example, DWT 716 can be the only analysis diagram added to system 700, and the baud_rate_rb_a signal can be passed to equalizer 717 and then to detector 718 to detect the first transform domain analysis set of channel_bit_a. Detector 718 can provide channel_bit_a as auxiliary information to detector 712, improving the ability of detector 712 to detect actual channel bits from the equalized baud_rate_rb signal.

[0053] The system may be further improved by adding additional layers of transform domain analysis nodes. For example, DWT 716 may provide a baud_rate_rb_a signal to a second DWT 720, which may correspond to a second low pass analysis filter such as Figure 44. The DWT 720 may output a second transform domain analysis sample set baud_rate_rb_aa, for example, to an equalizer 721 and a detector 722, which may output a second transform domain analysis set of channel_bits_aa. The channel_bits_aa may be passed to the detector 718 as auxiliary information to improve the detection of the channel_bits_a of the baud_rate_rb_a signal from the first DWT 716, and the improved channel_bits_aa may be provided to the detector 712 as auxiliary information. A further transform domain analysis layer may be added, such as a third DWT 724 to produce baud_rate_rb_aaa, which may be provided to the equalizer 724 and the detector 726 to output a third set of transform domain analysis channel_bits_aaa, which may be provided to the detector 722 as auxiliary information. Each additional transform domain analysis layer may generate an output with a higher equalized SNR, which may be provided to the previous layer to improve detector performance. Figure 8 Provided by Figure 7 The illustrated architecture performs an example method.

[0054] Figure 8 A flow chart of an example method 800 for channel design based on transform domain analysis according to certain embodiments of the present disclosure is depicted. Specifically, Figure 8 An example method is depicted for improving the ability of a channel to detect channel bits from a readback signal using one or more transform analysis nodes or modules. Method 800 may be performed via a data channel, such as via Figure 7 The transform domain analysis module (TDAM) 730 is used to perform the above operation.

[0055] Method 800 may include, at 802, decomposing a received signal using N transform domains, where the current transform domain n=N. The transform domain may refer to a layer of transform analysis modules. For example, Figure 2 A system can have a single transform domain (e.g., A L / A H ), Figure 3 The system may include two transform domains, and Figure 4 The system can include three transform domains. Figure 4 and Figure 7 In the example of LLL The domain of the node.

[0056] At 804, method 800 may include detecting a transform domain bit at a node having a transform domain n with a highest SNR based on the decomposed readback signal at the node. Figure 4 and Figure 7 In the example, the node with the highest SNR in each domain can be connected along A L →A LL →A LLL Path. Figure 7 At the highest domain of the transform domain, the decomposition and decoding signal at the third transform domain node can refer to baud_rate_rb_aaa, and generating transform domain bits can refer to generating channel_bits_aaa.

[0057] At 806, method 800 may include decrementing the current transform domain so that n=n-1. Then, method 800 may include detecting a transform domain bit (e.g., channel_bit) at the highest SNR node of domain n based on the decomposed readback signal at the current node and the detected bit from domain n+1 as auxiliary information at 808. Thus, at Figure 7 In the example of , at the second transform domain, channel_bit_aa may be generated based on baud_rate_rb_aa and channel_bit_aaa as auxiliary information.

[0058] At 810, it may be determined whether there are any remaining transform domains (e.g., n>1?). If so, the method may return to 806 and decrement the current transform domain by one. If there are no remaining transform domains, at 810, method 800 may include determining the number of transform domains based on the received signal and the detected bits from domain n (e.g., Figure 4 The channel bits can be provided to the ECC decoder or used by the system in other ways. Next, Fig. 9 Another example architecture for applying transform domain analysis based channel design is provided.

[0059] Fig. 9 is a diagram of a system (generally referred to as 900) implemented using transform domain analysis-based channel design according to certain embodiments of the present disclosure. Specifically, Fig. 9 An architecture for extracting user information from a signal using transform domain analysis is shown.

[0060] The example design path of system 900 is not as follows Figure 7 The illustrated method does not extract auxiliary information for use by a channel detector in detecting user bits, but focuses on extracting user bits or channel bits at the transform domain. In this example, a discrete wavelet transform may be used for transform domain analysis, so that the transform domain may be a discrete wavelet transform (DWT) domain. Fig. 9 The use of nested transform domains up to a depth of 3 is shown. Fig. 9 As shown, the transform domain may include corresponding analysis filters and synthesis filter banks. For example, transform domain 1 may include analysis filter A L and A H , and the synthesis filter S Land S H The transform domain 2 may include an analysis filter A LL , A LH , A HL and A HH , and the synthesis filter S LL , S LH , S HL and S HH Etc. According to examples herein, the higher the transform domain number, the deeper it is "nested" in the architecture, so for N nested domains, domain "N" is the deepest or highest domain. In the depicted example, all three transform domains may be included in a transform domain module or circuit.

[0061] As described above, some branches of the signal path through the transform domain will result in signals having equalized SNR values ​​higher than the original signal, while other branches will result in signals having equalized SNR values ​​significantly lower than the original signal. Fig.10 The distribution of equalized SNRs at different domain nodes in each transform domain up to a depth of 6 is shown. The first value 1002 may correspond to the equalized SNR of the original input signal (e.g., a sequence of digital samples from an ADC) that has not been processed by any transform domain node. 1 The value can be compared with the first transform domain (e.g., transform domain node A L and A H ) corresponds to the equalized SNR value of the decomposed signal at . 3 The value can be compared with the equalized SNR value at the transform domain with a depth of 3 (such as Fig. 9 The values ​​shown in (e.g., from transform domain node A LLL To A HHH Finally, DWT 6 The values ​​may correspond to equalizer SNR values ​​at six transform domain depths, which amounts to sixty-four taps and associated equalized SNR values. Fig.11 The equalized SNR values ​​for six different nested transform domain depths are plotted in .

[0062] Back to Fig. 9 , a signal S 902 may be received at the transform domain 1. The signal S 902 may correspond to a baud_rate_rb signal or a sampling sequence from an ADC. At the transform domain 1, the signal S may be filtered by an analysis filter A L and A H and associated downsamplers to generate two sub-signals (e.g., baud_rate_rb_a and baud_rate_rb_d, respectively) having half the samples of signal S 902. The sub-signals may be provided to transform domain 2 where they are further subdivided as they propagate through the analysis filter of the nested transform domain.

[0063] In the deepest DWT domain (e.g., transform domain 3), the sub-signals on each branch may be provided to an equalizer 908 and a detector 910 to determine the sequence of bit value transform domain representations from the sub-signals. The sequence of values ​​detected by the detector 910 may exhibit similarities to, for example, Fig.10 DWT in 3 Example values ​​for domain 1006 and Fig.11 The equalized SNR corresponding to the three-nested DWT graph of . The value determined by the detector 910 (and potentially decoded by the decoder 912, as described below) may be a domain representation of a transform domain (such as transform domain 3).

[0064] In some examples, in addition to the equalizer 908 or the detector 910, an ECC decoder 912 may be included on one or more branches. A channel architecture that includes an ECC decoder 912 along a transform domain branch may employ a multi-stage ECC design that may include initially encoding the data with a coding scheme that may be decoded after traversing the transform domain analysis filter. However, an architecture without an ECC 912 may employ other conventional binary ECC designs (e.g., decoding at the ECC 904) to recover the user bits. In some embodiments, some branches will include an ECC decoder 912, while other branches (e.g., branches with very high SNR or very low SNR) may not include an ECC decoder 912.

[0065] A branch or channel with a lower equalized SNR value may require a more complex detector than a branch or channel with a high equalized SNR value. During the channel design process, a threshold value can be established for the equalized SNR value to determine how to design the channels at different branches. Fig.11 The six nested DWT diagrams explain the thresholds in more detail. The diagram includes a first threshold, Threshold 1, for low SNR channel results, and a second threshold, Threshold 2, for depicting high SNR channel results. The values ​​of Threshold 1 and Threshold 2 can be determined during the design phase of the channel and can be stored in RAM or other memory for use by the channel at runtime. In other examples, Threshold 1 and Threshold 2 can be used as a basis for designing the channel (e.g., where to include a detector, etc.) so that the thresholds do not need to be referenced by the channel itself.

[0066] A first threshold, Threshold 1, may be defined such that decoding information below this SNR value requires impractical or undesirable detector complexity and ECC redundancy. The channel producing the signal with the lowest equalized SNR corresponds to the plot point below Threshold 1. The DWT domain representation (e.g., the sample output at the corresponding transform domain) corresponding to the SNR below Threshold 1 may be erased, discarded, or never collected. In some examples, the sample values ​​of the branches with SNR below Threshold 1 may be set to "0", and those branches may be designed not to include an equalizer, detector, or decoder, because it may be impractical to obtain useful information from those branches.

[0067] A second threshold, Threshold 2, can be defined so that the detection performance above the SNR value meets the selected performance parameters with reasonable detector complexity, and ECC redundancy and decoding may not be required. Therefore, DWT domain representations with SNR above Threshold 2 can be detected, but may not require any decoding, so those branches may not include an ECC decoder.

[0068] DWT domain representations with SNRs between threshold 1 and threshold 2 may be detected and decoded. In embodiments without an ECC decoder 912 that analyzes the channel along the transform domain, threshold 2 may not be needed and the signal may be detected along the branch without decoding. In either case, the transform domain representation output from the detector or decoder may be passed through an upsampler and synthesis filter to reassemble the signal and produce the current transform domain output.

[0069] In a subsequent continuous domain (e.g., at transform domain 2), a DWT domain representation of the signal may be made based on the detected (and optionally decoded) representation from a deeper transform domain (e.g., transform domain 3). For example, within the DWT domain representation of the current transform domain, any single sample value that exceeds an acceptable sample value range may be discarded or replaced with a value of 0. The comparison of the value to the acceptable value range may be performed at the synthesis filter, or in another module or circuit after the synthesis filter at each transform domain.

[0070] After processing all transform domains, the output signal value can be in the signal domain. In the signal domain, you can get the DWT 1 The output of the domain generates channel bits 906. Again, any values ​​outside the selected value range may be erased or replaced with a set value. Channel bits 906 can be provided to ECC 904. ECC 904 can decode channel bits 906, perform any necessary error correction, and output user bits. For example, ECC decoder 906 can apply erasure coding to recover erased bits, and can apply list decoding and error detection (e.g., cyclic redundancy check, CRC) codes to determine user bit values. Reference Fig.12A method for employing the architecture of system 900 is described.

[0071] Fig.12 A flow chart of an example method 1200 for transform domain analysis based channel design and application according to certain embodiments of the present disclosure is depicted. Specifically, Fig.12 An example method of designing a channel to extract user data from a readback signal using transform domain analysis is depicted. Method 1200 may be performed to design and utilize a data channel such as Fig. 9 The channel architecture.

[0072] At 1202, method 1200 may include decomposing a received signal using "N" nested transform domains. A current transform domain "n" may be set equal to the deepest of the nested transform domains, n=N. Method 1200 may include, at 1204, setting an SNR threshold of 1 for a minimum equalized SNR level on a transform domain representation output from a transform domain node, and erasing transform domain representations having SNR levels below threshold 1. During channel design, the performance of various branches may be tested to determine which branches output results below threshold 1. The channel may be configured to erase, ignore, or not generate outputs of branches with results below threshold 1.

[0073] At 1206, method 1200 may include setting an SNR threshold 2 for domain representations with high SNR levels, such that detection performance above the SNR threshold meets selected performance parameters with reasonable detector complexity. Transform domain representations above threshold 2 may be detected. Method 1200 may include detecting and decoding transform domain representations between threshold 1 and threshold 2 at 1208. From a channel design perspective, the SNR levels of the outputs of the various branches may be used to determine the placement of the detector and decoder, as well as to determine the complexity of the detector and decoder that produces acceptable results. At 1210, the current transform domain may be reduced by one, such that n=n-1.

[0074] The method 1200 may include forming a transform domain representation at the current transform domain based on a transform domain representation from a deeper domain (e.g., from domain n+1) at 1212. Forming the transform domain representation may include generating a set of sample values. At 1214, sample values ​​in the transform domain representation that exceed a selected acceptable range may be erased or replaced with a default value.

[0075] At 1216, method 1200 may include determining whether there are more transform domains remaining (e.g., n>1). If so, then at 1210, the current domain is decremented by one. If no additional transform domains remain, then at 1218, method 1200 may include forming bits using the transform domain representation from domain 1. At 1220, bits that exceed a selected acceptable range may be erased or replaced with a default value. Then, at 1222, ECC may be applied to recover the erased or erroneous bits, and the corrected bit sequence may be output as user bits. Fig.13 Another example implementation of read channel design based on transform domain analysis is discussed.

[0076] Fig.13 1 is a diagram of a system (generally referred to as 1300) implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure. Specifically, Fig.13 An architecture for using transform domain analysis to polarize signals and noise in order to extract user information from the signal is shown. System 1300 may include Figure 1 Example of TDAM 130.

[0077] If the equalized SNR value is Fig.11 The data points in Fig.10 If the equalizer SNR values ​​in are sorted, the plots reveal that the wavelet transform domain can polarize the signal and noise in the system, and this effect is reflected in the SNR values. This polarization can be used for channel design by freezing channels (e.g., transform domain analysis nodes) that exhibit very low SNRs, as those channels may be limited in their ability to obtain useful information about the underlying signal. On the other hand, channels (nodes) with very high SNRs can provide more information and can be detected using simple detection algorithms rather than complex detectors. The detected and frozen information can be propagated to higher nested domains.

[0078] exist Fig.13 In the architecture, system 1300 includes two nested domains and can freeze A exhibiting approximately 1dB of equalized SNR. HL As discussed herein, “freezing” a channel may refer to ignoring or discarding data from the frozen channel and replacing it with data derived from one or more other channels (eg, one or more channels exhibiting a high SNR).

[0079] In the example of system 1300 that does not include ECC blocks and no error correction coded redundant data, freezing one of the four channels results in a code rate of 3 / 4. The code rate can refer to the amount of useful data (e.g., "user data") over the total amount of data, and any data other than the useful data is "useless" redundant data. For example, error correction redundant bits can be considered "useless" data, so a system that uses one redundant bit for every seven user ("useful") bits can have a code rate of 7 / 8. In a system configured to include frozen channels, the code rate can be based on the number of frozen channels, where the useless redundant data is passed through the frozen channels. Since the low SNR channel does not provide useful data, ECC redundant bits are not added to the user data, but the redundant data can be used instead of the data to be passed along the frozen channel, so the code rate can be:

[0080]

[0081] Therefore, a data encoding scheme that reduces the amount of useful information transmitted through the frozen channel can be applied. In a system that uses both ECC encoding to add redundant bits to user bits and frozen channel redundancy, the code rate can take into account the amount of ECC redundancy plus frozen channel redundancy. However, to simplify the description herein, it will be assumed that the code rate is limited by the frozen channel redundancy. Fig.14 Presents the design and adoption Fig.13 An example approach to the architecture of .

[0082] Fig.14 A flow chart of an example method 1400 for transform domain analysis based channel design and application according to certain embodiments of the present disclosure is depicted. Specifically, Fig.14 Describes an example method of designing a channel and extracting user data from a readback signal using transform domain analysis. System 1400 can be composed of a data channel such as Fig.13 channel architecture) to execute.

[0083] At 1402, method 1400 may include decomposing a signal using an integer "N" transform domain, where a current transform domain "n" is set to N. Similar to method 1200, method 1400 may include setting a threshold SNR value. At 1404, method 1400 may include setting an SNR threshold of 1 for a minimum SNR result from a transform domain node, and freezing transform domain nodes having SNR results below threshold 1 (e.g., not detecting or discarding actual outputs of the nodes so that replacement values ​​may be assigned to the frozen nodes based on one or more nodes having higher SNR values). Thus, the system may be designed to not include a detector for freezing channels, and instead, values ​​for those channels may be determined based on outputs of one or more other channels.

[0084] At 1406, method 1400 may include identifying a code rate for the system based on the number of frozen channels. Fig.13 As discussed in , freezing one of the four channels in the deepest transform domain can result in a code rate of 3 / 4. Similarly, for a system with 6 transform domains and 64 branches or channels, freezing 6 channels will give a code rate of 58 / 64.

[0085] At 1408, method 1400 may include determining a coding scheme for user bits based on the identified code rate such that minimal content is allocated to or delivered via the frozen channel. In an example with a code rate of 3 / 4, a code may be designed that maps 3 useful bits to a 4-bit representation such that redundant information is delivered via the frozen channel(s). As an example, FIG. 15(a) shows Fig.13 All 4-bit combinations at the four DWT domains of and their representations, where channel_bit_aa and channel_bit_ad represent the first two domains, channel_bit_da and channel_bit_dd represent the second two domains, and channel_bit_da is the selected frozen channel. Figure 15(b) shows the same diagram with the 3rd bit selected as the redundant bit to minimize the channel_bit_da component, and this is achieved by having the smallest possible bit transition compared to using the 4th bit as the redundant bit. Since the 3rd bit is selected as the redundant bit in this example, the number of bit combinations in Figure 15(b) is reduced from 16 to 8, and all 8 combinations are in Fig.16 In Fig.13 and Fig.16 In the 4-branch embodiment, channel_bit_da is frozen and replaced with a redundant bit. The redundant third bit in each group of four bits can be determined based on the result of channel_bit_aa. When the channel_bit_aa sample value is -2, 2 or 0, the channel_bit_da sample value can be set to 0. When the channel_bit_aa sample value is -1, the channel_bit_da sample value can be set to 1, and when the channel_bit_aa sample value is 1, the channel_bit_da sample value can be set to -1. Therefore, in a simple four-branch design, the value of a single frozen channel can be determined by the result of a single other channel. A more complex system with multiple frozen channels can use the results of some or all of the non-frozen channels to determine the value of the frozen channel.

[0086] Back to Fig.14, method 1400 may include setting an SNR threshold 2 for high quality SNR results and detecting a transform domain representation above threshold 2 at 1410. At 1412, the transform domain representation of the node having an SNR level between threshold 1 and threshold 2 may be detected and decoded. At 1414, method 1400 may include identifying (multiple) values ​​for any frozen channel. In the above example, based on the sequence of values ​​detected for channel_bit_aa, the value for frozen channel_bit_da may be determined without detecting information from the frozen channel. Determining the value to be used for the frozen channel based on a subset or all of the non-frozen channels may be accomplished via a lookup table, where the value from the non-frozen channel is used to retrieve the value to be used for the frozen channel. In some examples, an and algorithm or equation may be used instead of a lookup table. Then at 1416, the current transform domain may be reduced by one so that n=n-1.

[0087] Then, steps 1418 to 1428 can be substantially as described with respect to Fig.12 The method 1400 proceeds as described in steps 1212 to 1222 of . However, in the method 1400, the domain representation formed at each of the continuously transformed domains may be based on artificial values ​​of the frozen channels determined at 1414 by means of the applied coding scheme, rather than on actual detection results from those channels. Fig.17 and Fig.18 A method of performing write and read operations using a data channel designed according to method 1400 is discussed.

[0088] Fig.17 A flow chart of an example method 1700 for transform domain analysis based channel design and application according to certain embodiments of the present disclosure is depicted. Specifically, Fig.17 Depicted is an example method of performing a write operation using a channel designed to apply transform domain analysis (including a frozen channel). Method 1700 may be performed by a data channel (such as Fig.13 channel architecture) to execute.

[0089] At 1702, method 1700 may include receiving a sector of user bits to be written. At 1704, the sector may be encoded for error detection and correction, such as by performing erasure coding and CRC encoding.

[0090] After encoding, method 1700 may include receiving a set of sequence coded bits from a sector at 1706. The set may have a number of bits based on a code rate for a data channel, which is based on the number of frozen channels. The number of bits may be equal to the number of non-frozen channels or branches at the deepest transform domain. For a code rate of M / N (non-frozen channels / total channels), the set of sequence bits may include M sequence bits from the coded sector. For example, if the code rate for system 1300 is determined to be 3 / 4, each set of sequence coded bits from the sector may have a number of bits equal to the numerator in the code rate (e.g., based on the total number of channels minus the number of frozen branches for data channels); in this example, 3 bits. In another example with 64 channels (of which 6 channels are frozen), the code rate may be 58 / 64 (or simply 29 / 32), with 58 user bits out of the 64 channel bits.

[0091] At 1708, method 1700 may include determining a coding scheme to apply to the set of sequence coded bits based on a code rate identified for the channel in accordance with the number of frozen channels as discussed with respect to FIG 15. The number of frozen channels and the coding scheme may be determined during design of the channel, and the coding scheme to be applied may be stored in a memory accessible to the data channel, or configured into the channel itself, such that during a read or write operation of the data channel, the coding scheme may be applied without determining the number of frozen channels.

[0092] At 1710, method 1700 may include adding (multiple) redundant bits to the set of coded bits based on the number of frozen channels to create a block of bits. Thus, for a system configured to be based on an M / N code rate with (NM) frozen channels, the number of redundant bits added to the set of sequence bits may be (NM). The redundant bits may be added according to a coding scheme configured in a manner to pass minimal information through the (multiple) frozen channels. For example, the (multiple) redundant bits may be selected based on the bit pattern of the set of coded bits and added to locations that distribute the bit transitions in such a manner that minimal useful information is sent through the (multiple) frozen channels when the data is read back. At 1712, once the (multiple) redundant bits are added to the set of sequence bits to create a block of bits, method 1700 may include writing the block to a medium.

[0093] At 1714, method 1700 may include determining whether there are any additional coded bits from the sector to be recorded. If so, method 1700 may return to 1706 to receive the next set of M coded bits. If there are no more coded bits from the sector at 1714, then at 1716, method 1700 may include completing the write operation, or receiving the next sector of user bits to be written. Next, reference will be made to Fig.18 Discuss read operations.

[0094] Fig.18 A flow chart of an example method 1800 for channel design and application based on transform domain analysis according to certain embodiments of the present disclosure is depicted. Specifically, Fig.18 Depicted is an example method of performing a read operation using a channel designed to apply transform domain analysis (including a frozen channel). Method 1800 may be performed by a data channel (such as Fig.13 channel architecture) to execute.

[0095] At 1802, method 1800 may include reading a block of samples. A block may include a set of digital samples corresponding to N recorded bits (from an M / N code rate based on the number of frozen channels), or a block may be samples corresponding to an entire sector or more of data, where a larger block of data is broken down into blocks of samples corresponding to N recorded bits. At 1804, the method may include passing the block of samples through a channel based on transform domain analysis to break up the data along multiple branches, as discussed herein.

[0096] At 1806, method 1800 may include determining frozen transform domain channel(s) with low SNR results from which there are no detected bits or the bits detected from those channels are discarded. Corresponding channel(s) with high SNR results may also be determined. The results from the corresponding high SNR channels may be used to determine the values ​​assigned to the frozen channel(s). From a channel design perspective, the frozen channels may be designed to not include a detector, and the modules may be designed and positioned to receive the output of the corresponding high SNR channels and use the output to generate replacement redundant data for the frozen channels.

[0097] At 1808, method 1800 may include detecting a transform domain representation or bit from a non-frozen channel. At 1810, method 1800 may include selecting a frozen channel corresponding to a low SNR transform domain node and setting a value of a domain representation of the channel based on the detected bits from one or more corresponding high SNR domains. For example, a lookup table or algorithm may be used to populate the value of frozen channel_da based on the detected value for channel_aa.

[0098] At 1812, it may be determined whether the transform domain representation or bit is set for all frozen channels. If not, method 1800 may include selecting a next frozen channel at 1814 and setting the transform domain or bit value for that channel at 1810.

[0099] Once the values ​​are set for all frozen channels, method 1800 may then include detecting channel bits corresponding to the sample block based on the transform domain representation or bits from the transform domain channels (including detected bits from non-frozen channels and set bits for frozen channels) at 1816. The transform domain representation used to detect the channel bits may correspond to the output of the shallowest or lowest transform domain, which may be formed based on results from deeper or higher transform domains, as described in methods 1200 and 1400.

[0100] At 1818, it may be determined whether all sample blocks of the sector have been read or processed. If not, the next sample block may be read and processed at 1802. Once all blocks of the sector have been processed to obtain the channel bits of the sector, method 1800 may include using ECC decoding to detect and correct errors. For example, errors may be detected based on a CRC code, and if an error is detected, the error may be corrected via list decoding. Erasure decoding may be applied to recover bits that cannot be formed based on the results of CRC and list decoding.

[0101] Now go to Fig.19 , a diagram of a system (generally referred to as 1900) implemented using transform domain analysis-based channel design according to certain embodiments of the present disclosure is shown and described. Specifically, Fig.19 An example device configured to perform signal processing using a data channel based on transform domain analysis, as described herein, is shown.

[0102] The system 1900 may include a data processing device 1902. The data processing device 1902 may be any device configured to process data signals via a data channel 1917. For example, the data processing device 1902 may include a storage device such as a hard disk drive (HDD) or a solid state drive (SSD). In another example, the data processing device 1902 may be a device configured to receive signals, transmit signals, or both via a wired or wireless communication medium such as a computer or laptop computer, a mobile phone, a GPS device, a radio, a set-top box, a smart vehicle, or other device.

[0103] The data processing device 1902 may include a data channel 1917 , a controller 1906 , a memory 1903 , an input / output (I / O) unit 1904 , and a receiver / transmitter 1919 . Fig.19 The functional blocks depicted may include one or more circuits or processors, such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and memory chips, and may include transistors and data storage buffers that are configured to perform the operations described for each component.

[0104] Controller 1906 can be configured to control the operation of data processing device 1902, such as sending data through data channel 1917 or receiving data from data channel 1917. Memory 1903 can be volatile or non-volatile memory, and can be read-only or writable. In an example, memory 1903 can include DRAM, SRAM or ROM memory types. Memory 1903 can store instructions or data for execution or use by controller 1906, data channel 1917, or other components of data processing device 1902. I / O unit 1904 can include one or more systems or devices for receiving or outputting data, such as keyboard and pointing device, touch screen, microphone, speaker or similar device. I / O unit 1904 can also include one or more interfaces to other devices, such as directional connection or networked host or client device. Data to be recorded or transmitted via data channel 1917 can be received at I / O unit 1904 and processed by controller 1906. Similarly, data received or read via data channel 1917 may be displayed or output via I / O unit 1904 .

[0105] As described, data channel 1917 can handle data that has been received or read, or data that is to be written or transmitted. Data channel 1917 can communicate with Figure 1 The receiver / transmitter 1919 may correspond to the data channel described herein and may include a transform domain analysis module 1930 configured to perform transform domain analysis and processing on the signal as described herein. The receiver / transmitter 1919 may be one or more read or write heads (e.g., transducer heads) for reading data from or recording data to a medium 1920, such as a magnetic storage disk or an optical storage disk or other storage element. In some embodiments, the medium 1920 may include a solid-state memory. The receiver / transmitter 1919 may also include one or more antennas for transmitting data via wireless signals such as WiFi signals, radio waves, communication, infrared signals, near field communication (NFC), etc.) or wired communication paths to receive or transmit signals. Fig. 20 A more specific example of the data processing device 1902 in the form of a data storage device is described.

[0106] Fig. 20 A diagram depicts a system (generally referred to as 2000) implemented using transform domain analysis based channel design according to certain embodiments of the present disclosure. Specifically, Fig. 20A functional block diagram of an example data storage device (DSD) 2000 is provided that is configured to perform signal processing using a data channel based on transform domain analysis. One or more of the circuit components of the DSD 2000 may be included on a single integrated circuit (e.g., a system on a chip, SoC), may be distributed among multiple circuits or hardware components, may be implemented as a firmware module executed by a microprocessor, or in other configurations.

[0107] The DSD 2000 may communicate with a host device 2002 via a hardware or firmware based interface circuit 2004. The interface 2004 may include any interface that allows wired or wireless communication between the host 2002 and the DSD 2000, such as USB, IEEE1394, Compact Flash, SATA, eSATA, PATA, SCSI, SAS, PCIe, NVMe, Fibre Channel, Ethernet, or Thunderbolt, etc. The interface 2004 may include a connector that allows the DSD 2000 to be physically removed from the host 2002. The DSD 2000 may have a housing 2040 that houses the components of the DSD 2000.

[0108] Commands received from host 2002 via interface 2004 may be stored in buffer 2012. Buffer 2012 may be DRAM, SRAM, or other types of memory. Buffer 2012 may temporarily store data during read and write operations, and may include a command queue (CQ) 2013 in which a plurality of pending host commands may be temporarily stored awaiting execution. Commands arriving through interface 2004 may be automatically received in CQ 2013, or may be stored in CQ 2013 by controller 2006, interface 2004, or another component.

[0109] DSD 2000 may include a programmable controller 2006, which may include associated memory 2008 and a processor 2010. Controller 2006 may control data access operations, such as reading and writing, to one or more disk memories 2009. DSD 2000 may include additional memory 2003 instead of disk memories 2009, or in addition to disk memories 2009. For example, additional memory 2003 may be solid-state memory, which may be volatile memory (such as DRAM or SRAM) or non-volatile memory (such as NAND flash memory). Additional memory 2003 may be used as a cache and store data that is recently or frequently read or written, or data that may be read soon. Additional memory 2003 may also be used as main memory or long-term storage instead of (multiple) disks 2009, or in addition to (multiple) disk memories 2009. Additional memory 2003 may also be used as main memory or long-term storage. A DSD 2000 that includes multiple types of non-volatile storage media, such as disk(s) 2009 and flash memory 2003, may be referred to as a hybrid storage device.

[0110] DSD 2000 may include R / W channel 2017, which may encode data during write operations and reconstruct data retrieved from memory (such as disk(s) 2009 or memory 2003) during read operations. Preamplifier circuit (preamp) 2018 may apply write current to head(s) 2019 and provide preamplification of readback signals. In some embodiments, preamp 2018 and head(s) 2019 may be considered part of R / W channel 2017. Servo control circuit 2020 may use servo data to provide appropriate current to coil 2024 (sometimes referred to as voice coil motor (VCM)) to position head(s) 2019 over a desired area of ​​disk(s) 2009. Controller 2006 may communicate with processor 2022 to move head(s) 2019 to a desired position on disk(s) 2009 during execution of various pending commands in command queue 2013.

[0111] The R / W channel 2017 may include a transform domain analysis module (TDAM) 2030. The TDAM 230 may perform the methods and processes described herein to detect useful data from a signal using transform domain analysis. As discussed above, the processing performed by the TDAM 2030 may be used to effectively manage jitter noise in the readback signal. The head 2019 field gradient and the grain size of the magnetic grains on the disk 2009 are the main sources of system jitter noise. In a heat-assisted magnetic recording (HAMR) system, a laser transmitter (not shown) near the head 2019 on an arm moved by the VCM 2024 may emit a laser during writing to the disk 2009, and the thermal gradient from the laser may be another important contributing factor to the jitter noise.

[0112] The description of the embodiments described herein is intended to provide a general understanding of the structure of each embodiment. The description is not intended to be a complete description of all elements and features of the devices and systems that utilize the structures or methods described herein. Many other embodiments will be apparent to those skilled in the art after reviewing the present invention. Other embodiments may also be utilized and derived from the present disclosure so that structural and logical substitutions and changes may be made without departing from the scope of the present disclosure. Moreover, although specific embodiments have been shown and described herein, it should be appreciated that any subsequent arrangements designed to achieve the same or similar purposes may replace the specific embodiments shown.

[0113] The present disclosure is intended to cover any subsequent modifications or variations of the various embodiments. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art after reading the above description. Additionally, these illustrations are merely representative and may be drawn to scale. Certain proportions in the illustrations may be amplified, while other proportions may be reduced. Therefore, the present disclosure and the accompanying drawings should be considered illustrative, not restrictive.

[0114] Further examples

[0115] Example 1. An apparatus comprising:

[0116] an analog-to-digital converter (ADC) configured to convert the analog signal into a sequence of digital samples;

[0117] A circuit configured to perform a transform domain analysis on the digital sample sequence, the circuit comprising:

[0118] a first transform domain analysis filter configured to apply a transform analysis signal to a received sample sequence to produce a first transformed sample sequence having a higher signal-to-noise ratio (SNR) than the received sample sequence;

[0119] a first detector configured to detect a bit sequence transform domain representation from the first transformed sample sequence; and

[0120] A second detector is configured to determine a sequence of user bits corresponding to the analog signal based on the digital sample sequence and the bit sequence transform domain representation.

[0121] Example 2. The apparatus of Example 1 further comprises:

[0122] The circuit further comprises:

[0123] A second transform domain analysis filter, wherein the second transform domain analysis filter is configured to:

[0124] applying the transformed analysis signal to the digital sample sequence to produce a second transformed sample sequence having a higher signal-to-noise ratio than the digital sample sequence;

[0125] providing the second transformed sample sequence to (1) the first transform domain analysis filter as the received sample sequence, and (2) a third detector;

[0126] The third detector is configured as:

[0127] receiving said bit sequence from said first detector and said second transformed sample sequence from said second transform domain analysis filter;

[0128] detecting a second bit sequence transform domain representation based on (1) the second transform sample sequence and (2) the bit sequence transform domain representation from the first detector; and

[0129] The second detector is further configured to determine the sequence of user bits based on the digital sample sequence and a second bit sequence.

[0130] Example 3. The apparatus of Example 1 further comprises:

[0131] The circuit further comprises:

[0132] a first equalizer, configured to equalize the first transformed sample sequence to a first target response to generate an equalized first transformed sample sequence; and

[0133] The first detector is configured to detect the transform domain representation of the bit sequence based on the equalized first transformed sample sequence.

[0134] Example 4. The apparatus of Example 3 further comprises:

[0135] a second equalizer configured to equalize the digital sample sequence to a second target response to generate an equalized digital sample sequence; and

[0136] The second detector is configured to determine the sequence of user bits based on the equalized sequence of digital samples and the bit sequence.

[0137] Example 5. The apparatus of Example 4 further comprises:

[0138] The circuit further comprises:

[0139] a first downsampler circuit configured to remove every other bit from the first transformed sampling sequence so that the first transformed sampling sequence includes half of the samples of the received sampling sequence;

[0140] The first equalizer is configured to equalize the downsampled first transformed sample sequence to the first target response; and

[0141] The first detector is configured to detect the bit sequence transform domain representation based on the equalized down-sampled first transform sample sequence.

[0142] Example 6. The apparatus of Example 5 further comprises:

[0143] The circuit further comprises:

[0144] a second downsampler circuit configured to remove every other bit from the second transformed sample sequence so that the second transformed sample sequence includes half of the samples of the digital sample sequence;

[0145] a third equalizer configured to equalize the downsampled second transformed sample sequence to a third target response; and

[0146] A third detector is configured to detect a transform domain representation of the second bit sequence based on the equalized down-sampled second transform sample sequence.

[0147] Example 7. The apparatus of Example 1 further comprises:

[0148] The apparatus comprises a read channel circuit of a data storage device; and

[0149] The analog signal is received from a read head of the data storage device based on a magnetic pattern recorded to a data storage medium.

[0150] Example 8. The apparatus as described in Example 1 further includes the first transform domain analysis filter, and the first transform domain analysis filter includes a low-pass analysis filter.

[0151] Example 9. The apparatus as described in Example 1 further includes the first transform domain analysis filter, and the first transform domain analysis filter applies discrete wavelet transform.

[0152] Example 10. A method includes:

[0153] Improving bit detection from a received analog signal at a data channel circuit, including:

[0154] Converting the analog signal into a set of digital samples;

[0155] Decomposing the set of digital samples by applying a transform domain analysis filter to the N sequence transform domain nodes of the data channel circuit, starting from the first transform domain node and ending at the Nth transform domain node;

[0156] For the current transform domain node n = N, detecting an Nth transform domain bit sequence representation having a higher signal-to-noise ratio (SNR) than the set of digital samples based on the decomposed sample set received from the (N - 1)th transform domain node;

[0157] Decrementing the current transform domain such that n is set to n - 1;

[0158] For the current transform domain node n, detecting an nth transform domain bit sequence representation based on the decomposed sample set received from the (n - 1)th transform domain node and the transform domain bit sequence received from the (n + 1)th transform domain node; and

[0159] Detecting a user data bit sequence based on the set of digital samples and the transform domain bit sequence representation received from the n = 1 transform domain node.

[0160] Example 11. The method as described in Example 10 further includes:

[0161] Decomposing the set of digital samples includes applying a transform analysis signal to a digital sampling sequence through the transform domain analysis filter of the N sequence transform domain nodes to generate a set of transform samples;

[0162] For a transform domain node n < N, detecting the nth transform domain bit sequence includes detecting the nth transform domain bit sequence representation at the detector of the nth transform domain node based on (1) the nth transform domain sample set and (2) the transform domain bit sequence representation from the (n + 1)th transform domain node.

[0163] Example 12. The method as described in Example 11 further includes:

[0164] downsampling, at a downsampler circuit of the nth transform domain node, the nth transform sample set to remove every other sample so that the nth transform sample set includes half of the samples of the decomposed sample set received from the n-1th transform domain node; and

[0165] At the equalizer of the nth transform domain node, the downsampled nth transform sample set is equalized to a target response.

[0166] Example 13. The method of Example 10, further comprising receiving the analog signal at a read channel from a read head of a data storage device.

[0167] Example 14. The method of Example 10 further comprises converting the analog signal into the digital sample set comprises periodically sampling the analog signal at an analog-to-digital converter (ADC) to obtain digital sample values ​​for the digital sample set.

[0168] Example 15. An apparatus comprising:

[0169] A channel circuit, wherein the channel circuit is configured to:

[0170] receiving an analog signal at an input of the channel circuit;

[0171] Sampling the analog signal to obtain a signal sample set;

[0172] applying a filter configured to perform a transform domain analysis on the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and a higher signal-to-noise ratio (SNR) than the set of signal samples;

[0173] detecting a first bit-transformed domain representation value from said first subset; and

[0174] Channel bit values ​​encoded in the analog signal are determined based on the set of signal samples and the first bit transform domain representation values ​​detected from the first subset.

[0175] Example 16. The apparatus of Example 15, wherein the channel circuit comprises:

[0176] an analog-to-digital converter (ADC) configured to sample the analog signal;

[0177] a first transform domain analysis filter configured to apply a first transform analysis signal to the received sequence of samples to produce the first subset;

[0178] a first detector configured to detect a first bit-value transform domain representation from the first subset; and

[0179] A second detector is configured to determine the channel bit value.

[0180] Example 17. The apparatus of Example 16, further comprising the received sampling sequence comprising the set of signal samples.

[0181] Example 18. The apparatus of Example 16, wherein the channel circuit further comprises:

[0182] A second transform domain analysis filter, wherein the second transform domain analysis filter is configured to:

[0183] applying a second transformed analysis signal to the set of signal samples to produce a second subset of samples, the second subset including fewer transitions and a higher SNR than the set of signal samples;

[0184] providing the second subset to: (1) the first transform domain analysis filter as the received sample sequence, wherein the first subset includes fewer transitions and a higher SNR than the second subset, (2) a third detector;

[0185] The third detector is configured as:

[0186] receiving a bit transform domain representation from said first detector and receiving said second subset from a second transform domain analysis filter;

[0187] detecting a second bit transform domain representation based on (1) the second subset and (2) the bit transform domain representation from the first detector as side information; and

[0188] The second detector is further configured to determine the channel bit value based on the set of signal samples and a second bit value.

[0189] Example 19. The apparatus of Example 18, wherein the channel circuit further comprises:

[0190] a first downsampler circuit disposed between the first transform domain analysis filter and the first detector, the first downsampler circuit being configured to remove every other sample from the first subset such that the first subset includes half of the samples of the received sampling sequence;

[0191] a first equalizer located between the first downsampler circuit and the first detector, the first equalizer configured to equalize the downsampled first subset to a first target response; and

[0192] The first detector is configured to detect the first bit transform domain representation value based on the downsampled equalized first subset.

[0193] Example 20. The apparatus of Example 19, wherein the channel circuit further comprises:

[0194] a second downsampler circuit located between the second transform domain analysis filter and the third detector, the second downsampler circuit being configured to remove every other sample from the second subset so that the second subset includes half of the samples of the signal sample set;

[0195] a second equalizer disposed between the second downsampler circuit and the third detector, the second equalizer configured to equalize the downsampled second subset to a second target response;

[0196] The third detector is configured to detect the second bit transform domain representation value based on the downsampled equalized second subset;

[0197] a third equalizer located between the ADC and the second detector, the third equalizer configured to equalize the signal sample set to a third target response; and

[0198] The second detector is further configured to determine the channel bit value based on the equalized signal sample set and the second bit transform domain representation value.

Claims

1. A device comprising: an analog-to-digital converter (ADC) configured to convert the analog signal into a sequence of digital samples; A circuit configured to perform a transform domain analysis on the digital sample sequence, the circuit comprising: a first transform domain analysis filter configured to apply a transform analysis signal to a received sample sequence to produce a first transformed sample sequence having a higher signal-to-noise ratio (SNR) than the received sample sequence; a first detector configured to detect a bit sequence transform domain representation from the first transformed sample sequence; and A second detector is configured to determine a sequence of user bits corresponding to the analog signal based on the digital sample sequence and the bit sequence transform domain representation.

2. The apparatus of claim 1, further comprising: The circuit further comprises: A second transform domain analysis filter, wherein the second transform domain analysis filter is configured to: applying the transformed analysis signal to the digital sample sequence to produce a second transformed sample sequence having a higher signal-to-noise ratio than the digital sample sequence; providing the second transformed sampling sequence to the first transform domain analysis filter as the received sampling sequence and to a third detector; The third detector is configured as: receiving said bit sequence from said first detector and said second transformed sample sequence from said second transform domain analysis filter; detecting a second bit sequence transform domain representation based on the second transform sample sequence and the bit sequence transform domain representation from the first detector; and The second detector is further configured to determine the sequence of user bits based on the digital sample sequence and a second bit sequence.

3. The apparatus of claim 1, further comprising: The circuit further comprises: a first equalizer, configured to equalize the first transformed sample sequence to a first target response to generate an equalized first transformed sample sequence; and The first detector is configured to detect the transform domain representation of the bit sequence based on the equalized first transformed sample sequence.

4. The apparatus of claim 3, further comprising: a second equalizer configured to equalize the digital sample sequence to a second target response to generate an equalized digital sample sequence; as well as The second detector is configured to determine the sequence of user bits based on the equalized sequence of digital samples and the bit sequence.

5. The apparatus of claim 4, further comprising: The circuit further comprises: a first downsampler circuit configured to remove every other bit from the first transformed sampling sequence so that the first transformed sampling sequence includes half of the samples of the received sampling sequence; The first equalizer is configured to equalize the downsampled first transformed sample sequence to the first target response; and The first detector is configured to detect the bit sequence transform domain representation based on the equalized and downsampled first transform sample sequence.

6. The apparatus according to claim 5, further comprising: The circuit further comprises: A second downsampler circuit configured to remove every other bit from a second transform sample sequence such that the second transform sample sequence comprises half of the samples of the digital sample sequence; A third equalizer for equalizing the downsampled second transform sample sequence to a third target response; and A third detector configured to detect the second bit sequence transform domain representation based on the equalized and downsampled second transform sample sequence.

7. The apparatus according to claim 1, further comprising: The apparatus includes a read channel circuit of a data storage device; and Receiving the analog signal from a read head of the data storage device based on a magnetic pattern recorded on a data storage medium.

8. The apparatus according to claim 1, further comprising the first transform domain analysis filter, the first transform domain analysis filter including a low-pass analysis filter.

9. The apparatus according to claim 1, further comprising the first transform domain analysis filter, the first transform domain analysis filter applying a discrete wavelet transform.

10. A method, comprising: Improving bit detection from a received analog signal at a data channel circuit, comprising: Converting the analog signal to a set of digital samples; Decomposing the set of digital samples by applying a transform domain analysis filter through N sequence transform domain nodes of the data channel circuit, starting from a first transform domain node and ending at an Nth transform domain node; For a current transform domain node n = N, detecting an Nth transform domain bit sequence representation having a higher signal-to-noise ratio (SNR) than the set of digital samples based on a decomposed sample set received from an (N - 1)th transform domain node; Decrementing the current transform domain such that n is set to n - 1; For a current transform domain node n, detecting an nth transform domain bit sequence representation based on a decomposed sample set received from an (n - 1)th transform domain node and a transform domain bit sequence received from an (n + 1)th transform domain node; and Detecting a user data bit sequence based on the set of digital samples and the transform domain bit sequence representation received from the n = 1 transform domain node.

11. The method according to claim 10, further comprising: Decomposing the set of digital samples includes applying a transform analysis signal to a digital sample sequence through a transform domain analysis filter of the N sequence transform domain nodes to produce a set of transform samples; For a transform domain node n < N, detecting the nth transform domain bit sequence includes detecting the nth transform domain bit sequence representation at a detector of the nth transform domain node based on the nth set of transform samples and the transform domain bit sequence representation from the (n + 1)th transform domain node.

12. The method according to claim 11, further comprising: downsampling, at a downsampler circuit of the nth transform domain node, the nth transform sample set to remove every other sample so that the nth transform sample set includes half of the samples of the decomposed sample set received from the n-1th transform domain node; as well as At the equalizer of the nth transform domain node, the downsampled nth transform sample set is equalized to a target response.

13. The method of claim 10, further comprising receiving the analog signal at a read channel from a read head of a data storage device.

14. The method of claim 10, further comprising converting the analog signal to the digital sample set comprises periodically sampling the analog signal at an analog-to-digital converter (ADC) to obtain digital sample values ​​for the digital sample set.

15. An apparatus comprising: A channel circuit, wherein the channel circuit is configured to: receiving an analog signal at an input of the channel circuit; Sampling the analog signal to obtain a signal sample set; applying a filter configured to perform a transform domain analysis on the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and a higher signal-to-noise ratio (SNR) than the set of signal samples; detecting a first bit-transformed domain representation value from said first subset; as well as Channel bit values ​​encoded in the analog signal are determined based on the set of signal samples and the first bit transform domain representation values ​​detected from the first subset.

16. The device according to claim 15, characterized in that The channel circuit comprises: an analog-to-digital converter (ADC) configured to sample the analog signal; a first transform domain analysis filter configured to apply a first transform analysis signal to the received sequence of samples to produce the first subset; a first detector configured to detect a first bit-value transform domain representation from the first subset; and A second detector is configured to determine the channel bit value.

17. The apparatus of claim 16, further comprising the received sampling sequence comprising the set of signal samples.

18. The device according to claim 16, characterized in that The channel circuit further comprises: A second transform domain analysis filter, wherein the second transform domain analysis filter is configured to: applying a second transformed analysis signal to the set of signal samples to produce a second subset of samples, the second subset including fewer transitions and a higher SNR than the set of signal samples; providing the second subset to the first transform domain analysis filter as the received sample sequence, wherein the first subset includes fewer transitions and a higher SNR than the second subset, and to a third detector; The third detector is configured as: receiving a bit transform domain representation from said first detector and receiving said second subset from a second transform domain analysis filter; detecting a second bit transform domain representation based on the second subset and the bit transform domain representation from the first detector as side information; and The second detector is further configured to determine the channel bit value based on the set of signal samples and a second bit value.

19. The device according to claim 18, characterized in that The channel circuit further comprises: a first downsampler circuit disposed between the first transform domain analysis filter and the first detector, the first downsampler circuit being configured to remove every other sample from the first subset such that the first subset includes half of the samples of the received sampling sequence; a first equalizer located between the first downsampler circuit and the first detector, the first equalizer configured to equalize the downsampled first subset to a first target response; and The first detector is configured to detect the first bit transform domain representation value based on the downsampled equalized first subset.

20. The device according to claim 19, characterized in that The channel circuit further comprises: a second downsampler circuit located between the second transform domain analysis filter and the third detector, the second downsampler circuit being configured to remove every other sample from the second subset so that the second subset includes half of the samples of the signal sample set; a second equalizer disposed between the second downsampler circuit and the third detector, the second equalizer configured to equalize the downsampled second subset to a second target response; The third detector is configured to detect the second bit transform domain representation value based on the downsampled equalized second subset; a third equalizer located between the ADC and the second detector, the third equalizer configured to equalize the signal sample set to a third target response; and The second detector is further configured to determine the channel bit value based on the equalized signal sample set and the second bit transform domain representation value.

Images