Display devices

Abstract

The present disclosure relates to a display device, comprising: a substrate; a first circuit unit, which is positioned on the substrate and includes a first thin film transistor and a first storage capacitor; a first dummy circuit unit, which is located on the substrate, includes a first dummy thin film transistor and a first dummy storage capacitor, and is located in the same layer as the first circuit unit; and a first dummy light-emitting unit, which is located on the first dummy circuit unit, is connected to the first circuit unit, and is configured to be driven by the first circuit unit, wherein the first dummy light-emitting unit overlaps with the first dummy circuit unit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0000490 filed on January 2, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display device, and more particularly, to a display device in which a light emitting unit is moved and / or extended. Background Art

[0004] A display device is a device for visually displaying data and is used as a display unit for small products such as mobile phones, and as a display unit for large products such as televisions.

[0005] The display device includes a substrate divided into a display area and a non-display area, and a gate line and a data line insulated from each other are formed in the display area. The gate line and the data line cross or intersect each other to define a plurality of pixel areas in the display area, and the plurality of pixel areas receive electrical signals to emit light and display an image to the outside. A thin film transistor (TFT) corresponding to each pixel area and a pixel electrode electrically connected to the TFT are provided, and a counter electrode is provided above the pixel area in common. Various suitable wirings, gate drivers, data drivers, controllers, etc. for transmitting or applying electrical signals to the display area can be provided in the non-display area.

[0006] Recently, display devices have been used for various suitable purposes. Furthermore, as the thickness and weight of display devices have decreased, the range of their applications has increased. As the number of users has increased, research has been actively conducted to provide users with visually satisfying displays. In one such research effort, various attempts have been made to expand the display area of ​​display devices. Summary of the Invention

[0007] Aspects of one or more embodiments relate to a display device in which a light emitting unit is moved and / or extended. However, the above aspects are merely examples and thus do not limit the scope of the present disclosure.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed embodiments of the disclosure.

[0009] According to one or more embodiments, a display device includes: a substrate; a first circuit unit, which is positioned on the substrate and includes a first thin film transistor (TFT) and a first storage capacitor; a first dummy circuit unit, which is located on the substrate, includes a first dummy TFT and a first dummy storage capacitor, and is located in the same layer as the first circuit unit; and a first dummy light-emitting unit, which is located on the first dummy circuit unit, connected to the first circuit unit, and configured to be driven by the first circuit unit, wherein the first dummy light-emitting unit overlaps with the first dummy circuit unit.

[0010] The display device may further include a first light emitting unit located on the first circuit unit, connected to the first circuit unit, and configured to be driven by the first circuit unit, wherein the first light emitting unit overlaps with the first circuit unit.

[0011] The display device may further include: a second circuit unit, which is positioned on the substrate and includes a second TFT and a second storage capacitor; a second dummy circuit unit, which is located on the substrate, includes a second dummy TFT and a second dummy storage capacitor, and is located in the same layer as the second circuit unit; and a second dummy light-emitting unit, which is located on the second dummy circuit unit, is connected to the second circuit unit, and is configured to be driven by the second circuit unit, wherein the second dummy light-emitting unit overlaps with the second dummy circuit unit.

[0012] The display device may further include: a second light emitting unit located on the second circuit unit, connected to the second circuit unit, and configured to be driven by the second circuit unit, wherein the second light emitting unit overlaps with the second circuit unit.

[0013] The substrate may include: a transmissive area; a first display area surrounding the transmissive area; a second display area located between the transmissive area and the first display area; and a first non-display area located between the transmissive area and the second display area, wherein the first circuit unit is located in the first display area, and wherein the first dummy circuit unit is located in the second display area.

[0014] The substrate may include: a third display area; a first display area, the first display area surrounding the third display area; and a second display area, the second display area being located between the first display area and the third display area, wherein the transmission unit is located in the third display area, wherein the first circuit unit is located in the first display area, and wherein the first dummy circuit unit is located in the second display area.

[0015] The display device may further include: a component positioned below the third display area.

[0016] According to one or more embodiments, a display device includes: a substrate; a first circuit unit, the first circuit unit being located on the substrate and including a first thin film transistor (TFT) and a first storage capacitor; a first pixel electrode, the first pixel electrode being located on the first circuit unit and connected to the first TFT; a pixel defining layer, the pixel defining layer covering an edge of the first pixel electrode and having a first opening and a second opening through which a portion of the first pixel electrode is exposed; a first intermediate layer, the first intermediate layer being located in the first opening; a second intermediate layer, the second intermediate layer being located in the second opening; and a relative electrode, the relative electrode being located on the pixel defining layer and covering the first intermediate layer and the second intermediate layer.

[0017] The first opening may overlap with the first circuit unit.

[0018] The display device may further include: a second circuit unit, which is located on the substrate, in the same layer as the first circuit unit, and includes a second TFT and a second storage capacitor; a second pixel electrode, which is located on the second circuit unit, in the same layer as the first pixel electrode, and is connected to the second TFT; a third intermediate layer, which is located on the second pixel electrode; and a fourth intermediate layer, which is located in the same layer as the third intermediate layer, wherein the pixel defining layer covers an edge of the second pixel electrode and also has a third opening and a fourth opening through which a portion of the second pixel electrode is exposed, wherein the third intermediate layer is located in the third opening, and wherein the fourth intermediate layer is located in the fourth opening.

[0019] The third opening may overlap with the second circuit unit.

[0020] The substrate may include: a transmissive area; a first display area surrounding the transmissive area; a second display area located between the transmissive area and the first display area; and a first non-display area located between the transmissive area and the second display area, wherein the first circuit unit is located in the first display area, and wherein one of the first opening and the second opening is located in the second display area.

[0021] The substrate may include: a third display area; a first display area, the first display area surrounding the third display area; and a second display area, the second display area being located between the first display area and the third display area, wherein the transmission unit is located in the third display area, wherein the first circuit unit is located in the first display area, and wherein one of the first opening and the second opening is located in the second display area.

[0022] The display device may further include: a component positioned below the third display area.

[0023] According to one or more embodiments, a display device includes: a substrate, the substrate including: a transmissive area, a first display area surrounding the transmissive area, a second display area located between the transmissive area and the first display area, and a first non-display area located between the transmissive area and the second display area; a first bypass wiring, the first bypass wiring is located in the second display area, extends in a first direction, and bypasses the transmissive area along an edge of the transmissive area; a first circuit unit, the first circuit unit is located in the first display area and includes a first thin film transistor (TFT) and a first storage capacitor; a first pixel electrode, the first pixel electrode is located on the first circuit unit and is connected to the first TFT; a pixel defining layer, the pixel defining layer covers an edge of the first pixel electrode and has a first opening and a second opening through which a portion of the first pixel electrode is exposed; a first intermediate layer, the first intermediate layer is located in the first opening; a second intermediate layer, the second intermediate layer is located in the second opening; and an opposing electrode, the opposing electrode is located on the pixel defining layer and covers the first intermediate layer and the second intermediate layer, wherein one of the first opening and the second opening overlaps with the first bypass wiring.

[0024] The display device may further include: a second circuit unit, which is located in the first display area, is located in the same layer as the first circuit unit, and includes a second TFT and a second storage capacitor; a second pixel electrode, which is located on the second circuit unit, is located in the same layer as the first pixel electrode, and is connected to the second TFT; a third intermediate layer, which is located on the second pixel electrode; and a fourth intermediate layer, which is located in the same layer as the third intermediate layer, wherein the pixel defining layer covers an edge of the second pixel electrode and also has a third opening and a fourth opening through which a portion of the second pixel electrode is exposed, wherein the third intermediate layer is located in the third opening, the fourth intermediate layer is located in the fourth opening, and one of the third opening and the fourth opening overlaps with the first bypass wiring.

[0025] The first non-display area may be a third display area, wherein the transmission unit is located in the third display area.

[0026] The display device may further include: a component located below the third display area;

[0027] The display device may further include a thin film encapsulation layer on the substrate and facing the substrate.

[0028] The first storage capacitor may include an upper electrode and a lower electrode, wherein the lower electrode overlaps the first TFT.

[0029] Other aspects and features will become apparent and better understood from the following description of the disclosed embodiments, the present disclosure, and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure;

[0032] Figure 2 is a cross-sectional view of a display device according to an embodiment of the present disclosure;

[0033] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure;

[0034] Figure 4A and Figure 4B Each is an equivalent circuit diagram showing one pixel of a display panel according to an embodiment of the present disclosure;

[0035] Figure 5 is a plan view showing one pixel of a display panel according to an embodiment of the present disclosure;

[0036] Figure 6 is a plan view showing a portion of a display device according to an embodiment of the present disclosure;

[0037] Figure 7A and Figure 7B Each is a cross-sectional view showing a portion of a display device according to an embodiment of the present disclosure;

[0038] Figure 8 is a plan view showing a portion of a display device according to an embodiment of the present disclosure;

[0039] Figure 9 is a plan view showing a portion of a display device according to an embodiment of the present disclosure;

[0040] Figure 10A and Figure 10B Each is a cross-sectional view showing a portion of a display device according to an embodiment of the present disclosure;

[0041] Figure 11 is a plan view showing a portion of a display device according to an embodiment of the present disclosure;

[0042] Figure 12 is a plan view showing a portion of a display device according to an embodiment of the present disclosure;

[0043] Figure 13 is a cross-sectional view illustrating a portion of a display device according to an embodiment of the present disclosure;

[0044] Figure 14 is a cross-sectional view illustrating a portion of a display device according to an embodiment of the present disclosure;

[0045] Figure 15 is a plan view showing a portion of a display device according to an embodiment of the present disclosure; and

[0046] Figure 16 is a cross-sectional view illustrating a portion of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] Now, with reference to embodiment in more detail, examples of embodiment are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, the present disclosure can have different forms and should not be construed as being limited to the embodiments disclosed herein. Therefore, only the disclosed embodiments are described below with reference to the accompanying drawings to illustrate various aspects of the present disclosure. As used herein, when describing an embodiment of the present disclosure, the term "may" is used to refer to "one or more embodiments of the present disclosure". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. Throughout the present disclosure, the expression "at least one (kind) of a, b and c" or "at least one (kind) selected from a, b and c" represents only a, only b, only c, both a and b, both a and c, both b and c, all a, b and c or their variations.

[0048] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, and in the drawings, like elements are denoted by like reference numerals, and description thereof will not be repeated.

[0049] It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms and these terms are only used to distinguish one element from another.

[0050] As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0051] It will also be understood that the terms “comprises” and “comprising” as used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0052] It will be understood that when a layer, region or element is referred to as being “on” another layer, region or element, it can be directly on the other layer, region or element, or intervening layers, regions or elements may be present between the layer, region or element and the other layer, region or element.

[0053] In the accompanying drawings, the sizes of the elements may be exaggerated for ease of description. Because the sizes and thicknesses of the elements in the accompanying drawings may be exaggerated for ease of description, the following embodiments are not limited thereto. As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation rather than terms of degree and are intended to take into account the inherent deviations of measured or calculated values ​​that would be recognized by one of ordinary skill in the art.

[0054] When a specific embodiment can be implemented differently, the order of processes may be different from the order described. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in the reverse order of the order described.

[0055] The term "A and / or B" means A only, B only, or both A and B.

[0056] It will be understood that when a layer, region, or element is referred to as being "connected" to another layer, region, or element, the layer, region, or element may be directly connected to the other layer, region, or element, or may be indirectly connected to the other layer, region, or element with the presence of an intervening layer(s), region(s), or element(s) between the layer, region, or element and the other layer, region, or element. For example, when a layer, region, or element is electrically connected to another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element, or may be indirectly electrically connected to the other layer, region, or element with the presence of an intervening layer, region, or element between the layer, region, or element and the other layer, region, or element.

[0057] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0058] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0059] Reference Figure 1 The display device 1 includes a display area DA that emits light and a non-display area NDA that does not emit light. The non-display area NDA and the display area DA are positioned adjacent to each other. The display device 1 can provide an image by utilizing light emitted by a plurality of pixels arranged in the display area DA.

[0060] The display device 1 includes a transmissive area TA at least partially surrounded by a display area DA. In an embodiment, the transmissive area TA is formed by Figure 1 The non-display area NDA may include a first non-display area NDA1 surrounding the transmissive area TA and a second non-display area NDA2 surrounding the outside of the display area DA. The first non-display area NDA1 may completely surround the transmissive area TA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0061] The display area DA may include a second display area DA2 surrounding the first non-display area NDA1, the first display area DA1 completely surrounding the second display area DA2, and a third display area DA3 surrounding the outside of the first display area DA1. As described below, the first display area DA1 corresponds to a normal display area, and the second display area DA2 and the third display area DA3 each correspond to a moved display area and / or an extended display area according to an embodiment. For example, in some embodiments, the first display area DA1 may extend from (e.g., may extend into) the second display area DA2 and / or the third display area DA3.

[0062] Although an organic light-emitting display device is described as the display device 1 according to an embodiment of the present disclosure, the display device 1 of the present disclosure is not limited thereto. In another embodiment, the display device 1 may be any of various suitable display devices such as an inorganic electroluminescent (EL) display or a quantum dot light-emitting display.

[0063] Figure 2 It is along Figure 1 FIG. 1 is a cross-sectional view of a display device according to an embodiment of the present disclosure taken along line II-II′.

[0064] Reference Figure 2 , display device 1 (see Figure 1 ) may include a display panel 10, an input sensing member 20 positioned on the display panel 10, and an optical functional member 30, and the display panel 10, the input sensing member 20, and the optical functional member 30 may be covered by a window 40. The display device 1 may be any of various suitable electronic devices such as a mobile phone, a notebook computer, or a smart watch.

[0065] The display panel 10 can display images. The display panel 10 includes pixels arranged in a display area DA. Each pixel may include a display element and a pixel circuit connected to the display element. The display element may include an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting diode.

[0066] The input sensing member 20 obtains coordinate information based on external input such as a touch event (e.g., a user's touch). The input sensing member 20 may include sensing electrodes (or touch electrodes) and signal lines (traces) connected to the sensing electrodes. The input sensing member 20 may be positioned above the display panel 10.

[0067] The input sensing member 20 may be formed on or directly on the display panel 10, or the input sensing member 20 may be formed separately and then coupled to the display panel 10 by using an adhesive layer such as an optically clear adhesive (OCA). For example, the input sensing member 20 may be formed continuously after the process of forming the display panel 10 (e.g., the input sensing member 20 may be formed directly on the display panel 10 after the display panel 10 is formed), and in this case, the adhesive layer may not be positioned between the input sensing member 20 and the display panel 10. Although the input sensing member 20 is shown as being positioned Figure 2 The input sensing member 20 is positioned between the display panel 10 and the optical functional member 30 , but in another embodiment, the input sensing member 20 may be positioned above the optical functional member 30 .

[0068] The optical functional member 30 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident on the display panel 10 from the outside through the window 40. The anti-reflection layer may include a phase retarder and a polarizer. The phase retarder may be a film type (e.g., a film-based phase retarder) or a liquid crystal coating type (e.g., a liquid crystal coating-based phase retarder), and may include a λ / 2 (e.g., half-wavelength) phase retarder and / or a λ / 4 (e.g., quarter-wavelength) phase retarder. The polarizer may also be a film type (e.g., a film-based polarizer) or a liquid crystal coating type (e.g., a liquid crystal coating-based polarizer). A film type (e.g., film-based) polarizer may include a stretched synthetic resin film, and a liquid crystal coating type (e.g., liquid crystal coating-based) polarizer may include liquid crystals arranged in a specific orientation. The phase retarder and polarizer may also include a protective film. The phase retarder and polarizer or protective film may be defined as a base layer (e.g., the bottom layer) of the anti-reflection layer. For example, in some embodiments, the phase retarder and the polarizer can be defined as a base layer (e.g., the bottom layer) of the anti-reflection layer, and in some embodiments in which a protective film is included, the protective film can be defined as a base layer (e.g., the bottom layer) of the anti-reflection layer.

[0069] In another embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged in consideration of (e.g., according to) the color of light emitted by each pixel of the display panel 10. In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer positioned on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, may destructively interfere with each other, thereby reducing the reflectivity of external light.

[0070] The optical functional member 30 may include a lens layer. The lens layer may improve the light extraction efficiency of the light emitted by the display panel 10 and / or reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or may include multiple layers having different refractive indices. The optical functional member 30 may include both an anti-reflection layer and a lens layer, or may include one of the anti-reflection layer and the lens layer.

[0071] The display panel 10, the input sensing member 20, and the optical function member 30 may have openings. Figure 2 In the embodiment of the present invention, the display panel 10, the input sensing member 20, and the optical function member 30 respectively have a first opening 10H, a second opening 20H, and a third opening 30H, and the first opening 10H, the second opening 20H, and the third opening 30H overlap each other. The first opening 10H, the second opening 20H, and the third opening 30H are formed to correspond to the transmission area TA. For example, the transmission area TA can be an area in which light and / or sound output from the component 50 to the outside or traveling from the outside toward an electronic component (e.g., an electronic component included in the component 50) can be transmitted, and can be an area formed by the first opening 10H, the second opening 20H, and the third opening 30H.

[0072] In another embodiment, the display panel 10, the input sensing member 20, and / or the optical functional member 30 may not have an opening. For example, one or both of the display panel 10, the input sensing member 20, and the optical functional member 30 may not have an opening, or all of the display panel 10, the input sensing member 20, and the optical functional member 30 may not have an opening.

[0073] The component 50 may correspond to the transmission area TA. Figure 2 The solid lines in FIG. 1 and FIG. 2 may be positioned in the first opening 10H, the second opening 20H, and the third opening 30H, or may be positioned in the first opening 10H, the second opening 20H, and the third opening 30H, as indicated by the solid lines in FIG. Figure 2 The area marked by the dotted line in FIG. 1 is positioned below the display panel 10 .

[0074] Component 50 may include electronic components. For example, component 50 may include (e.g., be) electronic components that utilize light and / or sound. Examples of electronic components may include sensors for receiving and utilizing light, such as infrared sensors, cameras for receiving light and capturing images, sensors for outputting and detecting light and / or sound to measure distance or identify fingerprints, small lamps for outputting light, and speakers for outputting sound. When component 50 includes (e.g., is) an electronic component that utilizes light, component 50 may utilize light of various suitable wavelengths, such as visible light, infrared light, or ultraviolet light.

[0075] In another embodiment, when the display device 1 is used as a smartwatch or a vehicle dashboard, the component 50 may be a component such as a clock hand or a pointer indicating specific information (e.g., vehicle speed). When the display device 1 includes a clock hand or a vehicle dashboard, the component 50 may pass through the window 40 and be exposed to the outside, and the window 40 may have an opening corresponding to the transmissive area TA.

[0076] The assembly 50 may include an element (or elements) related to the functions of the display panel 10 as described above, or may include elements such as accessories for enhancing the appearance (eg, aesthetics) of the display panel 10 .

[0077] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure.

[0078] Reference Figure 3 The display panel 10 includes a display area DA and a non-display area NDA. The display area DA includes a first display area DA1, a second display area DA2, and a third display area DA3, and the non-display area NDA includes a first non-display area NDA1 and a second non-display area NDA2. Figure 3 The substrate 100 of the display panel 10 is shown. For example, the substrate 100 may include a transmission area TA, a display area DA, and a non-display area NDA. In addition, the display panel 10 includes a plurality of pixels P arranged in the display area DA.

[0079] The first non-display area NDA1 may surround the transmissive area TA. The first non-display area NDA1 is an area in which a display element such as an organic light emitting diode to emit light is not positioned, and a signal line that applies a signal to the pixel P is arranged around the transmissive area TA and may pass through the first non-display area NDA1. A scan driver 1100 that applies a scan signal to each pixel P, a data driver 1200 that applies a data signal to each pixel P, and a main power wiring that applies a first power supply voltage and a second power supply voltage may be positioned in the second non-display area NDA2. Although the data driver 1200 is shown as being positioned Figure 3 The data driver 1200 is located on one side of the substrate 100 in the display panel 10 according to another embodiment, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the data driver 1200 may be located on a flexible printed circuit board (FPCB) that is electrically connected to the pad located on one side of the display panel 10 according to another embodiment.

[0080] Figure 4A and Figure 4B Each is an equivalent circuit diagram showing one pixel of a display panel according to an embodiment of the present disclosure.

[0081] Reference Figure 4AEach pixel P includes a pixel circuit PC and an organic light emitting diode (OLED) as a display element connected to the pixel circuit PC. The pixel circuit PC may include a driving thin film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst. Each pixel P can emit, for example, red, green, blue, or white light through the OLED.

[0082] The switching TFT T2 may be connected to the scan line SL and the data line DL and may transmit a data voltage input from the data line DL to the driving TFT T1 according to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the switching TFT T2 and the driving voltage line PL and may store a voltage corresponding to a difference between a voltage received from the switching TFT T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0083] The driving TFT T1 may be connected to the driving voltage line PL and the storage capacitor Cst and may control the driving current flowing from the driving voltage line PL to the OLED in response to the voltage stored in the storage capacitor Cst. The OLED may emit light having a brightness due to (e.g., corresponding to) the driving current. An opposing electrode (e.g., a cathode) of the OLED may receive a second power supply voltage ELVSS.

[0084] Despite Figure 4A The pixel circuit PC is shown as including two TFTs and one storage capacitor, but the present disclosure is not limited thereto. The number of TFTs and the number of storage capacitors may be changed in various suitable ways according to the design of the pixel circuit PC. The following description assumes that the pixel circuit PC includes seven TFTs and one storage capacitor. Figure 4B .

[0085] Reference Figure 4B Each pixel P may include a pixel circuit PC and an OLED connected to the pixel circuit PC, and the pixel circuit PC may include a plurality of TFTs and a storage capacitor Cst. The TFTs and the storage capacitor Cst may be connected to signal lines (e.g., a scan line SWL, a previous scan line SIL, an emission control line EL, and a data line DL), an initialization voltage line VL, and a driving voltage line PL.

[0086] Despite Figure 4B , each pixel P is shown as being connected to a signal line (e.g., a scan line SWL, a previous scan line SIL, an emission control line EL, and a data line DL), an initialization voltage line VL, and a drive voltage line PL, but the present disclosure is not limited thereto. In another embodiment, at least one of the signal line (e.g., a scan line SWL, a previous scan line SIL, an emission control line EL, and a data line DL), the initialization voltage line VL, and the drive voltage line PL may be shared by adjacent pixels.

[0087] The plurality of TFTs may include a driving TFT T1 , a switching TFT T2 , a compensation TFT T3 , a first initialization TFT T4 , an operation control TFT T5 , an emission control TFT T6 , and a second initialization TFT T7 .

[0088] The signal lines include a scan line SWL that transmits a scan signal GW, a previous scan line SIL that transmits a previous scan signal GI to a first initialization TFT T4 and a second initialization TFT T7, an emission control line EL that transmits an emission control signal EM to an operation control TFT T5 and an emission control TFT T6, and a data line DL that crosses or intersects the scan line SWL and transmits a data signal Dm. A driving voltage line PL transmits a first power supply voltage ELVDD to the driving TFT T1, and an initialization voltage line VL transmits an initialization voltage Vint to initialize the driving TFT T1 and a pixel electrode (e.g., a pixel electrode of an OLED).

[0089] The driving gate electrode G1 of the driving TFT T1 is connected to the first storage capacitor plate Cst11 of the storage capacitor Cst, the driving source electrode S1 of the driving TFT T1 is connected to (e.g., through) the operation control TFT T5 and is connected to the driving voltage line PL (e.g., through the operation control TFT T5), and the driving drain electrode D1 of the driving TFT T1 is connected to (e.g., through) the emission control TFT T6 and is electrically connected to the pixel electrode of the OLED (e.g., through the emission control TFT T6). The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2 and generates a driving current I OLED Supply to OLED.

[0090] A switching gate electrode G2 of the switching TFT T2 is connected to the scan line SWL; a switching source electrode S2 of the switching TFT T2 is connected to the data line DL; and a switching drain electrode D2 of the switching TFT T2 is connected to the driving source electrode S1 of the driving TFT T1, to (e.g., via) the operation control TFT T5, and to the driving voltage line PL (e.g., through the operation control TFT T5). The switching TFT T2 is turned on by a scan signal GW received through the scan line SWL and performs a switching operation of transmitting a data signal Dm received through the data line DL to the driving source electrode S1 of the driving TFT T1.

[0091] The compensation gate electrode G3 of the compensation TFT T3 is connected to the scan line SWL; the compensation source electrode S3 of the compensation TFT T3 is connected to the driving drain electrode D1 of the driving TFT T1, to (e.g., via) the emission control TFT T6, and to the pixel electrode of the OLED (e.g., through the emission control TFT T6); and the compensation drain electrode D3 of the compensation TFT T3 is connected to the first storage capacitor plate Cst11 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 is turned on by the scan signal GW received through the scan line SWL and is diode-connected to the driving TFT T1 by electrically connecting the driving gate electrode G1 and the driving drain electrode D1 of the driving TFT T1. In some embodiments, the compensation TFT T3 may have a dual TFT structure or a dual-gate structure.

[0092] A first initialization gate electrode G4 of the first initialization TFT T4 is connected to the previous scan line SIL. A first initialization source electrode S4 of the first initialization TFT T4 is connected to the second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line VL. Furthermore, a first initialization drain electrode D4 of the first initialization TFT T4 is connected to the first storage capacitor plate Cst11 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the drive gate electrode G1 of the drive TFT T1. The first initialization TFT T4 is turned on in response to a previous scan signal GI received via the previous scan line SIL and performs an initialization operation to initialize the voltage of the drive gate electrode G1 of the drive TFT T1 by transmitting an initialization voltage Vint to the drive gate electrode G1 of the drive TFT T1. In some embodiments, the first initialization TFT T4 may have a dual TFT structure or a dual-gate structure.

[0093] An operation control gate electrode G5 of the operation control TFT T5 is connected to the emission control line EL, an operation control source electrode S5 of the operation control TFT T5 is connected to the driving voltage line PL, and an operation control drain electrode D5 of the operation control TFT T5 is connected to the driving source electrode S1 of the driving TFT T1 and the switching drain electrode D2 of the switching TFT T2.

[0094] The emission control gate electrode G6 of the emission control TFT T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control TFT T6 is connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3, and the emission control drain electrode D6 of the emission control TFT T6 is electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the OLED.

[0095] The operation control TFT T5 and the emission control TFT T6 are concurrently or simultaneously turned on according to the emission control signal EM received through the emission control line EL, so that the first power voltage ELVDD is transmitted to the OLED and the driving current I OLED Flow through the OLED.

[0096] A second initialization gate electrode G7 of the second initialization TFT T7 is connected to the previous scan line SIL, a second initialization source electrode S7 of the second initialization TFT T7 is connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode of the OLED, and a second initialization drain electrode D7 of the second initialization TFT T7 is connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line VL. The second initialization TFT T7 is turned on according to the previous scan signal GI received through the previous scan line SIL, and initializes the pixel electrode of the OLED.

[0097] Despite Figure 4B , the first initialization TFT T4 and the second initialization TFT T7 are shown as being connected to the previous scan line SIL, but the present disclosure is not limited thereto. In another embodiment, the first initialization TFT T4 may be connected to the previous scan line SIL and may be driven according to the previous scan signal GI, and the second initialization TFT T7 may be connected to an additional signal line (e.g., the next scan line) and may be driven according to a signal transmitted to the additional signal line.

[0098] The second storage capacitor plate Cst22 of the storage capacitor Cst is connected to the driving voltage line PL, and the opposite electrode (eg, cathode) of the OLED is connected to the second power supply voltage ELVSS. Therefore, the OLED can receive the driving current I from the driving TFT T1. OLED and can emit light to display images.

[0099] Despite Figure 4B 3 , the compensation TFT T3 and the first initialization TFT T4 are illustrated as having a double gate electrode structure, but the present disclosure is not limited thereto, and the compensation TFT T3 and the first initialization TFT T4 may have one gate electrode.

[0100] Despite Figure 4B , the pixel circuit PC is shown as including seven TFTs and one storage capacitor, but the present disclosure is not limited thereto, and various suitable modifications may be made. For example, depending on the design of the pixel circuit PC, the number of TFTs may be equal to or less than 6 or equal to or greater than 8, and the number of storage capacitors may be equal to or greater than 2, or no storage capacitor may be included.

[0101] Figure 5 is a plan view illustrating one pixel circuit of a display panel according to an embodiment of the present disclosure.

[0102] Reference Figure 5 , the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 are arranged along the semiconductor layer 1130. The semiconductor layer 1130 may be positioned on the substrate 100 and include (e.g., be) a buffer layer 110 of an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride (see Figure 7A ) can be positioned below the semiconductor layer 1130.

[0103] Portions of the semiconductor layer 1130 correspond to the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7. For example, the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 may be connected to one another and may be bent into various suitable shapes.

[0104] The semiconductor layer 1130 may include a channel region (e.g., multiple channel regions) and a source region (e.g., multiple source regions) and a drain region (e.g., multiple drain regions) located on both sides of the channel region, and the source region and the drain region may be understood as (e.g., may be referred to as) a source electrode and a drain electrode of a corresponding TFT, respectively. For convenience, the source region and the drain region are referred to as a source electrode and a drain electrode, respectively.

[0105] The driving TFT T1 includes a driving gate electrode G1 overlapping a driving channel region, and a driving source electrode S1 and a driving drain electrode D1 positioned at both sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 may have a curved shape such as an omega (e.g., Ω) shape to form a long channel in a narrow space. When the driving channel region is long, the driving range of the gate voltage can be increased, and the OLED (see FIG. 1 ) can be more finely controlled. Figure 4A )The grayscale level of the emitted light and can improve the display quality.

[0106] The switching TFT T2 includes a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 positioned at both sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0107] The compensation TFT T3 having a dual TFT structure (or dual gate structure) may include a compensation gate electrode G3 overlapping two compensation channel regions, and a compensation source electrode S3 and a compensation drain electrode D3 positioned at both sides of the compensation gate electrode G3. The compensation TFT T3 may be connected to the driving gate electrode G1 of the driving TFT T1 via a node connection line 1174 as described below.

[0108] The first initialization TFT T4 having a dual TFT structure (or a dual gate structure) may include a first initialization gate electrode G4 overlapping two first initialization channel regions, and first initialization source and drain electrodes S4 and D4 positioned at both sides of the first initialization gate electrode G4.

[0109] The operation control TFT T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 positioned at both sides of the operation control gate electrode G5. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0110] The emission control TFT T6 may include an emission control gate electrode G6 overlapping the emission control channel region, and an emission control source electrode S6 and an emission control drain electrode D6 positioned at both sides of the emission control gate electrode G6. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0111] The second initialization TFT T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and second initialization source and drain electrodes S7 and D7 positioned at both sides of the second initialization gate electrode G7 .

[0112] The above-mentioned TFTs may be connected to signal lines (eg, a scan line SWL, a previous scan line SIL, an emission control line EL, and a data line DL), an initialization voltage line VL, and a driving voltage line PL.

[0113] The first gate insulating layer 111 (see Figure 7A ) may be positioned on the semiconductor layer 1130, and the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VL may be positioned on the first gate insulating layer 111. The first gate insulating layer 111 may include (e.g., be) an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride. Each of the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VL may include (e.g., be) a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or an alloy thereof.

[0114] The scan line SWL may extend in the x-direction. Portions of the scan line SWL may correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, a portion of the scan line SWL that overlaps with the channel region of the switching TFT T2 and a portion of the scan line SWL that overlaps with the channel region of the compensation TFT T3 may be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0115] The previous scan line SIL may extend in the x-direction, and some portions of the previous scan line SIL may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7. For example, a portion of the previous scan line SIL that overlaps with the channel region of the first initialization TFT T4 and a portion of the previous scan line SIL that overlaps with the channel region of the second initialization TFT T7 may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0116] The emission control line EL extends in the x-direction. Some portions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6. For example, a portion of the emission control line EL that overlaps with the channel region of the operation control TFT T5 and a portion of the emission control line EL that overlaps with the channel region of the emission control TFT T6 may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0117] The driving gate electrode G1 as a floating electrode may be connected to the compensation TFT T3 through a node connection line 1174 .

[0118] The initialization voltage line VL extends in the x direction and may be connected to the first initialization TFT T4 and the second initialization TFT T7 through the initialization connection line 1173 .

[0119] Despite Figure 5 The initialization voltage line VL is described as being positioned on the first gate insulating layer 111, but the present disclosure is not limited thereto. In some embodiments, the initialization voltage line VL may be positioned on the planarization layer 117 (see FIG. Figure 7A ) and may include (eg, be) the first pixel electrode 310 in another embodiment (see Figure 6 ) of the same material.

[0120] The electrode voltage line HL may be positioned on the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VL (e.g., on a higher layer than the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VL), and a second gate insulating layer 113 including (e.g., being) an inorganic material (see Figure 7A ) is located between the electrode voltage line HL and the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1 and the initialization voltage line VL.

[0121] A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G1 and may form a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 may be a first storage capacitor plate Cst11 of the storage capacitor Cst, and a portion of the electrode voltage line HL may be a second storage capacitor plate Cst22 of the storage capacitor Cst.

[0122] The electrode voltage line HL and the second storage capacitor plate Cst22 are electrically connected to the driving voltage line PL. Figure 5 In the embodiment, the electrode voltage line HL is connected to the driving voltage line PL located above the electrode voltage line HL through the contact hole 1158. The electrode voltage line HL and the driving voltage line PL may have the same voltage level (eg, a constant voltage of +5V). The electrode voltage line HL may be a horizontal driving voltage line.

[0123] Because the driving voltage line PL extends in the y direction and the electrode voltage line HL electrically connected to the driving voltage line PL extends in the x direction crossing or intersecting the y direction, a plurality of driving voltage lines PL and electrode voltage lines HL may be arranged in a grid structure in the display area.

[0124] The data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 may be positioned on the second storage capacitor plate Cst22 and the electrode voltage line HL, and a first interlayer insulating layer 115 including (eg, being) an inorganic material (see Figure 7A ) is located between the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 and the second storage capacitor plate Cst22 and the electrode voltage line HL. Each of the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 may include (e.g., be) aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure. In an embodiment, each of the driving voltage line PL and the data line DL may have a multi-layer structure including (e.g., be) Ti / Al / Ti.

[0125] The data line DL may extend in the y direction and may be connected to the switching source electrode S2 of the switching TFT T2 through the contact hole 1154. A portion of the data line DL may be understood as (eg, may be referred to as) a switching source electrode.

[0126] The driving voltage line PL extends in the y direction and is connected to the electrode voltage line HL through the contact hole 1158 as described above. In addition, the driving voltage line PL may be connected to the operation control TFT T5 through the contact hole 1155. The driving voltage line PL may be connected to the operation control source electrode S5 through the contact hole 1155.

[0127] One end of the initialization connection line 1173 may be connected to the first and second initialization TFTs T4 and T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to the initialization voltage line VL through the contact hole 1151 .

[0128] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 through the contact hole 1157 .

[0129] The first pixel electrode 310 can be connected to the connection metal 1175 through the contact hole 1163, and the connection metal 1175 can be connected to the connection metal 1175 by passing through the second interlayer insulating layer 116 (see FIG. Figure 7A ) and the contact hole 1153 passing through the first interlayer insulating layer 115 are connected to the emission control drain electrode D6.

[0130] Figure 6 is a plan view illustrating a portion of a display device according to an embodiment of the present disclosure. Figure 7A and Figure 7B Each is shown along Figure 6 1 is a cross-sectional view of a portion of a display device according to an embodiment of the present disclosure, taken along line IV-IV'.

[0131] Figure 6 Shown Figure 3The display panel 10 is a portion of the display panel 10, and the display panel 10 includes the transmissive area TA, the display area DA, and the non-display area NDA as described above. The non-display area NDA includes a first non-display area NDA1 surrounding the transmissive area TA and a second non-display area NDA2 surrounding (e.g., completely surrounding) the display area DA. The display area DA includes a second display area DA2 surrounding the first non-display area NDA1, a first display area DA1 surrounding (e.g., completely surrounding) the second display area DA2, and a third display area DA3 surrounding (e.g., completely surrounding) the first display area DA1. The first display area DA1 corresponds to a normal display area, and the second display area DA2 and the third display area DA3 each correspond to an extended display area according to an embodiment of the present disclosure.

[0132] The first area AR1 includes a portion of the first display area DA1 and a portion of the second display area DA2 close to the transmission area TA, and the second area AR2 includes a portion of the first display area DA1 and a portion of the third display area DA3.

[0133] Figure 6 The enlarged view shows a first area AR1 including a portion of the first display area DA1 and a portion of the second display area DA2. The data line DL and the driving voltage line PL pass through the first area AR1. The first area AR1 includes a first dummy light-emitting unit 300' positioned in the second display area DA2 and emitting light through the first pixel electrode 310, and a second light-emitting unit 200 positioned in the first display area DA1 and emitting light through the second pixel electrode 510.

[0134] In this embodiment, the first circuit unit PC1 may include a first TFT TFT1 and a first storage capacitor Cst1, and the first dummy circuit unit DPC1 may include a first dummy TFT TFT1' and a first dummy storage capacitor Cst1', and the first dummy circuit unit DPC1 may be provided at the same layer as the first circuit unit PC1 (for example, may be provided on the same layer as the first circuit unit PC1 or may be provided in the same layer as the first circuit unit PC1). The first dummy light-emitting cell 300' may be positioned on the first dummy circuit unit DPC1, and in this case, the first dummy light-emitting cell 300' is driven by the first circuit unit PC1, but overlaps with the first dummy circuit unit DPC1.

[0135] In more detail, the first dummy light-emitting cell 300' overlapping the first dummy circuit cell DPC1 is connected to the first TFT TFT1 through the contact hole 1163 formed in the planarization layer 117, and emits light due to the first circuit unit PC1 including the first TFT TFT1 (for example, emits light due to being connected to the first circuit unit PC1 including the first TFT TFT1 and being driven by the first circuit unit PC1 including the first TFT TFT1). For example, there is no contact hole connected to (for example, exposing) the first dummy TFT TFT1', and the first dummy light-emitting cell 300' overlaps the first dummy circuit cell DPC1 but is not connected to the first dummy circuit cell DPC1.

[0136] The second light emitting cell 200 that emits light due to the second pixel electrode 510 connected to the second circuit unit PC2 may be positioned in the first display area DA1, and the first dummy light emitting cell 300' that emits light due to the first pixel electrode 310 connected to the first circuit unit PC1 may be positioned in the second display area DA2. Although the light emitting cell overlapping with the first circuit unit PC1 may be positioned in the first display area DA1 similarly to the second light emitting cell 200 overlapping with the second circuit unit PC2, because the first dummy light emitting cell 300' is positioned in the second display area DA2, the display area DA may extend from the first display area DA1 to the second display area DA2 (e.g., may extend from the first display area DA1 to the second display area DA2).

[0137] Although the second display area DA2 includes the first dummy circuit unit DPC1, there is no light emitting unit that emits light due to the first dummy circuit unit DPC1 (for example, emits light due to being connected to and driven by the first dummy circuit unit DPC1). However, similar to the embodiment of the present disclosure, since the first dummy light emitting unit 300' that emits light due to the first circuit unit PC1 provided in the first display area DA1 is included in the second display area DA2, it is possible to prevent or reduce the impact on the pixel circuit PC (see FIG. 1 ) caused by static electricity existing around the transmission area TA. Figure 4A ), and the display area DA may extend from the first display area DA1 to the second display area DA2 (eg, from the first display area DA1 to the second display area DA2).

[0138] While the first area AR1 located near the transmissive area TA has been described, the same description can be applied to the second area AR2, which includes a portion of the first display area DA1 and a portion of the third display area DA3. For example, the second light-emitting cell 200, which emits light through the second pixel electrode 510, can be positioned in the first display area DA1 to correspond to the first area AR1, and the first dummy light-emitting cell 300', which emits light through the first pixel electrode 310, can be positioned in the third display area DA3. For example, based on the description of the second light-emitting cell 200 located in the first display area DA1 of the first area AR1, the second light-emitting cell can be located in the first display area DA1 of the second area AR2, and based on the description of the first dummy light-emitting cell 300' located in the second display area DA2 of the first area AR1, the first dummy light-emitting cell can be positioned in the third display area DA3 of the second area AR2. Therefore, the first display area DA1, which is a normal display area, can be extended to the second display area DA2 and the third display area DA3 (e.g., expanded to the second display area DA2 and the third display area DA3).

[0139] In some embodiments, the first dummy light-emitting unit 300' may be present in the second display area DA2 and the third display area DA3 as well as the first area AR1 and the second area AR2. For example, the first dummy light-emitting unit 300' is not limited to being present in the portions of the second display area DA2 and the third display area DA3 corresponding to the first area AR1 and the second area AR2, respectively. In some embodiments, the first dummy light-emitting unit 300' may be present in any or all portions of the second display area DA2 and / or the third display area DA3.

[0140] Reference Figure 7A and Figure 7B The display device according to an embodiment of the present disclosure includes a first TFT TFT1 positioned on (e.g., above) a substrate 100, a first storage capacitor Cst1, a first dummy TFT TFT1′, a first dummy storage capacitor Cst1′, and a first dummy light emitting unit 300′ as a display element. The display device may further include a third TFT TFT3 and a third dummy TFT TFT3′.

[0141] Will refer to Figure 7A The exemplary order of stacking the elements further describes the elements included in the display device, and Figure 7B Corresponding to Figure 7A of the modifications, and will therefore be briefly described Figure 7B .

[0142] The substrate 100 may include (e.g., be) a glass material, a ceramic material, a metal material, and / or a suitable flexible or bendable material. When the substrate 100 is flexible or bendable, the substrate 100 may include (e.g., be) a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate.

[0143] The substrate 100 may have a single-layer structure or a multi-layer structure including (e.g., being) the above-mentioned materials, and when the substrate 100 has a multi-layer structure, the substrate 100 may further include an inorganic layer. In some embodiments, the substrate 100 may have a structure including (e.g., being) an organic / inorganic / organic material.

[0144] A barrier layer may be further provided between the substrate 100 and the buffer layer 110. The barrier layer may prevent, reduce, or minimize the penetration of impurities from the substrate 100 into the semiconductor layers A1, A1', A3, and A3'. The barrier layer may include (e.g., be) an inorganic material such as an oxide and / or nitride, an organic material, or a combination of an organic material and an inorganic material, and may have a single-layer structure or a multi-layer structure including (e.g., be) an inorganic material and an organic material.

[0145] The semiconductor layers A1, A1', A3, and A3' may be positioned on the buffer layer 110. Each of the semiconductor layers A1, A1', A3, and A3' may include (e.g., be) amorphous silicon and / or polycrystalline silicon. In another embodiment, each of the semiconductor layers A1, A1', A3, and A3' may include (e.g., be) an oxide of at least one metal selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0146] Each of the semiconductor layers A1, A1', A3, and A3' may include a channel region and source and drain regions positioned at both sides of the channel region. Each of the semiconductor layers A1, A1', A3, and A3' may have a single layer structure or a multilayer structure.

[0147] The first gate insulating layer 111 and the second gate insulating layer 113 may be stacked on the substrate 100 (e.g., stacked above the substrate 100) to cover the semiconductor layers A1, A1', A3, and A3'. Each of the first gate insulating layer 111 and the second gate insulating layer 113 may include (e.g., be) silicon oxide (SiO2), silicon nitride (SiN x), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2).

[0148] The gate electrodes G1, G1', G3, and G3' may be positioned on the first gate insulating layer 111 to at least partially overlap with the semiconductor layers A1, A1', A3, and A3'. Figure 7A 1 , the gate electrodes G1, G1', G3, and G3' are shown as being positioned on the first gate insulating layer 111, but the present disclosure is not limited thereto, and in another embodiment, the gate electrodes G1, G1', G3, and G3' may be positioned on the top surface of the second gate insulating layer 113. In addition, the gate electrodes G1, G1', G3, and G3' may be positioned at the same layer or different layers (e.g., positioned on the same layer or different layers or positioned in the same layer or different layers).

[0149] In an embodiment, the first storage capacitor Cst1 may include a lower electrode CE1 and an upper electrode CE2, and may be configured as follows. Figure 7A 1. For example, the first gate electrode G1 of the first TFT TFT1 may function as the lower electrode CE1 of the first storage capacitor Cst1. In some embodiments, the first storage capacitor Cst1 may exist independently without overlapping the first TFT TFT1 (for example, when the first gate electrode G1 of the first TFT TFT1 does not function as the lower electrode CE1).

[0150] The upper electrode CE2 of the first storage capacitor Cst1 overlaps with the lower electrode CE1, and the second gate insulating layer 113 is located between the upper electrode CE2 and the lower electrode CE1 of the first storage capacitor Cst1 to form a capacitor. In this case, the second gate insulating layer 113 can serve as a dielectric layer of the first storage capacitor Cst1. Although the first storage capacitor Cst1 has been described, the same description applies to the first dummy storage capacitor Cst1'.

[0151] A first interlayer insulating layer 115 and a second interlayer insulating layer 116 may be provided on the second gate insulating layer 113 to cover the upper electrode CE2 of the first storage capacitor Cst1 and the upper electrode CE2' of the first dummy storage capacitor Cst1'. Each of the first interlayer insulating layer 115 and the second interlayer insulating layer 116 may include (e.g., be) silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2).

[0152] The source electrodes S1 , S1 ′, S3 , and S3 ′, the drain electrodes D1 , D1 ′, D3 , and D3 ′, and the data lines DL may be positioned on (eg, over) the first interlayer insulating layer 115 .

[0153] Each of the source electrodes S1, S1', S3 and S3', the drain electrodes D1, D1', D3 and D3', and the data lines DL may include (e.g., be) a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure including (e.g., being) the above materials. For example, each of the source electrodes S1, S1', S3 and S3', the drain electrodes D1, D1', D3 and D3', and the data lines DL may have a multi-layer structure including (e.g., being) Ti / Al / Ti. The source electrodes S1, S1', S3 and S3', and the drain electrodes D1, D1', D3 and D3' may be connected to the source region and the drain region of the semiconductor layers A1, A1', A3 and A3', respectively, through the contact holes 1143. As Figure 6 and Figure 7A As shown in FIG, the first drain electrode D1 and the first dummy drain electrode D1′ may be connected to the first semiconductor layer A1 and the first dummy semiconductor layer A1′, respectively, through contact holes 1143 and 1143′ formed in the first gate insulating layer 111, the second gate insulating layer 113, and the first interlayer insulating layer 115.

[0154] The source electrodes S1, S1', S3 and S3' and the drain electrodes D1, D1', D3 and D3' may be covered by an inorganic protective layer. The inorganic protective layer may have a structure including (eg, is) silicon nitride (SiN x ) and / or silicon oxide (SiO x The inorganic protective layer may cover and protect some wirings positioned on the first interlayer insulating layer 115.

[0155] The second interlayer insulating layer 116 may be positioned to cover the source electrodes S1 , S1 ′, S3 , and S3 ′ and the drain electrodes D1 , D1 ′, D3 , and D3 ′ and may have a contact hole 1153 for connecting the first TFT TFT1 and the first pixel electrode 310 .

[0156] although Figure 7AIt is shown that the first interlayer insulating layer 115 and the second interlayer insulating layer 116 are provided on the substrate 100 (e.g., provided above the substrate 100) and the first TFT TFT1 and the first pixel electrode 310 are connected through the contact holes 1143, 1153 and 1163 respectively passing through the first interlayer insulating layer 115, the second interlayer insulating layer 116 and the planarization layer 117, but the present disclosure is not limited thereto. In some embodiments, as Figure 7B As shown in , only the first interlayer insulating layer 115 of the first interlayer insulating layer 115 and the second interlayer insulating layer 116 may be provided, and the first TFT TFT1 and the first pixel electrode 310 may be connected through a contact hole 1143 passing through the first interlayer insulating layer 115 and a contact hole 1163 passing through the planarization layer 117.

[0157] A planarization layer 117 may be positioned on the second interlayer insulating layer 116 , and a first dummy light emitting cell 300 ′ may be positioned on the planarization layer 117 .

[0158] The planarization layer 117 may have a single-layer structure or a multi-layer structure including (e.g., being) an organic material and may have a flat top surface. The planarization layer 117 may include (e.g., being) benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), a general polymer such as polymethyl methacrylate (PMMA) and / or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylylene polymer, a vinyl alcohol polymer, or a blend thereof.

[0159] The first dummy light emitting unit 300 ′ is positioned on the planarization layer 117 . The first dummy light emitting unit 300 ′ includes a first pixel electrode 310 , a second intermediate layer 320 ′ including an organic emission layer, and an opposite electrode 330 .

[0160] The first pixel electrode 310 can be connected to the first drain electrode D1 of the first TFT TFT1 through a contact hole 1163 formed in the planarization layer 117, and can be a (semi-) light-transmitting electrode or a reflective electrode. In some embodiments, the first pixel electrode 310 may include a reflective film formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent electrode layer or a semi-transparent electrode layer formed on the reflective film. The transparent electrode layer or the semi-transparent electrode layer may include (for example, be) at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the first pixel electrode 310 may be formed of ITO / Ag / ITO.

[0161] The pixel defining layer 119 may be formed in the display area DA (see FIG. Figure 1 ) is positioned on the planarization layer 117. In addition, the pixel defining layer 119 can increase the distance between the edge of the first pixel electrode 310 and the opposite electrode 330 positioned on the first pixel electrode 310 (e.g., positioned above the first pixel electrode 310) to prevent or block arcing, etc., from occurring on the edge of the first pixel electrode 310. For example, in some embodiments, the pixel defining layer 119 can be positioned on the planarization layer 117 and can cover a portion (e.g., an edge) of the first pixel electrode 310, and the pixel defining layer 119 can have a second opening OP2 that exposes another portion of the first pixel electrode 310.

[0162] The pixel defining layer 119 may be formed of at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane, and phenolic resin by using spin coating or the like.

[0163] The second intermediate layer 320' of the first dummy light-emitting unit 300' can be positioned in the second opening OP2 formed by the pixel defining layer 119, and can include an organic emission layer. The organic emission layer may include (for example, be) an organic material containing a fluorescent and / or phosphorescent material that emits red light, green light, blue light, or white light. The organic emission layer may be formed of a low molecular weight organic material or a high molecular weight organic material, and, for example, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL) may be arranged below and above the organic emission layer.

[0164] The opposing electrode 330 may be a light-transmitting electrode or a reflective electrode. In some embodiments, the opposing electrode 330 may be a transparent or translucent electrode and may be formed of a metal film having a low work function and including (for example, being) lithium (Li), calcium (Ca), LiF, Al, Ag, Mg, or a compound thereof. In addition, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, and / or In2O3 may be further positioned on the metal film. The opposing electrode 330 may be positioned above the display area DA and may be positioned on the second intermediate layer 320' and the pixel defining layer 119. The opposing electrode 330 may be formed integrally with a plurality of OLEDs to correspond to a plurality of pixel electrodes 310 and 510.

[0165] In this embodiment, the first dummy light-emitting cell 300' is connected to and driven by the first circuit unit PC1 through contact holes 1143, 1153, and 1163 formed in the first interlayer insulating layer 115, the second interlayer insulating layer 116, and the planarization layer 117, respectively, but overlaps with the first dummy circuit unit DPC1. For example, the first dummy light-emitting cell 300' is positioned in the second display area DA2 in which the first dummy circuit unit DPC1 is positioned.

[0166] like Figure 7A As shown in , the electrode layer positioned on the first interlayer insulating layer 115 and the second interlayer insulating layer 116 may be connected to the first dummy semiconductor layer A1′ of the first dummy circuit unit DPC1 through contact holes 1143′ and 1153′ passing through the first interlayer insulating layer 115 and the second interlayer insulating layer 116. Figure 7B As shown in FIG, the electrode layer positioned on the first interlayer insulating layer 115 may be connected to the first dummy semiconductor layer A1 ′ of the first dummy circuit cell DPC1 through a contact hole 1143 ′ passing through the first interlayer insulating layer 115 .

[0167] In contrast, there may be no contact hole (e.g., a contact hole passing through the planarization layer 117) connected to the electrode layer positioned on the second interlayer insulating layer 116 and connected to the first dummy semiconductor layer A1'. For example, as described above, the first dummy light emitting unit 300' is driven not by the first dummy circuit unit DPC1 but by the first circuit unit PC1.

[0168] Figure 7A and Figure 7BThe planarization layer 117 is shown to not include a contact hole connecting the first dummy light-emitting cell 300' to the first dummy circuit cell DPC1. Since at least one selected from the first interlayer insulating layer 115, the second interlayer insulating layer 116, and the planarization layer 117 does not include a contact hole, the first dummy light-emitting cell 300' and the first dummy circuit cell DPC1 may not be connected. For example, the contact hole 1153' passing through the second interlayer insulating layer 116 may not be provided, or both the contact holes 1143' and 1153' passing through the first interlayer insulating layer 115 and the second interlayer insulating layer 116, respectively, may not be provided.

[0169] As described above, according to the present embodiment, since the first dummy light-emitting unit 300' that emits light due to the first circuit unit PC1 provided in the first display area DA1 is positioned in the second display area DA2, damage to the pixel circuit PC (for example, the pixel circuit of the first circuit unit PC1) due to the presence of static electricity around the transmission area TA can be prevented or reduced.

[0170] Figure 8 is a plan view illustrating a portion of a display device according to an embodiment of the present disclosure.

[0171] Reference Figure 8 The display device according to an embodiment of the present disclosure may further include a second circuit unit PC2 including a second TFT and a second storage capacitor and a second dummy circuit unit DPC2 including a second dummy TFT and a second dummy storage capacitor, and may further include a second dummy light-emitting unit 200' that emits light due to the second circuit unit PC2 (for example, emits light due to being connected to the second circuit unit PC2 and driven by the second circuit unit PC2).

[0172] As reference Figure 6 、 Figure 7A and Figure 7B As described above, the first pixel electrode 310 is connected to the first circuit unit PC1 through the contact hole 1163 formed in the planarization layer 117 , and the first dummy light emitting unit 300 ′ that emits light due to the first circuit unit PC1 overlaps the first dummy circuit unit DPC1 and is positioned in the second display area DA2 .

[0173] The second circuit unit PC2 including the second TFT and the second storage capacitor is connected to Figure 7A1 and the first dummy circuit unit DPC2. The first dummy circuit unit PC1 shown in FIG. 1 includes a first TFT TFT1 and a first storage capacitor Cst1. Furthermore, the second dummy circuit unit DPC2, including a second dummy TFT and a second dummy storage capacitor, corresponds to the first dummy circuit unit DPC1, including a first dummy TFT TFT1' and a first dummy storage capacitor Cst1'. For example, the structures of the second circuit unit PC2 and the second dummy circuit unit DPC2 may correspond to the description of the structures of the first circuit unit PC1 and the first dummy circuit unit DPC1, respectively.

[0174] The second drain electrode of the second TFT and the second dummy drain electrode of the second dummy TFT can be connected to the second semiconductor layer of the second TFT and the second dummy semiconductor layer of the second dummy TFT, respectively, through contact holes formed in the first gate insulating layer 111, the second gate insulating layer 113, and the first interlayer insulating layer 115, and contact holes 1150 and 1150' formed in the second interlayer insulating layer 116. In addition, the second pixel electrode 510 can be connected to the second drain electrode of the second TFT through a contact hole 1160 formed in the planarization layer 117.

[0175] In this way, the second pixel electrode 510 is connected to the second circuit unit PC2 positioned in the first display area DA1 through the contact hole 1160 formed in the planarization layer 117, and the second dummy light-emitting unit 200' that emits light due to the second pixel electrode 510 overlaps with the second dummy circuit unit DPC2 and is positioned in the second display area DA2.

[0176] Reference Figure 8 , the second dummy light emitting cell 200' that emits light due to the second pixel electrode 510 may be positioned in the left portion DA2' of the second display area DA2, and the first dummy light emitting cell 300' that emits light due to the first pixel electrode 310 may be positioned in the right portion DA2" of the second display area DA2. Although the light emitting cells may be positioned in the first display area DA1 to overlap with the first and second circuit units PC1 and PC2, because the first and second dummy light emitting cells 300' and 200' are positioned in the second display area DA2, the display area DA may extend from the first display area DA1 to the second display area DA2 (e.g., from the first display area DA1 to the second display area DA2).

[0177] Despite Figure 8 In the embodiment, the second dummy light emitting unit 200' and the first dummy light emitting unit 300' are respectively positioned in the left portion DA2' and the right portion DA2" of the second display area DA2, but in an embodiment, two or more light emitting units may be positioned in the second display area DA2.

[0178] Since the first dummy light emitting unit 300′ and the second dummy light emitting unit 200′, which emit light due to the first circuit unit PC1 and the second circuit unit PC2 provided in the first display area DA1, respectively, are positioned in the second display area DA2 according to an embodiment of the present disclosure, it is possible to prevent or reduce the damage to the pixel circuit PC (see FIG. 1 ) caused by static electricity existing around the transmission area TA. Figure 4A ) (e.g., pixel circuits of the first circuit unit PC1 and the second circuit unit PC2), and the display area DA may extend from the first display area DA1 to the second display area DA2 (e.g., from the first display area DA1 to the second display area DA2).

[0179] Although the first area AR1 close to the transmission area TA has been described, the same description may apply to the second area AR2 including a portion of the first display area DA1 and a portion of the third display area DA3 .

[0180] In some embodiments, the first dummy light-emitting unit 300' and the second dummy light-emitting unit 200' may be present in the second display area DA2 and the third display area DA3 as well as the first area AR1 and the second area AR2. For example, the first dummy light-emitting unit 300' and the second dummy light-emitting unit 200' are not limited to being located in a portion of the second display area DA2 and a portion of the third display area DA3 corresponding to the first area AR1 and the second area AR2, respectively. In some embodiments, the first dummy light-emitting unit 300' and the second dummy light-emitting unit 200' may be present in any or all portions of the second display area DA2 and the third display area DA3.

[0181] Figure 9 is a plan view illustrating a portion of a display device according to an embodiment of the present disclosure. Figure 10A and Figure 10B Each is shown along Figure 9 A cross-sectional view of a portion of a display device according to an embodiment of the present disclosure taken along line V-V'. Figure 9 、 Figure 10A and Figure 10B In, with Figure 6 、 Figure 7A and Figure 7B The same components in FIG. 1 are denoted by the same reference numerals, and thus repeated description thereof will not be given.

[0182] Reference Figure 9The display device according to the present embodiment may include a first circuit unit PC1 including a first TFT TFT1 and a first storage capacitor Cst1, and the first pixel electrode 310 may be positioned on the first circuit unit PC1 and connected to the first TFT TFT1. In addition, the display device may include: a pixel defining layer 119 (see Figure 10A and Figure 10B ), the pixel defining layer 119 covers the edge of the first pixel electrode 310 and includes a first opening OP1 and a second opening OP2 through which a portion of the first pixel electrode 310 is exposed; a first intermediate layer 320 and a second intermediate layer 320', the first intermediate layer 320 and the second intermediate layer 320' are positioned in the first opening OP1 and the second opening OP2, respectively; and a relative electrode 330, the relative electrode 330 is positioned on the pixel defining layer 119 and covers the first intermediate layer 320 and the second intermediate layer 320'. For example, the pixel defining layer 119 may cover the edge of the first pixel electrode 310, and may also cover the portion of the first pixel electrode 310 located between the first opening OP1 and the second opening OP2 (for example, the central portion). For example, when compared with Figure 6 Compared with the embodiment of FIG. 1 , the present embodiment may further include a first light emitting unit 300 driven by the first circuit unit PC1 and overlapping with the first circuit unit PC1.

[0183] The first opening OP1 may be positioned in the first display area DA1 to overlap with the first circuit unit PC1, and the second opening OP2 may be positioned in the second display area DA2 to overlap with the first dummy circuit unit DPC1. In some embodiments, the first opening OP1 may be positioned in the second display area DA2. In some embodiments, both the first opening OP1 and the second opening OP2 may be positioned in the first display area DA1 or the second display area DA2.

[0184] The second light emitting cell 200 that emits light due to the second pixel electrode 510 and the first light emitting cell 300 that emits light due to the first pixel electrode 310 may be positioned in the first display area DA1, and the first dummy light emitting cell 300' that emits light due to the first pixel electrode 310 may be positioned in the second display area DA2. For example, the light emitting cells (e.g., the first light emitting cell 300 and the second light emitting cell 200) may be positioned in the first display area DA1 to correspond to the first circuit unit PC1 and the second circuit unit PC2, respectively, and further, because the first dummy light emitting cell 300' is positioned in the second display area DA2, the display area DA may extend from the first display area DA1 to the second display area DA2 (e.g., from the first display area DA1 to the second display area DA2).

[0185] Because the first dummy light emitting unit 300' that emits light due to the first circuit unit PC1 provided in the first display area DA1 is also positioned in the second display area DA2 according to an embodiment of the present disclosure, damage to the pixel circuit PC due to static electricity existing around the transmission area TA can be prevented or reduced, and the display area DA can extend from the first display area DA1 to the second display area DA2 (for example, from the first display area DA1 to the second display area DA2). In addition, when compared with Figure 6 When compared with the embodiment of FIG. 4 , since the first light emitting unit 300 is also positioned in the first display area DA1 according to the present embodiment, the brightness can be improved.

[0186] Although the first area AR1 close to the transmission area TA has been described, the same description may apply to the second area AR2 including the first and third display areas DA1 and DA3 .

[0187] Reference Figure 10A , when with Figure 7A In contrast, the pixel defining layer 119 further includes a first opening OP1, and the first intermediate layer 320 is positioned in the first opening OP1. An opposing electrode 330 is provided to cover the first intermediate layer 320, and a first light emitting unit 300 including a first pixel electrode 310, the first intermediate layer 320, and the opposing electrode 330 is also provided. The first light emitting unit 300 is driven by the first circuit unit PC1 and overlaps with the first circuit unit PC1.

[0188] according to Figure 10A According to the embodiment, since the first light emitting unit 300 is also positioned in the first display area DA1, the brightness can be improved.

[0189] Figure 10B Corresponding to Figure 10A The modification and reference Figure 7B As described above, only the first interlayer insulating layer 115 of the first and second interlayer insulating layers 115 and 116 may be provided, and the first TFT TFT1 and the first pixel electrode 310 may be connected through the contact hole 1143 passing through the first interlayer insulating layer 115 and the contact hole 1163 passing through the planarization layer 117 .

[0190] Figure 11 is a plan view illustrating a portion of a display device according to an embodiment of the present disclosure.

[0191] Reference Figure 11The display device according to an embodiment of the present disclosure may further include a second circuit unit PC2 including a second TFT and a second storage capacitor and a second dummy circuit unit DPC2 including a second dummy TFT and a second dummy storage capacitor, and may further include a second dummy light emitting unit 200' that emits light due to the second circuit unit PC2.

[0192] As reference Figure 9 and Figure 10A As described above, the first pixel electrode 310 is connected to the first circuit unit PC1 through a contact hole 1163 formed in the planarization layer 117. The pixel defining layer 119 may cover the edge of the first pixel electrode 310 and may include a first opening OP1 and a second opening OP2 through which a portion of the first pixel electrode 310 is exposed. The first intermediate layer 320 and the second intermediate layer 320' may be positioned in the first opening OP1 and the second opening OP2, respectively, and the opposite electrode 330 may be positioned in the pixel defining layer 119 to cover the first intermediate layer 320 and the second intermediate layer 320', and thus two light emitting units may be provided on the first pixel electrode 310.

[0193] In another embodiment of the display device of the present disclosure, the second circuit unit PC2 may include a second TFT and a second storage capacitor, and the display device may further include a second pixel electrode 510 connected to the second TFT and positioned on the second circuit unit PC2. In addition, the pixel defining layer 119 may cover the edge of the second pixel electrode 510 and may further include a third opening OP3 and a fourth opening OP4 through which a portion of the second pixel electrode 510 is exposed. The third and fourth intermediate layers may be positioned in the third and fourth openings OP3 and OP4, respectively, and the opposing electrode 330 may be positioned on the pixel defining layer 119 to cover the third and fourth intermediate layers. Thus, two light-emitting units may be provided on the second pixel electrode 510.

[0194] The second circuit unit PC2 including the second TFT and the second storage capacitor corresponds to Figure 10A 1 . The first circuit unit PC1 including the first TFT TFT1 and the first storage capacitor Cst1 in FIG. In addition, the second dummy circuit unit DPC2 including the second dummy TFT and the second dummy storage capacitor corresponds to the first dummy circuit unit DPC1 including the first dummy TFT TFT1′ and the first dummy storage capacitor Cst1′. For example, the structures of the second circuit unit PC2 and the second dummy circuit unit DPC2 may correspond to the description of the structures of the first circuit unit PC1 and the first dummy circuit unit DPC1, respectively.

[0195] The second drain electrode and the second dummy drain electrode may be connected to the second semiconductor layer and the second dummy semiconductor layer through contact holes 1150 and 1150 ′ formed in the first gate insulating layer 111 , the second gate insulating layer 113 , and the first interlayer insulating layer 115 , and in the second interlayer insulating layer 116 , respectively.

[0196] The second pixel electrode 510 may be connected to the second drain electrode of the second TFT through a contact hole 1160 formed in the planarization layer 117. In this way, the second pixel electrode 510 is connected to the second circuit unit PC2 positioned in the first display area DA1 through the contact hole 1160 formed in the planarization layer 117, and the second light emitting unit 200 that emits light due to the second pixel electrode 510 is positioned in the first display area DA1, and the second dummy light emitting unit 200′ that emits light due to the second pixel electrode 510 is positioned in the second display area DA2.

[0197] like Figure 11 As shown in FIG, the first opening OP1 and the third opening OP3 may be positioned in the first display area DA1, and the second opening OP2 and the fourth opening OP4 may be positioned in the second display area DA2. In some embodiments, the first opening OP1 and the third opening OP3 may be positioned in the second display area DA2. In some embodiments, all of the first opening OP1, the second opening OP2, the third opening OP3, and the fourth opening OP4 may be positioned in the first display area DA1 or the second display area DA2.

[0198] Reference Figure 11 , the second dummy light emitting cell 200' that emits light due to the second pixel electrode 510 may be positioned in the left portion DA2' of the second display area DA2, and the first dummy light emitting cell 300' that emits light due to the first pixel electrode 310 may be positioned in the right portion DA2" of the second display area DA2. The first light emitting cell 300 and the second light emitting cell 200 may be positioned in the first display area DA1 to correspond to the first circuit unit PC1 and the second circuit unit PC2, respectively. Because the first dummy light emitting cell 300' and the second dummy light emitting cell 200' are positioned in the second display area DA2, the display area DA may extend from the first display area DA1 to the second display area DA2 (e.g., from the first display area DA1 to the second display area DA2).

[0199] Despite Figure 11 The second dummy light emitting unit 200' and the first dummy light emitting unit 300' are respectively illustrated in the left portion DA2' and the right portion DA2" of the second display area DA2, but in embodiments, two or more light emitting units may be positioned in the second display area DA2.

[0200] Because the first dummy light emitting unit 300' and the second dummy light emitting unit 200', which emit light due to the first circuit unit PC1 and the second circuit unit PC2 provided in the first display area DA1, respectively, are positioned in the second display area DA2 according to an embodiment of the present disclosure, damage to the pixel circuit PC due to static electricity existing around the transmission area TA can be prevented or reduced, and the display area DA can extend from the first display area DA1 to the second display area DA2 (for example, from the first display area DA1 to the second display area DA2). In addition, when compared with Figure 8 When compared with the embodiment of FIG. 4 , since the first light emitting unit 300 is also positioned in the first display area DA1 according to the present embodiment, the brightness can be improved.

[0201] In some embodiments, the first and second dummy light emitting cells 300 ′ and 200 ′ may exist in the second and third display areas DA2 and DA3 as well as the first and second areas AR1 and AR2 .

[0202] Figure 12 is a plan view illustrating a portion of a display device according to an embodiment of the present disclosure, particularly illustrating a signal line positioned in a second display area. Figure 13 It is shown along Figure 12 A cross-sectional view of a portion of a display device according to an embodiment of the present disclosure taken along line VI-VI'. Figure 12 and Figure 13 In, with Figure 6 、 Figure 7A and Figure 7B The same components are denoted by the same reference numerals, and thus repeated description thereof will not be given.

[0203] Reference Figure 12 , the pixels P may be positioned around the transmission area TA, and the first non-display area NDA1 may be positioned between the transmission area TA and the display area DA. The display area DA is as shown in FIG. Figure 3 The ground includes a first display area DA1, a second display area DA2 and a third display area DA3.

[0204] The pixels P may be positioned around the transmission area TA to be spaced apart from each other. The pixels P may be positioned above and below the transmission area TA and / or may be positioned at the left and right sides of the transmission area TA.

[0205] The signal lines (e.g., the scan line SWL, the previous scan line SIL, the emission control line EL, and the data line DL) that apply signals to the pixels P and are adjacent to the transmission area TA may bypass the transmission area TA. The first bypass wiring WL1 that passes through the first display area DA1 may be arranged in the first direction (corresponding to the first direction). Figure 12 The first bypass wiring WL1 passing through the first display area DA1 may be routed along the edge of the transmission area TA in the second display area DA2. The second bypass wiring WL2 and the third bypass wiring WL3 passing through the first display area DA1 may be routed in the second direction (corresponding to the y direction) to apply signals to the pixels P positioned above and below the transmission area TA. The transmission area TA is located between the pixels P positioned above and below the transmission area TA. Figure 12 The second bypass wiring WL2 and the third bypass wiring WL3 extending in the x-direction (in the x-direction) of the first display area DA1 may apply signals to pixels P located on the right and left sides of the transmission area TA, which is located between the pixels P located on the right and left sides of the transmission area TA. The second bypass wiring WL2 and the third bypass wiring WL3 passing through the first display area DA1 may detour along an edge of the transmission area TA in the second display area DA2. The first bypass wiring WL1, the second bypass wiring WL2, and the third bypass wiring WL3 may each correspond to one of the signal lines (e.g., the scan line SWL, the previous scan line SIL, the emission control line EL, and the data line DL).

[0206] Figure 12 The enlarged view shows a third area AR3 including a portion of the first display area DA1, a portion of the second display area DA2, and a portion of the first non-display area NDA1. According to an embodiment of the present disclosure, the second light-emitting unit 200 that emits light due to the second pixel electrode 510 and the first light-emitting unit 300 that emits light due to the first pixel electrode 310 can be positioned in the first display area DA1, and the first dummy light-emitting unit 300' that emits light due to the first pixel electrode 310 can be positioned in the second display area DA2. For example, a pixel defining layer 119 can be provided, the pixel defining layer 119 covers the edge of the first pixel electrode 310 and includes a first opening OP1 and a second opening OP2 through which a portion of the first pixel electrode 310 is exposed, and one of the first opening OP1 and the second opening OP2 can be positioned in the second display area DA2. Now, referring to Figure 13 The third area AR3 is described in more detail.

[0207] Reference Figure 13In some embodiments, the substrate 100 is positioned in the second display area DA2, and a buffer layer 110, a first gate insulating layer 111, a second gate insulating layer 113, a first interlayer insulating layer 115, a second interlayer insulating layer 116, and a planarization layer 117 are sequentially stacked on the substrate 100. The third bypass wiring WL3 is provided on the first gate insulating layer 111, the second bypass wiring WL2 is provided on the second gate insulating layer 113 (e.g., provided above the second gate insulating layer 113), and the first bypass wiring WL1 is provided on the first interlayer insulating layer 115 (e.g., provided above the first interlayer insulating layer 115). The first bypass wiring WL1, the second bypass wiring WL2, and the third bypass wiring WL3 can each correspond to one of the signal lines (e.g., the scan line SWL, the previous scan line SIL, the emission control line EL, and the data line DL).

[0208] The first light emitting unit 300 and the first dummy light emitting unit 300′ are positioned on the planarization layer 117. The first light emitting unit 300 and the first dummy light emitting unit 300′ share a first pixel electrode 310, and a first intermediate layer 320 and a second intermediate layer 320′, each including an organic emission layer, are positioned in a first opening OP1 and a second opening OP2, respectively, formed by the pixel defining layer 119. An opposing electrode 330 covering the first intermediate layer 320 and the second intermediate layer 320′ is positioned on the pixel defining layer 119.

[0209] The first pixel electrode 310 may be connected to the first drain electrode D1 of the first TFT TFT1 through a contact hole 1163 formed in the planarization layer 117 , and may be a (semi-) light-transmitting electrode or a reflective electrode.

[0210] Despite Figure 13 A first interlayer insulating layer 115, a second interlayer insulating layer 116, and a planarizing layer 117 are provided, and the first pixel electrode 310 is connected to the first TFT TFT1 through contact holes 1143, 1153, and 1163 respectively passing through the first interlayer insulating layer 115, the second interlayer insulating layer 116, and the planarizing layer 117, but the present disclosure is not limited thereto. In some embodiments, as shown in FIG. Figure 7B As described above, only the first interlayer insulating layer 115 of the first and second interlayer insulating layers 115 and 116 may be provided, and the first TFT TFT1 and the first pixel electrode 310 may be connected through the contact hole 1143 passing through the first interlayer insulating layer 115 and the contact hole 1163 passing through the planarization layer 117 .

[0211] According to an embodiment of the present disclosure, since the second light-emitting unit 200 that emits light due to the second circuit unit PC2 provided in the first display area DA1 (for example, emits light due to being connected to and driven by the second circuit unit PC2 provided in the first display area DA1) is positioned in the first display area DA1, the first opening OP1 and the second opening OP2 are defined by the pixel defining layer 119, and thus a first light-emitting unit 300 and a first dummy light-emitting unit 300' that emit light due to the first circuit unit PC1 (for example, emits light due to being connected to and driven by the first circuit unit PC1) are provided, the first light-emitting unit 300 is positioned in the first display area DA1 and the first dummy light-emitting unit 300' is positioned in the second display area DA2, damage to the pixel circuit PC due to static electricity existing around the transmission area TA can be prevented or reduced, and the display area DA can extend from the first display area DA1 to the second display area DA2 (for example, from the first display area DA1 to the second display area DA2).

[0212] Figure 14 is a cross-sectional view illustrating a portion of a display device according to an embodiment of the present disclosure.

[0213] In more detail, Figure 14 It is shown that it also includes Figure 13 1 is a cross-sectional view of a portion of a display device showing a thin film encapsulation layer 600 on the first light emitting unit 300 and the first dummy light emitting unit 300 ′.

[0214] Because OLED (see Figure 4A ) may be easily damaged by external moisture, oxygen, etc., so the OLED may be covered and protected by the thin film encapsulation layer 600. The thin film encapsulation layer 600 may cover the display area DA and may extend to the outside of the display area DA. For example, the thin film encapsulation layer 600 may be located on the substrate 100 and face the substrate 100. For example, the thin film encapsulation layer 600 may extend to at least a portion of the non-display area NDA. The thin film encapsulation layer 600 includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin film encapsulation layer 600 may include a first inorganic encapsulation layer 610, an organic encapsulation layer 620, and a second inorganic encapsulation layer 630.

[0215] The first inorganic encapsulation layer 610 may cover the opposing electrode 330 and may include (e.g., be) silicon oxide, silicon nitride and / or silicon oxynitride. In some embodiments, other layers such as a covering layer may be positioned between the first inorganic encapsulation layer 610 and the opposing electrode 330. Because the first inorganic encapsulation layer 610 is formed along the lower structure (e.g., the lower surface of the thin film encapsulation layer 600), the top surface of the first inorganic encapsulation layer 610 is uneven. Unlike the first inorganic encapsulation layer 610, the organic encapsulation layer 620 may cover the first inorganic encapsulation layer 610 to have a substantially flat top surface. In more detail, the top surface of the portion of the organic encapsulation layer 620 corresponding to the display area DA may be substantially flat. The organic encapsulation layer 620 may include (e.g., be) at least one material selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate and hexamethyldisiloxane. The second inorganic encapsulating layer 630 may cover the organic encapsulating layer 620 and may include (eg, be) silicon oxide, silicon nitride, and / or silicon oxynitride.

[0216] Because the thin film encapsulation layer 600 has the above-described multi-layer structure, even when cracks occur in the thin film encapsulation layer 600, the cracks do not connect between the first inorganic encapsulation layer 610 and the organic encapsulation layer 620 or between the organic encapsulation layer 620 and the second inorganic encapsulation layer 630. For example, when cracks occur in the thin film encapsulation layer 600, the cracks do not extend continuously through the entire thickness of the thin film encapsulation layer 600, either individually or in combination. Therefore, it is possible to prevent, minimize, or reduce the formation of a path through which external moisture and / or oxygen penetrate into the display area DA.

[0217] In addition, in an embodiment, a sealing substrate facing the substrate 100 may be included. Figure 1 ) is used to bond the substrate 100 and the sealing substrate using a sealing member such as glass frit.

[0218] Figure 15 is a plan view illustrating a portion of a display device according to an embodiment of the present disclosure. Figure 16 It is shown along Figure 15 1 is a cross-sectional view of a portion of a display device according to an embodiment of the present disclosure, taken along line VII-VII'.

[0219] Reference Figure 15 The display panel 10' includes a display area DA and a non-display area NDA. The display area DA includes a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 surrounds the third display area DA3, and the first display area DA1 completely surrounds the second display area DA2.

[0220] The component 60 can be positioned below the third display area DA3. For example, in some embodiments, the component 60 can be positioned in the third display area DA3 below the substrate 100. For example, the component 60 can be an electronic component that utilizes light and / or sound. Examples of the component 60 may include a sensor for receiving and utilizing light, such as an infrared sensor, a sensor for outputting and detecting light and / or sound to measure distance or identify fingerprints, a small lamp for outputting light, a speaker for outputting sound, and a camera. When the component 60 is an electronic component that utilizes light, the component 60 can use light of various suitable wavelengths, such as visible light, infrared light, or ultraviolet light. Multiple components 60 can be positioned in the third display area DA3. For example, a light-emitting device and a light-receiving device can be provided together as a component 60 in one third display area DA3. In some embodiments, the light-emitting unit and the light-receiving unit can both be provided (for example, can be provided simultaneously) in one component 60.

[0221] Reference Figure 15 In an enlarged view of a portion of FIG60 , a plurality of auxiliary pixels Pa may be positioned in the third display area DA3. Furthermore, a plurality of transmission units TA′, where no display element is positioned, may be positioned in the third display area DA3. The transmission units TA′ may be regions through which light (or signals) emitted from the assembly 60 or light (or signals) incident on the assembly 60 is transmitted.

[0222] The auxiliary pixels Pa may be continuously arranged to form one pixel group Pg. At least one auxiliary pixel Pa may be included in the pixel group Pg.

[0223] In this embodiment, the first dummy light emitting unit 300' can be formed by the first circuit unit PC1 (see Figure 6 ) drive, but can be connected to the first dummy circuit unit DPC1 (see Figure 6 ) overlap. For example, Figure 6 As shown in FIG, one light emitting unit can be moved to the second display area DA2. Figure 8 As shown in FIG, two light emitting units may be moved to the second display area DA2, or more light emitting units may be moved to the second display area DA2.

[0224] In this embodiment, a first light emitting unit 300 driven by the first circuit unit PC1 and overlapping with the first circuit unit PC1 may be further provided. Figure 9 As shown in FIG, the light emitting unit may extend to the second display area DA2 instead of moving to the second display area DA2. Figure 11 As shown in FIG, two light emitting units may extend to the second display area DA2, or more light emitting units may extend to the second display area DA2.

[0225] Reference Figure 16 The display device according to an embodiment of the present disclosure includes a third display area DA3. The auxiliary pixel Pa and the transmission unit TA' are positioned in the third display area DA3.

[0226] The auxiliary pixel Pa may include an auxiliary TFT TFT", an auxiliary storage capacitor Cst" and an auxiliary OLED'. The auxiliary TFT TFT" may include an auxiliary gate electrode G1", an auxiliary source electrode S1", an auxiliary drain electrode D1" and an auxiliary semiconductor layer A1". The auxiliary storage capacitor Cst" may include an auxiliary lower electrode CE1" and an auxiliary upper electrode CE2". The auxiliary OLED' may include an auxiliary pixel electrode 310', an auxiliary intermediate layer 320" including an organic emission layer and an auxiliary relative electrode 330'. The transmission unit TA' may include an opening portion TAH to correspond to the transmission unit TA'. In some embodiments, the substrate 100 is positioned in the third display area DA3, and the buffer layer 110, the first gate insulating layer 111, the second gate insulating layer 113, the first interlayer insulating layer 115, the planarization layer 117 and the pixel defining layer 119 are sequentially stacked on the substrate 100.

[0227] Because the transmission unit TA' is positioned in the third display area DA3, light transmitted to or received from the assembly 60 can be transmitted. For example, light emitted from the assembly 60 can pass through the transmission unit TA' in the z direction, and light generated outside the display device and incident on the assembly 60 can pass through the transmission unit TA' in the -z direction. In some embodiments, the assembly 60 may include a plurality of image sensors, and one image sensor may be positioned to correspond to one transmission unit TA'.

[0228] In this embodiment, the opposing electrode 330 may include an opening portion TAH corresponding to the transmission unit TA'. In some embodiments, the widths of the openings forming the opening portion TAH may be substantially the same. For example, the width of the opening of the opposing electrode 330 may be substantially the same as the width of the opening portion TAH.

[0229] When the opening portion TAH corresponds to the transmission unit TA', this means that the opening portion TAH overlaps the transmission unit TA'. In this case, the area of ​​the opening portion TAH (for example, the area when viewed from a plane) may be smaller than the area of ​​the first hole H1 formed in the second gate insulating layer 113. In some embodiments, the first hole H1 may be a hole formed in the first gate insulating layer 111, the second gate insulating layer 113, and the first interlayer insulating layer 115. To this end, Figure 16 , the width Wt of the opening portion TAH is smaller than the width W1 of the first hole H1. The area of ​​the opening portion TAH and the area of ​​the first hole H1 may be defined as the area of ​​the narrowest opening.

[0230] When the opening part TAH is formed, it means that members such as the opposite electrode 330 are removed from the transmission unit TA', and thus, the light transmittance of the transmission unit TA' may be significantly improved.

[0231] Because the first dummy light-emitting unit 300' driven by the first circuit unit PC1 and overlapping with the first dummy circuit unit DPC1 is provided according to an embodiment of the present disclosure, damage to the pixel circuit PC due to static electricity existing around the transmission area TA can be prevented or reduced, and the display area DA can extend from the first display area DA1 to the second display area DA2 (for example, from the first display area DA1 to the second display area DA2).

[0232] In addition, since the first light emitting unit 300 driven by and overlapping with the first circuit unit PC1 is further provided in another embodiment of the present disclosure, brightness may be improved.

[0233] Although the display device has been described, the present disclosure is not limited thereto. For example, a method of manufacturing a display device may also be within the scope of the present disclosure.

[0234] According to an embodiment of the present disclosure, a display device in which a light emitting unit is moved and / or extended may be provided. However, the scope of the present disclosure is not limited by the disclosed aspects and features.

[0235] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various appropriate changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims of the present disclosure and their equivalents.

Claims

1. A display device, wherein: The display device comprises: a substrate comprising a first display area and a second display area adjacent to the first display area; a first circuit unit positioned on the substrate and comprising a first driving thin film transistor and a first storage capacitor; a first dummy circuit unit, the first dummy circuit unit being located on the substrate, including a first dummy driving thin film transistor and a first dummy storage capacitor, and being located in the same layer as the first circuit unit; and a first dummy light-emitting unit, the first dummy light-emitting unit being located in the second display area on the first dummy circuit unit, being connected to the first circuit unit, and being configured to be driven by the first circuit unit; wherein the first circuit unit is located in the first display area, and the first dummy circuit unit is located in the second display area, The first dummy light-emitting unit overlaps with the first dummy circuit unit.

2. The display device according to claim 1, wherein The display device further includes a first light emitting unit, the first light emitting unit being located on the first circuit unit, connected to the first circuit unit, and configured to be driven by the first circuit unit. Wherein, the first light emitting unit overlaps with the first circuit unit.

3. The display device according to claim 1, wherein The display device further includes: a second circuit unit positioned on the substrate and including a second driving thin film transistor and a second storage capacitor; a second dummy circuit unit, which is located on the substrate, includes a second dummy driving thin film transistor and a second dummy storage capacitor, and is located in the same layer as the second circuit unit; and a second dummy light-emitting unit, the second dummy light-emitting unit being located on the second dummy circuit unit, connected to the second circuit unit, and configured to be driven by the second circuit unit, The second dummy light-emitting unit overlaps with the second dummy circuit unit.

4. The display device according to claim 3, wherein The display device further includes a second light emitting unit, the second light emitting unit being located on the second circuit unit, connected to the second circuit unit, and configured to be driven by the second circuit unit. Wherein, the second light emitting unit overlaps with the second circuit unit.

5. The display device according to claim 1, wherein The substrate further includes: a transmission area; and a first non-display area, The first display area surrounds the transmissive area, and the second display area is located between the transmissive area and the first display area. Wherein, the first non-display area is located between the transmission area and the second display area. The display device according to claim 1 , wherein: The substrate further includes: a third display area, Wherein, the transmission unit is located in the third display area, The first display area surrounds the third display area, and the second display area is located between the first display area and the third display area.

7. The display device according to claim 6, wherein The display device also includes a component positioned below the third display area.

8. A display device, wherein: The display device comprises: a substrate comprising a first display area and a second display area adjacent to the first display area; a first circuit unit, the first circuit unit being located on the substrate and comprising a first driving thin film transistor and a first storage capacitor; a first dummy circuit unit, the first dummy circuit unit being located on the substrate and comprising a first dummy driving thin film transistor and a first dummy storage capacitor; a first pixel electrode, the first pixel electrode being located on the first circuit unit and connected to the first driving thin film transistor; a pixel defining layer covering an edge of the first pixel electrode and having a first opening and a second opening through which a portion of the first pixel electrode is exposed; a first intermediate layer, the first intermediate layer being located in the first opening; a second intermediate layer, the second intermediate layer being located in the second opening; and an opposing electrode, the opposing electrode being located on the pixel defining layer and covering the first intermediate layer and the second intermediate layer, wherein the first circuit unit is located in the first display area, and the first dummy circuit unit is located in the second display area, One of the first opening and the second opening is located in the second display area and overlaps with the first dummy circuit unit.

9. The display device according to claim 8, wherein The first opening overlaps with the first circuit unit.

10. The display device according to claim 8, wherein The display device further includes: a second circuit unit, the second circuit unit being located on the substrate, in the same layer as the first circuit unit, and comprising a second driving thin film transistor and a second storage capacitor; a second pixel electrode, the second pixel electrode being located on the second circuit unit, being located in the same layer as the first pixel electrode, and being connected to the second driving thin film transistor; a third intermediate layer, the third intermediate layer being located on the second pixel electrode; and a fourth intermediate layer, said fourth intermediate layer being located in the same layer as said third intermediate layer, The pixel defining layer covers an edge of the second pixel electrode and further has a third opening and a fourth opening through which a portion of the second pixel electrode is exposed. Wherein, the third intermediate layer is located in the third opening, and Wherein, the fourth intermediate layer is located in the fourth opening.

11. The display device according to claim 10, wherein The third opening overlaps with the second circuit unit.

12. The display device according to claim 8, wherein The substrate further includes: a transmission area; and a first non-display area, wherein the first display area surrounds the transmission area, and the second display area is located between the transmission area and the first display area, Wherein, the first non-display area is located between the transmission area and the second display area.

13. The display device according to claim 8, wherein The substrate further includes: a third display area, Wherein, the transmission unit is located in the third display area, The first display area surrounds the third display area, and the second display area is located between the first display area and the third display area.

14. The display device according to claim 13, wherein The display device further includes a component positioned below the third display area.

15. A display device, wherein: The display device comprises: a substrate comprising: a transmissive area, a first display area surrounding the transmissive area, a second display area between the transmissive area and the first display area, and a first non-display area between the transmissive area and the second display area; a first bypass wiring, the first bypass wiring being located in the second display area, extending in a first direction, and bypassing the transmissive area along an edge of the transmissive area; a first circuit unit located in the first display area and comprising a first thin film transistor and a first storage capacitor; a first pixel electrode located on the first circuit unit and connected to the first thin film transistor; a pixel defining layer covering an edge of the first pixel electrode and having a first opening and a second opening through which a portion of the first pixel electrode is exposed; a first intermediate layer, the first intermediate layer being located in the first opening; a second intermediate layer, the second intermediate layer being located in the second opening; and an opposing electrode, the opposing electrode being located on the pixel defining layer and covering the first intermediate layer and the second intermediate layer, One of the first opening and the second opening overlaps with the first bypass wiring.

16. The display device according to claim 15, wherein The display device further includes: a second circuit unit located in the first display area, located in the same layer as the first circuit unit, and including a second thin film transistor and a second storage capacitor; a second pixel electrode, the second pixel electrode being located on the second circuit unit, being located in the same layer as the first pixel electrode, and being connected to the second thin film transistor; a third intermediate layer, the third intermediate layer being located on the second pixel electrode; and a fourth intermediate layer, said fourth intermediate layer being located in the same layer as said third intermediate layer, The pixel defining layer covers an edge of the second pixel electrode and further has a third opening and a fourth opening through which a portion of the second pixel electrode is exposed. Wherein, the third intermediate layer is located in the third opening, The fourth intermediate layer is located in the fourth opening, and One of the third opening and the fourth opening overlaps with the first bypass wiring.

17. The display device according to claim 15, wherein: The display device further includes a thin film encapsulation layer located on the substrate and facing the substrate.

18. The display device according to claim 15, in, The first storage capacitor includes an upper electrode and a lower electrode, and The lower electrode overlaps with the first thin film transistor.

19. A display device, wherein: The display device comprises: a substrate comprising a third display area, a first display area surrounding the third display area, and a second display area located between the third display area and the first display area; a first circuit unit located in the first display area and comprising a first thin film transistor and a first storage capacitor; a first pixel electrode located on the first circuit unit and connected to the first thin film transistor; a pixel defining layer covering an edge of the first pixel electrode and having a first opening and a second opening through which a portion of the first pixel electrode is exposed; a first intermediate layer, the first intermediate layer being located in the first opening; a second intermediate layer, the second intermediate layer being located in the second opening; and an opposing electrode, the opposing electrode being located on the pixel defining layer and covering the first intermediate layer and the second intermediate layer, wherein one of the first opening and the second opening overlaps with the second display area, and Wherein, the transmission unit is located in the third display area.

20. The display device according to claim 19, wherein The display device further includes: a component located below the third display area.

21. A display device, wherein: The display device comprises: a substrate comprising a transmissive area, a first display area surrounding the transmissive area, and a second display area between the transmissive area and the first display area; a first bypass wiring, the first bypass wiring being located in the second display area, bypassing the transmissive area, and extending along an edge of the transmissive area; a circuit unit, the circuit unit being disposed in the first display area and including a thin film transistor and a storage capacitor; a pixel electrode connected to the thin film transistor; a pixel defining layer, the pixel defining layer having a first opening, wherein the first opening exposes at least a portion of the pixel electrode; an intermediate layer, the intermediate layer being located in the first opening; and an opposing electrode, the opposing electrode being disposed on the pixel defining layer and covering the intermediate layer, The first opening is provided in the second display area and overlaps with the first bypass wiring.

22. The display device according to claim 21, wherein The display device further includes a component positioned below the transmissive area.

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