Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method for manufacturing the same are disclosed. A first redistribution layer pattern and a second redistribution layer pattern are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to expose a portion of the bonding pad portion and the edge pad portion. A dicing line is set on the scribe lane region. An invisible dicing process is performed along the dicing line to separate a semiconductor chip including a bonding pad portion from a semiconductor substrate. The semiconductor chip is set on a package substrate. A bonding wire is formed to connect the bonding pad portion to a bonding finger. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from an exposed portion of the edge pad portion.

Description

Technical Field

[0001] The present disclosure relates to semiconductor package technology, and more particularly, to semiconductor packages and methods of manufacturing the same. Background Art

[0002] The semiconductor package may be configured to include at least one semiconductor chip, a package substrate, and bonding wiring. At least one semiconductor chip may be mounted on the package substrate and may be electrically connected to the package substrate by bonding wiring. A plurality of semiconductor chips may be prepared on a semiconductor wafer, and the semiconductor wafer may be divided into a plurality of slices to provide separate semiconductor chips. A mechanical scribing process using a diamond wheel or an optical scribing process using a laser may be used to separate the semiconductor wafer into a plurality of semiconductor chips. Summary of the invention

[0003] According to an embodiment, a method for manufacturing a semiconductor package includes preparing a semiconductor substrate, the semiconductor substrate including a chip region provided with a first pad and a scribe lane region provided with a second pad. The scribe lane region surrounds the chip region. A dielectric layer is formed on the semiconductor substrate to expose the first pad and the second pad. A first redistribution layer pattern connected to the first pad and a second redistribution layer pattern connected to the second pad are formed on the dielectric layer. The first redistribution layer pattern extends to provide a bonding pad portion, and the second redistribution layer pattern extends to provide an edge pad portion located on the scribe lane region. A polymer pattern is formed to cover the first redistribution layer pattern and the second redistribution layer pattern. The polymer pattern is formed to expose the bonding pad portion and the boundary region, and the boundary region includes a portion of the dielectric layer on the scribe lane region and a portion of the edge pad portion. A dicing line is set in the boundary region. The dicing line extends to surround the chip region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including a portion of the chip region and the boundary region from the semiconductor substrate. The semiconductor chip is set on a package substrate including a bonding finger. A bonding wire is formed to be spaced apart from the exposed portion of the edge pad portion, a portion of the bonding wire being supported by an edge of the polymer pattern, and the bonding wire is formed to connect the bonding pad portion to the bonding finger.

[0004] According to another embodiment, a method for manufacturing a semiconductor package includes preparing a semiconductor substrate, the semiconductor substrate including a chip area provided with a bonding pad portion and a scribe lane area provided with an edge pad portion. The scribe lane area surrounds the chip area. A polymer pattern is formed to expose the bonding pad portion and a border area including a portion of the scribe lane area and a portion of the edge pad portion. A slicing line is set in the border area. The slicing line extends to surround the chip area. An invisible slicing process is performed along the slicing line to separate a semiconductor chip including a portion of the chip area and the border area from the semiconductor substrate. The semiconductor chip is set on a package substrate including a bonding finger. A bonding wiring is formed to be spaced apart from the exposed portion of the edge pad portion, and a portion of the bonding wiring is supported by the edge of the polymer pattern. The bonding wiring is formed to connect the bonding pad portion to the bonding finger.

[0005] According to another embodiment, a semiconductor package includes a semiconductor chip, the semiconductor chip includes an edge pad portion and a bonding pad portion. The edge of the edge pad portion is aligned with the edge of the semiconductor chip. The semiconductor chip is disposed on a package substrate including bonding fingers. The bonding pad portion is connected to the bonding fingers through bonding wiring. The semiconductor chip includes a semiconductor substrate and a polymer pattern formed on the semiconductor substrate. The polymer pattern exposes an edge portion of the semiconductor chip, a portion of the edge pad portion adjacent to the edge of the semiconductor chip, and the bonding pad portion. A portion of the bonding wiring is supported by the edge of the polymer pattern so that the bonding wiring is spaced apart from the edge pad portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a process flow chart illustrating a method of manufacturing a semiconductor package according to an embodiment.

[0007] Figures 2 to 12 A method of manufacturing a semiconductor package according to an embodiment is illustrated.

[0008] Fig.13 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0009] Fig.14 is a block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment.

[0010] Fig.15 is a block diagram illustrating another electronic system including a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0011] The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of these terms may be interpreted differently according to the technical personnel in the field to which the embodiments belong. If the terms are defined in detail, the terms may be interpreted according to these definitions. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meaning as those generally understood by the ordinary technicians in the field to which the embodiments belong.

[0012] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not used to indicate a specific order or quantity of elements.

[0013] It should also be understood that when an element or layer is referred to as being "on," "over," "under," "beneath," or "outside" another element or layer, the element or layer may be directly in contact with the other element or layer, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers (e.g., "between" versus "directly between" or "adjacent" versus "directly adjacent") should be interpreted in a similar manner.

[0014] Spatially relative terms such as "under," "below," "below," "above," "above," "top," "bottom," and the like may be used to describe the relationship of an element and / or feature to another element and / or feature, such as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the accompanying drawings. For example, when the device in the accompanying drawings is turned over, elements described as under and / or below other elements or features will be oriented above the other elements or features. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein shall be interpreted accordingly.

[0015] Semiconductor packages may include electronic devices such as semiconductor chips or semiconductor wafers. Semiconductor chips or semiconductor wafers may be obtained by separating semiconductor substrates such as wafers into multiple pieces using a wafer sawing process. Semiconductor chips may correspond to memory chips, logic chips, application specific integrated circuits (ASIC) chips, application processors (APs), graphics processing units (GPUs), central processing units (CPUs), or systems on chips (SoCs). Memory chips may include dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, NAND flash memory circuits, NOR flash memory circuits, magnetic random access memory (MRAM) circuits, resistive random access memory (ReRAM) circuits, ferroelectric random access memory (FeRAM) circuits, or phase change random access memory (PcRAM) circuits integrated on semiconductor substrates. Logic chips may include logic circuits integrated on semiconductor substrates. Semiconductor packages may be used in communication systems such as mobile phones, electronic systems associated with biotechnology or healthcare, or wearable electronic systems. Semiconductor packages may be applied to the Internet of Things (IoT).

[0016] Throughout the specification, the same reference numerals refer to the same elements. Even if a reference numeral is not mentioned or described with reference to a drawing, it may be mentioned or described with reference to another drawing. In addition, even if a reference numeral is not shown in a drawing, it may be mentioned or described with reference to another drawing.

[0017] Figure 1 is a process flow chart illustrating a method of manufacturing a semiconductor package according to an embodiment.

[0018] Reference Figure 1 , a method for manufacturing a semiconductor package may include preparing a semiconductor substrate including a chip area and a scribe line area (see step S1). A first redistribution layer pattern and a second redistribution layer pattern may be formed on the semiconductor substrate to provide a bonding pad portion and an edge pad portion (see step S2). The method for manufacturing a semiconductor package may also include: forming a border area that partially includes an edge pad portion and a polymer pattern that exposes a bonding pad portion (see step S3), setting a slicing line in the border area (see step S4), and separating the semiconductor chips by using a stealth slicing process performed along the slicing line (see step S5). At least one of the separated semiconductor chips may be mounted on a packaging substrate (see step S6). Subsequently, a portion of a bonding wiring supported by an edge of the polymer pattern may be formed to manufacture a semiconductor package (see step S7).

[0019] Figure 2is a plan view illustrating a layout M1 of a first RDL (redistribution layer) pattern 210 and a second RDL (redistribution layer) pattern 220 formed on a semiconductor substrate 100 . Figure 3 is a plan view illustrating a layout M2 of a polymer pattern 300 formed on a semiconductor substrate 100 . Figure 4 and Figure 5 1 and 2 are cross-sectional views each illustrating a semiconductor substrate 100 and a polymer pattern 300 . Figure 4 It is along Figure 3 A cross-sectional view taken along line XX′, and Figure 5 It is along Figure 3 Cross-sectional view along line CC′.

[0020] Reference Figure 1 , Figure 2 and Figure 4 , a semiconductor substrate 100 including a chip region 100C and a scribe lane region 100S may be provided (see Figure 1 In step S1), the chip regions 100C may be provided in the semiconductor substrate 100, and the scribe lane regions 100S may be defined as regions between the chip regions 100C. The semiconductor substrate 100 may correspond to a semiconductor wafer.

[0021] Each chip region 100C may be a region in which a semiconductor device such as a memory device is formed. The memory device may be a DRAM device or a flash memory device. Each chip region 100C may have a quadrilateral shape in a plan view. The chip region 100C may be arranged in a matrix form. The scribe lane region 100S may be defined as a region surrounding the periphery of the chip region 100C. The scribe lane region 100S may have a grid shape to define the chip region 100C. The scribe lane region 100S may be set to have a width of approximately 60 microns. Various test patterns or monitoring patterns may be set in the scribe lane region 100S.

[0022] The first pad 111 corresponding to the conductive pad may be provided in each chip region 100C of the semiconductor substrate 100. The second pad 112 corresponding to the conductive pad may be provided in the scribe lane region 100S of the semiconductor substrate 100. The second pad 112 may be provided to be spaced apart from the first pad 111. The first pad 111 may be a connection terminal for electrically connecting the integrated circuit of the chip region 100C to an external device. The first pad 111 may correspond to a chip pad. The second pad 112 may be a test terminal for measuring electrical characteristics of a test pattern or a monitoring pattern formed in the scribe lane region 100S.

[0023] The first RDL pattern 210 and the second RDL pattern 220 may be formed on the semiconductor substrate 100 (see Figure 1Step S2). Figure 4 , a dielectric layer 150 may be formed on the semiconductor substrate 100, and a portion of the dielectric layer 150 may be removed by patterning the dielectric layer 150 to expose the first pad 111 and the second pad 112. The dielectric layer 150 may be formed of a layer of a silicon-based insulating material. The dielectric layer 150 may be formed to include a silicon oxide layer such as a tetraethoxysilane (TEOS) layer. The dielectric layer 150 may be formed to have a thickness of about 4 micrometers to about 5 micrometers.

[0024] A conductive layer may be formed on the dielectric layer 150, and the conductive layer may be patterned to form a first RDL pattern 210 and a second RDL pattern 220. The first RDL pattern 210 and the second RDL pattern 220 may be formed of a metal layer containing an aluminum material or another conductive layer. The first RDL pattern 210 and the second RDL pattern 220 may be formed to have a similar thickness to the underlying dielectric layer 150. The first RDL pattern 210 and the second RDL pattern 220 may be formed to have a thickness of about 4 micrometers to about 5 micrometers.

[0025] Reference Figure 2 , the first RDL pattern 210 may be formed of a conductive pattern connected to the first pad 111 and extending to provide a bonding pad portion 211. Each first RDL pattern 210 may be a conductive pattern including an overlapping portion 213 overlapping any one of the first pads 111, a bonding pad portion 211 spaced apart from the overlapping portion 213, and a connecting portion 212 connecting the overlapping portion 213 to the bonding pad portion 211. The bonding pad portion 211 may be located at Figure 2 The scribe lane region 100S is adjacent to the scribe lane region 100S in a horizontal direction such that a distance between the scribe lane region 100S and the bonding pad portion 211 is smaller than a distance between the scribe lane region 100S and the first pad 111 .

[0026] The second RDL pattern 220 may be formed of a conductive pattern connected to the second pad 112 and extending to provide an edge pad portion 221. Each second RDL pattern 220 may be a conductive pattern including an overlapping portion 223 overlapping any one of the second pads 112, an edge pad portion 221 spaced apart from the overlapping portion 223, and a connecting portion 222 connecting the overlapping portion 223 to the edge pad portion 221. The distance between the bonding pad portion 211 and the edge pad portion 221 may be smaller than the distance between the first pad 111 and the edge pad portion 221. The edge pad portion 221 may correspond to a test pad that contacts a test probe of a test equipment to apply an electrical test signal to a second pad connected to the edge pad portion 221.

[0027] Reference Figure 1 , Figure 3 and Figure 4 , a polymer pattern 300 may be formed on the semiconductor substrate 100. The polymer pattern 300 may be formed of a passivation layer. The polymer patterns 300 may be formed to cover the chip regions 100C, respectively. Each polymer pattern 300 may be formed to have a first window 301 exposing the bonding pad portion 211. The polymer patterns 300 may be separated from each other by a second window 302 exposing the boundary region 100B.

[0028] The boundary region 100B opened by the second window 302 may correspond to a portion of the scribe lane region 100S. Figure 5 As shown, the boundary region 100B may be a region including a portion 151 of the dielectric layer 150 located in the scribe lane region 100S. Figure 4 As shown, the boundary region 100B may be a region including the portion 221 - 1 of each edge pad portion 221 located in the scribe lane region 100S.

[0029] The polymer pattern 300 may be formed to include a photosensitive polymer material. The polymer pattern 300 may be formed to include a photosensitive polyimide material such as a polyimide isoindole and quinazolinedione (PIQ) material. The polymer pattern 300 may be formed by forming a photosensitive polymer layer covering the dielectric layer 150 and the first and second RDL patterns 210 and 210, and by exposing and developing the photosensitive polymer layer to form the first and second windows 301 and 302.

[0030] Figure 6 is a plan view illustrating a layout M3 of dicing lines 400 provided on the semiconductor substrate 100 . Figure 7 It is along Figure 6 A cross-sectional view taken along line XX′.

[0031] Reference Figure 1 , Figure 6 and Figure 7 , the slicing line 400 may be arranged to extend along the boundary region 100B (see Figure 1 The slicing line 400 may correspond to a reference line or a reference area along which the semiconductor substrate 100 is cut in a subsequent slicing process to separate the chip area 100C. The slicing line 400 may be provided in a portion of the boundary area 100B.

[0032] Figure 8 and Fig. 9 2 is a cross-sectional view illustrating a process for separating the semiconductor chips 101C from each other. Fig.10 is a cross-sectional view illustrating a failure phenomenon occurring in a process of separating the semiconductor chip 101C.

[0033] Reference Figure 8 , defects 170 may be formed in the semiconductor substrate 100 using a stealth dicing process. A laser beam 501 for slicing the semiconductor substrate 100 may be directed into the semiconductor substrate 100 using a stealth dicing device 500D. The laser beam 501 may generate defects 170 in the semiconductor substrate 100. The laser beam 501 may be directed into the semiconductor substrate 100 while adjusting the focus of the laser beam 501 so that defects 170 spaced apart from each other are generated along a slicing line 400. The defects 170 may result in a damaged region in the semiconductor substrate 100. For example, the laser beam 501 may change the crystal structure of the semiconductor substrate 100 from a single crystal structure to an amorphous structure or a polycrystalline structure to form a damaged region including the crystal defects 170.

[0034] Reference Fig. 9 After the defect 170 is formed in the semiconductor substrate 100, tension may be applied to the semiconductor substrate 100 by expanding the semiconductor substrate 100. As a result, a crack may be formed from the defect 170 by the tension applied to the semiconductor substrate 100, and the crack may propagate into the semiconductor substrate 100. Since the defect 170 is formed along the slicing line ( Figure 7 400), so the crack can propagate along the dicing line 400, and the semiconductor substrate 100 can be separated into a plurality of semiconductor chips 101C by the propagation of the crack. This stealth dicing process can cut the semiconductor substrate 100 to provide a plurality of semiconductor chips 101C separated from each other. Each semiconductor chip 101C can be separated from the semiconductor substrate 100 to include any one chip region 100C and a portion of the boundary region 100B (see Figure 1 Step S5).

[0035] like Fig.10 As shown, if the polymer pattern 300-5 is formed to cover the edge pad portion 221-5 and the dicing line, the polymer pattern 300-5 may interfere with the propagation of the crack from the defect 170-5. Because the polymer pattern 300-5 has ductility, the polymer pattern 300-5 may interfere with the propagation of the crack, resulting in a dicing failure 179. That is, the crack does not propagate into the polymer pattern 300-5, so that the polymer pattern 300-5 holds the semiconductor chip 101C. Therefore, even after the stealth dicing process, the semiconductor chips 101C covered with the polymer pattern 300-5 are not separated from each other, resulting in a dicing failure 179.

[0036] like Figure 6 and Figure 8As shown, since the dicing line 400 is a region extending along the boundary region 100B, and the boundary region 100B is a region exposed through the second window 302 between the polymer patterns 300, there is no polymer pattern on the dicing line 400. Since the dicing line 400 is not covered with the polymer pattern 300, the dicing failure 179 can be prevented from occurring when the semiconductor substrate 100 is cut by the stealth dicing process.

[0037] Fig.11 is a cross-sectional view illustrating a process for mounting the semiconductor chip 101C on the package substrate 500 .

[0038] Reference Fig.11 The semiconductor chip 101C may be disposed on a package substrate 500 (see Figure 1 The semiconductor chip 101C may be mounted on the package substrate 500 using the adhesive layer 610. The package substrate 500 may include a conductive pattern for electrically connecting the bonding finger 510 to the semiconductor chip 101C. The package substrate 500 may be a printed circuit board (PCB) including an interconnection member. The bonding wire 700 may be formed to electrically connect the bonding finger 510 of the package substrate 500 to the bonding pad portion 211 of the semiconductor chip 101C (see FIG. Figure 1 Step S7).

[0039] Each bonding wire 700 may be formed to include a first end portion 701 contacting any one of the bonding pad portions 211, a second end portion 703 contacting any one of the bonding fingers 510, and an extension portion 702 connecting the first end portion 701 to the second end portion 703. The bonding wire 700 may be formed using a wire bonding process to provide the semiconductor package 10.

[0040] Fig.12 is an example Fig.11 An enlarged view of edge 300E of polymer pattern 300 is shown.

[0041] Reference Fig.11 and Fig.12 The bonding wires 700 may be formed such that a portion 702-1 of each bonding wire 700 is supported by the edge 300E of the polymer pattern 300. Since a portion 702-1 of the bonding wire 700 is supported by the edge 300E of the polymer pattern 300, the bonding wire 700 may extend to be spaced apart from the remaining edge pad portion 221D.

[0042] The remaining edge pad portion 221D may correspond to the remaining portion of the edge pad portion 221 after the edge pad portion 221 is cut by the stealth dicing process. Since the remaining edge pad portion 221D corresponds to the remaining portion of the edge pad portion 221 after the edge pad portion 221 is cut, Fig.12 As shown, the edge portion of the remaining edge pad portion 221D may be vertically aligned with the edge 101E of the semiconductor chip 101C. Because the portion 221E of the remaining edge pad portion 221D overlaps the boundary region 100B, the portion 221E of the remaining edge pad portion 221D may be exposed by the polymer pattern 300 even after the stealth dicing process.

[0043] The portion 221E of the remaining edge pad portion 221D may be exposed by the polymer pattern 300 to undesirably contact the bonding wiring 700. However, according to an embodiment, a portion 702-1 of the bonding wiring 700 may be supported by the edge 300E of the polymer pattern 300 so that the bonding wiring 700 is spaced apart from the portion 221E of the remaining edge pad portion 221D. Therefore, even if the portion 221E of the remaining edge pad portion 221D may be exposed by the polymer pattern 300, the portion 221E of the remaining edge pad portion 221D may be prevented from contacting the bonding wiring 700.

[0044] To reliably ensure electrical disconnection between the bonding wiring 700 and the exposed portion 221E of the remaining edge pad portion 221D, the width W3 of the exposed portion 221E of the remaining edge pad portion 221D and the thickness T of the edge portion 300D of the polymer pattern 300 on the remaining edge pad portion 221D may be appropriately adjusted.

[0045] Refer again Figure 4 and Fig.12 , before the semiconductor substrate 100 is cut by the stealth dicing process, the width of the portion 221 - 1 of the edge pad portion 221 exposed by the second window 302 between the polymer patterns 300 ( Figure 4 The width ( W1 ) of the exposed portion 221E of the remaining edge pad portion 221D may be within a range of one fifth to one half of the total width W2 of the edge pad portion 221. After the semiconductor substrate 100 is cut by the stealth dicing process, the width ( W1 ) of the exposed portion 221E of the remaining edge pad portion 221D may be within a range of one fifth to one half of the total width W2 of the edge pad portion 221. Figure 3 The width W3) may be equal to or smaller than the width (W3) of the portion 221-1 of the edge pad portion 221 exposed through the second window 302 between the polymer patterns 300. Figure 4 Therefore, the width of the portion 221-1 of the edge pad portion 221 exposed through the second window 302 between the polymer patterns 300 can be limited ( Figure 4 The width of the exposed portion 221E of the remaining edge pad portion 221D is adjusted by Fig.12 W3).

[0046] Figure 4 The edge pad portion 221 may be formed of a conductive pattern having a width W2 of about 40 micrometers to about 50 micrometers, and the second window 302 between the polymer patterns 300 may be formed to have a width W1 of about 10 micrometers to about 20 micrometers. The portion 221-1 of the edge pad portion 221 may be exposed through the second window 302 to have a width W1 of about 10 micrometers to about 20 micrometers. After the semiconductor substrate 100 is cut by the stealth dicing process, the width ( Fig.12 Thus, since the portion 221E of the remaining edge pad portion 221D is exposed to have a relatively narrow width W3, Fig.12 The bonding wire 700 may be sufficiently spaced apart from the exposed portion 221E of the remaining edge pad portion 221D.

[0047] like Figure 4 As shown, the thickness T of the edge portion 300D of the polymer pattern 300 on the edge pad portion 221 may be within a range of one-fifth of the width W1 of the portion 221-1 of the edge pad portion 221 exposed through the second window 302 to half of the width W1 of the portion 221-1 of the edge pad portion 221 exposed through the second window 302. When the portion 221-1 of the edge pad portion 221 exposed through the second window 302 has a width of 10 micrometers to 20 micrometers (corresponding to the width W1), the thickness T of the edge portion 300D of the polymer pattern 300 on the edge pad portion 221 may be about 4 micrometers. The polymer pattern 300 directly disposed on the dielectric layer 150 may have a thickness of about 8.5 micrometers. In this way, because the thickness T of the edge portion 300D of the polymer pattern 300 on the edge pad portion 221 is limited, the bonding wire 700 may be sufficiently spaced apart from the exposed portion 221E of the remaining edge pad portion 221D, as shown in FIG. Fig.12 shown.

[0048] Refer again Figure 4, the width of the boundary region 100B may be equal to the width of the second window 302 (corresponding to the width W1). The width of the boundary region 100B may be set in a range of about 10 micrometers to about 20 micrometers. The width of the scribe lane region 100S may be set in a range of three times the width of the boundary region 100B (corresponding to the width W1) to six times the width of the boundary region 100B (corresponding to the width W1). When the width of the boundary region 100B (corresponding to the width W1) is smaller than the width W2 of the edge pad portion 221, the bonding wiring ( Fig.12 700) may be spaced apart from the exposed portion 221E of the remaining edge pad portion 221D.

[0049] Fig.13 is a cross-sectional view illustrating a semiconductor package 20 according to another embodiment.

[0050] Reference Fig.13 , the upper semiconductor chip 101C-2 can be stacked on the semiconductor chip 101C. The upper semiconductor chip 101C-2 can be attached to the semiconductor chip 101C using an adhesive layer 630. In this case, a portion of the bonding wiring 700 can be embedded in the adhesive layer 630. The upper bonding wiring 700-2 can be additionally formed to electrically connect the upper semiconductor chip 101C-2 to the semiconductor chip 101C. The sealant 590 can be formed on the packaging substrate 500 to cover and protect the semiconductor chip 101C and the upper semiconductor chip 101C-2. The sealant 590 can be formed to include a sealant material such as an epoxy molding compound (EMC) material. The external connector 550 can be attached to the packaging substrate 500 to electrically connect the semiconductor package 20 to an external device or an external system. The external connector 550 can be formed by a connecting member such as a solder ball.

[0051] Fig.14 7800 is a block diagram illustrating an electronic system including a memory card 7800 using at least one semiconductor package according to an embodiment of the present disclosure. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one semiconductor package according to an embodiment.

[0052] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so that stored data is read out or data is stored in response to a read / write request from the host 7830 .

[0053] Fig.158710 is a block diagram illustrating an electronic system 8710 including at least one semiconductor package according to an embodiment of the present disclosure. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be connected to each other through a bus 8715, which provides a path through which data moves.

[0054] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include at least one semiconductor package according to an embodiment of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store commands and / or data executed by the controller 8711, etc.

[0055] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0056] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be a wired or wireless type. For example, the interface 8714 may include an antenna, or a wired or wireless transceiver.

[0057] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0058] If the electronic system 8710 is a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0059] The inventive concept has been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will appreciate that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive point of view but from an exemplary point of view. The scope of the inventive concept is not limited to the above description, but is defined by the appended claims, and all unique features within the scope of equivalents should be interpreted as included in the inventive concept.

[0060] CROSS-REFERENCE TO RELATED APPLICATIONS

[0061] This application claims priority from Korean Application No. 10-2020-0002724, filed on January 8, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor package, the method comprising the following steps: Prepare a semiconductor substrate, the semiconductor substrate comprising a chip region provided with a first pad and a scribe lane region provided with a second pad, wherein the scribe lane region surrounds the chip region; forming a dielectric layer on the semiconductor substrate to expose the first pad and the second pad; forming a first redistribution layer pattern connected to the first pad and a second redistribution layer pattern connected to the second pad on the dielectric layer, wherein the first redistribution layer pattern extends to provide a bonding pad portion and the second redistribution layer pattern extends to provide an edge pad portion located on the scribe lane area; forming a polymer pattern covering the first redistribution layer pattern and the second redistribution layer pattern, wherein the polymer pattern is formed to expose the bonding pad portion and a boundary region, the boundary region including a portion of the dielectric layer on the scribe lane region and a portion of the edge pad portion; providing a slicing line in the boundary region, the slicing line extending to surround the chip region; performing a stealth dicing process along the dicing line to separate a semiconductor chip including the chip region and a portion of the boundary region from the semiconductor substrate; disposing the semiconductor chip on a package substrate including bond fingers; and forming a bonding wire, a portion of which is supported by an edge of the polymer pattern to be spaced apart from an exposed portion of the edge pad portion, wherein the edge of the polymer pattern is in direct contact with the exposed portion of the edge pad portion, and wherein the bonding wire is formed to partially connect the bonding pad to the bonding finger.

2. The method according to claim 1, wherein: A distance between the bonding pad portion and the edge pad portion is smaller than a distance between the first pad and the edge pad portion.

3. The method according to claim 1, wherein: The polymer pattern is formed such that a width of a portion of the edge pad portion exposed by the polymer pattern is in a range from one fifth of a width of the edge pad portion to one half of the width of the edge pad portion.

4. The method according to claim 1, wherein: The polymer pattern is formed such that a thickness of an edge portion of the polymer pattern on the edge pad portion is in a range from one fifth to half the width of a portion of the edge pad portion exposed by the polymer pattern.

5. The method according to claim 1, wherein: The scribe lane region has a width in a range of three times the width of the boundary region to six times the width of the boundary region.

6. The method according to claim 1, wherein: The border region has a width of 10 micrometers to 20 micrometers.

7. The method according to claim 1, wherein: The step of forming the polymer pattern comprises the following steps: forming a photosensitive polymer layer covering the dielectric layer, the first redistribution layer pattern, and the second redistribution layer pattern; and The photopolymer layer is exposed and developed.

8. The method according to claim 7, wherein: The photosensitive polymer layer includes a photosensitive polyimide material.

9. A method for manufacturing a semiconductor package, the method comprising the following steps: Prepare a semiconductor substrate, the semiconductor substrate comprising a chip region provided with a bonding pad portion and a scribe lane region provided with an edge pad portion, wherein the scribe lane region surrounds the chip region; forming a polymer pattern, the polymer pattern exposing the bonding pad portion and a boundary region, the boundary region including a portion of the scribe lane region and a portion of the edge pad portion; providing a slicing line in the boundary region, the slicing line extending to surround the chip region; performing a stealth dicing process along the dicing line to separate a semiconductor chip including the chip region and a portion of the boundary region from the semiconductor substrate; disposing the semiconductor chip on a package substrate including bond fingers; and forming a bonding wire, a portion of which is supported by an edge of the polymer pattern to be spaced apart from an exposed portion of the edge pad portion, wherein the edge of the polymer pattern is in direct contact with the exposed portion of the edge pad portion, and wherein the bonding wire is formed to partially connect the bonding pad to the bonding finger.

10. A semiconductor package, comprising: a semiconductor chip comprising an edge pad portion and a bonding pad portion, wherein an edge of the edge pad portion is aligned with an edge of the semiconductor chip; a packaging substrate on which the semiconductor chip is disposed, wherein the packaging substrate comprises bonding fingers; and a bonding wire that connects the bonding pad portion to the bonding finger, Wherein, the semiconductor chip comprises: semiconductor substrate; and a polymer pattern formed on the semiconductor substrate to expose an edge portion of the semiconductor chip, a portion of the edge pad portion adjacent to an edge of the semiconductor chip, and the bonding pad portion, wherein a portion of the bonding wire is supported by an edge of the polymer pattern such that the bonding wire is partially spaced apart from the edge pad, and Wherein, the edge of the polymer pattern is in direct contact with the exposed portion of the edge pad portion.

11. The semiconductor package according to claim 10, wherein: The semiconductor substrate comprises: a first pad, the first pad being disposed in a chip region; and a second pad, the second pad being disposed in a scribe lane region, The scribe line area surrounds the chip area.

12. The semiconductor package according to claim 11, wherein The semiconductor chip further comprises: a dielectric layer formed on the semiconductor substrate to expose the first pad and the second pad; a first redistribution layer pattern formed on the dielectric layer to connect to the first pad and provide the bonding pad portion; and A second redistribution layer pattern is formed on the dielectric layer to be connected to the second pad and to provide the edge pad portion.

13. The semiconductor package according to claim 10, wherein: The polymer pattern includes a photosensitive polyimide material.

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