Semiconductor device and method of forming the same

Abstract

In an embodiment, the device includes: a first wafer including a first substrate and a first interconnect structure, wherein a sidewall of the first interconnect structure forms an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, wherein a sidewall of the first substrate is laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Since the development of integrated circuits (ICs), the semiconductor industry has experienced continuous rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For most, these increases in integration density have come from the continuous reduction of the minimum feature size, which allows more components to be integrated in a given area. With the growing demand for miniaturization, higher speed, greater bandwidth, and lower power consumption and latency, the demand for smaller and more innovative technologies for packaging semiconductor die has grown.

[0003] Stacked semiconductor devices have become an effective technology for further reducing the physical size of semiconductor devices. In a stacked semiconductor device, active circuits such as logic circuits and memory circuits are fabricated on different semiconductor wafers. Two or more semiconductor wafers can be bonded together by a suitable bonding technique to further reduce the form factor of the semiconductor device. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, including: obtaining a first processed wafer including a first substrate and a first interconnect structure, the first substrate including a semiconductor material, the first interconnect structure including metal interconnects between dielectric materials; removing an edge region of the first interconnect structure with a first trimming process that removes the dielectric material of the first interconnect structure at a rate faster than the semiconductor material of the first substrate; after removing the edge region of the first interconnect structure, removing an edge region of the first substrate with a second trimming process that removes the semiconductor material of the first substrate at a rate faster than the dielectric material of the first interconnect structure; and bonding a second processed wafer to a front side of the first processed wafer.

[0005] Some other embodiments of the present application provide a method of forming a semiconductor device, including: obtaining a first processed wafer including a substrate and an interconnect structure; etching the interconnect structure to remove the interconnect structure from an edge region of the first processed wafer; after etching the interconnect structure, sawing the substrate to remove a first portion of the substrate in the edge region of the first processed wafer; bonding the first processed wafer to a second processed wafer; and thinning the substrate to remove a second portion of the substrate in the edge region of the first processed wafer.

[0006] Some additional embodiments of the present application provide a semiconductor device, comprising: a first wafer including a first substrate and a first interconnect structure, wherein a sidewall of the first interconnect structure forms an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, wherein the sidewall of the first substrate is laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1 to 9 is a cross-sectional view of an intermediate step during a wafer bonding process according to some embodiments.

[0009] Figure 10A and Figure 10B illustrates a die stack according to some embodiments.

[0010] Figures 11 to 15 is a cross-sectional view of an intermediate step during a wafer bonding process according to some other embodiments.

[0011] Figures 16 to 20 is a cross-sectional view of an intermediate step during a wafer bonding process according to some other embodiments.

[0012] Figures 21 to 25 is a cross-sectional view of an intermediate step during a wafer bonding process according to some other embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Moreover, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0015] According to some embodiments, a first wafer (e.g., a top wafer) is processed, tested, and trimmed, and then subsequently bonded to a second wafer (e.g., a bottom wafer). The processed wafer may have a rounded or bulged edge due to, for example, uneven chemical mechanical polishing (CMP) that may occur at the wafer edge during processing. Trimming the edge of the first processed wafer prior to bonding can increase the uniformity of the bonding strength in the resulting bonded wafer structure. Additionally, trimming the edge of the first processed wafer prior to bonding can reduce the risk of edge breakage during subsequent thinning of the bonded first processed wafer. According to some embodiments, multiple types of trimming processes are used to trim the edge of the first wafer. Specifically, a first trimming process is used to trim the dielectric components at the wafer edge, and subsequently a second trimming process is used to trim the semiconductor components at the wafer edge. In some embodiments, the first trimming process is a chemical or ablation process, which, compared to a mechanical process, enables trimming of fragile components such as ultra-low k (ELK) dielectric layers with a reduced risk of damage. Thus, the yield of the resulting bonded wafer structure can be improved, thereby reducing the manufacturing cost.

[0016] Figures 1 to 9 is a cross-sectional view of an intermediate step during a wafer bonding process. As discussed in more detail below, Figures 1 to 9 shows trimming the first processed wafer (see Figure 1 ) and bonding it to the second processed wafer (see Figure 7) process. The wafer includes a plurality of integrated circuit dies 50 formed therein and / or thereon. The integrated circuit dies 50 can be logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system on a chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies (e.g., image sensor), microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) die), etc. or a combination thereof.

[0017] In Figure 1 , a first wafer is formed or obtained. The first wafer has a plurality of device regions 52D, and integrated circuit dies 50 are formed in and / or on each device region 52D. Additionally, the first wafer has an edge region 52E that is laterally disposed at the edge of the first wafer and surrounds the device regions 52D. As discussed in more detail below, multiple trimming processes will be performed in the edge region 52E. The first wafer includes a semiconductor substrate 52, an interconnect structure 54, conductive vias 56, one or more passivation layers 58, and contact pads 60.

[0018] The semiconductor substrate 52 can be doped or undoped silicon, or the active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 can include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates such as multi-layer or gradient substrates can also be used. The semiconductor substrate 52 has an active surface (e.g., the surface facing up in Figure 1 ), which is sometimes referred to as the front side, and a passive surface (e.g., the surface facing down in Figure 1 ), which is sometimes referred to as the back side.

[0019] Devices are formed at the active surface of the semiconductor substrate 52. The devices can be active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, etc.). The passive surface can be device-free. An interlayer dielectric (ILD) is above the active surface of the semiconductor substrate 52. The ILD surrounds and can cover the devices. The ILD can include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0020] The interconnect structure 54 is on the active surface of the semiconductor substrate 52. The interconnect structure 54 interconnects the devices at the active surface of the semiconductor substrate 52 to form an integrated circuit. The interconnect structure 54 can include, for example, a metallization pattern 54A in a dielectric material 54B. The dielectric material 54B can include one or more dielectric layers such as one or more low-k (LK) or ultra-low-k (ELK) dielectric material layers. The metallization pattern 54A can be metal interconnects (e.g., metal lines and vias) formed in one or more dielectric layers. The interconnect structure 54 can be formed by a damascene process such as a single damascene process, a dual damascene process, etc. The metallization pattern 54A of the interconnect structure 54 is electrically coupled to the devices at the active surface of the semiconductor substrate 52.

[0021] The conductive via 56 is formed to extend into the interconnect structure 54 and / or the semiconductor substrate 52. The conductive via 56 is electrically coupled to the metallization pattern 54A of the interconnect structure 54. As an example of forming the conductive via 56, a groove can be formed in the interconnect structure 54 and / or the semiconductor substrate 52 by, for example, etching, milling, laser technology, a combination thereof, etc. A thin dielectric material can be formed in the groove, such as by using an oxidation technique. A barrier layer can be conformally deposited in the opening by, for example, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, etc. The barrier layer can be formed of an oxide, nitride, or oxynitride such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, etc. A conductive material can be deposited over the barrier layer and in the opening. The conductive material can be formed by an electroplating process, CVD, PVD, a combination thereof, etc. Examples of the conductive material are copper, tungsten, aluminum, silver, gold, a combination thereof, etc. Excess conductive material and the barrier layer are removed from the surface of the interconnect structure 54 and / or the semiconductor substrate 52 by, for example, chemical mechanical polishing (CMP). The remaining portions of the barrier layer and the conductive material form the conductive via 56. In the illustrated embodiment, the conductive via 56 only extends into the semiconductor substrate 52, but it should be understood that the conductive via 56 can also extend into some (or all) of the layers of the interconnect structure 54.

[0022] In the illustrated embodiment, the conductive via 56 is not yet exposed at the back side (e.g., the back side of the semiconductor substrate 52) of the first wafer. Instead, the conductive via 56 is buried in the semiconductor substrate 52. As discussed in more detail below, in subsequent processing, the conductive via 56 will be exposed at the back side of the first wafer. After exposure, the conductive via 56 can be referred to as a through-silicon via or through-substrate via (TSV).

[0023] A passivation layer 58 is formed on the interconnect structure 54. The passivation layer 58 can be formed of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics (such as carbon-doped oxides), very low-k dielectrics (such as silica doped with porous carbon), polymers (such as polyimide), solder mask, polybenzoxazole (PBO), benzocyclobutene (BCB)-based polymers, molding compounds, etc. or combinations thereof. The passivation layer 58 can be formed by spin coating, lamination, chemical vapor deposition (CVD), etc. or combinations thereof. In some embodiments, the passivation layer 58 includes a silicon nitride layer and a silicon oxide layer on the silicon nitride layer.

[0024] Contact pads 60 are formed to extend through the passivation layer 58 to physically and electrically couple to the metallization pattern 54A of the interconnect structure 54. For example, the contact pads 60 can physically and electrically couple to metal components that are part of the topmost metallization pattern of the interconnect structure 54. The contact pads 60 are formed of a conductive material such as aluminum, copper, tungsten, silver, gold, combinations thereof, etc. In some embodiments, the contact pads 60 are formed of a conductive material (e.g., aluminum) that is less costly than the metallization pattern 54A of the interconnect structure 54. As an example of forming the contact pads 60, an opening can be formed in the passivation layer 58, and a seed layer can be formed along the passivation layer in the opening through the passivation layer 58. The opening can be formed by acceptable lithography and etching techniques. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD, etc. A photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. The pattern of the photoresist corresponds to the contact pads 60. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist can be removed by an acceptable ashing or stripping process such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, for example, by using an acceptable etching process (such as wet etching or dry etching). The remaining portions of the seed layer and the conductive material form the contact pads 60.

[0025] As discussed in more detail below, the contact pads 60 will be used for device testing. In some embodiments, the contact pads 60 are test pads that are only used for device testing and are not electrically coupled or enabled during the normal operation of the integrated circuit die 50. In some embodiments, the contact pads 60 are die connectors for both device testing and normal operation of the integrated circuit die 50.

[0026] In Figure 2 a circuit probe (CP) test is performed on an integrated circuit die 50 to confirm whether the integrated circuit die 50 is a known good die (KGD). The integrated circuit die 50 is tested by using probes 62. The probes 62 are physically and electrically coupled to contact pads 60 through, for example, reflow test connectors. Only wafers having integrated circuit dies 50 that are KGDs are subjected to subsequent processing and packaging, while wafers having integrated circuit dies 50 that fail the CP test are not packaged. The test may include testing the functions of various integrated circuit dies 50, or may include testing for known open or short circuits that can be expected based on the design of the integrated circuit die 50. After the test is completed, the probes 62 are removed and any excess reflow material on the contact pads 60 may be removed by, for example, an etching process, chemical mechanical polishing (CMP), a grinding process, etc.

[0027] In Figure 3 a dielectric layer 64 is formed at the front side of the wafer, for example, on the contact pads 60 and the passivation layer 58. The dielectric layer 64 buries the contact pads 60. When the contact pads 60 are test pads, the test pads will remain electrically isolated in the resulting integrated circuit die 50. The dielectric layer 64 may be a polymer such as PBO, polyimide, a BCB-based polymer, etc.; a nitride such as nitride; an oxide such as silicon oxide, TEOS-based oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or a combination thereof. The dielectric layer 64 may be formed, for example, by spin coating, lamination, deposition (e.g., CVD), etc.

[0028] Die connectors 66 are formed to extend through the dielectric layer 64 and the passivation layer 58 to physically and electrically couple to the metallization pattern 54A of the interconnect structure 54. The die connectors 66 are electrically coupled to the corresponding integrated circuits of the integrated circuit die 50. The die connectors 66 may include vias or conductive pillars and may be formed of a metal such as copper. In the illustrated embodiment, each of the die connectors 66 includes a contact pad portion and a via portion, where the via portion connects the contact pad portion to the metallization pattern 54A of the interconnect structure 54. The die connectors 66 may be formed by a damascene process such as a single damascene process, a dual damascene process, etc. After formation, the die connectors 66 and the dielectric layer 64 may be planarized. The planarization may be performed by an etching process, chemical mechanical polishing (CMP), a grinding process, etc.

[0029] In another embodiment, the die connector 66 is formed before the dielectric layer 64. For example, the die connector 66 can be formed in a manner similar to the contact pad 60 (which can be a die connector, for example), and then, the dielectric layer 64 can be deposited on the die connector 66. Then, the die connector 66 and the dielectric layer 64 can be planarized in a manner similar to that described above to expose the die connector 66.

[0030] After formation, the dielectric layer 64, the passivation layer 58, and / or the dielectric material 54B can extend into the edge region 52E. For example, when such layers are formed by a conformal deposition process, these layers can be formed in the edge region 52E. As discussed in more detail below, portions of these layers in the edge region 52E will be removed by performing multiple trimming processes.

[0031] In Figure 4 a first trimming process 70 is performed to remove the edge regions of the dielectric layer 64, the passivation layer 58, and the interconnect structure 54. Specifically, portions of the dielectric layer 64, the passivation layer 58, and the dielectric material 54B in the edge region 52E are removed by performing the first trimming process 70. A mask 72 can be used to cover portions of the dielectric layer 64, the passivation layer 58, and the dielectric material 54B in the device region 52D during the first trimming process 70. As discussed in more detail below, the first trimming process 70 is a non-mechanical process such as an etching process (such as a chemical process or an ablation process). As described above, the dielectric material 54B of the interconnect structure 54 can be formed of an ELK material. The ELK material is brittle and can be easily damaged by mechanical handling. By trimming the interconnect structure 54 with the first trimming process 70 (e.g., an etching process), damage to the interconnect structure 54 can be avoided or reduced.

[0032] The mask 72 can be formed before performing the first trimming process 70. The mask 72 can be formed of a photoresist such as a single-layer photoresist, a bilayer photoresist, a trilayer photoresist, etc. In some embodiments, the mask 72 is a trilayer mask including a bottom layer (e.g., a bottom anti-reflective coating (BARC) layer), an intermediate layer (e.g., nitride, oxide, oxynitride, etc.), and a top layer (e.g., photoresist). The mask 72 can be formed by spin coating, a deposition process such as CVD, a combination thereof, etc. The mask 72 can be patterned using acceptable lithography techniques such that it covers the device region 52D and exposes the edge region 52E. In embodiments where the mask 72 includes photoresist, the photoresist can be patterned by exposing the photoresist to a patterned energy source (e.g., a patterned light source) to cause a chemical reaction, thereby causing a physical change in those portions of the photoresist exposed to the patterned light source. Then, the photoresist can be developed by applying a developer to the exposed photoresist to utilize the physical change and selectively remove either the exposed portions or the unexposed portions of the photoresist according to the desired pattern.

[0033] After the first trimming process 70, the trimmed layers (e.g., dielectric layer 64, passivation layer 58, and dielectric material 54B) each have a recessed profile shape, which, for example, has a continuously increasing width in a direction extending away from the active surface of the semiconductor substrate 52. Note that the width W of the bottom surface of the dielectric material 54B 1 is greater than the width W of the top surface of the dielectric layer 64 2 . The width W 1 can be in the range of about 290 mm to about 299.5 mm, and the width W 2 can be in the range of about 290 mm to about 299.5 mm. Each of the widths W 1 , W 2 is less than the width W of the semiconductor substrate 52 3 . The width of W 3 can be in the range of about 299.8 mm to about 300.2 mm. Since the trimmed layers all have a recessed profile shape, the sidewalls of the trimmed layers each form a first obtuse angle θ with a plane parallel to the sidewalls of the semiconductor substrate 52 1 . For example, the first obtuse angle θ 1 can be in the range of about 170 degrees to about 180 degrees. Thus, the first trimming process 70 can be considered a directional trimming process performed along the first direction D 1 .

[0034] The first trimming process 70 is performed with material selectivity for the dielectric layer 64, the passivation layer 58, and the dielectric material 54B. In other words, the first trimming process 70 selectively removes the dielectric material of the trimmed layers (e.g., dielectric layer 64, passivation layer 58, and dielectric material 54B) at a rate faster than the semiconductor material of the semiconductor substrate 52. For example, the etch selectivity between the dielectric material (e.g., oxide) and the semiconductor material (e.g., silicon) with respect to the first trimming process 70 can be in the range of about 5 to about 50. The profile shape of the trimmed layers can be controlled by controlling the parameters of the first trimming process 70. Specifically, by performing the first trimming process 70 with a high etch selectivity, the trimmed layers can all be formed with a recessed profile shape. Performing the first trimming process 70 such that it has an etch selectivity within the ranges discussed above enables the trimmed layers to all have a recessed profile shape. Performing the first trimming process 70 such that it has an etch selectivity outside the ranges discussed above does not enable the trimmed layers to have a recessed profile shape.

[0035] In some embodiments, the first trimming process 70 is a chemical process such as plasma etching that is performed to have a desired etch selectivity. During the plasma etching process, the mask 72 covers the device region 52D. The plasma etching process is performed in the processing chamber with the process gas supplied to the process chamber. The process gas can be activated into a plasma by any suitable plasma generation method such as a transformer coupled plasma (TCP) system, an inductively coupled plasma (ICP) system, a capacitively coupled plasma (CCP) system, a magnetically enhanced reactive ion technique, an electron cyclotron resonance technique, etc. In some embodiments, during the plasma etching process, the plasma generation power pulsates between a low power and a high power. In some embodiments, during the plasma etching process, the applied bias voltage also pulsates between a low voltage and a high voltage. In some embodiments, the plasma generation power and the bias voltage have synchronous pulses such that the plasma generation power and the bias voltage are simultaneously in their respective low states or high states. The plasma etching process can be performed using a plasma generation power having a high power in the range of about 100 W to about 5000 W. The plasma etching process can be performed using a bias voltage having a high voltage in the range of about 100 volts to about 5000 volts. In some embodiments, the plasma generation power or the bias voltage can be pulsated with a duty cycle in the range of about 10% to about 90%, and the plasma generation power or the bias voltage can have a pulse frequency in the range of about 5 Hz to about 5000 Hz. The process gas used in the plasma etching process includes at least one or more etchant gases. When etching the dielectric materials discussed above (e.g., ELK dielectric), suitable examples of the etchant gas include fluorocarbons (C x F y ), hydrofluorocarbons (C x H y F z ), oxygen (O 2 ), etc. or combinations thereof. A carrier gas such as nitrogen, argon, helium, etc. can be used to carry the process gas into the process chamber. The plasma etching process can be performed in a temperature range of about -20°C to about 50°C. The pressure in the process chamber can be in the range of about 1 mTorr to about 500 mTorr. The plasma etching process can be performed for a duration in the range of about 10 seconds to about 600 seconds.

[0036] In some embodiments, the first trimming process 70 is an ablation process such as laser etching that is performed to have a desired etch selectivity. The laser etching process is performed by performing one or more laser irradiations that are all projected toward the edge region 52E. In some embodiments, the laser irradiation is directed toward the edge region 52E rather than the device region 52D, so the mask 72 can be omitted. In some embodiments, when the mask 72 covers the device region 52D, the laser irradiation is directed toward the entire active surface of the semiconductor substrate 52 such that only the edge region 52E is exposed to the laser irradiation. The lasers that can be used include CO 2 lasers, UV lasers, green lasers, fiber lasers, and yttrium aluminum garnet (YAG) lasers, etc. The wavelength of the laser can be in the range of about 300 nm to about 600 nm. The average output power of the laser can be in the range of about 1 W to about 30 W. The laser etching process can be performed for a duration in the range of about 10 -15 seconds to about 10 -9 seconds.

[0037] The first trimming process 70 can form a groove 74 in the semiconductor substrate 52 by removing some portions of the semiconductor substrate 52 in the edge region 52E. As described above, the first trimming process 70 is performed with a high etch selectivity such that the first trimming process 70 selectively removes the dielectric layer 64, the passivation layer 58, and the dielectric material of the dielectric material 54B at a rate faster than the semiconductor material of the semiconductor substrate 52. Thus, the groove 74 can be formed to a small depth D 3 . The depth D 3 of the groove 74 can be in the range of about 10 μm to about 150 μm.

[0038] In Figure 5 , a second trimming process 80 is performed to remove the edge region of the semiconductor substrate 52. Specifically, some of the portions of the semiconductor substrate 52 in the edge region 52E are removed by performing the second trimming process. The second trimming process 80 does not trim some of the layers trimmed by the first trimming process 70. Specifically, when the dielectric material 54B is an ELK material, the second trimming process 80 is not used to trim fragile components such as the interconnect structure 54. The second trimming process 80 can be a more aggressive trimming process than the first trimming process 70. For example, it can have a faster removal rate than the first trimming process 70. The second trimming process 80 is different from the first trimming process 70 and can be a different type of trimming process. The second trimming process 80 can be a mechanical process or an etching process, and in this embodiment, it is a mechanical process. By trimming the semiconductor substrate 52 with the second trimming process 80 (e.g., a mechanical process), the semiconductor substrate 52 can be trimmed more quickly, so the productivity of wafer processing can be improved.

[0039] A second trimming process 80 is performed on the material selectivity of the semiconductor substrate 52. In other words, the second trimming process 80 selectively removes the semiconductor material of the semiconductor substrate 52 at a rate faster than the dielectric materials of the dielectric layer 64, the passivation layer 58, and the dielectric material 54B. For example, when the second trimming process 80 is an etching process, the etching selectivity between the semiconductor material and the dielectric material with respect to the second trimming process 80 can be in the range of about 5 to about 50. Similarly, when the second trimming process 80 is a mechanical process, the removal rate of the dielectric material can be zero, and the removal rate of the semiconductor material can be non-zero.

[0040] The second trimming process 80 can deepen the groove 74 in the semiconductor substrate 52 by removing some portions of the semiconductor substrate 52 in the edge region 52E. Most of the material in the edge region 52E of the semiconductor substrate 52 is removed, but some portions 52P of the semiconductor substrate 52 remain in the edge region 52E. After the first trimming process 70 and the second trimming process 80, the groove 74 has a depth D 4 . The portions 52P of the semiconductor substrate 52 that remain in the edge region 52E have a depth less than the depth D 4 of the depth D 5 . The depth D 4 can be in the range of about 20 μm to about 300 μm, and the depth D 5 can be in the range of about 475 μm to about 755 μm. The portions 52P of the semiconductor substrate 52 that remain in the edge region 52E are thin enough such that they can subsequently be removed by an etching or grinding process (discussed in more detail below). The groove 74 is deepened along a second direction D 2 perpendicular to the active surface of the semiconductor substrate 52. Thus, the second trimming process 80 can be considered a directional trimming process performed along the second direction D 2 . Note that the first trimming process 70 and the second trimming process 80 are performed along different directions. The first direction D 1 (see Figure 4 ) and the second direction D 2 form a first obtuse angle θ 1 (see Figure 4 ).

[0041] In this embodiment, the second trimming process 80 is a mechanical process such as sawing. The cutting process can be performed by applying a rotating slicing blade 82 (such as, a half-cut slicing blade) to the edge region 52E of the semiconductor substrate 52. Figure 6 is a detailed view of the region 50R after the cutting process. The first trimming process 70 and the second trimming process 80 together remove the cutting region 52C from the semiconductor substrate 52. Specifically, the first trimming process 70 removes the first portion 52C of the cutting region1 And a second trimming process 80 removes a second portion 52C of the dicing region 2 . In the illustrated embodiment, the dicing blade 82 is shaped such that after the dicing process, the semiconductor substrate 52 has a first sidewall 52S in each edge region 52E 1 , a second sidewall 52S 2 and a third sidewall 52S 3 . The third sidewall 52S 3 has several portions. Specifically, the third sidewall 52S 3 has a first portion 52S 3A and a second portion 52S 3B . The first portion 52S 3A connects the second portion 52S 3B to the active surface of the semiconductor substrate 52. The first portion 52S 3A forms a first obtuse angle θ 3B with the second portion 52S 1 (discussed above), and also forms a second obtuse angle θ 2 with the active surface of the semiconductor substrate 52 2 . The second obtuse angle θ 3B can be in the range of about 90 degrees to about 100 degrees. The second portion 52S 1 is perpendicular to a plane parallel to the active surface of the semiconductor substrate 52. The first sidewall 52S 2 and the second sidewall 52S 4 are connected by a straight segment 52S 2 . The second sidewall 52S 3 and the third sidewall 52S 5 are connected by a curved segment 52S 2 . The second sidewall 52S 5 and the curved segment 52S together define a notch 52N at the corner of the dicing region 52C. Depending on the type and parameters of the second trimming process 80, the dicing region 52C can have other shapes (discussed in more detail below).

[0042] In Figure 7 , a second wafer is formed or obtained. The second wafer includes a semiconductor substrate 102, an interconnect structure 104, one or more passivation layers 108, and contact pads 110 that can be similar to the semiconductor substrate 52, the interconnect structure 54, the passivation layer 58, and the contact pads 60, respectively. A dielectric layer 114 is formed on the front side of the wafer, e.g., on the contact pads 110 and the passivation layer 108. Dielectric connectors 116 are formed to extend through the dielectric layer 114 and the passivation layer 108 to physically and electrically couple to the metallization pattern of the interconnect structure 104. The dielectric layer 114 and the dielectric connectors 116 can be similar to the dielectric layer 64 and the dielectric connectors 66, respectively

[0043] Then, the first wafer is bonded to the second wafer. In the illustrated embodiment, the wafers are bonded face-to-face by hybrid bonding such that the front side of the first wafer is bonded to the front side of the second wafer. The dielectric layer 114 is bonded to the dielectric layer 64 by dielectric-dielectric bonding without using any adhesive material (e.g., die attach film), and the die interconnect 116 is bonded to the die interconnect 66 by metal-metal bonding without using any eutectic material (e.g., solder). The bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the wafers against each other. Pre-bonding is performed at a low temperature such as room temperature (e.g., a temperature in the range of about 15 °C to about 30 °C), and after pre-bonding, the dielectric layer 64 and the dielectric layer 114 are bonded to each other. Then, the bonding strength is increased in a subsequent annealing step, in which the dielectric layer 64 and the dielectric layer 114 are annealed at a high temperature such as a temperature in the range of about 100 °C to about 400 °C. After annealing, a bond such as a fusion bond is formed between the dielectric layer 64 and the dielectric layer 114. For example, the bond may be a covalent bond between the material of the dielectric layer 114 and the material of the dielectric layer 64. The die interconnects 66 and the die interconnects 116 are connected to each other in a one-to-one correspondence. The die interconnect 66 and the die interconnect 116 may be in physical contact after pre-bonding, or may expand during annealing to be in physical contact. Additionally, during annealing, the materials (e.g., copper) of the die interconnect 66 and the die interconnect 116 are mixed such that a metal-metal bond is also formed. Thus, the resulting wafer-to-wafer bond is a hybrid bond including both dielectric-dielectric bonding and metal-metal bonding.

[0044] In Figure 8 , the semiconductor substrate 52 is thinned. The thinning may be performed by a CMP process, a grinding process, a back-etching process, etc. or a combination thereof, and is performed on the passive surface of the semiconductor substrate 52. The thinning exposes the conductive vias 56. After thinning, the surface of the conductive vias 56 is coplanar (within process variations) with the passive surface of the semiconductor substrate 52. Thus, the conductive vias 56 are exposed at the back side of the first wafer.

[0045] The thinning process removes the portion 52P of the semiconductor substrate 52 that remains in the edge region 52E. Thus, the first sidewall 52S 1 , the second sidewall 52S 2 , the straight segment 52S 4 , the curved segment 52S 5 and the notch 52N (see Figure 6 ) are removed. After the thinning process, only the third sidewall 52S of the semiconductor substrate 52 3 remains. As described above, the third sidewall 52S 3 all have a first part 52S3A and a second portion 52S 3B (see Figure 6 ). The third sidewall 52S 3 is the outermost sidewall 52S of the thinned semiconductor substrate 52. Since the first wafer is trimmed before bonding, the sidewalls 52S, 102S of the semiconductor substrates 52, 102 are laterally offset from each other. For example, the sidewall 52S of the semiconductor substrate 52 is laterally offset from the sidewall of the semiconductor substrate 102 and the sidewall of the interconnect structure 104. Some offset can occur during bonding such that the centers of the die connectors 66 and 116 are not laterally aligned with each other, but the die connectors 66 and 116 have sufficient surface area contact to form an electrical connection. Additionally, since the first wafer is trimmed, the coverage area of the semiconductor substrate 52 is laterally constrained within the coverage areas of the semiconductor substrate 102 and the interconnect structure 104.

[0046] In Figure 9 , a third wafer is formed or obtained. The third wafer includes a semiconductor substrate 152, an interconnect structure 154, conductive vias 156, one or more passivation layers 158, and contact pads 160 that can be similar to the semiconductor substrate 52, the interconnect structure 54, the conductive vias 56, the passivation layer 58, and the contact pads 60, respectively. A dielectric layer 164 is formed on the front side of the wafer, e.g., on the contact pads 160 and the passivation layer 158. Die connectors 166 are formed to extend through the dielectric layer 164 and the passivation layer 158 to physically and electrically couple to the metallization pattern of the interconnect structure 154. The dielectric layer 164 and the die connectors 166 can be similar to the dielectric layer 64 and the die connectors 66, respectively.

[0047] Then, a third wafer is bonded to the first wafer. In the illustrated embodiment, the wafers are bonded back-to-back by hybrid bonding such that the front side of the third wafer is bonded to the back side of the first wafer. The dielectric layer 164 is bonded to the semiconductor substrate 52 by dielectric-dielectric bonding without using any adhesive material (e.g., die attach film), and the die interconnects 166 are bonded to the conductive vias 56 by metal-metal bonding without using any eutectic material (e.g., solder). The bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the wafers against each other. Pre-bonding is performed at a low temperature such as room temperature (e.g., a temperature in the range of about 15°C to about 30°C), and after pre-bonding, the dielectric layer 164 and the semiconductor substrate 52 are bonded to each other. In some embodiments, an oxide such as an intrinsic oxide is formed at the back side of the semiconductor substrate 52 and is used for bonding. Then, the bonding strength is increased in a subsequent annealing step, in which the dielectric layer 164 and the semiconductor substrate 52 are annealed at a high temperature such as a temperature in the range of about 100°C to about 400°C. After annealing, a bond such as a fusion bond is formed between the dielectric layer 164 and the semiconductor substrate 52. For example, the bond may be a covalent bond between the dielectric layer 164 and the semiconductor substrate 52. The die interconnects 166 and the conductive vias 56 are connected to each other in a one-to-one correspondence. The die interconnects 166 and the conductive vias 56 may be in physical contact after pre-bonding, or may expand during annealing to be in physical contact. Additionally, during annealing, the materials (e.g., copper) of the die interconnects 166 and the conductive vias 56 mix such that a metal-metal bond is also formed. Thus, the resulting wafer-to-wafer bond is a hybrid bond including both dielectric-dielectric bonding and metal-metal bonding.

[0048] The third wafer may be trimmed before bonding and thinned after bonding in a manner similar to that discussed above, such that the sidewalls 152S of the semiconductor substrate 152 also each have two portions in a manner similar to Figure 6 the third sidewalls 52S of the semiconductor substrate 52 described 3 above. Because the third wafer is trimmed before bonding, the sidewalls of the semiconductor substrate 152 and the semiconductor substrate 52 are laterally offset from each other. For example, the sidewalls 152S of the semiconductor substrate 152 are laterally offset from the sidewalls 52S of the semiconductor substrate 52 and the sidewalls of the interconnect structure 54. Some offset may occur during bonding such that the centers of the die interconnects 166 and the conductive vias 56 are not laterally aligned with each other, but the die interconnects 166 and the conductive vias 56 have sufficient surface area contact to form an electrical connection. Additionally, because the third wafer is trimmed, the coverage area of the semiconductor substrate 152 is laterally constrained within the coverage areas of the semiconductor substrate 102 and the interconnect structure 104.

[0049] It should be understood that the steps described relative to Figures 7 to 9 can be repeated any desired number of times to form a stack of wafers. For example, the stack can include four wafers, eight wafers, etc. After wafer bonding is completed, a singulation process is performed by sawing along a scribe region (e.g., around the device region 52D). The singulation process separates the device regions 52D from each other to form a die stack.

[0050] Figure 10A and Figure 10B shows a die stack according to some embodiments. Figure 10A Shows a first die stack 202A that is singulated from a device region 52D disposed near the edge region 52E. Figure 10B Shows a second die stack 202B that is singulated from a device region 52D disposed away from the edge region 52E (e.g., at the center region of the wafer). For the first die stack 202A, the first sidewalls 52S A 、102S A 、152S A are laterally co-terminal within process variations, whereas the second sidewalls 52S of the semiconductor substrates 52, 102, 152 B 、102S B 、152S B are laterally offset from each other. The first sidewalls 52SA, 102SA, 152SA face in a direction opposite to that faced by the second sidewalls 52S B 、102S B 、152SB. For the second die stack 202B, the first sidewalls 52S of the semiconductor substrates 52, 102, 152 A 、102S A 、152S A are laterally co-terminal, and the second sidewalls 52S of the semiconductor substrates 52, 102, 152 B 、102S B 、152S B are also laterally co-terminal. The co-terminal sidewalls are those that are sawed during singulation. The laterally offset sidewalls are those that are trimmed prior to bonding.

[0051] Figures 11 to 15 is a cross-sectional view of an intermediate step during a wafer bonding process according to some other embodiments. In this embodiment, the second trimming process 80 is a non-mechanical process such as an etching process. Thus, the sidewalls of the semiconductor substrate 52 can have a profile shape different from that discussed above relative to Figure 6 discussed.

[0052] In Figure 11 , a first wafer similar to the first wafer described with respect to Figure 3 is formed or obtained. Then, a first trimming process 70 and a second trimming process 80 are performed to remove the edge regions of the semiconductor substrate 52. The second trimming process 80 in this embodiment is an etching process such as a chemical process or an ablation process. The second trimming process 80 can deepen the grooves 74 in the semiconductor substrate 52 by removing some portions of the semiconductor substrate 52 in the edge region 52E. As discussed above, the portions 52P of the semiconductor substrate 52 remaining in the edge region 52E are thin enough such that they can subsequently be removed by an etching or grinding process (discussed in more detail below).

[0053] In some embodiments, the second trimming process 80 is a chemical process such as plasma etching. The plasma etching process can be similar to the plasma etching process discussed above with respect to the first trimming process 70, except that it can be performed with some etching parameters different from those of the first trimming process 70. Specifically, the plasma etching process can be performed with a different etchant gas and a different plasma generation power. For example, when etching the semiconductor material of the semiconductor substrate 52, suitable examples of the etchant gas include sulfur hexafluoride (SF 6 ), hydrofluorocarbons (C x H y F z ), argon (Ar), oxygen (O 2 ), helium (He), etc. or combinations thereof, and the plasma etching process can be performed using a plasma generation power with a high power in the range of about 100 W to about 5000 W.

[0054] In some embodiments, the second trimming process 80 is an ablation process such as laser etching. The laser etching process can be similar to the laser etching process discussed above with respect to the first trimming process 70, except that it can be performed with some etching parameters different from those of the first trimming process 70. Specifically, the laser etching process can be performed with a different laser generation power at a different wavelength. For example, when etching the semiconductor material of the semiconductor substrate 52, the wavelength of the laser can be in the range of about 300 nm to about 600 nm, and the average output power of the laser can be in the range of about 1 W to about 30 W.

[0055] Figure 12 is a detailed view of the region 50R after the second trimming process 80. In the illustrated embodiment, the second trimming process 80 is performed such that after the trimming process, the semiconductor substrate 52 has a first sidewall 52S 1 and a second sidewall 52S 2 in each edge region 52E. The first sidewall 52S1 and the second sidewall 52S 2 are connected through the straight section 52S 3 . The second sidewall 52S 2 forms a first acute angle θ with the active surface of the semiconductor substrate 52 3 , and also forms a second acute angle θ with the straight section 52S 3 . The first acute angle θ 4 can be in the range of about 80 degrees to about 90 degrees, and the second acute angle θ 3 can be in the range of about 80 degrees to about 90 degrees. 4

[0056] In Figure 13 , a second wafer similar to the second wafer described with respect to Figure 7 is formed or obtained. Then, the first wafer is bonded to the second wafer. In the illustrated embodiment, the wafers are bonded face-to-face by hybrid bonding such that the front side of the first wafer is bonded to the front side of the second wafer.

[0057] In Figure 14 , the semiconductor substrate 52 is thinned. The thinning can be performed by a process similar to the process described with respect to Figure 8 . After thinning, the surface of the conductive via 56 is coplanar with the passive surface of the semiconductor substrate 52 (within process variations). Thus, the conductive via 56 is exposed at the back side of the first wafer. Additionally, after thinning, the sidewalls 52S, 102S of the semiconductor substrates 52, 102 are laterally offset from each other.

[0058] In Figure 15 , a third wafer similar to the third wafer described with respect to Figure 9 is formed or obtained. Then, the third wafer is bonded to the first wafer. In the illustrated embodiment, the wafers are bonded back-to-face by hybrid bonding such that the front side of the third wafer is bonded to the back side of the first wafer.

[0059] Figures 16 to 20 is a cross-sectional view of an intermediate step during a wafer bonding process according to some other embodiments. In this embodiment, the second trimming process 80 is a non-mechanical process such as an etching process. Thus, the sidewalls of the semiconductor substrate 52 can have a profile shape different from the profile shape discussed above with respect to Figure 6 . Additionally, in this embodiment, the parameters of the second trimming process 80 are modified such that the sidewalls of the semiconductor substrate 52 can have a profile shape different from the profile shape discussed above with respect to Figure 12 .

[0060] In Figure 16 , a second wafer similar to the second wafer described with respect to Figure 3 ​The described first wafer is similar to the first wafer. Then, a first trimming process 70 and a second trimming process 80 are performed to remove the edge regions of the semiconductor substrate 52. The second trimming process 80 in this embodiment is an etching process such as a chemical process or an ablation process. The second trimming process 80 can deepen the grooves 74 in the semiconductor substrate 52 by removing some portions of the semiconductor substrate 52 in the edge region 52E. As discussed above, the portions 52P of the semiconductor substrate 52 remaining in the edge region 52E are thin enough such that they can subsequently be removed by an etching or grinding process (discussed in more detail below).

[0061] In some embodiments, the second trimming process 80 is a chemical process such as plasma etching. The plasma etching process can be similar to the plasma etching process discussed above with respect to the first trimming process 70, except that it can be performed with some etching parameters different from those of the first trimming process 70. Specifically, the plasma etching process can be performed with a different etchant gas and a different plasma generation power. For example, when etching the semiconductor material of the semiconductor substrate 52, suitable examples of the etchant gas include sulfur hexafluoride (SF 6 ), hydrofluorocarbons (C x H y F z ), argon (Ar), oxygen (O 2 ), helium (He), etc. or combinations thereof, and the plasma etching process can be performed using a plasma generation power with a high power in the range of about 100 W to about 5000 W.

[0062] In some embodiments, the second trimming process 80 is an ablation process such as laser etching. The laser etching process can be similar to the laser etching process discussed above with respect to the first trimming process 70, except that it can be performed with some etching parameters different from those of the first trimming process 70. Specifically, the laser etching process can be performed with a different laser generation power at a different wavelength. For example, when etching the semiconductor material of the semiconductor substrate 52, the wavelength of the laser can be in the range of about 300 nm to about 600 nm, and the average output power of the laser can be in the range of about 1 W to about 30 W.

[0063] Figure 17 is a detailed view of the region 50R after the second trimming process 80. In the illustrated embodiment, the second trimming process 80 is performed such that after the trimming process, the semiconductor substrate 52 has a first sidewall 52S 1 and a second sidewall 52S 2 in each edge region 52E. The first sidewall 52S 1 and the second sidewall 52S 2 are connected by a straight segment 52S3 Connection. The second sidewall 52S 2 forms a first right angle θ with the active surface of the semiconductor substrate 52 3 and also forms a second right angle θ with the straight section 52S 3 6 .

[0064] In Figure 18 , a second wafer similar to the second wafer described with respect to Figure 7 is formed or obtained. Then, the first wafer is bonded to the second wafer. In the illustrated embodiment, the wafers are bonded face-to-face by hybrid bonding such that the front side of the first wafer is bonded to the front side of the second wafer.

[0065] In Figure 19 , the semiconductor substrate 52 is thinned. Thinning can be performed by a process similar to the process described with respect to Figure 8 . After thinning, the surface of the conductive via 56 is coplanar with the passive surface of the semiconductor substrate 52 (within process variations). Thus, the conductive via 56 is exposed at the back side of the first wafer. Additionally, after thinning, the sidewalls 52S, 102S of the semiconductor substrates 52, 102 are laterally offset from each other.

[0066] In Figure 20 , a third wafer similar to the third wafer described with respect to Figure 9 is formed or obtained. Then, the third wafer is bonded to the first wafer. In the illustrated embodiment, the wafers are bonded back-to-face by hybrid bonding such that the front side of the third wafer is bonded to the back side of the first wafer. Then, the semiconductor substrate 152 is thinned. After thinning, the sidewalls of the semiconductor substrate 152 and the semiconductor substrate 52 are laterally offset from each other.

[0067] Figures 21 to 25 is a cross-sectional view of an intermediate step during a wafer bonding process according to some other embodiments. In this embodiment, the first trimming process 70 and the second trimming process 80 are performed at an earlier stage of wafer processing. An embodiment of Figures 16 to 20 is shown using a trimming process similar to the trimming process described with respect to Figures 21 to 25 . It should be understood that the first trimming process 70 and the second trimming process 80 can also be performed at an earlier stage in the process described with respect to Figures 1 to 9 and in the process described with respect to Figures 11 to 15 .

[0068] In Figure 21 , a wafer similar to the wafer described with respect to Figure 1 ​The described first wafer is similar to the first wafer. Then, a first trimming process 70 and a second trimming process 80 are performed to remove the edge regions of the semiconductor substrate 52. Note that the first trimming process 70 and the second trimming process 80 are performed before forming the dielectric layer 64 (see Figure 22 ). After trimming is completed, circuit probe (CP) testing can be performed with the probe 62 in a manner similar to that described with respect to Figure 2 . Performing the test after trimming can help avoid further processing of wafers that may be damaged by trimming.

[0069] In Figure 22 , the dielectric layer 64 is formed on the front side of the wafer, e.g., on the contact pads 60 and the passivation layer 58. The die connectors 66 are formed to extend through the dielectric layer 64 and the passivation layer 58 to physically and electrically couple to the contact pads 60. The dielectric layer 64 and the die connectors 66 can be formed in a manner similar to that described with respect to Figure 3 . In this embodiment, the die connectors 66 connect to the contact pads 60 instead of the metallization pattern 54A of the interconnect structure 54. In another embodiment, the die connectors 66 connect to the metallization pattern of the interconnect structure 54.

[0070] In Figure 23 , a second wafer is formed or obtained that is similar to the second wafer described with respect to Figure 7 . In this embodiment, the die connectors 116 connect to the contact pads 110 instead of the metallization pattern of the interconnect structure 104. In another embodiment, the die connectors 116 connect to the metallization pattern of the interconnect structure 104. Then, the first wafer is bonded to the second wafer. In the illustrated embodiment, the wafers are bonded face-to-face by hybrid bonding such that the front side of the first wafer is bonded to the front side of the second wafer.

[0071] In Figure 24 , the semiconductor substrate 52 is thinned. The thinning can be performed by a process similar to that described with respect to Figure 8 . After thinning, the surface of the conductive vias 56 is coplanar (within process variations) with the passive surface of the semiconductor substrate 52. Thus, the conductive vias 56 are exposed at the back side of the first wafer. Since the dielectric layer 64 is formed and thinned before the first wafer is trimmed, the dielectric layer 64 extends along the sidewalls 52S of the semiconductor substrate 52 and contacts it. After thinning, the sidewalls 52S, 102S of the semiconductor substrates 52, 102 are laterally offset from each other.

[0072] In Figure 25 , a third wafer is formed or obtained that is similar to the third wafer described with respect to Figure 9A third wafer similar to the described third wafer. Then, the third wafer is bonded to the first wafer. In the illustrated embodiment, the wafers are bonded back-to-back by hybrid bonding such that the front side of the third wafer is bonded to the back side of the first wafer. Then, the semiconductor substrate 152 is thinned. After thinning, the sidewalls of the semiconductor substrate 152 and the semiconductor substrate 52 are laterally offset from each other.

[0073] The embodiments can achieve several advantages. A non-mechanical process, such as an etching process, is used to trim a dielectric component (such as the interconnect structure 54) at the wafer edge, enabling trimming of a fragile component such as an ultra-low-k (ELK) dielectric layer with a reduced risk of damage compared to a mechanical process. A mechanical process, such as sawing, is used to trim a semiconductor component (such as the semiconductor substrate 52) at the wafer edge, enabling faster trimming of a rigid component, which can increase wafer processing productivity. Optionally, a non-mechanical process, such as an etching process, is used to trim a semiconductor component (such as the semiconductor substrate 52) at the wafer edge, enabling simplification of wafer processing by avoiding performing a sawing step.

[0074] In an embodiment, a method includes: obtaining a first processed wafer including a first substrate and a first interconnect structure, the first substrate comprising a semiconductor material and the first interconnect structure including metal interconnects between dielectric materials; removing an edge region of the first interconnect structure with a first trimming process that removes the dielectric material of the first interconnect structure at a rate faster than the semiconductor material of the first substrate; after removing the edge region of the first interconnect structure, removing an edge region of the first substrate with a second trimming process that removes the semiconductor material of the first substrate at a rate faster than the dielectric material of the first interconnect structure; and bonding a second processed wafer to the front side of the first processed wafer.

[0075] In some embodiments of the method, a first trimming process removes an edge region of a first interconnect structure along a first direction, and a second trimming process removes an edge region of a first substrate along a second direction, the first direction and the second direction forming an obtuse angle, the second direction being perpendicular to an active surface of the first substrate. In some embodiments of the method, the first trimming process is a first etching process. In some embodiments of the method, the first etching process is a plasma etching performed with a fluorocarbon, a hydrofluorocarbon, or oxygen, the plasma etching being performed using a plasma generation power in the range of 100 W to 5000 W, the plasma etching being performed at a pressure in the range of 1 mTorr to 500 mTorr, the plasma etching being performed for a duration in the range of 10 seconds to 600 seconds. In some embodiments of the method, the first etching process is a laser etching performed with a wavelength in the range of 300 nm to 600 nm, the laser etching being performed using a laser generation power in the range of 1 W to 30 W, the laser etching being performed for a duration in the range of 10-15 seconds to 10-9 seconds. In some embodiments of the method, the second trimming process is a mechanical process. In some embodiments of the method, the second trimming process is a second etching process, the second etching process being performed with etching parameters different from those of the first etching process. In some embodiments of the method, bonding the second processed wafer to the first processed wafer includes: depositing a first dielectric layer on the first processed wafer; forming a first metal component in the first dielectric layer; depositing a second dielectric layer on the second processed wafer; forming a second metal component in the second dielectric layer; forming a dielectric-dielectric bond between the first dielectric layer and the second dielectric layer; and forming a metal-metal bond between the first metal component and the second metal component. In some embodiments of the method, after depositing the first dielectric layer on the first processed wafer, the edge region of the first substrate is removed. In some embodiments of the method, before depositing the first dielectric layer on the first processed wafer, the edge region of the first substrate is removed. In some embodiments, the method further includes: obtaining a third processed wafer including a third substrate and a third interconnect structure; removing an edge region of the third interconnect structure with a first trimming process; after removing the edge region of the third interconnect structure, removing an edge region of the third substrate with a second trimming process; and bonding the third processed wafer to a back surface of the first processed wafer, a sidewall of the third substrate being laterally offset from a sidewall of the first substrate.

[0076] In some embodiments, the method includes: obtaining a first processed wafer including a substrate and an interconnect structure; etching the interconnect structure to remove the interconnect structure from an edge region of the first processed wafer; after etching the interconnect structure, sawing the substrate to remove a first portion of the substrate in the edge region of the first processed wafer; bonding the first processed wafer to a second processed wafer; and thinning the substrate to remove a second portion of the substrate in the edge region of the first processed wafer.

[0077] In some embodiments of the method, etching the interconnect structure includes etching the interconnect structure using a plasma etching process that removes the dielectric material of the interconnect structure at a rate faster than the semiconductor material of the substrate, wherein the dielectric material of the interconnect structure is not removed during sawing the substrate. In some embodiments of the method, etching the interconnect structure includes etching the interconnect structure using a laser etching process that removes the dielectric material of the interconnect structure at a rate faster than the semiconductor material of the substrate, wherein the dielectric material of the interconnect structure is not removed during sawing the substrate.

[0078] In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, wherein a sidewall of the first interconnect structure forms an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, wherein a sidewall of the first substrate is laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

[0079] In some embodiments, the device further includes: a dielectric layer bonding the second wafer to the first wafer, wherein a sidewall of the dielectric layer forms an obtuse angle with a sidewall of the first substrate. In some embodiments, the device further includes: a dielectric layer bonding the second wafer to the first wafer, the dielectric layer extending along a sidewall of the first interconnect structure and a sidewall of the first substrate. In some embodiments of the device, a sidewall of the first substrate has a first portion and a second portion, the first portion connecting the second portion to an active surface of the first substrate, and the first portion forms an obtuse angle with the second portion. In some embodiments of the device, a sidewall of the first substrate forms a right angle with an active surface of the first substrate. In some embodiments of the device, a sidewall of the first substrate forms an acute angle with an active surface of the first substrate.

[0080] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor device, comprising: obtaining a first processed wafer including a first substrate and a first interconnect structure, the first substrate comprising a semiconductor material, and the first interconnect structure comprising metal interconnects between dielectric materials; removing an edge region of the first interconnect structure using a first trimming process, the first trimming process being a non-mechanical process that removes the dielectric material of the first interconnect structure at a rate faster than the semiconductor material of the first substrate; after removing the edge region of the first interconnect structure, removing an edge region of the first substrate using a second trimming process, the second trimming process removing the semiconductor material of the first substrate at a rate faster than the dielectric material of the first interconnect structure; and bonding a second processed wafer to a front side of the first processed wafer.

2. The method according to claim 1, wherein the first trimming process removes the edge region of the first interconnect structure along a first direction, and the second trimming process removes the edge region of the first substrate along a second direction, the first direction forming an obtuse angle with the second direction, and the second direction being perpendicular to an active surface of the first substrate.

3. The method according to claim 1, wherein the first trimming process is a first etching process.

4. The method according to claim 3, wherein the first etching process is a plasma etching performed using a fluorocarbon, a hydrofluorocarbon, or oxygen, the plasma etching being performed using a plasma generation power in the range of 100 W to 5000 W, the plasma etching being performed at a pressure in the range of 1 mTorr to 500 mTorr, and the plasma etching being performed for a duration in the range of 10 seconds to 600 seconds.

5. The method according to claim 3, wherein the first etching process is a laser etching performed with a wavelength in the range of 300 nm to 600 nm, the laser etching is performed with a laser output power in the range of 1 W to 30 W, and the laser etching is performed for a duration in the range of 10 -15 seconds to 10 -9 seconds.

6. The method according to claim 3, wherein the second trimming process is a mechanical process.

7. The method according to claim 3, wherein the second trimming process is a second etching process performed with etching parameters different from those of the first etching process.

8. The method according to claim 1, wherein bonding the second processed wafer to the first processed wafer comprises: depositing a first dielectric layer on the first processed wafer; forming a first metal component in the first dielectric layer; depositing a second dielectric layer on the second processed wafer; forming a second metal component in the second dielectric layer; forming a dielectric-dielectric bond between the first dielectric layer and the second dielectric layer; and forming a metal-metal bond between the first metal component and the second metal component.

9. The method according to claim 8, wherein after depositing the first dielectric layer on the first processed wafer, the edge region of the first substrate is removed.

10. The method according to claim 8, wherein before depositing the first dielectric layer on the first processed wafer, the edge region of the first substrate is removed.

11. The method according to claim 1, further comprising: Obtain a third processed wafer including a third substrate and a third interconnect structure; Use the first trimming process to remove the edge region of the third interconnect structure; After removing the edge region of the third interconnect structure, use a second trimming process to remove the edge region of the third substrate; And Bond the third processed wafer to the back side of the first processed wafer, with the sidewall of the third substrate laterally offset from the sidewall of the first substrate.

12. A method of forming a semiconductor device, comprising: Obtain a first processed wafer including a substrate and an interconnect structure; Etch the interconnect structure to remove the interconnect structure from the edge region of the first processed wafer; After etching the interconnect structure, saw the substrate to remove a first portion of the substrate in the edge region of the first processed wafer; Bond the first processed wafer to a second processed wafer; And Thin the substrate to remove a second portion of the substrate in the edge region of the first processed wafer.

13. The method according to claim 12, wherein etching the interconnect structure includes etching the interconnect structure using a plasma etching process that removes the dielectric material of the interconnect structure at a rate faster than the semiconductor material of the substrate, and wherein the dielectric material of the interconnect structure is not removed during sawing the substrate.

14. The method according to claim 12, wherein etching the interconnect structure includes etching the interconnect structure using a laser etching process that removes the dielectric material of the interconnect structure at a rate faster than the semiconductor material of the substrate, and wherein the dielectric material of the interconnect structure is not removed during sawing the substrate.

15. A semiconductor device, comprising: A first wafer including a first substrate and a first interconnect structure, the sidewall of the first interconnect structure forming an obtuse angle with the sidewall of the first substrate, and the sidewall of the first interconnect structure being a sidewall obtained after trimming the edge region using a non-mechanical process; And A second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, and the sidewall of the first substrate being laterally offset from the sidewalls of the second substrate and the second interconnect structure; wherein the width of the first interconnect structure on the side closer to the second substrate is smaller than the width of the first interconnect structure on the other side closer to the first substrate.

16. The semiconductor device according to claim 15, further comprising: A dielectric layer bonding the second wafer to the first wafer, and the sidewall of the dielectric layer forming an obtuse angle with the sidewall of the first substrate.

17. The semiconductor device according to claim 15, further comprising: A dielectric layer bonding the second wafer to the first wafer, and the dielectric layer extending along the sidewall of the first interconnect structure and the sidewall of the first substrate.

18. The semiconductor device according to claim 15, wherein the sidewall of the first substrate has a first portion and a second portion, the first portion connecting the second portion to the active surface of the first substrate, and the first portion and the second portion form an obtuse angle.

19. The semiconductor device according to claim 15, wherein the sidewall of the first substrate forms a right angle with the active surface of the first substrate.

20. The semiconductor device according to claim 15, wherein the sidewall of the first substrate forms an acute angle with the active surface of the first substrate.

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