Semiconductor package and method of manufacturing the same

Abstract

The present invention comprises: one or more first substrates (110) extending to form one or more first substrate terminals (111); one or more second substrates (120) bonded to the first substrates (110) by ultrasonic welding; one or more semiconductor chips (130) bonded to the second substrates (120); a package shell (140) covering the ultrasonically welded region of the one or more semiconductor chips (130) and the second substrate (120); and one or more terminals (150) formed separately from the first substrate (110), electrically connected to the one or more semiconductor chips (130) by an electrical signal line (151) and exposed to the outside of the package shell (140), wherein the thickness of the terminal (150) formed inside the package shell (140) is the same as or smaller than the thickness of the first substrate (110), and one or more embossed grooves (122) are formed on the upper surface of the second substrate (120).

Description

Technical Field

[0001] The present invention relates to a semiconductor package and a manufacturing method thereof, wherein a first substrate and a second substrate are formed of a material capable of ultrasonic welding and bonded to each other to reduce weight, thereby reducing battery consumption and saving material costs when applied to electric vehicles. Background Art

[0002] Generally speaking, a packaged power semiconductor device creates a higher-temperature environment than necessary due to the power dissipated during driving, and therefore it is important to dissipate the heat and cool it to a predetermined level to minimize thermal resistance.

[0003] In addition, as a related prior art, Korean registered patent gazette No. 0685253 is disclosed. Figure 1 As shown, the power semiconductor die 26 is directly soldered on a copper bonding (DBC) substrate 28, and the DBC substrate 28 includes a first copper layer 30 on the die side, a ceramic layer 32 and a second copper layer 34 on the rear side, and a sealing layer 36 is formed on the upper portion of a device wire 38 40 soldered on the power semiconductor die 26, the DBC substrate 28 and the first copper layer 30.

[0004] However, the wire 38 and the bare crystal side copper layer 30, which are the leads of the lead frame, are welded together. When they are deformed due to the high temperature environment, the structural bonding strength may be reduced. In addition, the bare crystal side copper layer 30, the ceramic layer 32, and the rear side copper layer 34, which are the heat diffusion layer, are introduced into the inner side molding of the sealing layer 36. Therefore, the heat release effect is limited. In addition, when the temperature characteristics of the heat diffusion layer change, pressure is applied to the power semiconductor bare crystal 26, and there is a possibility that the reliability of the semiconductor chip will be reduced.

[0005] Furthermore, in order to improve the thermal efficiency of semiconductors, thicker copper materials have been used to bond semiconductor chips and dissipate heat. However, due to the price of copper materials and the weight depending on the thickness, the weight of the semiconductor package itself increases. As a result, when it is applied to electric vehicles, there is a problem of increased battery consumption.

[0006] Therefore, there is a need for a technology that can effectively release heat generated by a semiconductor chip to the outside of a package housing for cooling, minimize deformation of the semiconductor package, and reduce the weight of the semiconductor package and manufacturing cost.

[0007]

Prior technical literature

[0008] [Patent Literature]

[0009] (Patent Document 0001) Korean Registered Patent Gazette No. 0685253 (Packaged Power Semiconductor Device, 2007.02.22)

[0010] (Patent Document 0002) Korean Patent Publication No. 2001-0111736 (Power module package having an insulating heat sink directly attached to the back of a lead frame, 2011.02.20)

[0011] (Patent Document 0003) Korean Registered Patent Publication No. 10-1682067 (Heat sink and lead frame bonding type semiconductor package using ultrasonic welding, 2016.12.02) Summary of the invention

[0012] Technical problem to be solved by the invention

[0013] The technical problem to be solved by the concept of the present invention is to provide a semiconductor package and a manufacturing method thereof in which the first substrate and the second substrate are formed of a material that can be ultrasonically welded, and are bonded to each other to form a lightweight semiconductor package that can reduce battery consumption and save material costs when suitable for electric vehicles.

[0014] Technical solutions to the problem

[0015] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a semiconductor package, comprising: one or more first substrates, which extend to form one or more first substrate terminals; one or more second substrates, which are bonded to the first substrate by ultrasonic welding; one or more semiconductor chips, which are bonded to the second substrate; a packaging shell, which covers the ultrasonic welding area of ​​the one or more semiconductor chips and the second substrate; and terminals, which are separated from the first substrate and electrically connected to the one or more semiconductor chips through electrical signal lines, and at least one is exposed to the outside of the packaging shell, and the thickness of the terminals formed inside the packaging shell is the same as or smaller than the thickness of the first substrate, and one or more embossing grooves are formed on the upper surface of the second substrate.

[0016] Furthermore, another embodiment of the present invention provides a semiconductor package, comprising: one or more first substrates; one or more second substrates, which are bonded on the first substrates by ultrasonic welding and have second substrate terminals extending therefrom; one or more semiconductor chips, which are bonded on the first substrates or the second substrates; a package shell, which covers the ultrasonically welded areas of the one or more semiconductor chips and the second substrates; and terminals, which are formed separately from the first substrates, are electrically connected to the one or more semiconductor chips through electrical signal lines, and are at least one exposed to the outside of the package shell, and the thickness of the terminals formed inside the package shell is the same as or smaller than the thickness of the first substrate, and at least one embossing groove is formed on the upper surface of the second substrate.

[0017] Here, the first substrate or the second substrate includes a conductive metal.

[0018] Furthermore, the conductive metal is formed by laminating two or more layers of different metals or alloy metals.

[0019] Furthermore, the first substrate or the second substrate includes one or more insulating layers formed by stacking.

[0020] Furthermore, the first substrate, the first substrate terminal, or the first substrate and the first substrate terminal are formed of a single material of Al, or are formed of an alloy material containing 50% or more of Al.

[0021] Furthermore, the second substrate, the second substrate terminal, or the second substrate and the second substrate terminal are formed of a single material of Cu, or are formed of an alloy material containing 50% or more of Cu.

[0022] Furthermore, at least one of the terminals is formed of a single material of Al or Cu, or is formed of an alloy material containing more than 50% of Al or Cu.

[0023] Furthermore, the first substrate, the second substrate, the first substrate and the second substrate, the first substrate terminal, the second substrate terminal, or more than one of the terminals have a coating layer formed on more than one side, and the coating layer is formed by a single layer or by stacking two or more layers of the same metal or different metals.

[0024] Furthermore, the coating layer is formed of a single layer of a single Ni material, or a Ni coating layer formed by stacking one or more layers of an alloy material containing more than 70% Ni, and the thickness of the Ni coating layer is 0.1 μm to 10 μm.

[0025] Furthermore, the outermost coating layer of one or more of the terminals may include Sn.

[0026] Furthermore, the semiconductor chip is bonded to the upper surface of the second substrate via a conductive adhesive.

[0027] Furthermore, the conductive adhesive is applied to at least a portion of the stamped groove on the surface of the second substrate.

[0028] Furthermore, the conductive adhesive is a solder series containing one or more of Sn, Pb and Bi components, or a sintered material containing one or more of Ag and Cu components.

[0029] Furthermore, the electrical signal line is in the form of a metal line or a metal clip of a metal component.

[0030] Furthermore, one or more of the terminals are arranged on the first substrate at a predetermined distance from each other.

[0031] Furthermore, one or more of the terminals are formed so as to overlap with the upper surface of the first substrate and be physically separated therefrom.

[0032] Furthermore, the first substrate and the second substrate are formed of conductive metals having different components from each other.

[0033] Furthermore, the first substrate, the first substrate terminals and the terminals are formed of a single Al material, or an alloy material containing 50% or more of Al.

[0034] Furthermore, the second substrate is formed of a single material of Al, or an alloy material containing 50% or more of Al.

[0035] Furthermore, the area of ​​the first substrate is larger than the area of ​​the second substrate.

[0036] Furthermore, the thickness of the first substrate is greater than the thickness of the second substrate.

[0037] Furthermore, a part or the entirety of the lower surface of the first substrate is exposed to the bottom surface of the package case.

[0038] Furthermore, a through hole for coupling with a heat sink is formed in a region of the first substrate to which the second substrate or the semiconductor chip is not bonded.

[0039] Furthermore, the thickness of the first substrate or the second substrate is the same as the thickness of the terminal excluding the coating layer.

[0040] Furthermore, the depth of the embossed groove is less than 100 μm.

[0041] Furthermore, the embossed groove forms a V-shaped, U-shaped or polygonal cross-sectional structure.

[0042] Furthermore, the embossed grooves are formed in the form of grids, dots or lines.

[0043] Furthermore, at least one burr is formed around at least one of the embossed grooves, and the burr does not exceed 100 μm.

[0044] Furthermore, the present invention provides a semiconductor package manufacturing method for manufacturing the semiconductor package.

[0045] Effects of the Invention

[0046] According to the present invention, the separated first substrate and second substrate are formed of a material that can be ultrasonically welded, and when they are bonded together to form a lightweight structure suitable for electric vehicles, battery consumption can be reduced and material costs can be saved. In addition, the semiconductor chip can be selectively mounted on the first substrate or the second substrate, so that the size and thickness of the substrate exposed to the outside of the package shell are relatively large and thick, thereby improving the heat dissipation effect, and the bonding strength with the semiconductor chip is improved by means of the stamped groove and burrs. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 Examples of conventional heat sink and lead frame bonding semiconductor packages using ultrasonic welding;

[0048] Figure 2 3D diagrams of a semiconductor package according to an embodiment of the present invention are respectively shown;

[0049] Figure 3 Respectively illustrated Figure 2 An exploded perspective view of a semiconductor package;

[0050] Figure 4 Graphics Figure 2 A side view of a semiconductor package;

[0051] Figure 5 A perspective view of a first example of a semiconductor package according to another embodiment of the present invention is shown respectively;

[0052] Figure 6 Respectively illustrated Figure 5 An exploded perspective view of a semiconductor package;

[0053] Figure 7 Graphics Figure 5 A side view of a semiconductor package;

[0054] Figure 8 A perspective view of a second example of a semiconductor package according to another embodiment of the present invention is shown respectively;

[0055] Fig. 9 Respectively illustrated Figure 8 An exploded perspective view of a semiconductor package;

[0056] Fig.10 Graphics Figure 8 A side view of a semiconductor package;

[0057] Fig.11 A perspective view of a third example of a semiconductor package according to another embodiment of the present invention is shown respectively;

[0058] Fig.12 Respectively illustrated Fig.11 An exploded perspective view of a semiconductor package;

[0059] Fig.13 Graphics Fig.11 A side view of a semiconductor package;

[0060] Fig.14 A perspective view of a fourth example of a semiconductor package according to another embodiment of the present invention is shown respectively;

[0061] Fig.15 Respectively illustrated Fig.14 An exploded perspective view of a semiconductor package;

[0062] Fig.16 Graphics Fig.15 A side view of a semiconductor package;

[0063] Fig.17 Schematic diagrams of stamping grooves of a semiconductor package according to an embodiment of the present invention are respectively shown;

[0064] Fig.18 Examples are Fig.17 The burrs formed by the embossing grooves.

[0065] Description of Reference Numerals

[0066] 110: 1st substrate 111: 1st substrate terminal

[0067] 120: second substrate 121: conductive adhesive

[0068] 122: embossing groove 123: burr

[0069] 124: Second substrate terminal 130: Semiconductor chip

[0070] 140: Encapsulation shell 150: Terminal

[0071] 151: electrical signal line 160: through hole DETAILED DESCRIPTION

[0072] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in various forms and is not limited to the embodiments described below.

[0073] Reference Figures 2 to 4According to an embodiment of the present invention, a semiconductor package comprises: one or more first substrates 110 extending and forming one or more first substrate terminals 111; one or more second substrates 120 bonded on the first substrates 110 by ultrasonic welding; one or more semiconductor chips 130 bonded on the second substrates 120; a package shell 140 covering the area where the one or more semiconductor chips 130 and the second substrates 120 are ultrasonically welded; and a package shell 140 formed separately from the first substrate 110 and electrically connected to the one or more semiconductor chips 130 by an electrical signal line 151. The present invention further comprises: a terminal 150 formed inside the package shell 140 has a thickness that is the same as or smaller than that of the first substrate 110; and one or more embossing grooves 122 are formed on the upper surface of the second substrate 120; the separated first substrate 110 and second substrate 120 are formed of a material that can be ultrasonically welded and bonded to reduce their weight; and the first substrate 110 is formed larger to improve the heat dissipation effect, and the bonding strength with the semiconductor chip 130 is improved by means of the embossing grooves 122.

[0074] First, the first substrate 110 is formed with one or more first substrate terminals 111 extending from one end of the first substrate 110, and the terminals 111 may extend to the same height as the top of the first substrate 110, or may extend to the same height as the top of the first substrate 110. Figure 4 As shown in (b), it extends from the upper surface of the first substrate 110 and is bent obliquely upward.

[0075] like Figure 2 As shown, one end of the first substrate terminal 111 is exposed to the outside of the package case 140 and is electrically connected to the external terminal.

[0076] Here, the first substrate 110, the first substrate terminal 111, or the first substrate 110 and the first substrate terminal 111 are all formed of a single Al material, or are formed of an alloy material containing more than 50% Al, and the second substrate 120 containing Cu material is bonded to the first substrate 110 by ultrasonic welding, thereby replacing the first substrate 110 or the first substrate terminal 111 formed of copper material in the past, making them lighter and saving material costs.

[0077] Then, at least one second substrate 120 is formed and bonded to the first substrate 110 by ultrasonic welding.

[0078] For reference, ultrasonic welding is a suitable method for welding Al or copper foil. It uses the friction heat generated by the high-frequency vibration energy of the ultrasonic welding machine to pressurize and bond them together, thereby minimizing the deformation of the bonded part, omitting the post-processing process of surface treatment, and improving productivity.

[0079] Furthermore, the first substrate 110 or the second substrate 120 may include a conductive metal, and the conductive metal may be a structure in which two or more layers are stacked together by different metals or different composite metals.

[0080] Furthermore, the first substrate 110 or the second substrate 120 may include more than one insulating layer formed by stacking.

[0081] For example, the second substrate 120 may be formed of a single material of Cu, or an alloy material containing 50% or more of Cu.

[0082] Furthermore, the first substrate 110 and the second substrate 120 may be formed of conductive metals having different components.

[0083] Furthermore, the area of ​​the first substrate 110 may be greater than the area of ​​the second substrate 120, or the thickness of the first substrate 110 may be greater than the thickness of the second substrate 120, and, as Figure 2 As shown in (c), part or all of the lower surface of the first substrate 110 is exposed to the bottom surface of the package case 140, so that the heat generated by the semiconductor chip 130 can be effectively dissipated to the outside of the package case 140.

[0084] And, if Figure 3 As shown in (a), a through hole 160 for combining with a heat dissipation device (not shown) may be formed in an area of ​​the first substrate 110 to which the second substrate 120 or the semiconductor chip 130 is not bonded, and the through hole 160 is connected to the package housing 140.

[0085] Then, one or more semiconductor chips 130 are formed and bonded onto the second substrate 120. Fig.17 (c), the semiconductor chip 130 can be bonded to the second substrate 120 by interposing a conductive adhesive 121 thereon.

[0086] Furthermore, one or more embossing grooves 122 are formed on the upper surface of the second substrate 120 , and a conductive adhesive 121 is applied to at least a portion of the embossing grooves 122 on the surface of the second substrate 120 , thereby improving the bonding strength between the second substrate 120 and the semiconductor chip 130 .

[0087] Here, the conductive adhesive 121 is a solder material suitable for soldering containing at least one of Sn, Pb and Bi, or a sintering material suitable for sintering containing at least one of Ag and Cu.

[0088] Furthermore, the second substrate 120 can be formed with an embossed groove 122 having a depth less than 100 μm by ultrasonic welding, and Fig.17 and Fig.18As shown, the embossed groove 122 can be formed in various shapes, for example, a V-shaped ( Fig.18 (a)), U-shaped ( Fig.17 (c)) or a polygonal cross-sectional structure, thereby maximizing the surface area of ​​the embossed groove 122 and improving the bonding strength with the conductive adhesive 121.

[0089] Or, if Fig.17 As shown in (a), the embossed groove 122 is formed by a lattice pattern, or as Fig.17 As shown in (b), the embossed grooves 122 are arranged in a dotted pattern or in various line patterns, thereby maximizing the surface area of ​​the embossed grooves 122 and improving the bonding strength with the conductive adhesive 121.

[0090] Furthermore, when the second substrate 120 is formed into the embossed groove 122 by ultrasonic welding, burrs 123 are inevitably generated. Fig.18 As shown in (b), one or more burrs 123 may be formed around one or more embossing grooves 122, and the height of the burrs 123 may be formed to be no more than 100 μm.

[0091] For reference, the semiconductor chip 130 may be a power semiconductor such as a silicon controlled rectifier (SCR), a power transistor, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a power rectifier, a power regulator, or a combination thereof.

[0092] Then, the package shell 140 covers one or more semiconductor chips 130 and the ultrasonically welded area of ​​the first substrate 110 and the second substrate 120, and as an insulator for protecting the semiconductor circuit, the package shell 140 can be formed of EMC (Epoxy Molding Compound), PPS (Poly Phenylene Sulfide) or PBT (Poly Butylene Terephtalate) material.

[0093] Then, the terminal 150 is physically separated from the first substrate 110 and electrically connected to one or more semiconductor chips 130 via an electric signal line 151 , and one or more of the terminals 150 are exposed to the outside of the package case 140 and electrically connected to an external terminal.

[0094] And, if Figure 3 (c) and Figure 4 As shown in (c), one or more terminals 150 are arranged on the first substrate 110 at a predetermined distance and are physically separated.

[0095] And, if Figure 3 As shown, the electrical signal line 151 is in the form of a metal wire, or a metal clip of a metal component.

[0096] Furthermore, the first substrate 110 , the first substrate terminals 111 , and the terminals 150 may be formed of a single material A, or may be formed of an alloy material containing more than 50% Al.

[0097] And, if Figure 4 As shown in (c) and (e), the thickness d1 of the terminal 150 formed inside the package case 140 is smaller than the thickness d2 of the first substrate 110 (c), or is formed to be the same as the thickness d2 of the first substrate 110 (e).

[0098] And, if Figure 4 As shown in (c), the thickness d3 of the second substrate 120 may be the same as the thickness d1 of the terminal 150 excluding the coating layer, or as Figure 4 As shown in (e), the thickness d2 of the first substrate 110 is the same as the thickness d1 of the terminal 150 excluding the coating layer.

[0099] Alternatively, one or more terminals 150 are formed of a single material of Al or Cu, or are formed of an alloy material containing more than 50% of Al or Cu.

[0100] Furthermore, the first substrate 110, the second substrate 120, the first substrate 110 and the second substrate 120, the first substrate terminal 111, the second substrate terminal 124, or one or more terminals 150 respectively form a coating layer on more than one side, wherein the coating layer forms a single layer, or is formed by stacking two or more layers of the same metal or different metals.

[0101] Furthermore, the coating layer may be formed as a single layer of a single Ni material, or may be formed as a Ni coating layer formed by stacking one or more layers of an alloy material containing more than 70% Ni. Here, the thickness of the Ni coating layer may be 0.1 μm to 10 μm.

[0102] Also, the outermost coating layer of one or more terminals 150 may contain Sn.

[0103] Therefore, according to a semiconductor package of one embodiment of the present invention, instead of an expensive copper substrate, the separated first substrate and second substrate are made of a material that can be ultrasonically welded, and are bonded to each other to make them lightweight. As a result, when used in electric vehicles, battery consumption can be reduced and material costs can be saved. In addition, the semiconductor chip is mounted on the second substrate so that the size and thickness of the substrate exposed to the outside of the package shell are relatively larger and thicker to improve the heat dissipation effect, and the bonding strength with the semiconductor chip is improved by means of the stamped grooves and burrs.

[0104] Reference Figures 5 to 16The gist of the semiconductor package of another embodiment of the present invention is that it comprises as a whole: one or more first substrates 110; one or more second substrates 120 bonded on the first substrate 110 by ultrasonic welding and extending to form second substrate terminals 124; one or more semiconductor chips 130 bonded on the first substrate 110 or the second substrate 120; a package shell 140 covering the one or more semiconductor chips 130 and the ultrasonically welded area of ​​the second substrate 120; and a package shell 140 formed separately from the first substrate 110 and connected to the one or more semiconductor chips through an electrical signal line 151. The chip 130 is electrically connected, and one or more terminals 150 are exposed to the outside of the packaging shell 140, and the thickness of the terminals 150 formed inside the packaging shell 140 is the same as or smaller than the thickness of the first substrate 110, and one or more embossing grooves 122 are formed on the upper surface of the second substrate 120, and the separated first substrate 110 and second substrate 120 are made of a material that can be ultrasonically welded and bonded to make them lightweight, and the size of the first substrate 110 is formed larger to improve the heat dissipation effect, and the bonding force with the semiconductor chip 130 is improved by means of the embossing grooves 122.

[0105] First, at least one first substrate 110 is formed, and the first substrate 110 is formed of a single material of Al, or an alloy material containing more than 50% of Al. In addition, the second substrate 120 is bonded to the first substrate 110 by ultrasonic welding, thereby replacing the first substrate 110 formed of copper in the past, making it lighter and saving material costs.

[0106] Then, at least one second substrate 120 is formed and bonded to the first substrate 110 by ultrasonic welding.

[0107] Furthermore, the first substrate 110 or the second substrate 120 may include a conductive metal, and the conductive metal may be formed into a structure in which two or more layers of different metals or different alloy metals are stacked.

[0108] Furthermore, the first substrate 110 or the second substrate 120 may include one or more insulating layers formed by stacking.

[0109] For example, the second substrate 120 is formed of a single material of Cu, or an alloy material containing 50% or more of Cu.

[0110] That is, Figure 6 The first case and Fig. 9 As shown in the second example, the second substrate 120 is bonded to the first substrate 110 containing an Al component by ultrasonic welding, and the semiconductor chip 130 is mounted on the first substrate 110 so as not to overlap with the second substrate 120.

[0111] Or, Fig.12 The third case and Fig.15 In the fourth example, a second substrate 120 is bonded to a first substrate 110 containing an Al component by ultrasonic welding, and a semiconductor chip 130 is mounted on the second substrate 120.

[0112] Furthermore, the first substrate 110 and the second substrate 120 may be formed of conductive metals having different compositions.

[0113] Furthermore, the area of ​​the first substrate 110 is greater than the area of ​​the second substrate 120, or the thickness of the first substrate 110 is greater than the thickness of the second substrate 120, and, as Figure 5 , Figure 8 , Fig.11 , Fig.14 As shown in (c), a part or all of the lower surface of the first substrate 110 is exposed to the bottom surface of the package casing 140, so that the heat generated by the semiconductor chip 130 is effectively dissipated to the outside of the package casing 140.

[0114] And, if Figure 6 , Fig. 9 , Fig.12 , Fig.15 As shown in (a), a through hole 160 for connecting with a heat sink (not shown) is formed in a region of the first substrate 110 to which the second substrate 120 or the semiconductor chip 130 is not bonded and communicates with the package case 140.

[0115] Then, the semiconductor chip 130 is formed into more than one, such as Figure 6 and Fig. 9 As shown in (b), it is bonded to the first substrate 110, or as Fig.12 and Fig.15 As shown in (b), it is bonded on the second substrate 120.

[0116] And, refer to Fig.17 (c), the semiconductor chip 130 may also be bonded to the second substrate 120 by interposing a conductive adhesive 121 thereon.

[0117] In addition, one or more embossing grooves 122 are formed on the upper surface of the second substrate 120 on which the semiconductor chip 130 is mounted, and the conductive adhesive 121 is coated on at least a portion of the embossing grooves 122 on the surface of the second substrate 120, thereby improving the bonding strength between the second substrate 120 and the semiconductor chip 130.

[0118] Here, the conductive adhesive 121 may be a solder series containing at least one of Sn, Pb and Bi, or a sintered material containing at least one of Ag and Cu.

[0119] Furthermore, an embossed groove 122 having a depth of less than 100 μm is formed on the second substrate 120 by ultrasonic welding, and Fig.17 and Fig.18 As shown, the embossing groove 122 can be formed into various shapes, for example, into a V-shaped ( Fig.18 (a)), U-shaped ( Fig.17 (c)) or a polygonal cross-sectional structure maximizes the surface area of ​​the stamped groove 122 and improves the bonding strength with the conductive adhesive 121.

[0120] Or, Fig.17 As shown in (a), the embossed groove 122 forms a lattice pattern, or as Fig.17 As shown in (b), the embossed grooves 122 are arranged in a dot shape or in various line shapes, so that the surface area of ​​the embossed grooves 122 is maximized and the bonding strength with the conductive adhesive 121 is improved.

[0121] Furthermore, when the second substrate 120 is formed into the embossed groove 122 by ultrasonic welding, burrs 123 are inevitably generated. Fig.18 As shown in (b), one or more burrs 123 may be formed around one or more embossing grooves 122, and the height of the burrs 123 does not exceed 100 μm.

[0122] Then, the package case 140 covers one or more semiconductor chips 130 and the ultrasonically welded region of the first substrate 110 and the second substrate 120, and is formed of EMC, PPS or PBT material as an insulator for protecting the semiconductor circuit.

[0123] Then, one or more terminals 150 are physically separated from the first substrate 110, such as Figure 6 and Fig.12 As shown in (c), it is formed without overlapping with the upper surface of the first substrate 110, or as shown in Fig. 9 and Fig.15 As shown in (c), it is overlapped with the top of the first substrate 110 and physically separated (separated), and is electrically connected to one or more semiconductor chips 130 through an electrical signal line 151, and at least one is exposed to the outside of the package shell 140 and electrically connected to an external terminal.

[0124] Also, the electric signal line 151 is in the shape of a metal line or a metal clip of a metal component.

[0125] Furthermore, the first substrate 110 is formed of a single material of Al, or an alloy material containing more than 50% of Al.

[0126] Furthermore, although not shown in the figure, Figure 4The same applies as shown in (c) and (e), the thickness d1 of the terminal 150 formed inside the package case 140 is smaller than the thickness d2 of the first substrate 110 (c), or is formed to be the same as the thickness d2 of the first substrate 110 (e).

[0127] Furthermore, although not shown in the figure, Figure 4 The same as shown in (c) of FIG. 1 is applicable, the thickness d3 of the second substrate 120 is the same as the thickness d1 of the terminal 150 excluding the coating layer, or as Figure 4 The same applies as shown in (e), and the thickness d2 of the first substrate 110 is the same as the thickness d1 of the terminal 150 excluding the coating layer.

[0128] Here, as described above, the second substrate 120, the second substrate terminal 124, or the second substrate 120 and the second substrate terminal 124 are formed of a single material of Cu, or are formed of an alloy material containing 50% or more of Cu.

[0129] Alternatively, one or more terminals 150 are formed of a single material of Al or Cu, or are formed of an alloy material containing 50% or more of Al or Cu.

[0130] Furthermore, the first substrate 110, the second substrate 120, the first substrate 110 and the second substrate 120, the second substrate terminal 124, or one or more terminals 150 respectively form a coating layer on more than one side, wherein the coating layer is formed by a single layer or by stacking two or more layers of the same metal or different metals.

[0131] Furthermore, the coating layer is formed as a single layer of Ni single material, or a Ni coating layer formed by stacking one or more layers of an alloy material containing more than 70% of Ni. Here, the thickness of the Ni coating layer can be 0.1μm to 10μm.

[0132] Furthermore, the outermost coating layer of one or more terminals 150 contains Sn.

[0133] Therefore, in a semiconductor package of another embodiment of the present invention, instead of an expensive copper substrate, the separated first substrate and second substrate are made of a material that can be ultrasonically welded, and are bonded together to make them lightweight, thereby reducing battery consumption and saving material costs when used in electric vehicles. In addition, the semiconductor chip is selectively mounted on the first substrate or the second substrate, so that the size and thickness of the substrate exposed to the outside of the package shell are relatively larger and thicker, thereby improving the heat dissipation effect, and the bonding strength with the semiconductor chip is improved by means of the stamped grooves and burrs.

[0134] The present invention has been described above with reference to the embodiments illustrated in the accompanying drawings. However, the present invention is not limited thereto, and a person skilled in the art of the present invention may make various modifications or other embodiments within the scope equivalent to the present invention. Therefore, the true protection scope of the present invention is defined by the claims.

Claims

1. A semiconductor package, characterized in that: include: One or more first substrates extending to form one or more first substrate terminals; One or more second substrates bonded to the first substrate by ultrasonic welding; One or more semiconductor chips bonded onto the second substrate; A package casing covering the ultrasonically welded area of ​​the one or more semiconductor chips and the second substrate; and A terminal is formed separately from the first substrate and is electrically connected to one or more semiconductor chips through an electrical signal line, and one or more of the terminals are exposed to the outside of the package housing. Furthermore, the thickness of the terminal formed inside the package case is the same as or smaller than the thickness of the first substrate, and one or more embossed grooves are formed on the upper surface of the second substrate.

2. The semiconductor package according to claim 1, wherein: The first substrate or the second substrate includes a conductive metal, or includes one or more insulating layers formed by stacking.

3. The semiconductor package according to claim 1, wherein: The first substrate, the second substrate, the first substrate and the second substrate, the first substrate terminal, or one or more of the terminals have a coating layer formed on one or more sides.

4. The semiconductor package according to claim 1, wherein: The semiconductor chip is bonded to the first substrate or the second substrate via a conductive adhesive.

5. The semiconductor package according to claim 4, wherein: The conductive adhesive is applied to at least a portion of the stamped groove on the surface of the second substrate.

6. The semiconductor package according to claim 1, wherein: One or more of the terminals are arranged on the first substrate at a predetermined distance from each other.

7. The semiconductor package according to claim 1, wherein: The area of ​​the first substrate is larger than the area of ​​the second substrate, or the thickness of the first substrate is larger than the thickness of the second substrate.

8. The semiconductor package according to claim 1, wherein: A through hole for coupling with a heat sink is formed in a region of the first substrate to which the second substrate or the semiconductor chip is not bonded.

9. The semiconductor package according to claim 1, wherein: The embossed grooves may have a V-shaped, U-shaped or polygonal cross-sectional structure, or may be formed in the form of a grid, dots or lines.

10. The semiconductor package according to claim 1, wherein: One or more burrs are formed around the periphery of one or more of the embossed grooves.

11. A semiconductor package, characterized in that: include: One or more first substrates; One or more second substrates are bonded to the first substrate by ultrasonic welding and have second substrate terminals extending therefrom; One or more semiconductor chips bonded onto the first substrate or the second substrate; A package casing covering the ultrasonically welded area of ​​the one or more semiconductor chips and the second substrate; and A terminal is formed separately from the first substrate and is electrically connected to one or more semiconductor chips through an electrical signal line, and one or more of the terminals are exposed to the outside of the package housing. Furthermore, the thickness of the terminal formed inside the package case is the same as or smaller than the thickness of the first substrate, and one or more embossed grooves are formed on the upper surface of the second substrate.

12. The semiconductor package according to claim 11, wherein: The first substrate or the second substrate includes a conductive metal, or includes one or more insulating layers formed by stacking.

13. The semiconductor package according to claim 11, wherein: The first substrate, the second substrate, the first substrate and the second substrate, the second substrate terminal, or one or more of the terminals have a coating layer formed on one or more sides.

14. The semiconductor package according to claim 11, wherein: The semiconductor chip is bonded to the first substrate or the second substrate via a conductive adhesive.

15. The semiconductor package according to claim 14, wherein: The conductive adhesive is applied to at least a portion of the stamped groove on the surface of the second substrate.

16. The semiconductor package according to claim 11, wherein: One or more of the terminals are arranged on the first substrate at a predetermined distance from each other.

17. The semiconductor package according to claim 11, wherein: The area of ​​the first substrate is larger than the area of ​​the second substrate, or the thickness of the first substrate is larger than the thickness of the second substrate.

18. The semiconductor package according to claim 11, wherein: A through hole for coupling with a heat sink is formed in a region of the first substrate to which the second substrate or the semiconductor chip is not bonded.

19. The semiconductor package according to claim 11, wherein: The embossed groove forms a V-shaped, U-shaped or polygonal cross-sectional structure, or is formed in the form of a grid, dots or lines.

20. The semiconductor package according to claim 11, wherein One or more burrs are formed around the periphery of one or more of the embossed grooves.

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