Semiconductor package and method of manufacturing the same

Abstract

Semiconductor package and method for manufacturing the same. The present invention provides a semiconductor package and a method for manufacturing the semiconductor package. As a non-limiting example, various aspects of the present invention provide a semiconductor package and a method for manufacturing the same, the semiconductor package comprising: a substrate having a first surface and a second surface opposite to the first surface, and including at least one first recessed portion formed in a direction from the first surface toward the second surface, a plurality of first recessed conductive patterns formed in the first recessed portion, and a first passive element, the first passive element being inserted into the first recessed portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recessed conductive patterns.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS / INCORPORATED BY REFERENCE

[0002] This application refers to and claims priority to and the benefit of Korean Patent Application No. 10-2015-0099070, filed on Jul. 13, 2015, in the Korean Intellectual Property Office, and entitled “SEMICONDUCTOR PACKAGE,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a semiconductor package and a method for manufacturing the same. Background Art

[0004] Current semiconductor packages and methods for forming semiconductor packages are inadequate, for example, resulting in excessive cost, reduced reliability, or excessive package size. Additional limitations and disadvantages of such methods will be apparent to those skilled in the art by comparing conventional and traditional methods with the present invention as described with reference to the drawings in the remainder of this application. Summary of the invention

[0005] Various aspects of the present invention provide a semiconductor package and a method for manufacturing a semiconductor package. As a non-limiting example, various aspects of the present invention provide a semiconductor package and a method for manufacturing the semiconductor package, the semiconductor package comprising: a substrate having a first surface and a second surface opposite to the first surface, and including at least one first notch portion formed in a direction from the first surface toward the second surface, a plurality of first notch conductive patterns formed in the first notch portion, and a first passive element, the first passive element being inserted into the first notch portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first notch conductive patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1D are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention;

[0007] Figure 2 A cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention;

[0008] Figure 3 A cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention;

[0009] Figures 4A to 4M are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention;

[0010] Figure 5A cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention;

[0011] Figures 6A to 6M are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention; and

[0012] Figures 7A to 7F It is a step-by-step description Fig.6I A cross-sectional view of another method for manufacturing a substrate illustrated in FIG. DETAILED DESCRIPTION

[0013] The following discussion presents various aspects of the present invention by providing examples of the present invention. Such examples are non-limiting, and thus the scope of the various aspects of the present invention should not necessarily be limited by any particular characteristics of the examples provided. In the following discussion, the phrases "for example," "for example," and "exemplary" are non-limiting and are generally synonymous with "by way of example and not limitation," "for example and not limitation," and the like.

[0014] As used herein, “and / or” means any one or more of the items in the list connected by “and / or”. As an example, “x and / or y” means any element in the three-element set {(x), (y), (x, y)}. In other words, “x and / or y” means “one or both of x and y”. As another example, “x, y, and / or z” means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y, and / or z” means “one or more of x, y, and z”.

[0015] The terms used herein are only for the purpose of describing specific examples and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will be further understood that the terms "comprise", "include", "have", etc., when used in this specification, represent the existence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0016] It should be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, for example, without departing from the teachings of the present invention, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part. Similarly, various spatial terms, such as "upper", "lower", "side", etc., may be used to distinguish one element from another element in a relative manner. However, it should be understood that the assembly can be oriented in different ways, for example, without departing from the teachings of the present invention, the semiconductor device can be turned sideways so that its "top" surface is horizontally oriented and its "side" surface is vertically oriented.

[0017] In the drawings, the thickness or size of layers, regions and / or components may be exaggerated for clarity. Therefore, the scope of the present invention should not be limited by such thickness or size. In addition, in the drawings, similar reference numerals may refer to similar elements throughout the discussion.

[0018] Furthermore, it should be understood that when element A is referred to as being “connected to” or “coupled to” element B, element A may be directly connected to element B or indirectly connected to element B (e.g., intervening element C (and / or other elements) may be present between element A and element B).

[0019] The present invention relates to a semiconductor package and a method of manufacturing the same, which can reduce the overall thickness of the semiconductor package by inserting a passive element into a recessed portion provided on a substrate.

[0020] Generally speaking, a plurality of active components and passive components are mounted on a planar surface of a substrate including a plurality of semiconductor dies. In addition, common passive components generally have a greater thickness than active components. Therefore, when a plurality of active components and passive components are mounted on a planar surface, the overall thickness of the semiconductor package may be increased due to the passive components. In addition, since the passive components have a limited capacity, it is necessary to newly develop the passive components to reduce their thickness.

[0021] Various example embodiments of the present invention provide a semiconductor package.

[0022] According to one aspect of the present invention, a semiconductor package and a method for manufacturing the same are provided, the semiconductor package comprising: a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recessed portion formed in a direction from the first surface toward the second surface, and a plurality of first recessed conductive patterns formed in the first recessed portion; and a first passive element inserted into the first recessed portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recessed conductive patterns.

[0023] According to another aspect of the present invention, a semiconductor package and a method for manufacturing the same are provided, the semiconductor package comprising: a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one second recessed portion formed in a direction from the second surface toward the first surface, and a plurality of second recessed conductive patterns formed in the second recessed portion; and a second passive element inserted into the second recessed portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of second recessed conductive patterns, wherein the substrate further comprises: a dielectric layer having a second recessed portion formed in a direction from the second surface toward the first surface; a first conductive pattern exposed to the first surface of the dielectric layer; a second conductive pattern exposed to the second surface of the dielectric layer; and a conductive via electrically connected to the first conductive pattern and the second conductive pattern when passing through the dielectric layer.

[0024] As described above, the semiconductor package according to one embodiment of the present invention can reduce the overall thickness of the semiconductor package by inserting a passive element into a recessed portion provided on a substrate.

[0025] The above and other aspects of the invention will be described in or apparent from the following description of various example embodiments.Aspects of the invention will now be presented with reference to the accompanying drawings.

[0026] See also Figures 1A to 1D , illustrating cross-sectional views sequentially illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0027] like Figures 1A to 1D As described in the specification, the manufacturing method of the semiconductor package according to the embodiment of the present invention may include: forming a plurality of first recessed conductive patterns 111 on the core substrate 10; forming a first insulating barrier 112 to surround the plurality of first recessed conductive patterns 111; forming a first insulating layer 113 to fill the outside of the first insulating barrier 112 and cover the first surface 10a of the core substrate 10; and preparing the substrate 110; and installing a first passive element 120 to be electrically connected to the first recessed conductive patterns 111. In the process of preparing the substrate 110, the formation of the insulating barrier 112 and the formation of the first insulating layer 113 may be alternately repeated one to five times or more. Now refer to Figures 1A to 1D A method of manufacturing a semiconductor package according to an embodiment of the present invention is described in more detail.

[0028] like Figure 1AAs described in the figure, in the process of forming the plurality of first recessed conductive patterns 111 on the core substrate 10, the plurality of first recessed conductive patterns 111 are formed on the first surface 10a of the core substrate 10 in a plate shape, wherein the first surface 10a is planar and the second surface 10b is planar and opposite to the first surface 10a. The first recessed conductive patterns 111 may be formed at positions corresponding to the regions on which the first passive element 120 will be mounted. The plurality of first recessed conductive patterns 111 may include two first recessed conductive patterns, which form a group to be connected to the first electrode 121 and the second electrode 122 of the first passive element 120, respectively. In order to allow the plurality of first passive elements 120 to be mounted on the first surface 10a of the core substrate 10, the plurality of first recessed conductive patterns 111 (where each two form a group) may be provided on the core substrate 10. The core substrate 10 includes a conductive pattern exposed to the first surface 10a and a conductive pattern exposed to the second surface 10b, and may be a printed circuit board having a conductive via that electrically connects the conductive patterns formed on the first surface 10a and the second surface 10b when passing through the first surface 10a and the second surface 10b. Here, the first recessed conductive pattern 111 may be formed simultaneously with the conductive pattern provided on the core substrate 10. The first recessed conductive pattern 111 may be generally made of one selected from the group consisting of: copper, aluminum, and their equivalents, but the scope of the present invention is not limited thereto.

[0029] like Figure 1B , in the process of forming the first insulating barrier 112 to surround the plurality of first recessed conductive patterns 111, the first insulating barrier 112 is formed to be spaced apart from each of the first recessed conductive patterns 111 on the first surface 10a of the core substrate 10 and to have a predetermined height to form a space on the region having the first recessed conductive patterns 111. Here, the first insulating barrier 112 is formed on the first surface 10a of the core substrate 10 to surround the first recessed conductive patterns 111. That is, the first insulating barrier 112 is configured so that two first recessed conductive patterns 111 to be connected to the corresponding electrodes of the first passive element 120 are spaced apart from the outside of the first surface 10a of the core substrate 10. The first insulating barrier 112 may be made of solder resist, but aspects of the present invention are not limited thereto.

[0030] like Figure 1CAs described in the foregoing, in the process of preparing the substrate 110, the substrate 110 is prepared by forming the first insulating layer 113 to cover the outer side of the first insulating barrier 112 on the first surface 10a of the core substrate 10. That is, the first insulating layer 113 is formed to completely cover the first surface 10a of the core substrate 10 in the outer side of the first insulating barrier 112 on the first surface 10a of the core substrate 10. The first insulating layer 113 may be formed to have the same height as the first insulating barrier 112. The first insulating layer 113 may be made of a semi-cured resin or a prepreg material, but aspects of the present invention are not limited thereto. The first insulating barrier 112 may prevent the first insulating layer 113 in a semi-cured state from covering the first recessed conductive pattern 111 when the first insulating layer 113 is formed. In addition, the formation of the first insulating barrier 112 and the formation of the first insulating layer 113 may be alternately repeated one to five times or more. Although the first insulating barrier 112 and the first insulating layer 113 , which are a single layer, are described in the present invention, they may be formed of a plurality of layers according to the height of the first passive element 120 .

[0031] As described above, one can use Figures 1A to 1C The method for manufacturing a semiconductor package described in the embodiment of the present invention forms a substrate 110. The substrate 110 may include at least one first notch portion 110c formed in a direction from the first surface 110a toward the second surface 110b. The first notch portion 110c is a region in which the first notch conductive pattern 111 is formed, and may correspond to an inner region formed by the first insulating barrier 112. The first notch portion 110c may include a plurality of first notch portions to mount a plurality of first passive elements 120 on the substrate 110, but the present invention does not limit the number of the first notch portions 110c.

[0032] like Figure 1D , in the process of installing the first passive element 120, the first passive element 120 is installed to be electrically connected to the first recess conductive pattern 111 provided in the first recess portion 110c of the substrate 110. The first passive element 120 may include a first electrode 121 and a second electrode 122, and may be electrically connected to the first recess conductive pattern 111. The first passive element 120 may include a resistor, a capacitor, an inductor, a connector, etc., but aspects of the present invention are not limited thereto. The first passive element 120 is inserted into the first recess portion 110c, thereby preventing the overall thickness of the semiconductor package 100 from increasing.

[0033] See also Figure 2 , is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

[0034] like Figure 2As described in the figure, the semiconductor package 200 includes a substrate 210 and a first passive element 120. In addition, the substrate 210 includes a core substrate 10, a first recessed conductive pattern 111, a first insulating barrier 112, a first insulating layer 113, and a conductive layer 214. The core substrate 10, the first recessed conductive pattern 111, the first insulating barrier 112, the first insulating layer 113, and the first passive element 120 of the substrate 210 are connected to the substrate 210. Figure 1D The following description will focus on the conductive layer 214, which is Figure 1D 1 and 2. The different features of the semiconductor package 100 are described in detail in FIG.

[0035] The conductive layer 214 may be formed to cover the first surface 111a of the first recess conductive pattern 111 after the first recess conductive pattern 111 is formed on the core substrate 10. The conductive layer 214 may be made of solder. The conductive layer 214 may be inserted between the first electrode 121 of the first passive element 120 and the first recess conductive pattern 111 and between the second electrode 122 of the first passive element 120 and the first recess conductive pattern 111, respectively. The conductive layer 214 may facilitate the connection of the first and second electrodes 121 and 122 of the first passive element 120 to the first recess conductive pattern 111.

[0036] See also Figure 3 , is a cross-sectional view of a semiconductor package according to yet another embodiment of the present invention.

[0037] like Figure 3 As described in the figure, the semiconductor package 300 includes a substrate 310, a first passive element 120 and a second passive element 330. In addition, the substrate 210 includes a core substrate 10, a first recessed conductive pattern 111, a first insulating barrier 112, a first insulating layer 113, a second recessed conductive pattern 314, a second insulating barrier 315 and a second insulating layer 316. The core substrate 10, the first recessed conductive pattern 111, the first insulating barrier 112, the first insulating layer 113 and the first passive element 120 of the substrate 310 are connected to the substrate 310. Figure 1D The following description will focus on the second recessed conductive pattern 314, the second insulating barrier 315, the second insulating layer 316 and the second passive element 330, which are Figure 1D 1 and 2. The different features of the semiconductor package 100 are described in detail in FIG.

[0038] The second recess conductive pattern 314 may include a plurality of second recess conductive patterns formed on the second surface 10b of the core substrate 10 of the plate shape. The second recess conductive pattern 314 may be formed at a position corresponding to the area on which the second passive element 330 will be installed. The plurality of second recess conductive patterns 314 may include a pair of second recess conductive patterns (which form a group) to be connected to the first electrode 331 and the second electrode 332 of the second passive element 330, respectively. In order to allow the plurality of second passive elements 330 to be mounted on the second surface 10b of the core substrate 10, the plurality of second recess conductive patterns 314 (wherein each two form a group) may be provided on the core substrate 10. Here, the second recess conductive pattern 314 may be electrically connected to the conductive pattern provided on the core substrate 10. The second recess conductive pattern 314 may be generally made of one of the groups selected from the following: copper, aluminum and its equivalent, but the scope of the present invention is not limited thereto. In addition, the second recess conductive pattern 314 may further include solder formed at its end.

[0039] The second insulating barrier 315 is separated from the second recess conductive pattern 314 on the second surface 10b of the core substrate 10, and is formed to have a predetermined height to form a space in the region where the second recess conductive pattern 314 is provided. The second insulating barrier 315 is formed to surround the second recess conductive pattern 314 on the second surface 10b of the core substrate 10. That is, the second insulating barrier 315 is configured so that the two second recess conductive patterns 314 to be connected to the corresponding electrodes 331 and 332 of the second passive element 330 are separated from the outside of the second surface 10b of the core substrate 10. The second insulating barrier 315 may be made of solder resist, but aspects of the present invention are not limited thereto.

[0040] The second insulating layer 316 is formed to cover the outer side of the second insulating barrier 315 on the second surface 10b of the core substrate 10. That is, the second insulating layer 316 is formed to completely cover the second surface 10b of the core substrate 10 in the outer side of the second insulating barrier 315 on the second surface 10b of the core substrate 10. The second insulating layer 316 may be formed to have the same height as the second insulating barrier 315. The second insulating layer 316 may be made of a semi-cured resin or a prepreg material, but aspects of the present invention are not limited thereto. The second insulating barrier 315 may prevent the second insulating layer 316 in a semi-cured state from covering the second recess conductive pattern 314 when the second insulating layer 316 is formed. In addition, the second insulating barrier 315 and the second insulating layer 316 may be alternately repeated one to five or more times. Although the second insulating barrier 315 and the second insulating layer 316 (which are a single layer) are described in the present invention, they may be formed of multiple layers according to the height of the second passive element 330.

[0041] The substrate 310 may include at least one first notch portion 110c formed in a direction from the first surface 310a toward the second surface 310b, and at least one second notch portion 310d formed in a direction from the second surface 310b to the first surface 310a. That is, the substrate 310 may include notch portions provided at opposite sides of the core substrate 10. The second notch portion 310d is a region in which the second notch conductive pattern 314 is formed, and may correspond to an inner region formed by the second insulating barrier 315. The second notch portion 310d may include a plurality of second notch portions to mount a plurality of second passive elements 330 on the substrate 110, but the present invention does not limit the number of the second notch portions 310d.

[0042] The second passive element 330 is installed in the second notch portion 310d of the substrate 110 to be electrically connected to the second notch conductive pattern 314 provided in the second notch portion 310d in the substrate 310. The second passive element 330 may include a first electrode 331 and a second electrode 332, and may be electrically connected to the second notch conductive pattern 314. The second passive element 330 may include a resistor, a capacitor, an inductor, a connector, etc., but aspects of the present invention are not limited thereto. The semiconductor is configured so that the first passive element 120 and the second passive element 330 are inserted into the first notch portion 110c and the second notch portion 310d, thereby preventing the overall thickness of the semiconductor package 300 from increasing.

[0043] See also Figures 4A to 4M , illustrating cross-sectional views sequentially illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention.

[0044] like Figures 4A to 4M As described in the figure, a method for manufacturing a semiconductor package according to another embodiment of the present invention may include: preparing a substrate 410; installing a first passive element 120 to be electrically connected to a first recessed conductive pattern 415a provided in a first recessed portion 410c of the substrate 410; encapsulating a semiconductor die 430 and the first passive element 120 to be covered by an encapsulant 440; and forming an external conductive bump 450 on a second conductive pattern 418 of the substrate 410.

[0045] Figures 4A to 4I4. The preparation of the substrate 410 is described in the figure. The preparation of the substrate 410 may include: forming a seed layer 2 on a carrier 1; forming a first conductive pattern 411 and a dummy pattern 412 using the seed layer 2; forming a first dielectric layer 413 to cover the first conductive pattern 411 and the dummy pattern 412; forming a first conductive via 414 and a third conductive pattern 415 on the first dielectric layer 413; forming a second dielectric layer 416 to cover the first conductive via 414 and the third conductive pattern 415; forming a second conductive via 417 and a second conductive pattern 418 on the second dielectric layer 416; separating the carrier 1 from the seed layer 2; removing the seed layer 2 from the first dielectric layer 413; forming a protective layer 419 on the dielectric layers 413 and 416 to expose the first and second conductive patterns 411 and 418; and removing the dummy pattern 412 from the first dielectric layer 413. Although the substrate 410 is formed on one surface of the carrier 1 in the illustrated embodiment, it may be formed on one and the other surfaces of the carrier 1 .

[0046] The substrate 410 may be formed by accumulating layers using the seed layer 2 formed on one and the other surface of the carrier 1 as a starting layer. That is, the substrate 410 may be formed using the seed layer 2 formed on one and the other surface of the carrier 1 as a starting layer. The following description will focus on the substrate 410 formed on one surface of the carrier 1. However, according to various aspects of the present invention, the substrate 410 may also be formed on the other surface of the carrier 1 using the same manufacturing method.

[0047] In the following, we will refer to Figures 4A to 4M The method of manufacturing the semiconductor package 400 is described in more detail.

[0048] exist Figure 4A In the process of forming the seed layer 2 on the carrier 1 described in , the seed layer 2 made of a conductive material is formed to cover one surface of the carrier 1 in the shape of a plate (or a wafer or a panel). The seed layer 2 may be formed to have a uniform thickness so as to cover one surface of the carrier 1. The seed layer 2 may be a copper layer, a titanium layer, or a titanium-tungsten layer, but aspects of the present invention are not limited thereto. In addition, the carrier 1 may be generally made of one selected from the group consisting of: copper, a core, stainless steel, glass, silicon, a dummy wafer, ceramics, sapphire, quartz, and equivalents thereof, but aspects of the present invention are not limited thereto.

[0049] In use Figure 4BIn the process of forming the first conductive pattern 411 and the dummy pattern 412 from the seed layer 2 described in the embodiment, a mask pattern (not shown) is formed to partially cover the seed layer 2, and then electroplating is performed on the seed layer 2 exposed to the outside through the mask pattern, thereby forming the first conductive pattern 411. In addition, when forming the first conductive pattern 411, the dummy pattern 412 may also be formed by electroplating the seed layer 2. Here, the dummy pattern 412 may be formed to have a greater thickness than the first conductive pattern 411. Subsequently, after forming the first conductive pattern 411 and the dummy pattern 412, the mask pattern is removed. The first conductive pattern 411 and the dummy pattern 412 may be made of copper (Cu), but aspects of the present invention are not limited thereto.

[0050] After forming the first dielectric layer 413 to cover Figure 4CIn the process of forming the first conductive pattern 411 and the dummy pattern 412 described in the embodiment of the present invention, the first dielectric layer 413 may be formed, and the first conductive via 414 and the third conductive pattern 415 may be further formed on the first dielectric layer 413. The first dielectric layer 413 may be formed to have a predetermined thickness sufficient to completely cover the first conductive pattern 411 and the dummy pattern 412 formed on the seed layer 2. The first dielectric layer 413 may electrically protect the first conductive pattern 411 and the dummy pattern 412. The first dielectric layer 413 may be made of one selected from the group consisting of: a prepreg material, a deposited film, a silicon oxide layer, a silicon nitride layer, and their equivalents, but aspects of the present invention are not limited thereto. In addition, the through hole may be formed to expose the first conductive pattern 411 to the outside when passing through the first dielectric layer 413, the first conductive via 414 may be further formed to fill at least a portion of the through hole, and then the third conductive pattern 415 may be further formed on the first dielectric layer 413 to be electrically connected to the first conductive via 414. The first conductive via 414 electrically connects the first conductive pattern 411 formed on one surface of the first dielectric layer 413 with the third conductive pattern 415 formed on the other surface of the first dielectric layer 413 when passing through the first dielectric layer 413. The first conductive via 414 may be formed by forming a seed layer 414x to completely cover the first conductive pattern 411 exposed to the outside through the through hole and the sidewall of the through hole of the first dielectric layer 413 and then performing electroplating on the seed layer 414x. The third conductive pattern 415 may be formed by forming a seed layer 414x on the first dielectric layer 413 and then performing electroplating on the seed layer 414x. In addition, the third conductive pattern 415 electrically connected to the first conductive via 414 may also be formed to extend along the exposed surface portion of the first dielectric layer 413 when the first conductive via 414 is formed by electroplating. That is, the seed layer 414x may be inserted between the first conductive via 414 and the first dielectric layer 413 and between the third conductive pattern 415 and the first dielectric layer 413. In addition, at least one third conductive pattern 415 is formed on the dummy pattern 412. The third conductive pattern 415 formed on the dummy pattern 412 becomes a first recessed conductive pattern 415a provided in the recessed portion of the substrate 410.

[0051] The second dielectric layer 416 is formed to cover Figure 4DIn the process of forming the first conductive via 414 and the third conductive pattern 415 described in the embodiment of the present invention, the second dielectric layer 416 has a predetermined thickness sufficient to completely cover the first conductive via 414, the third conductive pattern 415 and the first dielectric layer 413. The second dielectric layer 416 can electrically protect the first conductive via 414 and the third conductive pattern 415. The second dielectric layer 416 can be made of one or more selected from the group consisting of: a prepreg material, a deposited film, a silicon oxide layer, a silicon nitride layer and their equivalents, but aspects of the present invention are not limited thereto.

[0052] In the formation Figure 4E In the process of forming the second conductive via 417 and the second conductive pattern 418 illustrated in FIG. 4 , the via is formed to expose the third conductive pattern 415 to the outside while passing through the second dielectric layer 416, the second conductive via 417 is further formed to fill at least a portion of the via, and then the second conductive pattern 418 is formed on the second dielectric layer 416 to be electrically connected to the second conductive via 417. The second conductive via 417 electrically connects the third conductive pattern 415 formed on one surface of the second dielectric layer 416 with the second conductive pattern 418 formed on the other surface of the second dielectric layer 416 while passing through the second dielectric layer 416. The second conductive via 417 may be formed by forming a seed layer 417x to completely cover the third conductive pattern 415 exposed to the outside through the via and the sidewall of the via of the second dielectric layer 416, and then performing electroplating on the seed layer 417x. The second conductive pattern 418 may be formed by forming a seed layer 417x on the second dielectric layer 416 and then performing electroplating on the seed layer 417x. In addition, the second conductive pattern 418 electrically connected to the second conductive via 417 may also be formed to extend along the exposed surface portion of the second dielectric layer 416 when the second conductive via 417 is formed by electroplating. That is, the seed layer 417x may be inserted between the second conductive via 417 and the second dielectric layer 416 and between the second conductive pattern 418 and the second dielectric layer 416.

[0053] In making vector 1 and Figure 4F In the process of separating the seed layer 2 described in the figure, the carrier 1 is separated from the seed layer 2 to expose the seed layer 2 to the outside. The carrier 1 is removed by general grinding and / or chemical etching or by UV or laser release, but aspects of the present invention are not limited thereto.

[0054] In from Figure 4GIn the process of removing the seed layer 2 from the first dielectric layer 413 described in the figure, the substrate 410x separated from the carrier 1 is flipped, and then the seed layer 2 is removed from the first dielectric layer 413, thereby exposing the first conductive pattern 411, the first dielectric layer 413 and the dummy pattern 412 to the outside. The first surface 413a of the first dielectric layer 413 exposed to the outside and the first surface 411a of the first conductive pattern 411 can be coplanarly positioned (or coplanar). In addition, the second conductive pattern 418 formed on the second surface 416b of the second dielectric layer 416 can extend from the second surface 416b of the second dielectric layer 416 on the substrate 410x. The seed layer 2 can be removed by general grinding and / or chemical etching, but aspects of the present invention are not limited thereto.

[0055] A protective layer 419 is formed on the dielectric layers 413 and 416 to expose Figure 4H 416, protective layers 419a and 419b are respectively formed on the first surface 413a of the first dielectric layer 413 and the second surface 416b of the second dielectric layer 416. The protective layers 419a and 419b are formed to expose the first conductive pattern 411 and the dummy pattern 412 exposed through the first surface 413a of the first dielectric layer 413 and the second conductive pattern 418 exposed through the second surface 416b of the second dielectric layer 416 to the outside. That is, the protective layers 419a and 419b are respectively formed on the first surface 413a of the first dielectric layer 413 and the second surface 416b of the second dielectric layer 416 to expose the first conductive pattern 411, the dummy pattern 412 and the second conductive pattern 418 to the outside. The protective layers 419a and 419b may be made of solder resist, but aspects of the present invention are not limited thereto.

[0056] In from Fig. 4I In the process of removing the dummy pattern 412 from the dielectric layer 413 described in the above, the dummy pattern 412 exposed to the outside when the seed layer 2 is removed is removed, thereby forming a substrate 410 having a first notch portion 410c. The first notch conductive pattern 415a is exposed to the outside in the first notch portion 410c of the substrate 410 when the dummy pattern 412 is removed. The first notch conductive pattern 415a may be Figure 4C The third conductive pattern 415 is formed in the dummy pattern 412 in the step described in the embodiment of the present invention. The dummy pattern 412 may be removed by etching, but aspects of the present invention are not limited thereto.

[0057] exist Figure 4JIn the process of mounting the first passive element 120 on the substrate 410 illustrated in FIG. 1 , the first passive element 120 is mounted in the first notch portion 410c to be electrically connected to the first notch conductive pattern 415a provided in the first notch portion 410c. The first passive element 120 may include a first electrode 121 and a second electrode 122, which are electrically connected to the first notch conductive pattern 415a. The first passive element 120 may include a resistor, a capacitor, an inductor, a connector, etc., but aspects of the present invention are not limited thereto. The first passive element 120 is inserted into the first notch portion 410c, thereby preventing the overall thickness of the semiconductor package 400 from increasing.

[0058] During installation Figure 4K 4. In the process of bonding the semiconductor die 430 illustrated in FIG. 4, the semiconductor die 430 is mounted on the first surface 410a of the substrate 410 to be electrically connected to the first conductive pattern 411 of the substrate 410. The semiconductor die 430 may be mounted on the first surface 410a of the substrate 410 to completely cover the first passive element 120 and the first recessed portion 410c. The semiconductor die 430 may be electrically connected to the first conductive pattern 411 by flip chip bonding, temperature compression (TC) bonding, temperature compression non-conductive paste (TCNCP) bonding, or wire bonding. The semiconductor die 430 has a planar first surface 430a and a planar second surface 430b opposite to the first surface 430a, and a plurality of conductive bumps 431 are formed on the second surface 410b. The semiconductor die 430 is electrically connected to the first conductive pattern 411 via the plurality of conductive bumps 431. The conductive bumps 431 may include conductive pillars, copper pillars, conductive balls, solder balls, or copper balls, but aspects of the present invention are not limited thereto. In addition, a plurality of bonding pads are provided on the first surface 430a of the semiconductor die 430 instead of the plurality of conductive bumps 431, and the bonding pads and the first conductive pattern 411 may be electrically connected via wires (not shown). The semiconductor die 430 may include a general memory, a graphics processing unit (GPU), a central processing unit (CPU), and their equivalents, but aspects of the present invention are not limited thereto.

[0059] exist Figure 4L In the encapsulation process described in , encapsulation is performed using an encapsulant 440 to cover the first surface 410a of the substrate 410, the semiconductor die 430, and the first passive element 120. The encapsulant 440 can electrically protect the first surface 410a of the substrate 410, the first passive element 120, and the semiconductor die 430 from external conditions.

[0060] In the formation Figure 4MIn the process of forming the external conductive bump 450 as described in the embodiment of the present invention, the second conductive pattern 418 and the external conductive bump 450 exposed to the second surface 410b of the substrate 410 are formed. The external conductive bump 450 is an input and / or output terminal for mounting the semiconductor package 400 on an external board of an electronic device. The external conductive bump 450 may include a conductive pillar, a copper pillar, a conductive ball, a solder ball, or a copper ball, but aspects of the present invention are not limited thereto.

[0061] In the semiconductor package 400 thus manufactured, the first passive element 120 is inserted into the first notch portion 410 c of the substrate 410 , thereby preventing the overall thickness of the semiconductor package 400 from increasing.

[0062] See also Figure 5 , illustrates a cross-sectional view of a semiconductor package according to yet another embodiment of the present invention.

[0063] like Figure 5 As illustrated in FIG. 5 , the semiconductor package 500 includes a substrate 410, a first passive element 120, a semiconductor die 530, an encapsulant 440, and external conductive bumps 450. The substrate 410, the first passive element 120, the encapsulant 440, and the external conductive bumps 450 are connected to the semiconductor die 530. Figure 4M The following description will focus on the semiconductor die 530, which is Figure 4M 4. The different features of the semiconductor package 400 are illustrated in FIG.

[0064] The semiconductor die 530 is mounted on the first surface 410a of the substrate 410 to be electrically connected to the first conductive pattern 411 of the substrate 410. The semiconductor die 530 may be formed on the first surface 410a of the substrate 410 so as to cover the first passive element 120 and the first recessed portion 410c. Figure 5 In the embodiment, two semiconductor dies 530 are mounted on the substrate 410, but one semiconductor die 530 or one or more semiconductor dies 530 may be mounted on the substrate 410, but aspects of the present invention are not limited thereto. The semiconductor die 530 may be mounted on the first conductive pattern 411 by flip chip bonding, temperature compression (TC) bonding, or temperature compression non-conductive paste (TCNCP) bonding, but the scope of the present invention is not limited thereto. The semiconductor die 530 may include a plurality of conductive bumps 531. The semiconductor die 530 is electrically connected to the first conductive pattern 411 via the plurality of conductive bumps 531. The conductive bumps 531 may include conductive pillars, copper pillars, conductive balls, solder balls, or copper balls, but aspects of the present invention are not limited thereto. The semiconductor die 530 may include a general memory, a graphics processing unit (GPU), a central processing unit (CPU), and equivalents thereof, but aspects of the present invention are not limited thereto.

[0065] See also Figures 6A to 6M, are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0066] like Figures 6A to 6M As described in the figure, a semiconductor package according to another embodiment of the present invention may include: preparing a substrate 610; installing a third passive element 330 to be electrically connected to a second recess conductive pattern 615a provided in a second recess portion 610c of the substrate 610; installing a semiconductor die 430 to be electrically connected to a first conductive pattern 611 of the substrate 610; encapsulating the semiconductor die 430 to be covered by an encapsulant 440; and forming an external conductive bump 450 on the second conductive pattern 618 of the substrate 610.

[0067] Figures 6A to 6I 610. The preparation of the substrate 610 may include: forming a first conductive pattern 611 using a seed layer 2; forming a first dielectric layer 613 to cover the first conductive pattern 611; forming a first conductive via 614 and a third conductive pattern 615 on the first dielectric layer 613; forming a dummy pattern 612 on the third conductive pattern 615; forming a second dielectric layer 616 to cover the dummy pattern 612, the first conductive via 614, and the third conductive pattern 615; forming a second conductive via 617 and a second conductive pattern 618 on the second dielectric layer 616; separating the carrier 1 from the seed layer 2; removing the seed layer 2 from the first dielectric layer 613; forming a protective layer 619 on the dielectric layers 613 and 616 to expose the first and second conductive patterns 611 and 618; and removing the dummy pattern 612 from the second dielectric layer 616.

[0068] During the preparation of the substrate 610, Figure 4A After forming a seed layer 2 on the carrier 1 described in the above, forming Fig. 6A The first conductive pattern 611 described in FIG.

[0069] Although the substrate 610 formed on one surface of the carrier 1 is described, the substrate 610 may be formed on both one and the other surfaces of the carrier 1. The substrate 610 may be formed by accumulating layers using the seed layer 2 formed on one and the other surfaces of the carrier 1 as a starting layer. That is, the substrate 610 may be formed using the seed layer 2 formed on one and the other surfaces of the carrier 1 as a starting layer. The following description will focus on the substrate 610 formed on one surface of the carrier 1. However, according to various aspects of the present invention, the substrate 610 may also be formed on the other surface of the carrier 1 using the same manufacturing method.

[0070] In the following, we will refer to Figures 6A to 6M The method of manufacturing the semiconductor package 600 is described in more detail.

[0071] In use Fig. 6AIn the process of forming the first conductive pattern 611 from the seed layer 2 described in the embodiment, a mask pattern (not shown) is formed to partially cover the seed layer 2, and then electroplating is performed on the seed layer 2 exposed to the outside through the mask pattern, thereby forming the first conductive pattern 611 having a uniform thickness. After the first conductive pattern 611 is formed, the mask pattern is removed. The first conductive pattern 611 may be made of copper (Cu), but aspects of the present invention are not limited thereto.

[0072] After forming the first dielectric layer 613 to cover Figure 6B 614, a first conductive via 614 and a third conductive pattern 615 are formed on the first dielectric layer 613. The first dielectric layer 613 is formed to have a predetermined thickness sufficient to completely cover the first conductive pattern 611 formed on the seed layer 2. The first dielectric layer 613 can electrically protect the first conductive pattern 611. The first dielectric layer 613 can be made of one selected from the group consisting of: a prepreg material, a deposited film, a silicon oxide layer, a silicon nitride layer, and their equivalents, but the aspects of the present invention are not limited thereto. In addition, a through hole can be formed to expose the first conductive pattern 611 to the outside when passing through the first dielectric layer 613, the first conductive via 614 can be further formed to fill at least a portion of the through hole, and then the third conductive pattern 615 can be further formed on the first dielectric layer 613 to be electrically connected to the first conductive via 614. The first conductive via 614 electrically connects the first conductive pattern 611 formed on one surface of the first dielectric layer 613 with the third conductive pattern 615 formed on the other surface of the first dielectric layer 613 when passing through the first dielectric layer 613. The first conductive via 614 may be formed by forming a seed layer 614x to completely cover the first conductive pattern 611 exposed to the outside through the through hole and the sidewall of the through hole of the first dielectric layer 613 and then performing electroplating on the seed layer 614x. The third conductive pattern 615 may be formed by forming a seed layer 614x on the first dielectric layer 613 and then performing electroplating on the seed layer 614x. In addition, the third conductive pattern 615 electrically connected to the first conductive via 614 may also be formed to extend along the exposed surface portion of the first dielectric layer 613 when the first conductive via 614 is formed by electroplating. That is, the seed layer 614x may be inserted between the first conductive via 614 and the first dielectric layer 613 and between the third conductive pattern 615 and the first dielectric layer 613. The seed layer 614x may surround a region between the first conductive pattern 611 and the first conductive via 614 and a sidewall of the first conductive via 614.

[0073] exist Figure 6C615, the dummy pattern 612 is formed to cover at least one of the third conductive patterns 615 formed on the first dielectric layer 613. The dummy pattern 612 may have a predetermined height. In addition, the dummy pattern 612 may be formed on the third conductive pattern 615 that is not connected to the first conductive via 614 among the third conductive patterns 615 formed on the first dielectric layer 613. The third conductive pattern 615 having the dummy pattern 612 becomes a second recessed conductive pattern 615a provided in the recessed portion of the substrate 610.

[0074] After forming the second dielectric layer 616 to cover Fig.6D 614, and the third conductive pattern 615, a second dielectric layer 616 having a predetermined thickness is formed to cover the dummy pattern 612, the first conductive via 614, the third conductive pattern 615, and the first dielectric layer 613. Here, the first surface 612a of the dummy pattern 612 is exposed to the outside via the second dielectric layer 616. The second dielectric layer 616 can electrically protect the first conductive via 614 and the third conductive pattern 615. The second dielectric layer 616 can be made of one selected from the group consisting of: a prepreg material, a deposited film, a silicon oxide layer, a silicon nitride layer, and equivalents thereof, but aspects of the present invention are not limited thereto.

[0075] In the formation Fig. 6E In the process of forming the second conductive via 617 and the second conductive pattern 618 illustrated in FIG. 1 , the via is formed to expose the third conductive pattern 615 to the outside while passing through the second dielectric layer 616, the second conductive via 617 is further formed to fill at least a portion of the via, and the second conductive pattern 618 is then formed on the second dielectric layer 616 to be electrically connected to the second conductive via 617. The second conductive via 617 may be formed by forming a seed layer 617x to completely cover the third conductive pattern 615 exposed to the outside through the via and the sidewall of the via of the second dielectric layer 616 and then performing electroplating on the seed layer 617x. The second conductive pattern 618 may be formed by forming a seed layer 617x on the second dielectric layer 616 and then performing electroplating on the seed layer 617x. In addition, the second conductive pattern 618 electrically connected to the second conductive via 617 may also be formed to extend along the exposed surface portion of the second dielectric layer 616 when the second conductive via 617 is formed by electroplating. That is, the seed layer 617 x may be inserted between the second conductive via 617 and the second dielectric layer 616 and between the second conductive pattern 618 and the second dielectric layer 616 .

[0076] In making vector 1 and Fig. 6FIn the process of separating the seed layer 2 described in the figure, the carrier 1 is separated from the seed layer 2 to expose the seed layer 2 to the outside. The carrier 1 is removed by general grinding and / or chemical etching or by UV or laser release, but aspects of the present invention are not limited thereto.

[0077] In from Figure 6G In the process of removing the seed layer 2 described in , the substrate 610x separated from the carrier 1 is flipped, and then the seed layer 2 is removed from the first dielectric layer 613, thereby exposing the first conductive pattern 611, the first dielectric layer 613 and the dummy pattern 612 to the outside. The first surface 613a of the first dielectric layer 613 exposed to the outside and the first surface 611a of the first conductive pattern 611 may be coplanarly positioned (or coplanar). In addition, the second conductive pattern 618 formed on the second surface 616b of the second dielectric layer 616 may extend from the second surface 616b of the second dielectric layer 616 on the substrate 610x. The seed layer 2 may be removed by general grinding and / or chemical etching, but aspects of the present invention are not limited thereto.

[0078] A protective layer 619 is formed on the dielectric layers 613 and 616 to expose Figure 6H In the process of forming the conductive patterns 611 and 618 described in the embodiment of the present invention, protective layers 619a and 619b are respectively formed on the first surface 613a of the first dielectric layer 613 and the second surface 616b of the second dielectric layer 616. The protective layers 619a and 619b are formed to expose the first conductive pattern 611 exposed through the first surface 613a of the first dielectric layer 613 and the second conductive pattern 618 and the dummy pattern 612 exposed through the second surface 616b of the second dielectric layer 616 to the outside. That is, the protective layers 619a and 619b are respectively formed on the first surface 613a of the first dielectric layer 613 and the second surface 616b of the second dielectric layer 616 to expose the first conductive pattern 611, the dummy pattern 612 and the second conductive pattern 618 to the outside. The protective layers 619a and 619b may be made of solder resist, but aspects of the present invention are not limited thereto.

[0079] In from Fig.6I In the process of removing the dummy pattern 612 from the dielectric layer 616 described in the above, the dummy pattern 612 is removed, thereby forming a substrate 610 having a second notch portion 610c. The second notch conductive pattern 615a of the substrate 610 is exposed to the outside in the second notch portion 610c provided when the dummy pattern 612 is removed. The second notch conductive pattern 615a may be a conductive pattern having a dielectric layer formed in the substrate 610. Figure 6C The dummy pattern 612 may be removed by etching, but aspects of the present invention are not limited thereto.

[0080] exist Figure 6J In the process of mounting the second passive element 330 on the substrate 610 described in the figure, the second passive element 330 is mounted in the second notch portion 610c to be electrically connected to the second notch conductive pattern 615a provided in the second notch portion 610c. The second passive element 330 may include a first electrode 331 and a second electrode 332 and may be electrically connected to the first notch conductive pattern 615a. The second passive element 330 may include a resistor, a capacitor, an inductor, a connector, etc., but aspects of the present invention are not limited thereto. The second passive element 330 is inserted into the second notch portion 610c, thereby preventing the overall thickness of the semiconductor package 600 from increasing.

[0081] During installation Figure 6K In the process of mounting the semiconductor die 430 illustrated in FIG. 6 , the semiconductor die 430 is mounted on the first surface 610 a of the substrate 610 to be electrically connected to the first conductive pattern 611 of the substrate 610 . Figure 6K The semiconductor die 430 described in the embodiment of the present invention can be mounted with Figure 4K The installation of the semiconductor die 430 is the same as described in .

[0082] exist Figure 6L In the encapsulation process described in , encapsulation is performed using an encapsulant 440 to cover the first surface 610a of the substrate 610 and the semiconductor die 430. The encapsulant 440 may electrically protect the first surface 610a of the substrate 610 and the semiconductor die 430 from external conditions.

[0083] In the formation Figure 6M In the process of forming the external conductive bump 450 described in the figure, the external conductive bump 450 is formed to be electrically connected to the second conductive pattern 618 exposed to the second surface 610b of the substrate 610. The external conductive bump 450 is an output pad for mounting the semiconductor package 600 in an external board of an electronic device. The external conductive bump 450 may include a conductive pillar, a copper pillar, a conductive ball, a solder ball, or a copper ball, but aspects of the present invention are not limited thereto.

[0084] In the semiconductor package 600 thus manufactured, the second passive element 330 is inserted into the second notch portion 610 c of the substrate 610 , thereby preventing the overall thickness of the semiconductor package 600 from increasing.

[0085] See also Figures 7A to 7F , which is a step-by-step description Fig.6I A cross-sectional view of another method for manufacturing a substrate illustrated in FIG.

[0086] like Figures 7A to 7FAs described in , the preparation of the substrate 610 may include: forming a second dielectric layer 616 to cover the first conductive via 614 and the third conductive pattern 615; forming a second conductive via 617 and a second conductive pattern 618 on the second dielectric layer 616; separating the carrier 1 from the seed layer 2; removing the seed layer 2 from the first dielectric layer 613; forming a protective layer on the dielectric layers 613 and 616 to expose the first and second conductive patterns 611 and 618; and forming a second recessed portion 610c on the second dielectric layer 616. The preparation of the substrate 610 is performed by the following operations: Figure 4A , 6A or forming a seed layer 2 on the carrier 1 described in 6B; forming a first conductive pattern 611 using the seed layer 2; forming a first dielectric layer 613 to cover the first conductive pattern 611 and forming a first conductive via 614 and a third conductive pattern 615 on the first dielectric layer 613; and forming Fig. 7A The second dielectric layer 616 illustrated in FIG.

[0087] After forming the second dielectric layer 616 to cover Fig. 7A In the process of forming the first conductive via 614 and the third conductive pattern 615 described in the embodiment of the present invention, a second dielectric layer 616 having a predetermined thickness is formed to cover the first conductive via 614, the third conductive pattern 615 and the first dielectric layer 613. The second dielectric layer 616 can electrically protect the first conductive via 614 and the third conductive pattern 615. The second dielectric layer 616 can be made of one selected from the group consisting of: a prepreg material, a deposited film, a silicon oxide layer, a silicon nitride layer and equivalents thereof, but aspects of the present invention are not limited thereto.

[0088] In the formation Figure 7B In the process of forming the second conductive via 617 and the second conductive pattern 618 described in the figure, the via can be formed to expose the third conductive pattern 615 to the outside when passing through the second dielectric layer 616, the second conductive via 617 can be further formed to fill at least a portion of the via, and the second conductive pattern 618 can then be further formed on the second dielectric layer 616 to be electrically connected to the second conductive via 617. Figure 7B The formation of the second conductive via 617 and the second conductive pattern 618 described in Fig. 6E The formation of the second conductive via 617 and the second conductive pattern 618 described in is the same.

[0089] In from Figure 7C In the process of removing the seed layer 2 from the carrier 1 described in , the carrier 1 is removed from the seed layer 2 to expose the seed layer 2 to the outside. Figure 7C The removal of the carrier 1 described in Fig. 6F The removal of carrier 1 is the same as described in .

[0090] In from Fig.7D In the process of removing the seed layer 2 from the first dielectric layer 613 illustrated in FIG. 6 , the substrate 610 x separated from the carrier 1 is turned over, and then the seed layer 2 is removed from the first dielectric layer 613 , thereby exposing the first conductive pattern 611 and the first dielectric layer 613 . Fig.7D The removal of the seed layer 2 described in Figure 6G The removal of the seed layer 2 is the same as described in .

[0091] A protective layer 619 is formed on the dielectric layers 613 and 616 to expose Fig. 7E During the process of forming the conductive patterns 611 and 618 described in the above description, protective layers 619a and 619b are formed on the first surface 613a of the first dielectric layer 613 and the second surface 616b of the second dielectric layer 616, respectively. Fig. 7E The formation of the protective layer 619 described in Figure 6H The formation of the protective layer 619 described in is the same.

[0092] exist Figure 7F In the process of forming the second notch portion 610c on the second dielectric layer 616 described in the figure, the second notch portion 610c with a predetermined depth from the substrate 610 is formed on the second dielectric layer 616. The second notch portion 610c can be formed by removing a region with a predetermined height of the second dielectric layer 616. The second notch portion 610c can be formed by photolithography and / or laser, but aspects of the present invention are not limited thereto. The substrate 610 has a second notch portion 610c as a notch with a predetermined depth in a direction from the second surface 610b toward the first surface 610a. The second notch portion 610c of the substrate 610 exposes at least one of the third conductive pads 623 to the outside in the second notch portion 610c. In addition, the third conductive pad 623 exposed to the outside via the second notch portion 610c may be a second notch conductive pattern 615a. That is, the second notch conductive pattern 615a is exposed to the outside in the second notch portion 610c.

[0093] Discussion herein includes numerous illustrative diagrams showing various parts of electronic packaging assemblies and methods of making the same. For clarity, these figures do not show all aspects of each example assembly. Any example assembly and / or method provided herein may share any or all characteristics with any or all other assemblies and / or methods provided herein.

[0094] In summary, various aspects of the present invention provide a semiconductor package and a method for manufacturing a semiconductor package. As a non-limiting example, various aspects of the present invention provide a semiconductor package and a method for manufacturing the semiconductor package, the semiconductor package comprising: a substrate having a first surface and a second surface opposite to the first surface, and including at least one first notch portion formed in a direction from the first surface toward the second surface, a plurality of first notch conductive patterns formed in the first notch portion; and a first passive element inserted into the first notch portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first notch conductive patterns. Although the above has been described with reference to certain aspects and examples, it should be understood by those skilled in the art that various modifications may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt specific situations or materials to the teachings of the present invention without departing from the scope of the present invention. Therefore, it is desired that the present invention is not limited to the specific examples disclosed, but that the present invention will include all examples falling within the scope of the appended claims.

Claims

1. An electronic device, comprising: A substrate, comprising: a top substrate structure having a top substrate structure top side, a top substrate structure bottom side, and a plurality of top substrate structure peripheral sides, wherein the top substrate structure comprises a top substrate structure conductive layer and a top substrate structure dielectric layer; as well as A recessed hole substrate structure having a recessed hole substrate structure top side coupled to the bottom side of the top substrate structure, a recessed hole substrate structure bottom side, and a plurality of recessed hole substrate structure surrounding sides, wherein: The concave hole substrate structure comprises a concave hole substrate structure conductive layer and a concave hole substrate structure dielectric layer; and and The recessed hole substrate structure includes a bottom recessed hole and a bottom recessed hole opening in a bottom side of the recessed hole substrate structure; a top electronic component having a top electronic component top side, a top electronic component bottom side coupled to the top substrate structure top side, and a plurality of top electronic component peripheral sides; a bottom electronic component having a bottom electronic component top side, a bottom electronic component bottom side, and a plurality of bottom electronic component peripheral sides, the bottom electronic component top side being coupled to a portion of a well substrate structure bottom side in the well, wherein at least a portion of the bottom electronic component is disposed in the bottom well; as well as an encapsulation material, the encapsulation material covering at least the top substrate structure top side and the top electronic component peripheral side, the encapsulation material having an encapsulation top side, an encapsulation bottom side facing the top substrate structure top side, and a plurality of encapsulation peripheral sides, Wherein each of the plurality of top substrate structure peripheral sides is coplanar with a corresponding one of the plurality of recessed hole substrate structure peripheral sides and coplanar with a corresponding one of the plurality of encapsulation peripheral sides. 2 . The electronic device of claim 1 , wherein a portion of the encapsulation material is disposed vertically directly between the top substrate structure top side and the top electronic component bottom side.

3. The electronic device of claim 1, wherein one or both of the top substrate structure dielectric layer and the recessed hole substrate structure dielectric layer comprises an organic dielectric material.

4. The electronic device according to claim 1, wherein: The top substrate structure conductive layer is located on the top side of the top substrate structure; The top substrate structure includes a second top substrate structure conductive layer, the second top substrate structure conductive layer is located at the bottom side of the top substrate structure; A top side of the top substrate structure conductive layer is coplanar with a top side of the top substrate structure dielectric layer; and A bottom side of the second top substrate structure conductive layer extends downwardly from a bottom side of the top substrate structure dielectric layer.

5. The electronic device of claim 4, wherein the top substrate structure comprises a conductive via extending vertically directly between the top substrate structure conductive layer and the second top substrate structure conductive layer and electrically connecting the top substrate structure conductive layer and the second top substrate structure conductive layer.

6. The electronic device of claim 1, comprising a volume laterally surrounding the bottom electronic component and laterally separating a surrounding side of the bottom electronic component from the recessed hole substrate structure dielectric layer.

7. The electronic device according to claim 1, wherein: The recessed hole substrate structure conductive layer includes a recessed hole pad, and the recessed hole pad is exposed in the bottom recessed hole; The bottom electronic component includes an electrode directly coupled to the recessed hole pad; and The recessed hole substrate structure dielectric layer laterally surrounds the recessed hole pad.

8. The electronic device of claim 1, wherein a portion of the recessed hole substrate structure dielectric layer is disposed vertically directly between the top substrate structure bottom side and the bottom electronic component.

9. The electronic device of claim 1, wherein the recessed hole comprises a hole extending entirely through the recessed hole substrate structure dielectric layer.

10. The electronic device according to claim 1, wherein: The recessed hole comprises a hole, and the hole extends entirely through the recessed hole substrate structure dielectric layer; The recessed hole substrate structure includes a second recessed hole substrate structure dielectric layer; and The recessed hole extends only partially through the second recessed hole substrate structure dielectric layer.

11. The electronic device according to claim 1, wherein: At least a portion of the bottom electronic component is exposed from the electronic device; and Any portion of the top electronic component is exposed from the electronic device.

12. The electronic device of claim 1, wherein the bottom electronic component is a passive electronic component.

13. An electronic device comprising: A substrate, comprising: a top substrate structure having a top substrate structure top side, a top substrate structure bottom side, and a plurality of top substrate structure peripheral sides, wherein the top substrate structure comprises a top substrate structure conductive layer and a top substrate structure dielectric layer; as well as A recessed hole substrate structure having a recessed hole substrate structure top side coupled to the bottom side of the top substrate structure, a recessed hole substrate structure bottom side, and a plurality of recessed hole substrate structure surrounding sides, wherein: The recessed hole substrate structure comprises a recessed hole substrate structure conductive layer, a first recessed hole substrate structure dielectric layer and a second recessed hole substrate structure dielectric layer; and The recessed hole substrate structure includes a bottom recessed hole and a bottom recessed hole opening in a bottom side of the recessed hole substrate structure; a top electronic component having a top electronic component top side, a top electronic component bottom side coupled to the top substrate structure top side, and a plurality of top electronic component peripheral sides; a bottom electronic component having a bottom electronic component top side, a bottom electronic component bottom side, and a plurality of bottom electronic component peripheral sides, the bottom electronic component top side being coupled to a portion of the well substrate structure bottom side in the well, wherein at least a portion of the bottom electronic component is disposed in the bottom well; as well as an encapsulation material, the encapsulation material covering at least the top substrate structure top side and the top electronic component peripheral side, the encapsulation material having an encapsulation top side, an encapsulation bottom side facing the top substrate structure top side, and a plurality of encapsulation peripheral sides; in: The first recessed hole substrate structure dielectric layer and the second recessed hole substrate structure dielectric layer laterally surround the bottom electronic component; and A portion of the first recessed hole substrate structure dielectric layer is disposed vertically directly between the bottom electronic component and the top substrate structure bottom side.

14. An electronic device according to claim 13, wherein each of the top substrate structure peripheral sides is coplanar with a corresponding one of the multiple recessed hole substrate structure peripheral sides, coplanar with the corresponding peripheral side of the first recessed hole substrate structure dielectric layer, and coplanar with the corresponding peripheral side of the second recessed hole substrate structure dielectric layer.

15. The electronic device of claim 13, wherein a bottom side of the bottom electronic component is exposed from the electronic device. 16 . The electronic device according to claim 13 , wherein the second recessed hole substrate structure dielectric layer covers a bottom side of the first recessed hole substrate structure dielectric layer around a periphery of the recessed hole.

17. The electronic device according to claim 13, wherein: The top substrate structure includes a second top substrate structure conductive layer located at a bottom side of the top substrate structure; and The first recessed hole substrate structure dielectric layer laterally surrounds at least a portion of the second top substrate structure conductive layer. The electronic device of claim 13 , wherein the bottom recessed hole is exposed from the completed electronic device.

19. The electronic device of claim 13, further comprising interconnect bumps on a bottom side of the recessed hole substrate structure for connecting the electronic device to other components, wherein the interconnect bumps comprise one or more of conductive balls, solder balls, or copper balls.

20. An electronic device comprising: A substrate, comprising: a top substrate structure having a top substrate structure top side, a top substrate structure bottom side, and a plurality of top substrate structure peripheral sides, wherein the top substrate structure comprises a top substrate structure conductive layer and a top substrate structure dielectric layer; as well as A recessed hole substrate structure having a recessed hole substrate structure top side, a recessed hole substrate structure bottom side, and a plurality of recessed hole substrate structure surrounding sides, wherein the recessed hole substrate structure top side is coupled to the top substrate structure bottom side, wherein: The concave hole substrate structure comprises a concave hole substrate structure conductive layer and a concave hole substrate structure dielectric layer; and The recessed hole substrate structure includes a bottom recessed hole and a bottom recessed hole opening in a bottom side of the recessed hole substrate structure; a top electronic component having a top electronic component top side, a top electronic component bottom side coupled to the top substrate structure top side, and a plurality of top electronic component peripheral sides; a bottom electronic component having a bottom electronic component top side, a bottom electronic component bottom side, and a plurality of bottom electronic component peripheral sides, the bottom electronic component top side being coupled to a portion of the recessed hole substrate structure bottom side in the bottom recessed hole, wherein at least a portion of the bottom electronic component is disposed in the bottom recessed hole; a gap disposed laterally directly between the recessed hole substrate structure dielectric layer and a peripheral side of the bottom electronic component; as well as An encapsulation material covers at least the top substrate structure top side and the top electronic component peripheral side, the encapsulation material having an encapsulation top side, an encapsulation bottom side facing the top substrate structure top side, and a plurality of encapsulation peripheral sides. The electronic device of claim 20 , wherein the gap comprises an air gap.

22. The electronic device according to claim 20, wherein a peripheral side of the bottom electronic component is completely exposed.

23. The electronic device according to claim 20, wherein: The recessed hole substrate structure includes a second recessed hole substrate structure dielectric layer; and The recessed hole substrate structure dielectric layer and the second recessed hole substrate structure dielectric layer both laterally surround the bottom electronic component.

24. The electronic device of claim 23, wherein: The bottom recessed hole extends completely through the second recessed hole substrate structure dielectric layer; The bottom recessed hole extension portion passes through the recessed hole substrate structure dielectric layer; and A portion of the recessed hole substrate structure dielectric layer is disposed vertically directly between the bottom electronic component and the top substrate structure bottom side.

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