Semiconductor packaging structure and preparation method

Abstract

The present invention discloses a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure includes: a plastic package, at least one chip module, at least one receiving antenna module, and at least one transmitting antenna module; the chip module, the receiving antenna module, and the transmitting antenna module are located within the plastic package, and the projections of the chip module, the receiving antenna module, and the transmitting antenna module within the plastic package do not overlap and are spaced apart by a preset distance; a receiving antenna is provided on the first surface of the receiving antenna module, and a transmitting antenna is provided on the first surface of the transmitting antenna module; a first connection pad is provided on the second surface of the receiving antenna module, a second connection pad is provided on the second surface of the transmitting antenna module, and a third connection pad is provided on the surface of the chip module. The technical solution provided by the embodiments of the present invention reduces the volume and thickness of the semiconductor packaging structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] In communication devices, it is necessary to package a chip module and an antenna together to form a semiconductor packaging structure. Among them, the antenna is a device for receiving and transmitting electromagnetic wave signals and serves as a carrier for signal transmission between different chip modules.

[0003] Currently, the traditional semiconductor packaging structure includes a package body provided with a chip module and an antenna module vertically stacked on the surface of the package body. Among them, the package body includes a substrate, a chip module located on the surface of the substrate, metal posts, and a plastic encapsulation material. The antenna module is mounted on the surface of the package body and welded to the metal posts.

[0004] The defect of the traditional semiconductor packaging structure with an antenna module is that it is necessary to form metal posts with a relatively high height in the package body. The thickness of the entire semiconductor packaging structure is equal to the sum of the thickness of the substrate, the height of the metal posts, and the thickness of the antenna module, resulting in a relatively large volume and thickness of the entire semiconductor packaging structure. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a semiconductor packaging structure and a manufacturing method thereof to reduce the volume and thickness of the semiconductor packaging structure.

[0006] In a first aspect, embodiments of the present invention provide a semiconductor packaging structure, including:

[0007] A plastic encapsulation body, at least one chip module, at least one receiving antenna module, and at least one transmitting antenna module;

[0008] The chip module, the receiving antenna module, and the transmitting antenna module are located in the plastic encapsulation body. The projections of the chip module, the receiving antenna module, and the transmitting antenna module in the plastic encapsulation body do not overlap and are spaced apart by a preset distance;

[0009] At least one first opening structure and at least one second opening structure are provided on a first surface of the plastic encapsulation body. The first opening structure exposes a first surface of the receiving antenna module, and the second opening structure exposes a first surface of the transmitting antenna module;

[0010] At least one third opening structure, at least one fourth opening structure, and at least one fifth opening structure are provided on the second surface of the plastic package body. The third opening structure exposes the second surface of the receiving antenna module opposite to the first surface, the fourth opening structure exposes the second surface of the transmitting antenna module opposite to the first surface, and the fifth opening structure exposes the surface of the chip module.

[0011] A receiving antenna is provided on the first surface of the receiving antenna module, and a transmitting antenna is provided on the first surface of the transmitting antenna module. A first connection pad is provided on the second surface of the receiving antenna module, a second connection pad is provided on the second surface of the transmitting antenna module, and a third connection pad is provided on the surface of the chip module.

[0012] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor package structure, including:

[0013] Forming at least one chip module, at least one receiving antenna module, and at least one transmitting antenna module;

[0014] Forming a plastic package body; wherein, the chip module, the receiving antenna module, and the transmitting antenna module are located within the plastic package body, and the projections of the chip module, the receiving antenna module, and the transmitting antenna module within the plastic package body do not overlap and are spaced apart by a preset distance;

[0015] At least one first opening structure and at least one second opening structure are provided on the first surface of the plastic package body. The first opening structure exposes the first surface of the receiving antenna module, and the second opening structure exposes the first surface of the transmitting antenna module;

[0016] At least one third opening structure, at least one fourth opening structure, and at least one fifth opening structure are provided on the second surface of the plastic package body. The third opening structure exposes the second surface of the receiving antenna module opposite to the first surface, the fourth opening structure exposes the second surface of the transmitting antenna module opposite to the first surface, and the fifth opening structure exposes the surface of the chip module;

[0017] A receiving antenna is provided on the first surface of the receiving antenna module, and a transmitting antenna is provided on the first surface of the transmitting antenna module. A first connection pad is provided on the second surface of the receiving antenna module, a second connection pad is provided on the second surface of the transmitting antenna module, and a third connection pad is provided on the surface of the chip module.

[0018] In the technical solution provided in this embodiment, the projections of the chip module, the receiving antenna module, and the transmitting antenna module in the plastic package do not overlap and are spaced apart by a preset distance. Compared with the semiconductor package structure in which the receiving antenna module and the transmitting antenna module are vertically stacked on the chip module, the thickness and volume of the semiconductor package structure are reduced. Moreover, in the technical solution of this embodiment, the chip module, the receiving antenna module, and the transmitting antenna module are arranged in the plastic package, eliminating the need for a substrate, simplifying the film layer structure of the semiconductor package structure, improving the heat dissipation performance of the semiconductor package structure, and further reducing the thickness and volume of the semiconductor package structure, achieving miniaturization and thinning of the semiconductor package structure. And since the receiving antenna module and the transmitting antenna module are independent functional modules capable of receiving and transmitting electromagnetic wave signals, the heights of the receiving antenna module and the transmitting antenna module can be accurately controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. is a schematic structural diagram of a semiconductor package structure provided by an embodiment of the present invention;

[0020] Figure 2 is Figure 1 a top view of the plastic package in FIG.

[0021] Figure 3 is Figure 1 a bottom view of the plastic package in FIG.

[0022] Figure 4 FIG. is a schematic structural diagram of another semiconductor package structure provided by an embodiment of the present invention;

[0023] Figure 5 is Figure 4 a bottom view of the solder mask layer in FIG.

[0024] Figure 6 FIG. is a flowchart of a method for manufacturing a semiconductor package structure provided by an embodiment of the present invention;

[0025] Figure 7 is Figure 6 a schematic diagram of the process included in step S110 in FIG.

[0026] Figure 8 is Figure 6 a schematic diagram of the process included in step S120 in FIG.

[0027] Figure 9 FIG. is a schematic diagram of the process of another method for manufacturing a semiconductor package structure provided by an embodiment of the present invention;

[0028] Figures 10 - 11 FIG. is a schematic cross-sectional structure diagram corresponding to each step of a method for manufacturing a semiconductor package structure provided by an embodiment of the present invention;

[0029] Figures 12 - 24 Schematic cross-sectional structures corresponding to the steps of another method for manufacturing a semiconductor package structure provided by an embodiment of the present invention. Detailed implementation manners

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for ease of description, only parts related to the present invention rather than all structures are shown in the drawings.

[0031] An embodiment of the present invention provides a semiconductor package structure. Figure 1 Schematic structure diagram of a semiconductor package structure provided by an embodiment of the present invention. Figure 2 For Figure 1 Top view of the plastic package body. Figure 3 For Figure 1 Bottom view of the plastic package body. Refer to Figure 1 、 Figure 2 and Figure 3 , the semiconductor package structure includes: a plastic package body 10, at least one chip module 11, at least one receiving antenna module 12, and at least one transmitting antenna module 13; the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 are located inside the plastic package body 10, and the projections of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 inside the plastic package body 10 do not overlap and are spaced apart by a preset distance; at least one first opening structure 10A and at least one second opening structure 10B are provided on the first surface 100 of the plastic package body 10, the first opening structure 10A exposes the first surface 120 of the receiving antenna module 12, and the second opening structure 10B exposes the first surface 130 of the transmitting antenna module 13; at least one third opening structure 10C, at least one fourth opening structure 10D, and at least one fifth opening structure 10E are provided on the second surface 101 of the plastic package body 10, the third opening structure 10C exposes the second surface 121 of the receiving antenna module 12 opposite to the first surface 120, the fourth opening structure 10D exposes the second surface 131 of the transmitting antenna module 13 opposite to the first surface 130, and the fifth opening structure 10E exposes the surface of the chip module 11; a receiving antenna 12A is provided on the first surface 120 of the receiving antenna module 12, a transmitting antenna 13A is provided on the first surface 130 of the transmitting antenna module 13; a first connection pad 12B is provided on the second surface 121 of the receiving antenna module 12, a second connection pad 13B is provided on the second surface 131 of the transmitting antenna module 13, and a third connection pad 11A is provided on the surface of the chip module 11.

[0032] Optionally, the receiving antenna module 12 further includes a first encapsulation unit 12C, a first radio frequency circuit 12D, and a first passivation structure 12E. The first encapsulation unit 12C is configured to encapsulate the receiving antenna 12A, the first radio frequency circuit 12D, the first passivation structure 12E, and the first connection pad 12B together to form the receiving antenna module 12. The receiving antenna 12A is electrically connected through the first radio frequency circuit 12D and the first connection pad 12B. The first passivation structure 12E is used to protect the receiving antenna 12A and the first connection pad 12B from external force damage. Optionally, the transmitting antenna module 13 further includes a second encapsulation unit 13C, a second radio frequency circuit 13D, and a second passivation structure 13E. The second encapsulation unit 13C is configured to encapsulate the transmitting antenna 13A, the second radio frequency circuit 13D, the second passivation structure 13E, and the second connection pad 13B together to form the transmitting antenna module 13. The transmitting antenna 13A is electrically connected through the second radio frequency circuit 13D and the second connection pad 13B. The second passivation structure 13E is used to protect the transmitting antenna 13A and the second connection pad 13B from external force damage. Optionally, the chip module 11 further includes a substrate 11B, wherein chip units are disposed on the surface of the substrate 11B, and the third connection pad 11A is used to lead out the electrical signals of the chip units.

[0033] Specifically, the projections of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 in the plastic package 10 do not overlap and are spaced apart by a preset distance. Compared with the semiconductor package structure in which the receiving antenna module 12 and the transmitting antenna module 13 are vertically stacked on the chip module 11, the thickness and volume of the semiconductor package structure are reduced. And the technical solution in this embodiment disposes the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 in the plastic package 10, without using a substrate, simplifies the film layer structure of the semiconductor package structure, improves the heat dissipation performance of the semiconductor package structure, and further reduces the thickness and volume of the semiconductor package structure, realizing the miniaturization and thinning of the semiconductor package structure. And since the receiving antenna module 12 and the transmitting antenna module 13 are independent functional modules that can receive and transmit electromagnetic wave signals, the effect of accurately controlling the heights of the receiving antenna module 12 and the transmitting antenna module 13 can be achieved.

[0034] Figure 4 It is a schematic structural diagram of another semiconductor package structure provided by an embodiment of the present invention. Optionally, on the basis of the above technical solution, referring to Figure 4 , the semiconductor package structure further includes a redistribution layer 20. The redistribution layer 20 is located on the second surface 101 of the plastic package 10. The redistribution layer 20 is provided with a first connection end, a second connection end, and a third connection end. The first connection end is electrically connected to the first connection pad 12B, the second connection end is electrically connected to the second connection pad 13B, and the third connection end is electrically connected to the third connection pad 11A.

[0035] It should be noted that the first connection end, the second connection end, and the third connection end of the redistribution layer 20 are not shown in this embodiment. Specifically, the redistribution layer 20 is used to lead out the electrical signals of the first connection pad 12B, the second connection pad 13B, and the third connection pad 11A respectively, and thus the electrical signals of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 can be led out. The redistribution layer 20 can be a single metal layer or a stack of multiple metal layers.

[0036] Optionally, based on the above technical solution, referring to Figure 4 , the semiconductor package structure further includes an under-bump metal layer 30. The under-bump metal layer 30 is located on the surface of the redistribution layer 20 facing away from the encapsulant 10. The under-bump metal layer 30 includes a first bump 31, a second bump 32, and a third bump 33. The first bump 31 is electrically connected to the first connection end, the second bump 32 is electrically connected to the second connection end, and the third bump 33 is electrically connected to the third connection end.

[0037] Specifically, the under-bump metal layer (UBM) 30 includes a copper layer, a nickel layer, and a Cu-Ni-Sn intermetallic compound (IMC) layer between the copper layer and the nickel layer. The under-bump metal layer 30 is used to lead out the electrical signals of the first connection pad 12B, the second connection pad 13B, and the third connection pad 11A respectively, and thus the electrical signals of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 can be led out.

[0038] Figure 5 For Figure 4 the bottom view of the solder mask layer. Optionally, based on the above technical solution, referring to Figure 4 and Figure 5 , the semiconductor package structure further includes a solder mask layer 40. The solder mask layer 40 is located on the surface of the redistribution layer 20 facing away from the encapsulant 10. The solder mask layer 40 is provided with a sixth opening structure 40A, a seventh opening structure 40B, and an eighth opening structure 40C; the sixth opening structure 40A exposes the first bump 31, the seventh opening structure 40B exposes the second bump 32, and the eighth opening structure 40C exposes the third bump 33.

[0039] Specifically, the solder mask layer 40 is used to protect the under-bump metal layer 30 while providing the sixth opening structure 40A, the seventh opening structure 40B, and the eighth opening structure 40C to expose the first bump 31, the second bump 32, and the third bump 33, facilitating the formation of structures electrically connected to the first bump 31, the second bump 32, and the third bump 33.

[0040] Optionally, based on the above technical solution, referring to Figure 4, the semiconductor package structure further includes a first solder ball 51, a second solder ball 52, and a third solder ball 53. The first solder ball 51 is located on the surface of the first bump 31 away from the redistribution layer 20, the second solder ball 52 is located on the surface of the second bump 32 away from the redistribution layer 20, and the third solder ball 53 is located on the surface of the third bump 33 away from the redistribution layer 20.

[0041] Specifically, the first solder ball 51 is electrically connected to the first bump 31, the second solder ball 52 is electrically connected to the second bump 32, and the third solder ball 53 is electrically connected to the third bump 33, facilitating the extraction of the electrical signals of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13. It should be noted that the semiconductor package structure can be disposed on the surface of a printed circuit board and jointly form a circuit with other semiconductor package structures through the circuits on the surface of the printed circuit board.

[0042] An embodiment of the present invention further provides a method for manufacturing a semiconductor package structure. Figure 6 It is a flowchart of a method for manufacturing a semiconductor package structure provided by an embodiment of the present invention. Figures 10 - 11 It is a schematic cross-sectional structure diagram corresponding to each step of a method for manufacturing a semiconductor package structure provided by an embodiment of the present invention. Refer to Figure 6 , the method for manufacturing the semiconductor package structure includes the following steps:

[0043] S110, form at least one chip module, at least one receiving antenna module, and at least one transmitting antenna module.

[0044] Refer to Figure 10, at least one chip module 11, at least one receiving antenna module 12, and at least one transmitting antenna module 13 are formed. Optionally, the receiving antenna module 12 further includes a first encapsulation unit 12C, a first radio frequency circuit 12D, and a first passivation structure 12E. The first encapsulation unit 12C is configured to encapsulate the receiving antenna 12A, the first radio frequency circuit 12D, the first passivation structure 12E, and the first connection pad 12B together to form the receiving antenna module 12. The receiving antenna 12A is electrically connected through the first radio frequency circuit 12D and the first connection pad 12B. The first passivation structure 12E is used to protect the receiving antenna 12A and the first connection pad 12B from external force damage. Optionally, the transmitting antenna module 13 further includes a second encapsulation unit 13C, a second radio frequency circuit 13D, and a second passivation structure 13E. The second encapsulation unit 13C is configured to encapsulate the transmitting antenna 13A, the second radio frequency circuit 13D, the second passivation structure 13E, and the second connection pad 13B together to form the transmitting antenna module 13. The transmitting antenna 13A is electrically connected through the second radio frequency circuit 13D and the second connection pad 13B. The second passivation structure 13E is used to protect the transmitting antenna 13A and the second connection pad 13B from external force damage. Optionally, the chip module 11 further includes a substrate 11B, where a chip unit is disposed on the surface of the substrate 11B, and the third connection pad 11A is used to lead out the electrical signal of the chip unit.

[0045] S120, form a plastic package body; wherein, the chip module, the receiving antenna module, and the transmitting antenna module are located inside the plastic package body, and the projections of the chip module, the receiving antenna module, and the transmitting antenna module inside the plastic package body do not overlap and are spaced apart by a preset distance; at least one first opening structure and at least one second opening structure are disposed on the first surface of the plastic package body, the first opening structure exposes the first surface of the receiving antenna module, and the second opening structure exposes the first surface of the transmitting antenna module; at least one third opening structure, at least one fourth opening structure, and at least one fifth opening structure are disposed on the second surface of the plastic package body, the third opening structure exposes the second surface of the receiving antenna module opposite to the first surface, the fourth opening structure exposes the second surface of the transmitting antenna module opposite to the first surface, and the fifth opening structure exposes the surface of the chip module; a receiving antenna is disposed on the first surface of the receiving antenna module, and a transmitting antenna is disposed on the first surface of the transmitting antenna module; a first connection pad is disposed on the second surface of the receiving antenna module, a second connection pad is disposed on the second surface of the transmitting antenna module, and a third connection pad is disposed on the surface of the chip module.

[0046] See Figure 11 , form a plastic package body 10. Wherein, see Figure 11 Figure 2 and Figure 3, the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 are located within the plastic package 10. The projections of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 within the plastic package 10 do not overlap and are spaced apart by a preset distance. At least one first opening structure 10A and at least one second opening structure 10B are provided on the first surface 100 of the plastic package 10. The first opening structure 10A exposes the first surface 120 of the receiving antenna module 12, and the second opening structure 10B exposes the first surface 130 of the transmitting antenna module 13. At least one third opening structure 10C, at least one fourth opening structure 10D, and at least one fifth opening structure 10E are provided on the second surface 101 of the plastic package 10. The third opening structure 10C exposes the second surface 121 of the receiving antenna module 12 opposite to the first surface 120, the fourth opening structure 10D exposes the second surface 131 of the transmitting antenna module 13 opposite to the first surface 130, and the fifth opening structure 10E exposes the surface of the chip module 11. A receiving antenna 12A is provided on the first surface 120 of the receiving antenna module 12, a transmitting antenna 13A is provided on the first surface 130 of the transmitting antenna module 13. A first connection pad 12B is provided on the second surface 121 of the receiving antenna module 12, a second connection pad 13B is provided on the second surface 131 of the transmitting antenna module 13, and a third connection pad 11A is provided on the surface of the chip module 11.

[0047] In the technical solution provided in this embodiment, the projections of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 within the plastic package 10 do not overlap and are spaced apart by a preset distance. Compared with the semiconductor package structure in which the receiving antenna module 12 and the transmitting antenna module 13 are vertically stacked on the chip module 11, the thickness and volume of the semiconductor package structure are reduced. And in the technical solution of this embodiment, the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 are arranged within the plastic package 10, without using a substrate, simplifying the film layer structure of the semiconductor package structure, improving the heat dissipation performance of the semiconductor package structure while further reducing the thickness and volume of the semiconductor package structure, realizing the miniaturization and thinning of the semiconductor package structure. And since the receiving antenna module 12 and the transmitting antenna module 13 are independent functional modules that can receive and transmit electromagnetic wave signals, the effect of accurately controlling the heights of the receiving antenna module 12 and the transmitting antenna module 13 can be achieved.

[0048] Figure 7 For Figure 6 the flow diagram included in step 110 in Figure 8 For Figure 6 the flow diagram included in step 120 in Figures 12 - 24 This is the cross-sectional structure diagram corresponding to each step of another method for manufacturing a semiconductor package structure provided by an embodiment of the present invention.

[0049] Optionally, based on the above technical solution, refer to Figure 7 , step 110 of at least one chip module, at least one receiving antenna module, and at least one transmitting antenna module includes:

[0050] S1101. Provide a motherboard, the motherboard includes N receiving antenna modules and M transmitting antenna modules, where the value of N includes integers greater than or equal to 1, and the value of M includes integers greater than or equal to 1.

[0051] Refer to Figure 12 , provide motherboard 1, motherboard 1 includes N receiving antenna modules 12 and M transmitting antenna modules 13, where the value of N includes integers greater than or equal to 1, and the value of M includes integers greater than or equal to 1. Exemplarily, Figure 12 in

[0052] the value of N is 2 and the value of M is 3.

[0053] Refer to Figure 13 , cut motherboard 1 to obtain N receiving antenna modules 12 and M transmitting antenna modules 13.

[0054] S1103. Provide a substrate. Refer to Figure 14 , provide substrate 2. Exemplarily, substrate 2 can be a substrate made of semiconductor material.

[0055] S1104. Form at least one chip module, at least one receiving antenna module, and at least one transmitting antenna module on the surface of the substrate, where the projections of the chip module, the receiving antenna module, and the transmitting antenna module on the substrate do not overlap and are spaced apart by a preset distance.

[0056] Refer to Figure 15 , form at least one chip module 11, at least one receiving antenna module 12, and at least one transmitting antenna module 13 on the surface of substrate 2, where the projections of chip module 11, receiving antenna module 12, and transmitting antenna module 13 on substrate 2 do not overlap and are spaced apart by a preset distance. Substrate 2 is used to support chip module 11, receiving antenna module 12, and transmitting antenna module 13. Exemplarily, Figure 15 shows 2 chip modules 11, 2 receiving antenna modules 12, and 2 transmitting antenna modules 13.

[0057] Refer to Figure 8 , S120 for forming the encapsulant includes: S1201. Form an encapsulant on the surface of at least one chip module, at least one receiving antenna module, and at least one transmitting antenna module that faces away from the substrate. Refer to Figure 16, a plastic package body 10 is formed on the surfaces of at least one chip module 11, at least one receiving antenna module 12, and at least one transmitting antenna module 13 facing away from the substrate 2.

[0058] S1202. Remove the substrate. Refer to Figure 17 , remove the substrate 2. The function of the substrate 2 is to support the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13. Since after the plastic package body 10 is formed, the plastic package body 10 can play the role of fixing and supporting the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13, the substrate 2 can be removed.

[0059] Figure 9 is a schematic flowchart of a preparation method for another semiconductor package structure provided by an embodiment of the present invention. Optionally, on the basis of the above technical solution, refer to Figure 9 , after forming the plastic package body in S120, it further includes: S130. Form a redistribution layer, where the redistribution layer is located on the second surface of the plastic package body, and the redistribution layer is provided with a first connection end, a second connection end, and a third connection end. The first connection end is electrically connected to the first connection pad, the second connection end is electrically connected to the second connection pad, and the third connection end is electrically connected to the third connection pad.

[0060] Refer to Figure 18 , form a redistribution layer 20, where the redistribution layer 20 is located on the second surface 101 of the plastic package body 10, and the redistribution layer 20 is provided with a first connection end, a second connection end, and a third connection end. The first connection end is electrically connected to the first connection pad 12B, the second connection end is electrically connected to the second connection pad 13B, and the third connection end is electrically connected to the third connection pad 11A. It should be noted that the first connection end, the second connection end, and the third connection end of the redistribution layer 20 are not shown in this embodiment. Specifically, the redistribution layer 20 is used to lead out the electrical signals of the first connection pad 12B, the second connection pad 13B, and the third connection pad 11A respectively, and thus the electrical signals of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 can be led out. Exemplarily, the redistribution layer 20 can be a layer of metal formed by a sputtering process or a stack of multiple metal layers.

[0061] Optionally, on the basis of the above technical solution, refer to Figure 9 , after forming the redistribution layer in S130, it further includes: S140. Form an under-bump metal layer, where the under-bump metal layer is located on the surface of the redistribution layer facing away from the plastic package body, and the under-bump metal layer includes a first bump, a second bump, and a third bump. The first bump is electrically connected to the first connection end, the second bump is electrically connected to the second connection end, and the third bump is electrically connected to the third connection end.

[0062] Refer to Figure 19, a metal layer 30 under the bump is formed. Among them, the metal layer 30 under the bump is located on the surface of the redistribution layer 20 on the side away from the encapsulant 10. The metal layer 30 under the bump includes a first bump 31, a second bump 32, and a third bump 33. The first bump 31 is electrically connected to the first connection end, the second bump 32 is electrically connected to the second connection end, and the third bump 33 is electrically connected to the third connection end. The metal layer 30 under the bump is used to lead out the electrical signals of the first connection pad 12B, the second connection pad 13B, and the third connection pad 11A respectively, and thus the electrical signals of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13 can be led out.

[0063] Optionally, on the basis of the above technical solution, referring to Figure 9 , after forming the metal layer 30 under the bump in S140, it further includes: S150, forming a solder mask layer. The solder mask layer is located on the surface of the redistribution layer on the side away from the encapsulant. The solder mask layer is provided with a sixth opening structure, a seventh opening structure, and an eighth opening structure; the sixth opening structure exposes the first bump, the seventh opening structure exposes the second bump, and the eighth opening structure exposes the third bump.

[0064] Referring to Figure 20 and Figure 5 , a solder mask layer 40 is formed. The solder mask layer 40 is located on the surface of the redistribution layer 20 on the side away from the encapsulant 10. The solder mask layer 40 is provided with a sixth opening structure 40A, a seventh opening structure 40B, and an eighth opening structure 40C; the sixth opening structure 40A exposes the first bump 31, the seventh opening structure 40B exposes the second bump 32, and the eighth opening structure 40C exposes the third bump 33. Specifically, while protecting the metal layer 30 under the bump, the solder mask layer 40 is provided with the sixth opening structure 40A, the seventh opening structure 40B, and the eighth opening structure 40C to expose the first bump 31, the second bump 32, and the third bump 33, facilitating the formation of a structure electrically connected to the first bump 31, the second bump 32, and the third bump 33. Optionally, the sixth opening structure 40A, the seventh opening structure 40B, and the eighth opening structure 40C can be formed in the solder mask layer 40 through a patterning process.

[0065] Optionally, on the basis of the above technical solution, referring to Figure 9 , after forming the solder mask layer in S150, it further includes: S160, forming a protective layer on the first surface of the encapsulant. Referring to Figure 21 , a protective layer 60 is formed on the first surface 100 of the encapsulant 10. The protective layer 60 is used to play a supporting role in the subsequent process of forming solder balls.

[0066] S170. Form a first solder ball, a second solder ball, and a third solder ball on the second surface of the plastic package body. The first solder ball is located on the surface of the first bump away from the redistribution layer, the second solder ball is located on the surface of the second bump away from the redistribution layer, and the third solder ball is located on the surface of the third bump away from the redistribution layer.

[0067] Refer to Figure 22 , form a first solder ball 51, a second solder ball 52, and a third solder ball 53 on the second surface 101 of the plastic package body 10. The first solder ball 51 is located on the surface of the first bump 31 away from the redistribution layer 20, the second solder ball 52 is located on the surface of the second bump 32 away from the redistribution layer 20, and the third solder ball 53 is located on the surface of the third bump 33 away from the redistribution layer 20. Specifically, the first solder ball 51 is electrically connected to the first bump 31, the second solder ball 52 is electrically connected to the second bump 32, and the third solder ball 53 is electrically connected to the third bump 33, facilitating the extraction of the electrical signals of the chip module 11, the receiving antenna module 12, and the transmitting antenna module 13. It should be noted that this semiconductor package structure can be disposed on the surface of a printed circuit board, and together with the circuits on the surface of the printed circuit board, it forms a circuit with other semiconductor package structures.

[0068] S180. Cut the scribe lines located on the second surface of the plastic package body. Refer to Figure 23 , cut the scribe lines located on the second surface 101 of the plastic package body 10. During the cutting process, the protective layer 60 plays a supporting role for the semiconductor package structure.

[0069] S190. Remove the protective layer. Refer to Figure 24 , remove the protective layer 60. Exemplarily, the protective layer 60 can be selected as a photosensitive material. During the removal process, under the irradiation of light with a preset wavelength, the bonding effect between the protective layer 60 and the plastic package body 10 is reduced, facilitating the rapid removal of the protective layer 60 while not damaging the film layer of the semiconductor package structure.

[0070] Note that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, it can also include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor package structure, characterized in that, it includes: a plastic package, at least one chip module, at least one receiving antenna module, and at least one transmitting antenna module; the chip module, the receiving antenna module, and the transmitting antenna module are located within the plastic package, and the projections of the chip module, the receiving antenna module, and the transmitting antenna module within the plastic package do not overlap and are spaced apart by a preset distance; at least one first opening structure and at least one second opening structure are provided on a first surface of the plastic package, the first opening structure exposes a first surface of the receiving antenna module, and the second opening structure exposes a first surface of the transmitting antenna module; at least one third opening structure, at least one fourth opening structure, and at least one fifth opening structure are provided on a second surface of the plastic package, the third opening structure exposes a second surface of the receiving antenna module opposite to the first surface, the fourth opening structure exposes a second surface of the transmitting antenna module opposite to the first surface, and the fifth opening structure exposes a surface of the chip module; a receiving antenna is provided on a first surface of the receiving antenna module, and a transmitting antenna is provided on a first surface of the transmitting antenna module; a first connection pad is provided on a second surface of the receiving antenna module, a second connection pad is provided on a second surface of the transmitting antenna module, and a third connection pad is provided on a surface of the chip module; the receiving antenna module includes a first encapsulation unit, a first radio frequency circuit, and a first passivation structure, the first encapsulation unit is used to encapsulate the receiving antenna, the first radio frequency circuit, the first passivation structure, and the first connection pad together to form the receiving antenna module, the receiving antenna is electrically connected through the first radio frequency circuit and the first connection pad, and the first passivation structure is used to protect the receiving antenna and the first connection pad; the transmitting antenna module includes a second encapsulation unit, a second radio frequency circuit, and a second passivation structure, the second encapsulation unit is used to encapsulate the transmitting antenna, the second radio frequency circuit, the second passivation structure, and the second connection pad together to form the transmitting antenna module, the transmitting antenna is electrically connected through the second radio frequency circuit and the second connection pad, and the second passivation structure is used to protect the transmitting antenna and the second connection pad.

2. The semiconductor package structure according to claim 1, characterized in that, it further includes a redistribution layer, the redistribution layer is located on the second surface of the plastic package, and the redistribution layer is provided with a first connection end, a second connection end, and a third connection end, the first connection end is electrically connected to the first connection pad, the second connection end is electrically connected to the second connection pad, and the third connection end is electrically connected to the third connection pad.

3. The semiconductor package structure according to claim 2, characterized in that, It also includes an under-bump metal layer, which is located on the surface of the redistribution layer away from the plastic package body. The under-bump metal layer includes a first bump, a second bump and a third bump. The first bump is electrically connected to the first connection end, the second bump is electrically connected to the second connection end, and the third bump is electrically connected to the third connection end.

4. The semiconductor package structure according to claim 3, It is characterized in that It also includes a first solder ball, a second solder ball and a third solder ball. The first solder ball is located on the surface of the first bump away from the redistribution layer, the second solder ball is located on the surface of the second bump away from the redistribution layer, and the third solder ball is located on the surface of the third bump away from the redistribution layer.

5. A method for preparing a semiconductor packaging structure, It is characterized in that include: forming at least one chip module, at least one receiving antenna module and at least one transmitting antenna module; Forming a plastic package; wherein the chip module, the receiving antenna module and the transmitting antenna module are located in the plastic package, and the projections of the chip module, the receiving antenna module and the transmitting antenna module in the plastic package do not overlap and are spaced by a preset distance; The first surface of the plastic package body is provided with at least one first opening structure and at least one second opening structure, the first opening structure exposes the first surface of the receiving antenna module, and the second opening structure exposes the first surface of the transmitting antenna module; The second surface of the plastic package body is provided with at least one third opening structure, at least one fourth opening structure and at least one fifth opening structure, the third opening structure exposes the second surface of the receiving antenna module opposite to the first surface, the fourth opening structure exposes the second surface of the transmitting antenna module opposite to the first surface, and the fifth opening structure exposes the surface of the chip module; The first surface of the receiving antenna module is provided with a receiving antenna, and the first surface of the transmitting antenna module is provided with a transmitting antenna; the second surface of the receiving antenna module is provided with a first connecting pad, the second surface of the transmitting antenna module is provided with a second connecting pad, and the surface of the chip module is provided with a third connecting pad; The receiving antenna module includes a first packaging unit, a first radio frequency circuit and a first passivation structure, wherein the first packaging unit is used to package the receiving antenna, the first radio frequency circuit, the first passivation structure and the first connection pad together to form the receiving antenna module, the receiving antenna is electrically connected to the first connection pad through the first radio frequency circuit, and the first passivation structure is used to protect the receiving antenna and the first connection pad; The transmitting antenna module includes a second encapsulation unit, a second radio frequency circuit, and a second passivation structure. The second encapsulation unit is configured to encapsulate the transmitting antenna, the second radio frequency circuit, the second passivation structure, and the second connection pad together to form the transmitting antenna module. The transmitting antenna is electrically connected through the second radio frequency circuit and the second connection pad. The second passivation structure is used to protect the transmitting antenna and the second connection pad.

6. The method for manufacturing a semiconductor package structure according to claim 5, wherein, forming at least one chip module, at least one receiving antenna module, and at least one transmitting antenna module includes: providing a mother board, the mother board including N receiving antenna modules and M transmitting antenna modules, where the value of N includes an integer greater than or equal to 1, and the value of M includes an integer greater than or equal to 1; dicing the mother board to obtain N receiving antenna modules and M transmitting antenna modules; providing a substrate; forming at least one chip module, at least one of the receiving antenna modules, and at least one of the transmitting antenna modules on the surface of the substrate, wherein the projections of the chip module, the receiving antenna module, and the transmitting antenna module on the substrate do not overlap and are spaced apart by a preset distance; forming a molding compound includes: forming a molding compound on the surfaces of at least one of the chip modules, at least one of the receiving antenna modules, and at least one of the transmitting antenna modules facing away from the substrate; removing the substrate.

7. The method for manufacturing a semiconductor package structure according to claim 5, wherein, after forming the molding compound, further includes: forming a redistribution layer, wherein the redistribution layer is located on the second surface of the molding compound, and the redistribution layer is provided with a first connection end, a second connection end, and a third connection end. The first connection end is electrically connected to the first connection pad, the second connection end is electrically connected to the second connection pad, and the third connection end is electrically connected to the third connection pad.

8. The method for manufacturing a semiconductor package structure according to claim 7, wherein, after forming the redistribution layer, further includes: forming an under-bump metal layer, wherein the under-bump metal layer is located on the surface of the redistribution layer facing away from the molding compound, and the under-bump metal layer includes a first bump, a second bump, and a third bump. The first bump is electrically connected to the first connection end, the second bump is electrically connected to the second connection end, and the third bump is electrically connected to the third connection end.

9. The method for manufacturing a semiconductor package structure according to claim 8, wherein, after forming the under-bump metal layer, further includes: forming a solder mask layer, wherein the solder mask layer is located on the surface of the redistribution layer facing away from the molding compound, and the solder mask layer is provided with a sixth opening structure, a seventh opening structure, and an eighth opening structure; the sixth opening structure exposes the first bump, the seventh opening structure exposes the second bump, and the eighth opening structure exposes the third bump.

10. The method for manufacturing a semiconductor package structure according to claim 9, wherein, after forming the solder mask layer, further includes: Form a protective layer on the first surface of the encapsulant body; Form a first solder ball, a second solder ball, and a third solder ball on the second surface of the encapsulant body, where the first solder ball is located on the surface of the first bump away from the redistribution layer, the second solder ball is located on the surface of the second bump away from the redistribution layer, and the third solder ball is located on the surface of the third bump away from the redistribution layer; Cut the scribe line located on the second surface of the encapsulant body; Remove the protective layer.

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