Storage device, storage system, and method for operating a storage device

Abstract

Disclosed are a storage device, a storage system, and a method for operating the storage device. The storage device includes: an interface circuit that exchanges data with a host device; and a power management unit that supplies power to the interface circuit. The interface circuit includes: a first input terminal that receives a first signal from the host device; a second input terminal that receives a second signal complementary to the first signal from the host device; a receiving module that processes the first signal and the second signal; a squelch circuit that detects a level of the first signal and a level of the second signal; and a reference clock detector that detects whether a reference clock for operating the storage device is received. The power management unit selectively supplies power to the squelch circuit based on the detection result of the reference clock detector.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0003793 filed on January 10, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure described herein relate to a memory device. For example, at least some example embodiments relate to a memory device configured to change a power state based on a reference clock received from a host device. Background Art

[0004] Among semiconductor memory devices, examples of nonvolatile memory devices that retain data stored therein even if power is cut off are flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. In order to improve the performance of semiconductor memories, various attempts have been made to improve the performance of an interface between a memory device and a host device. As an example of the attempt, a universal flash storage (UFS) protocol for a memory device or a mobile device requiring low power consumption is adopted.

[0005] In addition to adopting protocols such as UFS, research and development is continuously being conducted to further reduce the power consumption of electronic devices, especially in idle mode. Generally, the switching of the power state of the UFS storage device can be triggered based on the result of a level change of a signal input to an input terminal of the UFS storage device detected at a squelch circuit. However, even when the UFS storage device is in an idle state, the squelch circuit may need to be powered on to perform the detection of the level change, resulting in unnecessary power consumption. Summary of the invention

[0006] Embodiments of the present disclosure relate to a storage device.

[0007] In some example embodiments, the storage device includes an interface circuit and a power manager. The interface circuit may be configured to exchange data with a host device, the interface circuit including: a first input terminal configured to receive a first signal from the host device; a second input terminal configured to receive a second signal from the host device, the second signal being complementary to the first signal; a squelch circuit configured to detect a level of the first signal and a level of the second signal; and a reference clock detector configured to detect reception of a reference clock from the host device. The power manager may be configured to supply power to the interface circuit, such that the power manager selectively supplies the power to the squelch circuit based on whether the reference clock detector detects the reception of the reference clock from the host device.

[0008] Some example embodiments of the inventive concepts relate to a storage system.

[0009] In some example embodiments, the storage system includes a host device and a storage device. The host device may have a first interface circuit, the first interface circuit including a transmission channel configured to transmit a first signal and a second signal, the second signal being complementary to the first signal. The storage device may have a second interface circuit, the second interface circuit including: a receiving channel configured to receive the first signal and the second signal; a squelch circuit configured to detect a level of the first signal and a level of the second signal; and a reference clock detector configured to detect reception of a reference clock from the host device. In some example embodiments, an operation mode of the storage device changes between an active mode and an idle mode based on whether the reference clock detector detects the reception of the reference clock from the host device.

[0010] Some example embodiments relate to a method of operating a storage device, the storage device including an interface circuit having a receiving channel and a squelch circuit, the receiving channel being configured to receive a first signal and a second signal from a host device, the squelch circuit being configured to detect a level of the first signal and a level of the second signal, the second signal being complementary to the first signal.

[0011] In some example embodiments, the method includes: detecting, by a reference clock detector, reception of a reference clock from the host device; and selectively supplying, by a power manager, power to the squelch circuit based on whether the reference clock detector detects the reception of the reference clock from the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of exemplary embodiments of the present disclosure will become readily understood by describing in detail some exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0013] Figure 1 A system to which a storage device according to an example embodiment of the present disclosure is applied is shown.

[0014] Figure 2 A configuration of a UFS system according to an embodiment of the present disclosure is shown.

[0015] Figure 3 Shown in Figure 2 Signals exchanged between the UIC layer of the UFS host and the UIC layer of the UFS device in the UFS system.

[0016] Figure 4 Shows that compliance can be applied to Figure 2 and Figure 3 The layer structure of the storage system interface protocol.

[0017] Figure 5 Shows Figures 2 to 4 The operating method of the UFS device.

[0018] Figure 6 Shows Figures 2 to 4 The operating method of the UFS device.

[0019] Fig. 7A and Figure 7B Shows Figures 2 to 4 The state machine of the UIC layer.

[0020] Fig. 8A and Figure 8B Shows Figures 2 to 4 The state machine of the UIC layer.

[0021] Fig. 9 and Fig.10 An example configuration of a UFS device according to an embodiment of the present disclosure is shown.

[0022] Fig.11 Waveforms of signals associated with a storage device according to an example embodiment of the present disclosure are shown.

[0023] Fig.12 An operating method of a UFS system according to an example embodiment of the present disclosure is illustrated.

[0024] Fig.13 An operating method of a UFS system according to an example embodiment of the present disclosure is illustrated.

[0025] Fig.14A storage system according to an example embodiment of the present disclosure is shown.

[0026] Fig.15 is a block diagram illustrating a storage system according to an example embodiment of the present disclosure.

[0027] Fig.16 Shows Fig.15 An example configuration of a storage device.

[0028] Fig.17 is a diagram for describing a 3D V-NAND structure applicable to a UFS device according to example embodiments of the present disclosure.

[0029] Fig.18 is a diagram for describing a 3D V-NAND structure applicable to a UFS device according to example embodiments of the present disclosure. DETAILED DESCRIPTION

[0030] Below, embodiments of the present disclosure may be described in detail and clearly to such an extent that a person having ordinary skill in the art can easily implement the present disclosure.

[0031] The components described with reference to the terms "unit", "module", "block", "device or part" in the detailed description and the functional blocks shown in the drawings will be implemented in software, hardware or a combination thereof. For example, the software may be machine code, firmware, embedded code and application software. For example, the hardware may include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), passive components or a combination thereof.

[0032] Figure 1 A system to which a storage device according to an embodiment of the present disclosure is applied is shown. Figure 1 The system 1000 may be a mobile system, such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a medical device, or an Internet of Things (IoT) device. However, Figure 1 The system 1000 is not limited to a mobile system. For example, the system 1000 may be a personal computer, a laptop computer, a server, an automotive device such as a media player or a navigation system, etc.

[0033] Reference Figure 1 , the system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b. The system 1000 may also include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0034] The main processor 1100 may control the overall operation of the system 1000, and in detail, may control the operations of the remaining components of the system 1000. For example, the main processor 1100 may be implemented with a general-purpose processor, a dedicated processor, an application processor, and the like.

[0035] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. In an example embodiment, the main processor 1100 may also include an accelerator block 1130, which is a dedicated circuit for high-speed data calculations such as artificial intelligence (AI) data calculations. The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented with a separate chip that is physically independent of any other components of the main processor 1100.

[0036] Memories 1200a and 1200b may be used as main storage devices of system 1000, and may include volatile memories, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM). However, memories 1200a and 1200b may include non-volatile memories, such as flash memory, phase change RAM (PRAM) and / or resistive RAM (RRAM). Memories 1200a and 1200b may be implemented in the same package as main processor 1100.

[0037] The storage devices 1300a and 1300b may be used as non-volatile storage devices that can store data regardless of whether they are powered on, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage device 1300a may include a storage controller 1310a and a non-volatile storage (NVM) memory 1320a that stores data under the control of the storage controller 1310a, and the storage device 1300b may include a storage controller 1310b and a non-volatile storage (NVM) memory 1320b that stores data under the control of the storage controller 1310b. The non-volatile storage memories 1320a and 1320b may each include a flash memory of a two-dimensional (2D) structure or a V-NAND flash memory of a three-dimensional structure, or may include different types of non-volatile memories, such as PRAM or RRAM.

[0038] The storage devices 1300a and 1300b may be included in the system 1000 in a state physically separated from the main processor 1100, or may be implemented in the same package as the main processor 1100. Alternatively, the storage devices 1300a and 1300b may be implemented in the form of a solid state drive (SSD) or a memory card. In this case, the storage devices 1300a and 1300b may be removably connected to any other component of the system 1000 via an interface (such as a connection interface 1480) to be described later. The storage devices 1300a and 1300b may include, but are not limited to, devices to which standards such as Universal Flash Storage (UFS) are applied.

[0039] The image capture device 1410 may capture still images or moving images and may include a camera, a camcorder, and / or a webcam.

[0040] The user input device 1420 may receive various types of data input by a user of the system 1000 and may include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0041] The sensor 1430 may detect various types of physical quantities that can be obtained from the outside of the system 1000, and may convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0042] The communication device 1440 may transmit and receive signals to and from external devices of the system 1000 according to various communication protocols. The communication device 1440 may be implemented to include an antenna, a transceiver, and / or a modem.

[0043] Display 1450 and speaker 1460 may be used as output devices for outputting visual information and auditory information, respectively, to a user of system 1000 .

[0044] The power supply device 1470 may appropriately convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source to supply to each component of the system 1000 .

[0045] When an external device capable of exchanging data with the system 1000 is connected to the system 1000, the connection interface 1480 may provide a connection between the system 1000 and the external device. The connection interface 1480 may be implemented with various interfaces such as an ATA (Advanced Technology Attachment) interface, a SATA (Serial ATA) interface, an e-SATA (External SATA) interface, a SCSI (Small Computer Small Form Factor Interface) interface, a SAS (Serial Attached SCSI) interface, a PCI (Peripheral Component Interconnect) interface, a PCIe (PCI express) interface, an NVMe (NVM express) interface, an IEEE 1394 interface, a USB (Universal Serial Bus) interface, an SD (Secure Digital) card interface, an MMC (Multimedia Card) interface, an eMMC (Embedded Multimedia Card) interface, a UFS (Universal Flash Memory) interface, an eUFS (Embedded Universal Flash Memory) interface, and a CF (Compact Flash) card interface.

[0046] Figure 2 2 shows a configuration of a UFS system 2000 according to an exemplary embodiment of the present disclosure. The UFS system 2000, which is a system conforming to the UFS standard issued by JEDEC (Joint Electron Device Engineering Council), may include a UFS host 2100, a UFS device 2200, and a UFS interface 2300. Figure 2 The description given contradicts, otherwise Figure 1 The above description associated with the system 1000 may be applied to Figure 2 UFS system 2000.

[0047] Reference Figure 2 , the UFS host 2100 and the UFS device 2200 may be interconnected through a UFS interface 2300. Figure 1 In the case where the main processor 1100 is an application processor, the UFS host 2100 may be implemented as a part of the application processor. The UFS host controller 2110 and the host memory 2140 may correspond to Figure 1 The UFS device 2200 may correspond to the controller 1120 of the main processor 1100 and the memories 1200a and 1200b. Figure 1 The storage devices 1300a and 1300b, and the UFS device controller 2210 and the non-volatile storage memory 2220 may correspond to Figure 1 The memory controllers 1310a and 1310b and the non-volatile storage memories 1320a and 1320b.

[0048] The UFS host 2100 may include a UFS host controller 2110, an application 2120, a UFS driver 2130, a host memory 2140, and a UFS interconnect (UIC) layer 2150. The UFS device 2200 may include a UFS device controller 2210, a nonvolatile storage memory 2220, a memory interface 2230, a device memory 2240, a UIC layer 2250, and a regulator 2260. The nonvolatile storage memory 2220 may be composed of a plurality of storage components 2221, and each storage component 2221 may include a flash memory of a two-dimensional (2D) structure or a V-NAND flash memory of a three-dimensional structure, or may include different kinds of nonvolatile memories, such as PRAM or RRAM. The UFS device controller 2210 and the nonvolatile storage memory 2220 may be interconnected through a memory interface 2230. The memory interface 2230 may be implemented to comply with a standard such as Toggle or ONFI (Open NAND Flash Interface).

[0049] The application 2120 may represent a program that wants to communicate with the UFS device 2200 to use the functions of the UFS device 2200. For input / output associated with the UFS device 2200, the application 2120 may transmit an input-output request IOR to the UFS driver 2130. The input-output request IOR may represent, but is not limited to, a request to read data, a request to write data, and / or a request to discard data.

[0050] The UFS driver 2130 may manage the UFS host controller 2110 through a UFS-HCI (Host Controller Interface). The UFS driver 2130 may convert an input-output request generated by the application 2120 into a UFS command defined by the UFS standard, and may transmit the UFS command to the UFS host controller 2110. One input-output request may be converted into a plurality of UFS commands. The UFS command may be basically a command defined by the SCSI standard, but may also be a command dedicated to the UFS standard.

[0051] The UFS host controller 2110 may transfer the UFS command converted by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 through the UIC layer 2150 and the UFS interface 2300. In this process, the UFS host register 2111 of the UFS host controller 2110 may perform the role of a command queue (CQ).

[0052] The UIC layer 2150 of the UFS host 2100 may include a MIPI M-PHY 2151 and a MIPI UniPro 2152 , and the UIC layer 2250 of the UFS device 2200 may also include a MIPI M-PHY 2251 and a MIPI UniPro 2252 .

[0053] The UFS interface 2300 may include a line transmitting a reference clock REF_CLK, a line transmitting a hardware reset signal RESET_n for the UFS device 2200 , a pair of lines transmitting a differential input signal pair DIN_t and DIN_c, and a pair of lines transmitting a differential output signal pair DOUT_t and DOUT_c.

[0054] The frequency value of the reference clock provided from the UFS host 2100 to the UFS device 2200 may be, but is not limited to, one of the following frequency values: 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz. The UFS host 2100 may change the frequency value of the reference clock even in operation, that is, even when data is exchanged between the UFS host 2100 and the UFS device 2200. The UFS device 2200 may generate clocks of various frequencies from the reference clock provided by the UFS host 2100 by using a phase-locked loop (PLL) or the like. Moreover, the UFS host 2100 may set the value of the data rate between the UFS host 2100 and the UFS device 2200 by the frequency value of the reference clock. That is, the value of the data rate may be determined according to the frequency value of the reference clock.

[0055] The UFS interface 2300 may support multiple channels, and each channel may be implemented with a differential pair. For example, the UFS interface 2300 may include one or more receiving channels and one or more transmitting channels. Figure 2 In , a pair of lines that transmit a differential input signal pair DIN_T and DIN_C may constitute a receiving channel, and a pair of lines that transmit a differential output signal pair DOUT_T and DOUT_C ​​may constitute a transmitting channel. Figure 2 One transmission channel and one reception channel are shown in FIG. 1 , but the number of transmission channels and reception channels may vary.

[0056] The receiving channel and the transmitting channel may allow data transmission in a serial communication manner, and the structure in which the receiving channel and the transmitting channel are separated from each other enables the UFS host 2100 and the UFS device 2200 to communicate with each other in a full-duplex manner. That is, while the UFS device 2200 receives data from the UFS host 2100 through the receiving channel, the UFS device 2200 may transmit data to the UFS host 2100 through the transmitting channel. Moreover, control data (such as commands) from the UFS host 2100 to the UFS device 2200 and user data that the UFS host 2100 wants to write into or read from the non-volatile storage memory 2220 of the UFS device 2200 may be transmitted through the same channel. In this way, in addition to one receiving channel and one transmitting channel, a separate channel for data transmission may be provided between the UFS host 2100 and the UFS device 2200.

[0057] The UFS device controller 2210 of the UFS device 2200 may generally control the operation of the UFS device 2200. The UFS device controller 2210 may manage the nonvolatile storage memory 2220 through a logical unit (LU) 2211 as a logical data storage component. The number of LUs 2211 may be, but is not limited to, "8". The UFS device controller 2210 may include a flash translation layer (FTL), and may convert a logical data address (i.e., a logical block address (LBA)) transmitted from the UFS host 2100 into a physical data address (e.g., a physical block address (PBA)) by using address mapping information of the FTL. In the UFS system 2000, a logical block for storing user data may have a size of a given range. For example, the minimum size of a logical block may be set to 4 kilobytes.

[0058] When a command from the UFS host 2100 is input to the UFS device 2200 through the UIC layer 2250 , the UFS device controller 2210 may perform an operation corresponding to the input command; when the operation is completed, the UFS device controller 2210 may transmit a completion response to the UFS host 2100 .

[0059] In an example embodiment, when the UFS host 2100 wants to write user data in the UFS device 2200, the UFS host 2100 may transmit a data write command to the UFS device 2200. When receiving a response indicating that the transmission is ready from the UFS device 2200, the UFS host 2100 may transmit the user data to the UFS device 2200. The UFS device controller 2210 may temporarily store the received user data in the device memory 2240, and may store the user data temporarily stored in the device memory 2240 at a selected location of the nonvolatile storage memory 2220 based on the address mapping information of the FTL.

[0060] In an example embodiment, when the UFS host 2100 wants to read user data stored in the UFS device 2200, the UFS host 2100 may transmit a data read command to the UFS device 2200. The UFS device controller 2210 may read the user data from the nonvolatile storage memory 2220 based on the data read command, and may temporarily store the read user data in the device memory 2240. In this reading process, the UFS device controller 2210 may detect and correct errors of the read user data by using an embedded error correction code (ECC) engine (not shown). The UFS device controller 2210 may transmit the user data temporarily stored in the device memory 2240 to the UFS host 2100. The UFS device controller 2210 may further include an advanced encryption standard (AES) engine (not shown). The AES engine may perform at least one of an encryption operation and a decryption operation on input data by using a symmetric key algorithm.

[0061] The UFS host 2100 may store the commands to be transmitted to the UFS device 2200 in the UFS host register 2111 capable of serving as a command queue according to the order, and may send the commands to the UFS device 2200 according to the order. In this case, even if the UFS device 2200 is still processing the previously sent command, that is, even before receiving a notification indicating that the UFS device 2200 has completely processed the previously sent command, the UFS host 2100 may send the next command queued in the command queue to the UFS device 2200, and thus, even while processing the previously sent command, the UFS device 2200 may receive the next command from the UFS host 2100. The maximum number of commands that can be stored in the command queue (that is, the queue depth) may be, for example, 32. The command queue may be implemented in the type of a circular queue in which the start and end of the commands queued therein are indicated by a head pointer and a tail pointer, respectively.

[0062] Each of the plurality of storage units 2221 may include a storage cell array (not shown) and a control circuit (not shown) for controlling the operation of the storage cell array. The storage cell array may include a two-dimensional storage cell array or a three-dimensional storage cell array. The storage cell array may include a plurality of storage cells, and each storage cell may be a single level cell (SLC) storing 1 bit of information, or may be a cell storing two or more bits of information, such as a multi-level cell (MLC), a triple level cell (TLC), or a quadruple level cell (QLC). The three-dimensional storage cell array may include a vertical NAND string oriented vertically such that at least one storage cell is disposed above another storage cell.

[0063] As power supply voltages, VCC, VCCQ1, VCCQ2, etc. may be input to the UFS device 2200. The power supply voltage VCC as the main power supply voltage of the UFS device 2200 may have a value of 2.4V to 3.6V. The power supply voltage VCCQ1 as a power supply voltage for supplying a low range voltage may be mainly used for the UFS device controller 2210 and may have a value of 1.14V to 1.26V. The power supply voltage VCCQ2 as a power supply voltage for supplying a high range voltage less than the power supply voltage VCC but compared to the power supply voltage VCCQ1 may have a value of 1.7V to 1.95V. The power supply voltages VCC, VCCQ1, and VCCQ2 may be supplied to the components of the UFS device 2200 by the regulator 2260. The regulator 2260 may be implemented with a group of unit regulators, each of which is connected to a different one of the above-mentioned power supply voltages.

[0064] The regulator 2260 may manage the power supply voltage provided to the components of the UFS device 2200. In an embodiment, the regulator 2260 may be implemented separately from a power management integrated circuit (PMIC) (not shown), or may be implemented as part of a power management integrated circuit. The regulator 2260 may block the power supply voltage supplied to some components of the UFS device 2200 according to the operating mode. The regulator 2260 may selectively apply the power supply voltage to a squelch circuit that detects that the UFS device 2200 switches from an idle mode to an active mode. For example, in the idle mode of the UFS device 2200, the regulator 2260 may block the power supply voltage from being supplied to the squelch circuit.

[0065] The UFS device 2200 may receive a reference clock REF_CLK from outside the UFS device 2200 (eg, from the UFS host 2100), and may be used to operate the UFS device 2200. For example, a phase-locked loop (not shown) included in at least one of various components constituting the UFS device 2200 may generate a clock based on the reference clock REF_CLK to operate the UFS device 2200.

[0066] Meanwhile, in the case where the UFS device 2200 enters the idle mode, the UFS host 2100 may not provide the reference clock REF_CLK to the UFS device 2200. The UIC layer 2250 may detect that the reference clock REF_CLK is not provided. The UIC layer 2250 may generate a trigger signal for causing the UFS device 2200 to enter the idle mode based on the detection result. As discussed below, in an example embodiment, the regulator 2260 may block the power supply voltage applied to at least some components of the UFS device 2200. In particular, the regulator 2260 may block the power supply voltage applied to the squelch circuit of the UIC layer 2250.

[0067] In addition, as discussed below in an example embodiment, in the case where the UFS device 2200 enters the active mode from the idle mode, the UFS host 2100 may provide the reference clock REF_CLK to the UFS device 2200, and the UIC layer 2250 may detect the reference clock REF_CLK. The UIC layer 2250 may generate a trigger signal for causing the UFS device 2200 to enter the active mode based on the detection result. The regulator 2260 may apply the power supply voltage to the components of the UFS device 2200 (e.g., the muting circuit of the UIC layer 2250, the UFS device controller 2210, and the non-volatile storage memory 2220) again.

[0068] Conventionally, the squelch circuit of the UIC layer 2250 may be powered on regardless of whether the UFS device 2200 enters the idle mode, so that the squelch circuit detects a level change of a signal input to an input terminal of the storage device. However, such a configuration may make it difficult to manage power in the idle mode. In contrast, according to one or more example embodiments, the squelch circuit may be powered off in the idle mode, and a mode switch between the idle mode and the active mode may be performed based on detecting whether the reference clock REF_CLK is supplied or blocked. Therefore, the power consumption of the UFS device 2200 in the idle mode may be efficiently managed.

[0069] Figure 3 Shown in Figure 2 Signals exchanged between the UIC layer 2150 of the UFS host 2100 and the UIC layer 2250 of the UFS device 2200 in the UFS system 2000 .

[0070] The physical layer (M-PHY) 2151 of the UIC layer 2150 may transmit a signal to the UIC layer 2250 through the output terminals DOUT_t and DOUT_c. The output terminals DOUT_t and DOUT_c may constitute a transmission channel M-TX of the UIC layer 2150. For example, the signal transmitted through the output terminals DOUT_t and DOUT_c may be a pair of differential signals. That is, the signal transmitted through the output terminal DOUT_c may be complementary to the signal transmitted through the output terminal DOUT_t.

[0071] The physical layer (M-PHY) 2151 of the UIC layer 2150 may receive a signal from the UIC layer 2250 through the input terminals DIN_t and DIN_c. The input terminals DIN_t and DIN_c may constitute a receiving channel M-RX of the UIC layer 2150. For example, the signal received through the input terminals DIN_t and DIN_c may be a pair of differential signals. That is, the signal received through the input terminal DIN_c may be complementary to the signal received through the input terminal DIN_t.

[0072] The output terminals DOUT_t and DOUT_c and the input terminals DIN_t and DIN_c can be controlled to one of various states according to a given protocol. For example, the output terminals DOUT_t and DOUT_c and the input terminals DIN_t and DIN_c can be controlled to a positive state DIF-P, a negative state DIF-N, a ground state DIF-Z or a floating state DIF-Q.

[0073] When the level (e.g., voltage level) of the output signal of the first output terminal DOUT_t is higher than the level of the output signal of the second output terminal DOUT_c, the output terminals DOUT_t and DOUT_c may be in a positive state DIF-P. When the level of the output signal of the first output terminal DOUT_t is lower than the level of the output signal of the second output terminal DOUT_c, the output terminals DOUT_t and DOUT_c may be in a negative state DIF-N. When the first output terminal DOUT_t and the second output terminal DOUT_c are floated, the output terminals DOUT_t and DOUT_c may be in a floating state DIF-Q. When the level of the first output terminal DOUT_t and the level of the second output terminal DOUT_c are equal, the output terminals DOUT_t and DOUT_c may be in a base state DIF-Z.

[0074] When the level of the input signal of the first input terminal DIN_t is higher than the level of the input signal of the second input terminal DIN_c, the input terminals DIN_t and DIN_c may be in a positive state DIF-P. When the level of the input signal of the first input terminal DIN_t is lower than the level of the input signal of the second input terminal DIN_c, the input terminals DIN_t and DIN_c may be in a negative state DIF-N. When the first input terminal DIN_t and the second input terminal DIN_c are connected to the terminal of the base state, the input terminals DIN_t and DIN_c may be in a base state DIF-Z. When the first input terminal DIN_t and the second input terminal DIN_c are floated, the input terminals DIN_t and DIN_c may be in a floating state DIF-Q.

[0075] The output terminals DOUT_t and DOUT_c of the UIC layer 2250 may correspond to the input terminals DIN_t and DIN_c of the UIC layer 2150 , and the input terminals DIN_t and DIN_c of the UIC layer 2250 may correspond to the output terminals DOUT_t and DOUT_c of the UIC layer 2150 .

[0076] The physical layer (M-PHY) 2251 of the UIC layer 2250 can receive signals through the input terminals DIN_t and DIN_c, and can transmit signals through the output terminals DOUT_t and DOUT_c. As in the description given above with reference to the UIC layer 2150, the output terminals DOUT_t and DOUT_c and the input terminals DIN_t and DIN_c of the UIC layer 2250 can be controlled to be a positive state DIF-P, a negative state DIF-N, a ground state DIF-Z, or a floating state DIF-Q.

[0077] Meanwhile, according to the MIPI M-PHY specification, the physical layer (M-PHY) 2251 of the UIC layer 2250 may be configured to detect the levels of the input terminals DIN_t and DIN_c. In an example embodiment, as a way of detecting the levels of the terminals, the physical layer (M-PHY) 2251 may include a squelch circuit 2254 for detecting the levels of the input terminals DIN_t and DIN_c. In addition, the physical layer (M-PHY) 2251 according to an example embodiment may further include a reference clock detector 2255. The squelch circuit 2254 and / or the reference clock detector 2255 may detect a change in the UFS device 2200 between an idle mode and an active mode.

[0078] When the UFS device 2200 does not perform any operation, the UFS device 2200 may be in the first idle mode or the second idle mode. When the UFS device 2200 is in the first idle mode or the second idle mode, the UIC layer 2150 may not transmit the reference clock REF_CLK to the UIC layer 2250. When the UFS device 2200 switches from the first idle mode and / or the second idle mode to the active mode, the input terminals DIN_t and DIN_c of the UIC layer 2250 may switch from the floating state DIF-Q to the negative state DIF-N. When the UFS device 2200 switches from the first idle mode and / or the second idle mode to the active mode, the UIC layer 2150 may resume transmitting the reference clock REF_CLK to the UIC layer 2250.

[0079] In an example embodiment, when the UFS device 2200 is in the first idle mode, the squelch circuit 2254 may be in an active state (i.e., in a state where a power supply voltage is supplied thereto). Therefore, when the UFS device 2200 switches from the first idle mode to the active mode, the squelch circuit 2254 may detect that the input terminals DIN_t and DIN_c of the UIC layer 2250 switch from the floating state DIF-Q to the negative state DIF-N. The squelch circuit 2254 may generate a trigger signal for causing the UFS device 2200 to enter the active mode based on the detection result.

[0080] In example embodiments, when the UFS device 2200 is in the second idle mode, the squelch circuit 2254 may be in an inactive state (i.e., in a state where a power supply voltage is not supplied thereto). Instead, the reference clock detector 2255 may generate a trigger signal for causing the UFS device 2200 to enter an active mode based on toggling of the reference clock REF_CLK.

[0081] Generally, the switching of the detection input terminals DIN_t and DIN_c from the floating state DIF-Q to the negative state DIF-N may require power consumption greater than the power consumption for switching of the detection clock. Therefore, the power consumption of the reference clock detector 2255 may be less than the power consumption of the squelch circuit 2254. In other words, the power consumption of the UFS device 2200 in the second idle mode may be less than the power consumption of the UFS device 2200 in the first idle mode.

[0082] Figure 4 Shows that compliance can be applied to Figure 2 and Figure 3 The layer structure of the storage system interface protocol.

[0083] Reference Figures 1 to 3For the purpose of executing the unique functions of the application AP-h, the file system FS-h, the device manager DM-h, the UFS application layer UAP-h, the UFS transport protocol layer UTP-h and the UFS interconnect layer UIC-h, the UFS host 2100 may include physical hardware circuits and / or processor executable program codes.

[0084] The application AP-h may include various application programs, processes, etc. driven on the UFS host 2100. The application AP-h as an upper layer may process a request from a user of the system 2000. The application AP-h may process common commands such as a read command and a write command. The application AP-h may provide control of a device level such as a query request.

[0085] The file system FS-h may organize and manage various data (files) generated by the application AP-h. The file system FS-h may generate a logical address corresponding to an access request (e.g., a write request, etc.) to the UFS device 2200. For example, the file system FS-h may include FAT (File Allocation Table), FAT32, NTFS (NT File System), HFS (Hierarchical File System), JSF2 (Journaling File System 2), XFS, ODS-5 (Disk Structure 5), UDF, ZFS, UFS (Unix File System), ext2, ext3, ext4, ReiserFS, Reiser4, ISO 9660, Gnome VFS, BFS, WinFS, etc.

[0086] The UFS application layer UAP-h is configured to support various commands between the UFS host 2100 and the UFS device 2200. For example, the UFS application layer UAP-h may include an input / output (I / O) stream manager IOSM-h and a UFS command set UCS-h. The I / O stream manager IOSM-h is configured to manage requests from an application AP-h or a file system FS-h.

[0087] In an example embodiment, the I / O stream manager IOSM-h may be configured to recognize a specific value of input / output from the application AP-h or the file system FS-h. The I / O stream manager IOSM-h may be configured to manage the priority of the request from the application AP-h or the file system FS-h, or to support various functions corresponding to the request from the application AP-h or the file system FS-h.

[0088] The UFS command set UCS-h may support various command sets supported between the UFS host 2100 and the UFS device 2200. For example, the UFS command set UCS-h may include a UFS native command set and a UFS SCSI command set. The UFS command set UCS-h may configure a command to be transmitted to the UFS device 2200 according to a request from an application AP-h or a file system FS-h.

[0089] Although not shown in the drawings, the UFS application layer UAP-h may further include a task manager that processes commands for controlling the command queue.

[0090] The device manager DM-h can manage device-level operations and device-level configurations. For example, the device manager DM-h can manage query requests for setting or checking various information.

[0091] The UFS transport protocol layer UTP-h can provide services to the upper layer. The UFS transport protocol layer UTP-h can generate a command or information provided from the UFS application layer UAP-h or a query request provided from the device manager DM-h in the form of a UPIU (UFS Protocol Information Unit) packet.

[0092] In an embodiment, the UFS transport protocol layer UTP-h and the device manager DM-h can communicate with each other through UDM-SAP (UDM-Service Access Point). The UFS transport protocol layer UTP-h and the UFS application layer UAP-h can communicate with each other through UTP_CMD_SAP or UTP_TM_SAP.

[0093] The UFS interconnect layer UIC-h may manage the connection with the UFS device 2200. The UFS interconnect layer UIC-h may include hardware components such as MIPI Unipro and MIPI M-PHY that are physically connected to the UFS interconnect layer UIC-d of the UFS device 2200. The UFS interconnect layer UIC-h and the UFS transport protocol layer UTP-h may communicate with each other through UIC-SAP, and the UFS interconnect layer UIC-h and the device manager DM-h may communicate with each other through UIO-SAP.

[0094] Although not shown in the drawings, the UFS host 2100 may further include a device driver. The device driver may control devices and / or layers included in the UFS host 2100. The device driver may convert a request (e.g., a write request, etc.) to the UFS device 2200 generated by the file system FS-h into a command that can be recognized by the UFS device 2200. For example, the file system FS-h and the device driver may be included in an operating system (OS), and the application AP-h may be installed in the OS. The device driver may control communication with the UFS device 2200 while managing hardware resources.

[0095] For the purpose of executing the unique functions of the device manager DM-d, the UFS application layer UAP-d, the UFS transport protocol layer UTP-d, and the UFS interconnect layer UIC-d, the UFS device 2200 may include physical hardware circuits and / or program codes executable by a processor. The configurations of the UFS application layer UAP-d, the UFS transport protocol layer UTP-d, and the UFS interconnect layer UIC-d may be understood as configurations similar to those of the UFS application layer UAP-h, the UFS transport protocol layer UTP-h, and the UFS interconnect layer UIC-h of the UFS host 2100, and logical communication is performed between the corresponding layers, and therefore, additional descriptions will be omitted to avoid redundancy.

[0096] However, unlike the physical layer M-PHY of the UFS interconnect layer UIC-h, the physical layer M-PHY of the UFS interconnect layer UIC-d may monitor the reference clock REF_CLK received from the UFS host 2100. When the monitoring result indicates that the input of the reference clock REF_CLK is suspended in the active mode of the UFS device 2200, at least some components (especially the reference clock REF_CLK) of the UFS device 2200 may be blocked. Figure 2 When the monitoring result indicates that the input of the reference clock REF_CLK is detected in the idle mode of the UFS device 2200, the supply of the power supply voltage to the components of the UFS device 2200 may be restored.

[0097] Meanwhile, the above hierarchical structure and function of each of the UFS host 2100 and the UFS device 2200 are examples and are helpful for understanding the present disclosure. Therefore, the present disclosure is not limited thereto.

[0098] Figure 5 Shows Figures 2 to 4 An operating method of the UFS device 2200 is disclosed.

[0099] Reference Figures 1 to 4In S110, the UFS device 2200 (e.g., the reference clock detector 2255) may detect whether the reference clock REF_CLK is received from the UFS host 2100. When the UFS device 2200 is in the active mode, the UFS host 2100 may transmit the reference clock REF_CLK to the UFS device 2200. However, in the case where the UFS host 2100 enters the idle mode, the UFS host 2100 may not provide the reference clock REF_CLK to the UFS device 2200.

[0100] In the case where the input of the reference clock REF_CLK is suspended when the UFS device 2200 is in the active mode, this may mean that the UFS device 2200 is scheduled to enter the idle mode. Therefore, the reference clock detector 2255 may generate a first trigger signal corresponding to entering the idle mode in response to the input of the reference clock REF_CLK being suspended.

[0101] When the input of the reference clock REF_CLK is restored while the UFS device 2200 is in the idle mode, this may mean that the UFS device 2200 is scheduled to enter the active mode. Therefore, the reference clock detector 2255 may generate a second trigger signal corresponding to entering the active mode in response to the input of the reference clock REF_CLK being restored.

[0102] In operation S120, the UFS device 2200 (eg, the regulator 2260) may selectively supply power to the squelch circuit 2254 based on the detection result. For example, when the UFS device 2200 is in the active mode, the regulator 2260 (see Figure 2 ) may suspend power supply to at least some components of the UFS device 2200 in response to the first trigger signal. In particular, the regulator 2260 may prevent power from being supplied to the squelch circuit 2254 in response to the first trigger signal. For example, when the UFS device 2200 is in the idle mode, the regulator 2260 may resume power supply to at least some components of the UFS device 2200 in response to the second trigger signal.

[0103] Figure 6 Shows Figures 2 to 4 An operating method of the UFS device 2200 is disclosed.

[0104] Reference Figures 1 to 5In operation S210, the UFS device 2200 may monitor the reference clock REF_CLK received from the UFS host 2100. When the monitoring result indicates that the reference clock REF_CLK is always received (Yes), the monitoring result may mean that the UFS device 2200 is in the active mode. Therefore, the UFS device 2200 may continue to monitor the reference clock REF_CLK. On the contrary, when the monitoring result indicates that the reference clock REF_CLK is not received (No), the monitoring result may mean that the UFS host 2100 has entered the idle mode and the UFS device 2200 is scheduled to enter the idle mode.

[0105] In operation S220, when the reference clock REF_CLK is not detected within a given time, the UFS device 2200 may enter the idle mode. For example, the reference clock detector 2255 may generate a trigger signal for causing the UFS device 2200 to enter the idle mode. The power management unit (e.g., Figure 2 The regulator 2260 of the UFS device 2200 may prevent the power voltage from being applied to at least some components of the UFS device 2200 (especially the squelch circuit 2254) in response to the trigger signal, and the UFS device 2200 may enter the idle mode.

[0106] For example, the idle mode may correspond to the sleep state HIBERN8 called in the MIPI M-PHY specification. For example, the idle mode may correspond to the pause state STALL or the sleep state SLEEP called in the MIPI M-PHY specification. For example, the sleep state HIBERN8, the pause state STALL and the sleep state SLEEP may be collectively referred to as a "power saving state".

[0107] However, even if the UFS device 2200 is in idle mode, the power supply voltage may be maintained to at least some components of the UIC layer 2250. Therefore, in idle mode, the physical connection between the UIC layer 2150 and the UIC layer 2250 may not be completely disconnected. For example, the Unipro link startup sequence for the physical connection may not be required.

[0108] When the UFS device 2200 enters the idle mode, the input terminals DIN_t and DIN_c of the UIC layer 2250 may be maintained in the floating state DIF-Q, and the UIC layer 2150 may not transmit the reference clock REF_CLK to the UIC layer 2250 .

[0109] In operation S230, the reference clock detector 2255 may always monitor whether the reference clock REF_CLK is received from the UFS host 2100. When the reference clock REF_CLK is not detected ("No" in operation S230), the UFS device 2200 may determine that the UFS host 2100 is maintaining the idle mode. On the contrary, when the reference clock REF_CLK is detected ("Yes" in operation S230), the UFS device 2200 may determine that the UFS host 2100 enters the active mode.

[0110] In operation S240 , the reference clock detector 2255 may generate a trigger signal for causing the UFS device 2200 to enter an active mode.

[0111] In operation S250, the regulator 2260 (see Figure 2 ) may resume supplying the power voltage to the UFS device 2200 (especially to the mute circuit 2254) in response to the trigger signal, and the UFS device 2200 may enter the active mode.

[0112] Fig. 7A and Figure 7B Shows Figures 1 to 3 The state machine of the UIC layer 2250. In detail, Fig. 7A shows the state machine of the output terminal M-TX of the UIC layer 2150, Figure 7B The state machine of the input terminal M-RX of the UIC layer 2250 is shown. For example, Fig. 7A and Figure 7B The state machine may be associated with a Type I module defined in the M-PHY protocol.

[0113] Reference Figures 2 to 4 , Fig. 7A and Figure 7B , the M-PHY protocol defines the high-speed mode HS-MODE and the low-speed mode LS-MODE of the UIC layer 2250. Both the high-speed mode HS-MODE and the low-speed mode LS-MODE may include a burst data transmission mode and a power saving state. In addition, the M-PHY protocol defines the sleep state HIBERN8 as an ultra-low power state. The power saving state of the high-speed mode HS-MODE may be a pause state STALL, and the power saving state of the low-speed mode LS-MODE may be a sleep state SLEEP.

[0114] For example, Fig. 7A and Figure 7B The sleep state SLEEP and the pause state STALL can correspond to the reference Figures 2 to 6 The active mode and sleep state HIBERN8 may correspond to the reference Figures 2 to 6 Describes the idle mode.

[0115] The UFS device 2200 may even perform mode switching between a sleep state SLEEP or a pause state STALL as a power saving state and a hibernation state HIBERN8 as an ultra-low power state. For example, in the hibernation state HIBERN8, a power supply voltage may not be supplied to at least some components of the UIC layer 2250. However, in the hibernation state HIBERN8, a power supply voltage may be supplied to some components of the UIC layer 2250. That is, the hibernation state HIBERN8 may be a state in which a Unipro link startup sequence for a physical connection between the UIC layer 2150 and the UIC layer 2250 is not required.

[0116] As shown, when the UIC layer 2250 is in the hibernation state HIBERN8, the UFS host 2100 may not provide the reference clock REF_CLK to the UFS device 2200. When the UIC layer 2250 is in the sleep state SLEEP or the pause state STALL, the UFS host 2100 may provide the reference clock REF_CLK to the UFS device 2200.

[0117] Unlike the usual case, according to the present disclosure, when the UIC layer 2250 is in the sleep state HIBERN8, the power supply voltage may not be supplied to the squelch circuit 2254. Therefore, when switching from the sleep state HIBERN8 to the sleep state SLEEP or the pause state STALL, even if the levels of the output terminals DOUT_t and DOUT_c change from DIF-Z to DIF-N, the squelch circuit 2254 cannot detect the change from DIF-Z to DIF-N. Instead, the reference clock detector 2255 may detect the switching of the reference clock REF_CLK received from the UIC layer 2150, and may generate a trigger signal for causing the UFS device 2200 to enter the active mode based on the detection result.

[0118] Fig. 8A and Figure 8B Shows Figures 2 to 4 The state machine of the UIC layer 2250. In detail, Fig. 8A shows the state machine of the output terminal M-TX of the UIC layer 2150, Figure 8B The state machine of the input terminal M-RX of the UIC layer 2250 is shown. For example, Fig. 8A and Figure 8B The state machine may be associated with a Type II module defined in the M-PHY protocol.

[0119] In addition to the undefined LINE-CFG state, Fig. 8A and Figure 8B The state machine and Fig. 7A and Figure 7BThe state machines of the UFS host 2100 and the UFS host 2100 are mostly similar. For example, when the UIC layer 2250 is in the hibernation state HIBERN8, the UFS host 2100 may not provide the reference clock REF_CLK to the UFS device 2200. When the UIC layer 2250 is in the sleep state SLEEP or the pause state STALL, the UFS host 2100 may provide the reference clock REF_CLK to the UFS device 2200.

[0120] The reference clock detector 2255 of the present disclosure detects the switching of the reference clock REF_CLK received from the UIC layer 2150, and generates a trigger signal for changing the operation mode of the UFS device 2200 based on the detection result. In the case where the UIC layer 2250 is in the sleep state HIBERN8, as shown in FIG. Fig. 7A and Figure 7B As described, the squelch circuit 2254 is not powered.

[0121] Fig. 9 and Fig.10 2 shows an example configuration of a UFS device 2200 according to an example embodiment of the present disclosure. For example, Fig. 9 conceptually illustrates how the interface circuit enters an idle mode (e.g., HIBERN8 state) from an active mode, Fig.10 It is conceptually shown how the interface circuit enters the active mode from the idle mode (eg, HIBERN8 state).

[0122] Reference Fig. 9 and Fig.10 , the UFS device 2200 may include a physical layer 2251, a regulator 2260, and a processor 2216. The physical layer 2251 may include an M-PHY receiving module 2253, a squelch circuit 2254, and a reference clock detector 2255. For example, the physical layer 2251 may be included in Figures 2 to 4 The UIC layer 2250 and the processor 2216 may be included in Figure 2 The M-PHY receiving module 2253 may include a module for processing the UFS device controller 2210 (see Figure 2 ) is a circuit (e.g., an analog front end) for receiving a signal received by the M-PHY receiving module 2253. The M-PHY receiving module 2253 may be connected to the line "LINE" through the input terminals DIN_t and DIN_c. The line "LINE", the input terminals DIN_t and DIN_c, and the M-PHY receiving module 2253 may be referred to as a "lane (LANE)".

[0123] In the case where the reference clock REF_CLK is not received during a given time (or a predetermined period), the UIC layer 2150 (see Figure 2) may have entered the sleep state HIBERN8. In this case, the reference clock detector 2255 may generate a trigger signal for causing the UIC layer 2250 to enter the sleep state HIBERN8, and may transmit the trigger signal to the regulator 2260.

[0124] In response to the trigger signal, the regulator 2260 may control the power supply voltage provided to the components of the UFS device 2200. For example, the regulator 2260 may prevent the power supply voltage PW1 from being input to the squelch circuit 2254, and may prevent the power supply voltage PW2 from being input to the processor 2216. Therefore, the processor 2216 (or a separate system clock generator (not shown) controlled by the processor 2216) may not generate the system clock SYS_CLK for operating the UFS device 2200, and the squelch circuit 2254 may not operate.

[0125] Reference Fig.10 , when the UIC layer 2250 is in the sleep state HIBERN8, the squelch circuit 2254 may not work. Instead, the reference clock detector 2255 may detect whether the reference clock REF_CLK is received. The reference clock detector 2255 detects the edge of the reference clock REF_CLK and generates a trigger signal for causing the UFS device 2200 to enter the active mode based on the detection result.

[0126] The regulator 2260 may supply the power supply voltage PW1 to the power-off component of the physical layer M-PHY (especially the squelch circuit 2254) in response to the trigger signal. The regulator 2260 may also supply the power supply voltage PW2 to the processor 2216. The processor 2216 (or a component (not shown) for generating a system clock controlled by the processor 2216) may generate a system clock SYS_CLK, and the UFS device 2200 may enter an active mode.

[0127] Fig.11 Waveforms of signals associated with a storage device according to example embodiments of the present disclosure are schematically illustrated.

[0128] Reference Figure 3 and Fig.11 , during the sleep interval T HIBERN8 During the sleep interval T, the UIC layer 2150 may not transmit the reference clock REF_CLK to the UIC layer 2250. HIBERN8 During this period, the state of the line "LINE" connecting the output terminals DOUT_t and DOUT_c of the UIC layer 2150 and the input terminals DIN_t and DIN_c of the UIC layer 2250 may be DIF-Z. HIBERN8In the case of entering the sleep state SLEEP or the pause state STALL, the state of the line "LINE" can be switched to DIF-N.

[0129] For example, the sleep state HIBERN8 of the UIC layer 2250 may correspond to the sleep interval T HIBERN8 During the sleep interval T HIBERN8 In the embodiment, the reference clock detector 2255 may detect whether the reference clock REF_CLK is received from the UFS host 2100. At time t2 when the reference clock REF_CLK is detected, the UIC layer 2250 may enter an active mode (eg, a sleep state or a suspend state).

[0130] Fig.12 An operating method of a UFS system according to an embodiment of the present disclosure is illustrated.

[0131] Reference Figure 3 and Fig.12 , in the case where the UFS host 2100 does not perform any operation, the UFS host 2100 may request the UFS device 2200 to enter the idle mode (S310). When the UFS device 2200 is ready to enter the idle mode, the UFS device 2200 transmits a confirmation signal indicating that the system 2000 can enter the idle mode to the UFS host 2100 (S320), and the UFS host 2100 and the UFS device 2200 enter the idle mode (S330). Together with the entry into the idle mode, the transmission of the reference clock REF_CLK from the UFS host 2100 to the UFS device 2200 is blocked.

[0132] After the UFS system 2000 enters the idle mode, the reference clock detector 2255 may monitor whether the reference clock REF_CLK is received from the UFS host 2100. Thereafter, when the UFS host 2100 enters the active mode (S340), the UFS host 2100 may transmit the reference clock REF_CLK to the UFS device 2200, and the reference clock detector 2255 may detect the reference clock REF_CLK (S350). The reference clock detector 2255 may generate a trigger signal for causing the UFS device 2200 to enter the active mode based on the detection result, and when the regulator 2260 may resume power supply to the UFS device 2200, the UFS device 2200 may enter the active mode (S360).

[0133] Fig.13 An operating method of a UFS system according to an embodiment of the present disclosure is illustrated. Fig.13 Example embodiments of Fig.12 However, there may be differences in the manner in which the UFS device 2200 enters the idle mode and the timing at which the UFS device 2200 enters the idle mode.

[0134] Reference Figure 3 and Fig.13 , the UFS host 2100 requests the UFS device 2200 to enter the idle mode (S410), and the UFS device 2200 transmits an idle mode confirmation signal to the UFS host 2100 (S420). The UFS host 2100 enters the idle mode in response to the idle mode confirmation signal (S430), and the transmission of the reference clock REF_CLK is blocked. When the reference clock detector 2255 of the UFS device 2200 detects the disconnection of the reference clock REF_CLK (S440), the UFS device 2200 enters the idle mode (S450).

[0135] Thereafter, when the UFS host 2100 enters the active mode (S460), the UFS host 2100 may transmit the reference clock REF_CLK to the UFS device 2200, and the reference clock detector 2255 may detect the reference clock REF_CLK (S470). The reference clock detector 2255 may generate a trigger signal for causing the UFS device 2200 to enter the active mode based on the detection result, and when the regulator 2260 may restore power to the UFS device 2200, the UFS device 2200 may enter the active mode (S480).

[0136] Fig.14 A storage system according to an embodiment of the present disclosure is shown. Fig.14 , the storage system 10 may include a storage device 100 and a storage controller 200. The storage system 10 may support a plurality of channels CH1 to CHm, and the storage device 100 and the storage controller 200 may be connected through the plurality of channels CH1 to CHm. For example, the storage system 10 may be implemented with a storage device such as a solid state drive (SSD).

[0137] The storage device 100 may include a plurality of nonvolatile memory devices NVM11 to NVMmn. Each of the nonvolatile memory devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm in a related manner. For example, the nonvolatile memory devices NVM11 to NVM1n may be connected to the first channel CH1 through paths W11 to W1n, and the nonvolatile memory devices NVM21 to NVM2n may be connected to the second channel CH2 through paths W21 to W2n. In an embodiment, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented using a storage unit that can operate according to a separate command from the storage controller 200. For example, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented using a chip or a die, but the present disclosure is not limited thereto.

[0138] The memory controller 200 may exchange signals with the memory device 100 through a plurality of channels CH1 to CHm. For example, the memory controller 200 may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 100 through the channels CH1 to CHm, or may receive data DATAa to DATAm from the memory device 100.

[0139] Through each channel, the memory controller 200 can select one of the nonvolatile memory devices connected to each channel, and can exchange data with the selected nonvolatile memory device. For example, the memory controller 200 can select the nonvolatile memory device NVM11 among the nonvolatile memory devices NVM11 to NVM1n connected to the first channel CH1. Through the first channel CH1, the memory controller 200 can transmit a command CMDa, an address ADDRa, and data DATAa to the selected nonvolatile memory device NVM11, or can receive data DATAa from the selected nonvolatile memory device NVM11.

[0140] The memory controller 200 may exchange signals with the memory device 100 through different channels in parallel. For example, while the memory controller 200 transmits a command CMDa to the memory device 100 through the first channel CH1, the memory controller 200 may transmit a command CMDb to the memory device 100 through the second channel CH2. For example, while the memory controller 200 receives data DATAa from the memory device 100 through the first channel CH1, the memory controller 200 may receive data DATAb from the memory device 100 through the second channel CH2.

[0141] The memory controller 200 may control the overall operation of the memory device 100. The memory controller 200 may transmit signals to the channels CH1 to CHm, and may control the nonvolatile memory devices NVM11 to NVMmn respectively connected to the channels CH1 to CHm. For example, the memory controller 200 may transmit a command CMDa and an address ADDRa to the first channel CH1, and may control a nonvolatile memory device selected from the nonvolatile memory devices NVM11 to NVM1n.

[0142] Each of the nonvolatile memory devices NVM11 to NVMmn may operate under the control of the memory controller 200. For example, the nonvolatile memory device NVM11 may receive a command CMDa, an address ADDRa, and data DATAa provided to the first channel CH1, and may program the data DATAa based on the command CMDa and the address ADDRa. For example, the nonvolatile memory device NVM21 may read data DATAb based on a command CMDb and an address ADDRb provided to the second channel CH2, and may transmit the read data DATAb to the memory controller 200.

[0143] exist Fig.14 The embodiment is shown as the memory device 100 communicating with the memory controller 200 through “m” channels and the memory device 100 includes “n” nonvolatile memory devices for each channel, but the number of channels and the number of nonvolatile memory devices connected to one channel may be variously changed.

[0144] Fig.15 is a block diagram showing a storage system according to an embodiment of the present disclosure. Fig.15 , the memory system 20 may include a memory device 300 and a memory controller 400. The memory device 300 may correspond to one of the nonvolatile memory devices NVM11 to NVMmn, which is based on Fig.14 The memory controller 400 may communicate with the memory controller 200 through one of the plurality of channels CH1 to CHm. Fig.14 A storage controller 200 is provided.

[0145] The memory device 300 may include first to eighth pins P11 to P18 , a memory interface circuit 310 , a control logic circuit 320 , and a memory cell array 330 .

[0146] The memory interface circuit 310 may receive a chip enable signal nCE from the memory controller 400 through the first pin P11. The memory interface circuit 310 may send a signal to / receive a signal from the memory controller 400 through the second pin P12 to the eighth pin P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., at a low level), the memory interface circuit 310 may send a signal to / receive a signal from the memory controller 400 through the second pin P12 to the eighth pin P18.

[0147] The memory interface circuit 310 may receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 400 through the second pin P12 to the fourth pin P14. Through the seventh pin P17, the memory interface circuit 310 may receive a data signal DQ from the memory controller 400, or may transmit the data signal DQ to the memory controller 400. The command CMD, the address ADDR, and the data "DATA" may be transmitted through the data signal DQ. For example, the data signal DQ may be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to the plurality of data signals, respectively.

[0148] The memory interface circuit 310 may acquire a command CMD from a data signal DQ received in an enable period (e.g., in a high level state) of a command latch enable signal CLE based on the switching timing of the write enable signal nWE. The memory interface circuit 310 may acquire an address ADDR from a data signal DQ received in an enable period (e.g., in a high level state) of an address latch enable signal ALE based on the switching timing of the write enable signal nWE.

[0149] In an embodiment, the write enable signal nWE may remain static (e.g., high level or low level), and then may switch between high level and low level. For example, the write enable signal nWE may switch during a period of transmitting a command CMD or an address ADDR. In this way, the memory interface circuit 310 may obtain the command CMD or the address ADDR based on the switching timing of the write enable signal nWE.

[0150] The memory interface circuit 310 may receive a read enable signal nRE from the memory controller 400 through a fifth pin P15. The memory interface circuit 310 may receive a data strobe signal DQS from the memory controller 400 or may transmit the data strobe signal DQS to the memory controller 400 through a sixth pin P16.

[0151] In the operation of the memory device 300 outputting the data "DATA", before the data "DATA" is output, the memory interface circuit 310 may receive the switching of the read enable signal nRE through the fifth pin P15. The memory interface circuit 310 may generate the switching of the data strobe signal DQS based on the switching of the read enable signal nRE. For example, the memory interface circuit 310 may generate a data strobe signal DQS, which starts switching after a given delay (e.g., tDQSRE) from the time when the read enable signal nRE starts switching. The memory interface circuit 310 may transmit a data signal DQ including the data "DATA" based on the switching timing of the data strobe signal DQS. In this way, the data "DATA" may be consistent with the switching timing of the data strobe signal DQS and may be transmitted to the memory controller 400.

[0152] In the operation of receiving data "DATA" by the memory device 300, when receiving the data signal DQ including the data "DATA" from the memory controller 400, the memory interface circuit 310 may receive the switching of the data strobe signal DQS and the data "DATA" from the memory controller 400. The memory interface circuit 310 may acquire the data "DATA" from the data signal DQ based on the switching timing of the data strobe signal DQS. For example, the memory interface circuit 310 may acquire the data "DATA" by sampling the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS.

[0153] The memory interface circuit 310 may transmit the ready / busy signal nR / B to the memory controller 400 through the eighth pin P18. The memory interface circuit 310 may transmit the state information of the memory device 300 to the memory controller 400 through the ready / busy signal nR / B. When the memory device 300 is in a busy state (i.e., when the internal operation of the memory device 300 is being performed), the memory interface circuit 310 may transmit the ready / busy signal nR / B indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (i.e., when the internal operation of the memory device 300 is not being performed or completed), the memory interface circuit 310 may transmit the ready / busy signal nR / B indicating the ready state to the memory controller 400. For example, while the memory device 300 reads data "DATA" from the memory cell array 330 in response to a page read command, the memory interface circuit 310 may transmit the ready / busy signal nR / B (e.g., a low level) indicating the busy state to the memory controller 400. For example, while the memory device 300 programs the data “DATA” in the memory cell array 330 in response to a program command, the memory interface circuit 310 may transmit a ready / busy signal nR / B indicating a busy state to the memory controller 400 .

[0154] The control logic circuit 320 may control various operations of the memory device 300. The control logic circuit 320 may receive the command / address CMD / ADDR obtained by the memory interface circuit 310. The control logic circuit 320 may generate control signals for controlling the remaining components of the memory device 300 according to the received command / address CMD / ADDR. For example, the control logic circuit 320 may generate various control signals for programming data “DATA” in the memory cell array 330 or reading data “DATA” from the memory cell array 330.

[0155] The memory cell array 330 may store the data “DATA” obtained by the memory interface circuit 310 under the control of the control logic circuit 320. Under the control of the control logic circuit 320, the memory cell array 330 may output the data “DATA” stored therein to the memory interface circuit 310.

[0156] The memory cell array 330 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present disclosure is not limited thereto. For example, the memory cell may include a resistance random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, or a magnetic random access memory (MRAM) cell. Hereinafter, an embodiment of the present disclosure will be described based on an embodiment in which the memory cell is a NAND flash memory cell.

[0157] The memory controller 400 may include first to eighth pins P21 to P28 and a controller interface circuit 410. The first to eighth pins P21 to P28 correspond to the first to eighth pins P11 to P18 of the memory device 300, respectively.

[0158] The controller interface circuit 410 may transmit the chip enable signal nCE to the memory device 300 through the first pin P21. The controller interface circuit 410 may send / receive a signal to / from the memory device 300 selected by the chip enable signal nCE through the second to eighth pins P22 to P28.

[0159] The controller interface circuit 410 may transmit the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 300 through the second pin P22 to the fourth pin P24. Through the seventh pin P27, the controller interface circuit 410 may transmit the data signal DQ to the memory device 300, or may receive the data signal DQ from the memory device 300.

[0160] The controller interface circuit 410 may transmit the data signal DQ including the command CMD or the address ADDR together with the switching of the write enable signal nWE to the memory device 300. The controller interface circuit 410 may transmit the data signal DQ including the command CMD to the memory device 300 by transmitting the command latch enable signal CLE having an enable state, and may transmit the data signal DQ including the address ADDR to the memory device 300 by transmitting the address latch enable signal ALE having an enable state.

[0161] The controller interface circuit 410 may transmit the read enable signal nRE to the memory device 300 through the fifth pin P25. The controller interface circuit 410 may receive the data strobe signal DQS from the memory device 300 or may transmit the data strobe signal DQS to the memory device 300 through the sixth pin P26.

[0162] In the operation of outputting data "DATA" from the memory device 300, the controller interface circuit 410 may generate a switch of the read enable signal nRE, and may transmit the read enable signal nRE to the memory device 300. For example, before outputting the data "DATA" from the memory device 300, the controller interface circuit 410 may generate a read enable signal nRE that changes from a static state (e.g., a high level or a low level) to a switch state. In this way, a data strobe signal DQS that switches based on the read enable signal nRE may be generated in the memory device 300. The controller interface circuit 410 may receive a data signal DQ including the data "DATA" and a switch of the data strobe signal DQS from the memory device 300. The controller interface circuit 410 may obtain the data "DATA" from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0163] In the operation of outputting the data "DATA" to the memory device 300, the controller interface circuit 410 may generate a switch of the data strobe signal DQS. For example, before transmitting the data "DATA" to the memory device 300, the controller interface circuit 410 may generate the data strobe signal DQS that changes from a static state (e.g., a high level or a low level) to a switch state. The controller interface circuit 410 may transmit the data signal DQ including the data "DATA" to the memory device 300 based on the switch timing of the data strobe signal DQS.

[0164] The controller interface circuit 410 may receive the ready / busy signal nR / B from the memory device 300 through the eighth pin P28. The controller interface circuit 410 may determine the state information of the memory device 300 based on the ready / busy signal nR / B.

[0165] Fig.16 Shows Fig.15Configuration of storage devices. Fig.16 , the memory device 300 may include a control logic circuit 320, a memory cell array 330, a page buffer unit 340, a voltage generator 350, and a row decoder 360. Fig.16 Not shown, but the storage device 300 may also include Fig.15 The memory interface circuit 310 shown may also include a column decoder, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

[0166] The control logic circuit 320 may control various operations of the memory device 300. The control logic circuit 320 may output various control signals in response to a command CMD and / or an address ADDR from the memory interface circuit 310. For example, the control logic circuit 320 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0167] The memory cell array 330 may include a plurality of memory blocks BLK1 to BLKz (z is an integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory cell array 330 may be connected to the page buffer unit 340 through the bit lines BL, and may be connected to the row decoder 360 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0168] In an embodiment, the memory cell array 330 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include a memory cell connected to a word line stacked vertically above a substrate. The following patent documents are incorporated herein by reference: U.S. Patents 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648. In an embodiment, the memory cell array 330 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0169] The page buffer unit 340 may include a plurality of page buffers PB1 to PBn (n is an integer of 3 or more), and the plurality of page buffers PB1 to PBn may be connected to the memory cell through the bit line BL. The page buffer unit 340 may select at least one bit line BL in response to the column address Y-ADDR. The page buffer unit 340 may operate as a write driver or a sense amplifier according to the operation mode. For example, in a programming operation, the page buffer unit 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. In a read operation, the page buffer unit 340 may sense the data stored in the memory cell by sensing the current or voltage of the selected bit line.

[0170] The voltage generator 350 may generate various voltages for performing programming, reading and erasing operations based on the voltage control signal CTRL_vol. For example, the voltage generator 350 may generate a program voltage, a read voltage, a program verification voltage, an erase voltage, etc. as a word line voltage VWL.

[0171] In response to the row address X-ADDR, the row decoder 360 may select one of the word lines WL and may select one of the string selection lines SSL. For example, the row decoder 360 may apply a program voltage / program verification voltage to the selected word line in a program operation and may apply a read voltage to the selected word line in a read operation.

[0172] Fig.17 3D V-NAND flash memory. Fig.17 The equivalent circuit shown is represented.

[0173] Fig.17 The illustrated memory block BLKi represents a three-dimensional memory block formed in a three-dimensional structure over a substrate. For example, a plurality of NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

[0174] Reference Fig.17 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. Fig.17 The embodiment is illustrated as each of the plurality of memory NAND strings NS11 to NS33 including 8 memory cells MC1 to MC8 , but the embodiment is not limited thereto.

[0175] The string selection transistors SST of the storage NAND strings NS11 to NS33 may be connected to the string selection lines SSL1, SSL2, and SSL3. The memory cells MC1 to MC8 of the multiple storage NAND strings NS11 to NS33 may be connected to the gate lines GTL1 to GTL8. The gate lines GTL1 to GTL8 may correspond to word lines, and a portion of the gate lines GTL1 to GTL8 may correspond to dummy word lines. The ground selection transistors GST of the multiple storage NAND strings NS11 to NS33 may be connected to the ground selection lines GSL1, GSL2, and GSL3. The string selection transistors SST of the multiple storage NAND strings NS11 to NS33 may be connected to the bit lines BL1, BL2, and BL3, and the ground selection transistors GST of the multiple storage NAND strings NS11 to NS33 may be connected to the common source line CSL.

[0176] Gate lines (eg, GTL1) of the same height may be commonly connected, ground selection lines GSL1, GSL2, and GSL3 may be separated from each other, and string selection lines SSL1, SSL2, and SSL3 may be separated from each other. Fig.17 The embodiment is shown in FIG. 1 as a memory block BLKi connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3 , but the embodiment is not limited thereto.

[0177] Fig.18 3D V-NAND structure applicable to a UFS device according to an embodiment of the present disclosure. Fig.18 , the memory device 1800 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by: manufacturing an upper chip including a cell area CELL on a first wafer; manufacturing a lower chip including a peripheral circuit area PERI on a second wafer different from the first wafer; and then connecting the upper chip and the lower chip in a bonding manner. For example, the bonding method may include a method of electrically connecting a bonding metal formed in the uppermost metal layer of the upper chip and a bonding metal formed in the uppermost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

[0178] The peripheral circuit region PERI and the cell region CELL of the memory device 1800 may each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0179] The peripheral circuit region PERI may include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, respectively, and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c. In an embodiment, the first metal layers 230a, 230b, and 230c may be formed of tungsten having a relatively high resistance, and the second metal layers 240a, 240b, and 240c may be formed of copper having a relatively low resistance.

[0180] In the present specification, although the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are shown and described, the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are not limited thereto, and one or more metal layers may be further formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more metal layers formed on the second metal layers 240a, 240b, and 240c may be formed of aluminum or the like having a lower resistance than the resistance of copper forming the second metal layers 240a, 240b, and 240c.

[0181] An interlayer insulating layer 215 may be disposed on the first substrate 210 to cover the plurality of circuit elements 220a, 220b, and 220c, the first metal layers 230a, 230b, and 230c, and the second metal layers 240a, 240b, and 240c. The interlayer insulating layer 215 may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0182] The lower bonding metals 271b and 272b may be formed on the second metal layer 240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b in the peripheral circuit area PERI may be electrically connected to the upper bonding metals 371b and 372b in the cell area CELL in a bonding manner, and the lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b may be formed of aluminum, copper, tungsten, etc.

[0183] The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate 1810 and a common source line 1820. On the second substrate 1810, a plurality of word lines 331 to 338 (i.e., 1830) may be stacked in a direction perpendicular to the upper surface of the second substrate 1810 (i.e., the Z-axis direction). The string selection line and the ground selection line may be arranged on and below the plurality of word lines 1830, respectively, and the plurality of word lines 1830 may be arranged between the string selection line and the ground selection line.

[0184] In the bit line bonding area BLBA, the channel structure CH may extend in a direction perpendicular to the upper surface of the second substrate 1810, and may pass through a plurality of word lines 1830, string selection lines, and ground selection lines. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In an embodiment, the bit line 360c may extend in a first direction (ie, a Y-axis direction) parallel to the upper surface of the second substrate 1810.

[0185] exist Fig.18 In the illustrated embodiment, a region where a channel structure CH, a bit line 360c, etc. are provided may be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 360c may be electrically connected to a circuit element 220c constituting a page buffer 393 in the peripheral circuit region PERI. The bit line 360c may be connected to upper bonding metals 371c and 372c in the cell region CELL, and the upper bonding metals 371c and 372c may be connected to lower bonding metals 271c and 272c connected to the circuit element 220c of the page buffer 393.

[0186] In the word line bonding area WLBA, a plurality of word lines 1830 may extend in a second direction (i.e., an X-axis direction) parallel to the upper surface of the second substrate 1810, and may be connected to a plurality of cell contact plugs 341 to 347 (i.e., 1840). The word lines 1830 and the cell contact plugs 1840 may be connected to each other at pads provided by at least some of the plurality of word lines 1830 extending in the second direction with different lengths. The first metal layer 350b and the second metal layer 360b may be sequentially connected to the upper portion of each cell contact plug 1840 connected to the word line 1830. The cell contact plugs 1840 may be connected to the peripheral circuit region PERI in the word line bonding area WLBA through the upper bonding metals 371b and 372b of the cell region CELL and the lower bonding metals 271b and 272b of the peripheral circuit region PERI.

[0187] The cell contact plug 1840 may be electrically connected to the circuit element 220b providing the row decoder 394 in the peripheral circuit region PERI. In an embodiment, the operating voltage of the circuit element 220b providing the row decoder 394 may be different from the operating voltage of the circuit element 220c providing the page buffer 393. For example, the operating voltage of the circuit element 220c providing the page buffer 393 may be greater than the operating voltage of the circuit element 220b providing the row decoder 394.

[0188] The common source line contact plug 380 may be disposed in the external pad bonding area PA. The common source line contact plug 380 may be formed of a conductive material such as a metal, a metal compound, polysilicon, etc., and may be electrically connected to the common source line 1820. The first metal layer 350a and the second metal layer 360a may be sequentially stacked on the upper portion of the common source line contact plug 380. For example, an area where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed may be defined as the external pad bonding area PA.

[0189] Meanwhile, the input / output pads 205 and 305 may be disposed in the external pad bonding area PA. Fig.18 , a lower insulating film 201 covering the lower surface of the first substrate 210 may be formed under the first substrate 210, and a first input / output pad 205 may be formed on the lower insulating film 201. The first input / output pad 205 may be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c provided in the peripheral circuit region PERI through the first input / output contact plug 203, and may be separated from the first substrate 210 by the lower insulating film 201. In addition, a side insulating film may be provided between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 and the first substrate 210.

[0190] Reference Fig.18 , an upper insulating film 301 covering the upper surface of the second substrate 1810 may be formed on the second substrate 1810, and a second input / output pad 305 may be disposed on the upper insulating film 301. The second input / output pad 305 may be connected to at least one of the plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI through a second input / output contact plug 303.

[0191] According to an embodiment, the second substrate 1810 and the common source line 1820 may not be disposed in the region where the second input / output contact plug 303 is disposed. Also, the second input / output pad 305 may not overlap the word line 1830 in the third direction (ie, the Z-axis direction). Fig.18The second input / output contact plug 303 may be separated from the second substrate 1810 in a direction parallel to the upper surface of the second substrate 1810 , may pass through the interlayer insulating layer 315 of the cell region CELL, and may be connected to the second input / output pad 305 .

[0192] According to an embodiment, the first input / output pad 205 and the second input / output pad 305 may be selectively formed. For example, the memory device 1800 may include only the first input / output pad 205 disposed on the first substrate 210, or may include only the second input / output pad 305 disposed on the second substrate 1810. Alternatively, the memory device 1800 may include both the first input / output pad 205 and the second input / output pad 305.

[0193] In each of the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, a metal pattern in the uppermost metal layer may be set as a dummy pattern, or the uppermost metal layer may not exist.

[0194] In the external pad bonding area PA, the memory device 1800 may include a lower metal pattern 273a in the uppermost metal layer of the peripheral circuit area PERI corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell area CELL and having the same shape as the upper metal pattern 372a of the cell area CELL. In the peripheral circuit area PERI, the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to the contact. As described above, in the external pad bonding area PA, an upper metal pattern corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit area PERI and having the same shape as the lower metal pattern of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL.

[0195] Lower bonding metals 271b and 272b may be formed on the second metal layer 240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 371b and 372b of the cell area CELL by Cu-Cu bonding.

[0196] Also, in the bit line bonding area BLBA, an upper metal pattern 392 corresponding to the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit area PERI and having the same shape as the lower metal pattern 252 of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL. No contact may be formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell area CELL.

[0197] According to the present disclosure, unlike a conventional way of changing a power state based on a level change of a packet input to an input terminal, since the power state is changed based on a reference clock, power consumption of a storage device in an idle mode can be further reduced.

[0198] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A storage device, comprising: An interface circuit, the interface circuit being configured to exchange data with a host device, the interface circuit comprising: a first input terminal configured to receive a first signal from the host device, a second input terminal configured to receive a second signal from the host device, the second signal being complementary to the first signal, a squelch circuit configured to detect a level of the first signal and a level of the second signal, a reference clock detector configured to detect receipt of a reference clock from the host device and to detect whether the host device has suspended transmission of the reference clock to the storage device when the storage device is in an active mode, a phase-locked loop configured to generate a plurality of clocks based on the reference clock; and a power manager configured to supply power to the interface circuit, such that the power manager selectively supplies the power to the squelch circuit of the storage device by blocking the supply of power to the squelch circuit of the storage device in response to the reference clock detector detecting that the host device has suspended transmission of the reference clock to the storage device when the storage device is in an active mode, wherein The squelch circuit and the reference clock detector are implemented in a physical layer of the interface circuit, The reference clock detector is implemented outside the squelch circuit, and The reference clock detector is configured to detect switching of the reference clock from the host device when the squelch circuit is powered off.

2. The storage device according to claim 1, wherein: The reference clock detector is configured to generate a first trigger signal in response to detecting that the host device has suspended transmission of the reference clock to the storage device while the storage device is in the active mode.

3. The storage device according to claim 1, wherein: The reference clock detector is configured to, detecting resumption of the reception of the reference clock while the storage device is in an idle mode, and In response to detecting the resumption of the reception of the reference clock, a second trigger signal is generated.

4. The storage device according to claim 3, wherein: The power manager is configured to supply the power to the squelch circuit in response to the second trigger signal.

5. The storage device according to claim 1, wherein: The interface circuit is implemented using a universal flash memory interconnect layer including a physical layer, wherein the physical layer includes the squelch circuit and the reference clock detector.

6. The storage device according to claim 2, wherein: The first trigger signal instructs the interface circuit to enter a dormant state from a suspended state or a sleep state.

7. The storage device according to claim 3, wherein: The second trigger signal instructs the interface circuit to enter a pause state or a sleep state from a dormant state.

8. The storage device according to claim 1, wherein: The interface circuit communicates with the host device according to a universal flash memory protocol.

9. A storage system, comprising: a host device, the host device comprising a first interface circuit, the first interface circuit comprising a transmission channel configured to transmit a first signal and a second signal, the second signal being complementary to the first signal; as well as A storage device, the storage device comprising a second interface circuit and a power manager, the power manager being configured to supply power to the second interface circuit, the second interface circuit comprising: a receiving channel configured to receive the first signal and the second signal, a squelch circuit configured to detect a level of the first signal and a level of the second signal, a reference clock detector configured to detect receipt of a reference clock from the host device and, when the memory device is in an active mode, detect whether the host device has suspended transmission of the reference clock to the memory device, and a phase-locked loop configured to generate a plurality of clocks based on the reference clock, wherein the power manager is configured to selectively supply the power to the squelch circuit of the storage device by blocking the supply of power to the squelch circuit of the storage device in response to the reference clock detector detecting that the host device has suspended transmission of the reference clock to the storage device when the storage device is in an active mode, wherein the operation mode of the storage device changes between the active mode and the idle mode based on whether the reference clock detector detects the reception of the reference clock from the host device, wherein the squelch circuit and the reference clock detector are implemented in the physical layer of the second interface circuit, wherein the reference clock detector is implemented outside the squelch circuit, and The reference clock detector is configured to detect a switch of the reference clock from the host device when the squelch circuit is powered off.

10. The storage system according to claim 9, wherein: An interruption of the reception of the reference clock while the storage device is in the active mode instructs the second interface circuit to enter a hibernation state from a suspend state or a sleep state.

11. The storage system according to claim 9, wherein: The reference clock detector is configured to detect resumption of the reception of the reference clock when the storage device is in the idle mode, and The power manager is configured to, in response to the reference clock detector detecting the resumption of the reception of the reference clock, supply the power to the squelch circuit.

12. The storage system according to claim 11, wherein: The resumption of the reception of the reference clock while the storage device is in the idle mode indicates that the second interface circuit enters a suspend state or a sleep state from a hibernation state.

13. The storage system according to claim 9, wherein: The first interface circuit and the second interface circuit are both implemented using a universal flash memory interconnect layer including a physical layer.

14. A method for operating a storage device, the storage device comprising an interface circuit, the interface circuit having a receiving channel and a squelch circuit, the receiving channel being configured to receive a first signal and a second signal from a host device, the squelch circuit being configured to detect a level of the first signal and a level of the second signal, the second signal being complementary to the first signal, the method comprising: detecting, by a reference clock detector, receipt of a reference clock from the host device; The reference clock detector detects, when the storage device is in an active mode, whether the host device has suspended transmitting the reference clock to the storage device; Generate multiple clocks based on the reference clock by a phase-locked loop; as well as In response to the reference clock detector detecting that the host device has suspended transmission of the reference clock to the storage device while the storage device is in an active mode, the power manager selectively supplies the power to the squelch circuit by blocking the supply of power to the squelch circuit of the storage device, wherein The squelch circuit and the reference clock detector are implemented in a physical layer of the interface circuit, The reference clock detector is implemented outside the squelch circuit, and The reference clock detector is configured to detect switching of the reference clock from the host device when the squelch circuit is powered off.

15. The method according to claim 14, wherein: The selectively supplying power to the squelch circuit comprises: In response to detecting resumption of the reception of the reference clock, power to the squelch circuit is restored.

16. The method according to claim 14, wherein: The interface circuit is implemented using a universal flash interconnect layer including a physical layer, wherein the physical layer includes the receive channel and the squelch circuit.

Images