Image sensor and method of forming the same
By introducing a deep trench isolation structure and doped pads on the back side into the image sensor, the isolation problem between adjacent pixels is solved, improving the photolithography process and device performance, and reducing blurring and crosstalk.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2020-12-21
- Publication Date
- 2026-04-17
AI Technical Summary
In existing image sensor manufacturing processes, the electrical and optical isolation between adjacent pixels is poor, leading to blurring and crosstalk problems. Furthermore, the thickness of the photoresist layer limits the realization of precise photolithography processes.
The back deep trench isolation (BDTI) structure is adopted. By forming deep trenches between the doped layers of the photodiode and forming doped pads and dielectric filling layers on its sidewall surface, combined with low temperature epitaxy and laser annealing processes, conformal and smooth doped pads are formed, reducing the bending tips and defect layers of the trench.
It improves the electrical and optical isolation of image sensors, reduces crosstalk and blurring between pixels, improves the accuracy and filling quality of photolithography, and enhances device performance.
Smart Images

Figure CN113113433B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to image sensors and methods for forming the same. Background Technology
[0002] Many modern electronic devices include optical imaging devices that use image sensors (e.g., digital cameras). An image sensor can include an array of pixel sensors and supporting logic. The pixel sensors measure incident radiation (e.g., light) and convert it into digital data, while the supporting logic facilitates the readout of the measured values. One type of image sensor is the back-illuminated (BSI) image sensor device. BSI image sensor devices are used to sense the amount of light projected toward the back side of a substrate (opposite to the front side, on which an interconnect structure comprising multiple metal and dielectric layers is constructed). Compared to front-illuminated (FSI) image sensor devices, BSI image sensor devices offer reduced destructive interference. Summary of the Invention
[0003] According to one aspect of the present invention, a method for forming an image sensor is provided, comprising: forming a plurality of photodiodes for a plurality of pixel regions from the front side of an image sensing die, wherein the photodiodes are formed as photodiode doped pillars having a first doping type, the photodiode doped pillars being surrounded by a photodiode doped layer of a second doping type, the second doping type being different from the first doping type; forming a deep trench from the front side of the image sensing die between adjacent pixel regions in the photodiode doped layer, wherein the upper portion of the photodiode doped layer exposed in the deep trench is transformed into a defect layer during etching of the deep trench; alternately performing a periodic cleaning process with at least two etchants to remove the defect layer; forming a doped pad of the second doping type lining the sidewall surface of the deep trench; and forming a dielectric filling layer filling the internal space of the deep trench to form a back-side deep trench isolation structure.
[0004] According to another aspect of the present invention, a method for forming an image sensor is provided, comprising: forming photodiodes for a plurality of pixel regions from the front side of an image sensing die, wherein the photodiodes are formed as photodiode doped pillars having a first doping type, the photodiode doped pillars being surrounded by a photodiode doped layer of a second doping type, the second doping type being different from the first doping type; forming a doped isolation well from the front side of the image sensing die by implanting dopant into the photodiode doped layer via at least one implantation process; and forming a gate structure and a metallization stack on the front side of the image sensing die, wherein the metallization stack... The method includes multiple metal interconnect layers disposed within one or more interlayer dielectric layers, bonding the image sensing die to a logic die from the front side, wherein the logic die includes logic devices; forming deep trenches between adjacent pixel regions in the back side of the image sensing die; performing a cleaning process to remove the exposed upper portion of the photodiode doped layer in the deep trenches, wherein the cleaning process includes a first etchant of hydrofluoric acid and a second etchant of a mixture of ammonia and hydrogen peroxide; forming a doped pad of a second doping type to line the sidewall surfaces of the deep trenches; and forming a dielectric filling layer to fill the internal space of the deep trenches to form a back-side deep trench isolation structure.
[0005] According to another aspect of the present invention, an image sensor is provided, comprising: an image sensing die having a front side and a back side opposite to the front side; a plurality of pixel regions disposed within the image sensing die, each including a photodiode configured to convert radiation entering from the back side of the image sensing die into an electrical signal, the photodiode including a photodiode doped pillar of a first doping type surrounded by a photodiode doping layer having a second doping type different from the first doping type; and a back trench isolation structure disposed between adjacent pixel regions and extending from the back side of the image sensing die into the photodiode doping layer; wherein the back trench isolation structure includes a doped pad of the second doping type and a dielectric filling layer, the doped pad lining the sidewall surface of the dielectric filling layer. Attached Figure Description
[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.
[0007] Figure 1 Cross-sectional views of some embodiments of an image sensor are shown, including a photodiode surrounded by a back-side deep trench isolation (BDTI) structure with doped pads.
[0008] Figures 2A-2D A series of schematic diagrams illustrating some embodiments of methods for forming BDTI structures with doped pads for image sensors are shown.
[0009] Figure 3 Cross-sectional views of some other embodiments of an image sensor are shown, including a photodiode isolated by a shallow isolation well and a BDTI structure with a doped pad.
[0010] Figure 4 Cross-sectional views of several other embodiments of an image sensor are shown, including a photodiode surrounded by a BDTI structure with a doped pad, a shallow isolation well, and a shallow trench isolation structure.
[0011] Figure 5 Cross-sectional views of some embodiments of an integrated chip including an image sensing die and a logic die bonded together are shown, wherein the image sensing die has a photodiode surrounded by a BDTI structure with a doped pad.
[0012] Figures 6-20 Cross-sectional views of some embodiments of a method for forming an image sensor are shown, the image sensor having a photodiode surrounded by a BDTI structure with a conformal doped layer.
[0013] Figure 21 Flowcharts illustrating some embodiments of a method for forming an image sensor having a photodiode surrounded by a BDTI structure with a doped layer are shown. Detailed Implementation
[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0015] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.
[0016] Integrated circuit (IC) technology is constantly being improved. These improvements often involve shrinking device geometry to achieve lower manufacturing costs, higher device integration density, higher speeds, and better performance. Due to device scaling, the pixels of image sensors are smaller in size and closer together. Improved electrical and optical isolation between adjacent pixels in image sensors is needed to reduce blooming and crosstalk. Dielectric trenches and injection wells can be fabricated as isolation structures to isolate image sensor pixels. One type of image sensor manufacturing process involves an injection process to form deep injection wells that extend through the depth of a photodiode as isolation walls (e.g., an injection process known as array deep p-well injection). However, in addition to manufacturing complexity, these injection processes involve thick photoresist layers that reduce exposure resolution. For example, if the critical dimension is less than 0.2 μm, it becomes difficult to achieve precise photolithography with photoresist layers larger than 3 μm.
[0017] In view of the above, this disclosure relates to an image sensor including a backside deep trench isolation (BDTI) structure with doped pads and an associated method of forming it. In some embodiments, the image sensor has a plurality of pixel regions disposed within an image sensing die. Each pixel region has a photodiode configured to convert radiation into an electrical signal. The photodiode includes a first-doped column surrounded by a photodiode doped layer having a second doping type different from the first doping type. The BDTI structure is disposed between adjacent pixel regions and extends from the backside of the image sensing die to a location within the photodiode doped layer. The BDTI structure includes second-doped pads lining the sidewall surfaces of the deep trenches of the photodiode doped layer and a fill layer disposed within the remaining interior space of the deep trenches. With the BDTI structure extending deeply and acting as a deep depletion and isolation structure between adjacent pixels, deep implantation from the front side of the sensing die is not required.
[0018] Furthermore, in some embodiments, a periodic cleaning process is performed after the formation of the deep trench and before the formation of the doped pads within the deep trench. This removes or at least reduces the defective upper portions of the photodiode doped layer exposed to the deep trench, as well as the bowing tip at the top corner of the deep trench, leaving a smooth sidewall surface and a less curved neck for the deep trench. Consequently, a smooth and uniform filling result is more easily obtained during subsequent trench filling processes. In some further embodiments, the doped pads are formed via a low-temperature epitaxial process followed by a laser annealing process for dopant activation. This allows for the formation of conformal, smooth pads with fewer defects without introducing undesirable anomalous thermal budgets. The following explanation, in conjunction with the manufacturing process, further details... Figures 2A-2D and Figures 13-15 Further details are provided for some embodiments of methods for forming doped pads.
[0019] Figure 1 A cross-sectional view of an image sensor 100 according to some embodiments is shown, having a photodiode 104 surrounded by a BDTI structure 111 with a doped pad 114. The image sensing die 134 has a front side 122 and a back side 124. The image sensor 100 includes an image sensing die 134 having multiple pixel regions, which can be arranged in an array including rows and / or columns, such as... Figure 1 The pixel regions 103a and 103b shown are illustrated. Pixel regions 103a and 103b each include a photodiode 104 configured to convert incident radiation or incident light 120 (e.g., photons) into an electrical signal. In some embodiments, the photodiode 104 includes a first region, such as a photodiode doped pillar 104a having a first doping type (e.g., n-type doping with dopants such as phosphorus, arsenic, antimony, etc.), and an adjacent second region, such as a photodiode doped layer 128 having a second doping type different from the first doping type (e.g., p-type doping with dopants such as boron, aluminum, indium, etc.).
[0020] The BDTI structure 111 is placed between adjacent pixel regions 103a and 103b and isolates these adjacent pixel regions. The BDTI structure 111 can extend from the back surface 124 of the image sensing die 134 to a position within the photodiode doped layer 128 or extend through the photodiode doped layer 128, such as... Figure 1As shown. In some embodiments, the BDTI structure 111 includes a doped pad 114 of a second doping type (e.g., p-type doping) and a dielectric filling layer 112. The doped pad 114 liner the sidewall surface of the deep trench of the photodiode doped layer 128, and the dielectric filling layer 112 fills the remaining space of the deep trench. The doped pad 114 may comprise doped silicon or other doped semiconductor materials with boron or other p-type dopants. The dielectric filling layer 112 may be made of silicon dioxide, silicon nitride, and / or other suitable dielectric materials. The doped pad 114 and the dielectric filling layer 112 may extend laterally along the back surface 124 of the image sensing die 134. In some embodiments, the bending angle of the bent tip at the top corner of the BDTI structure 111 from the upper sidewall to a vertical line perpendicular to the lateral plane of the photodiode doped layer 128 is in the range of about 8° to 15°. In some embodiments, the bending tip is less than about 8°. As disclosed above and below, the bent tip can be introduced through a fabrication step of forming a deep trench for the BDTI structure 111 via an etching process. The etching process may involve anisotropic etching processes that can create an under-cut profile, including dry etching and wet etching. The bent tip can then be removed or at least reduced by a periodic cleaning process, leaving a smooth sidewall surface and a less bent neck for the deep trench.
[0021] In some embodiments, a plurality of color filters 116 are arranged above the back surface 124 of the image sensing die 134. The plurality of color filters 116 are respectively configured to transmit incident radiation or incident light 120 of a specific wavelength. For example, a first color filter (e.g., a red filter) may transmit light with wavelengths in a first range, while a second color filter may transmit light with wavelengths in a second range different from the first range. In some embodiments, the plurality of color filters 116 may be arranged within a grid structure covering a plurality of photodiodes 104.
[0022] In some embodiments, a plurality of microlenses 118 are arranged above a plurality of color filters 116. Each microlens 118 is laterally aligned with the color filters 116 and covers pixel regions 103a, 103b. In some embodiments, the plurality of microlenses 118 have a substantially flat bottom surface adjacent to the plurality of color filters 116 and a curved upper surface. The curved upper surface is configured to focus incident radiation or incident light 120 (e.g., light directed toward the underlying pixel regions 103a, 103b). During operation of the image sensor, the incident radiation or incident light 120 is focused by the microlenses 118 onto the underlying pixel regions 103a, 103b. When incident radiation or incident light of sufficient energy irradiates a photodiode 104, it generates electron-hole pairs, which produce a photocurrent. Notably, although the microlenses 118 are located in… Figure 1The image sensor is shown as being fixed to the image sensor, but it should be understood that the image sensor may not include the microlens, and the microlens may be attached to the image sensor later in a separate manufacturing process.
[0023] Figures 2A-2D A series of schematic diagrams illustrate a method for fabricating a deep trench 1202 and forming a doped pad 114 for an image sensor on the sidewall surface of the deep trench 1202 according to some embodiments. Figures 2A-2D The image sensor disclosed in this application (such as those described above) is shown during the manufacturing process. Figure 1 Some intermediate components of the image sensor 100 disclosed herein. Due to the available forming methods, the deep trench 1202 is not a straight column. For example, as Figure 2A As shown, a deep trench 1202 is formed from the back surface 124 of the photodiode doped layer 128 by an etching process. The etching process involves anisotropic etching processes, including dry etching and wet etching such as using tetramethylammonium hydroxide (TMAH) as an etchant. The deep trench 1202 may have an undercut profile and a bent tip at the top corner of the deep trench 1202. The bending angle θ1 of the bent tip from the upper sidewall of the deep trench 1202 to a vertical line perpendicular to the plane of the photodiode doped layer 128 can be in the range of about 15° to 30°. Furthermore, the upper portion of the photodiode doped layer 128 exposed to the deep trench 1202 is damaged due to dislocation and native oxide formation, and the damage result of the etching process is translated into a thickness T d The defect layer 128'.
[0024] Figure 2B A deep trench 1202 after a periodic cleaning process is shown. In some embodiments, the periodic cleaning process is used to remove the defect layer 128' and smooth the sidewall surfaces of the deep trench 1202. The periodic cleaning process may include multiple cycles of alternating solutions using at least two different etchants, such as hydrofluoric acid (HF) and a mixture of ammonia and hydrogen peroxide (APM). This process differs from general cleaning methods such as wet cleaning using hydrofluoric acid solutions, SiCoNi pre-cleaning, and / or other plasma-enhanced pre-cleaning processes because the periodic cleaning process aims to remove most of the upper portion of the photodiode doped layer 128 to completely remove the defect layer 128' and obtain a smooth surface for subsequent deposition processes. In some embodiments, the periodic cleaning process removes a thickness T d A defect layer 128' in the range of approximately 1-20 nm, or at least approximately 20 nm. This results in a smooth sidewall surface of the deep trench 1202 and a reduced bending tip. Bending width W b Defined as the lateral distance from the curved tip to the body of the deep groove 1202, such as Figure 2B As shown. Bending width Wb This can be reduced linearly with increasing cleaning cycle times. The bending angle θ2 of the resulting bend tip, from the upper sidewall of the deep trench 1202 to a vertical line perpendicular to the plane of the photodiode doped layer 128, can be reduced to less than 15°. For example, approximately 21 nanometers (nm) of the upper portion of the photodiode doped layer 128 can be removed, while approximately 6 angstroms are removed per cycle. Through 36 cycles of this cleaning process, the bending width W b It can be reduced to about 10nm. Therefore, the sidewall profile of the BDTI structure is formed with a less curved neck, and the performance of the image sensor can be improved because the trench fill quality will be improved by the straighter sidewalls of the deep trench 1202.
[0025] Then, as Figure 2C As shown, a doped pad precursor 114' is formed on the smooth sidewall surface of the deep trench 1202 by an epitaxial deposition process before filling the remaining space of the deep trench 1202. The doped pad precursor 114' is formed by a lower-temperature epitaxial deposition process with delta doping of a p-type dopant. In some embodiments, the thickness of the doped pad precursor 114' can be about 1.3 nm, wherein the boron concentration is about 1 × 10⁻⁶. 19 cm -3 In some embodiments, the dopant concentration of the doped pad precursor 114' can be approximately 5 × 10⁻⁶. 19 atoms / cm 3 With approximately 2×10 20 atoms / cm 3 The thickness of the doped pad precursor 114' can be between approximately 0.5 nm and approximately 3 nm. The thickness of the doped pad precursor 114' can not exceed 10 nm. Thicker doped pads, higher formation temperatures, or lower dopant concentrations adversely affect the number of white pixels and / or dark current in the image sensor. For example, a doped pad precursor with a thickness of approximately 10 nm and the same dopant concentration as the doped pad precursor 114' results in more than five times the number of white pixels and / or dark current in the image sensor. A dopant concentration less than 8 × 10⁻⁶... 19 cm -3 The doped pads significantly increase the number of white pixels and may even cause image sensor failure.
[0026] like Figure 2DAs shown, following the formation of the doped pad precursor 114' is a dopant activation process to facilitate the diffusion of dopant from the doped pad precursor 114' to adjacent portions of the doped pad precursor 114' to form the doped pad 114. In some embodiments, the dopant activation process is a laser annealing process, such as a dynamic surface annealing process, and may include multiple rounds to achieve a uniform dopant distribution. For example, the dopant may be boron. The surface concentration of boron may be greater than 10. 20 cm -3 Furthermore, the diffusion depth can be approximately 20 nm, at which point the concentration decreases from the highest boron concentration to approximately 10 nm. 15 cm -3 In some embodiments, after forming the doped pad 114, the bending width W of the deep trench 1202 is... b And the bending angle θ2 can be essentially maintained, such as Figure 2C and Figure 2D As shown.
[0027] Figure 3 A cross-sectional view of an image sensor 300, according to some other embodiments, is shown, comprising a photodiode 104 isolated by a doped shallow isolation well 110 and a BDTI structure 111 with a doped pad 114. Figure 1 Other components of the image sensor 100 shown in the figures can be incorporated into the image sensor 300 where applicable. In some embodiments, the depth D of the BDTI structure 111 can be in the range of about 1.5 μm to about 5 μm. The lateral dimension W of the BDTI structure 111 can be in the range of about 0.1 μm to about 0.3 μm. The lateral dimension of the BDTI structure 111 should be sufficient for the formation of the doped pad 114 and other layers within the BDTI structure (e.g., as described below). Figures 13-16 (As described). The surface roughness of the doped pad 114 can be less than... The doped pad 114 exhibits a top-to-bottom uniformity greater than 90%. In some embodiments, this is achieved by using the above-described combination. Figures 2B-2D The described cycle cleaning process, epitaxial deposition process, and dopant activation process achieve a more conformal thickness, smoother surface, and more uniform dopant concentration in the doped pad 114. It also incorporates... Figures 13-15 Further details regarding the formation method of the doped pad 114 are discussed.
[0028] Furthermore, in some embodiments, a doped shallow isolation well 110 is disposed between adjacent pixel regions 103a, 103b and isolates these adjacent pixel regions, extending from the front side 122 of the image sensing die 134 into the photodiode doped layer 128. The doped shallow isolation well 110 may have a second doping type (e.g., p-type doping). In some embodiments, the bottom portion of the BDTI structure 111 may be placed within the recessed top surface of the doped shallow isolation well 110. In this case, the doped shallow isolation well 110 may be less than half or even less than 1 / 4 the depth of the BDTI structure 111. The doped shallow isolation well 110 may be vertically aligned with the BDTI structure 111 (e.g., sharing a common centerline 126). The BDTI structure 111 and the doped shallow isolation well 110 together act as isolation portions for the pixel regions 103a, 103b, thereby reducing crosstalk and blurring between the pixel regions 103a, 103b. Since the BDTI structure 111 and the doped shallow isolation well 110 provide additional p-type dopant to the photodiode 104, the BDTI structure 111 and the doped shallow isolation well 110 also jointly promote the depletion of the photodiode 104 during operation, thereby improving the full-well capacity.
[0029] In some embodiments, the BDTI structure 111 further includes a high-k dielectric pad 113, which is placed between the doped pad 114 and the dielectric filling layer 112 and separates the doped pad 114 from the dielectric filling layer 112. The high-k dielectric pad 113 may also be a conformal layer. The high-k dielectric pad 113 may, for example, include aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), tantalum oxide (Ta2O5), or hafnium tantalum oxide (HfTaO). Other suitable high-k dielectric materials are also within the scope of this disclosure. In some embodiments, the thickness of the high-k dielectric pad 113 may be in the range of about 30 nm to about 100 nm, and may be made of a composite of various high-k dielectric materials. The doped pad 114, the high-k dielectric pad 113, and the dielectric fill layer 112 can extend laterally along the back surface 124 of the image sensing die 134.
[0030] In some embodiments, a floating diffusion well 204 is placed between adjacent pixel regions 103a, 103b, extending from the front side 122 of the image sensing die 134 to a location within the photodiode doped layer 128. In some embodiments, a BDTI structure 111 extends to cover the floating diffusion well 204. The BDTI structure 111 and the floating diffusion well 204 may be vertically aligned (e.g., sharing a common centerline 302). A transfer gate 202 is arranged laterally above the photodiode doped layer 128 at a location between the photodiode 104 and the floating diffusion well 204. During operation, the transfer gate 202 controls charge transfer from the photodiode 104 to the floating diffusion well 204. If the charge level within the floating diffusion well 204 is sufficiently high, a source follower transistor (not shown) is activated and selectively outputs charge according to the operation of a row select transistor (not shown) used for addressing. A reset transistor (not shown) may be used to reset the photodiode 104 between exposure times.
[0031] Figure 4 A cross-sectional view of an image sensor 400, according to some other embodiments, is shown, including a photodiode 104 surrounded by a BDTI structure 111 with a doped pad 114. Figure 1 and Figure 3 The image sensors 100 and 300 shown, as well as other components of the image sensors shown in the figures, can be incorporated into image sensor 400 where applicable. Furthermore, in alternative... Figure 3In some embodiments, the doped shallow isolation well 110 can be separated from the BDTI structure 111 by the photodiode doped layer 128. Furthermore, a shallow trench isolation (STI) structure 402 can be placed between adjacent pixel regions 103a, 103b, extending from the front side 122 of the image sensing die 134 to a location within the photodiode doped layer 128. The STI structure 402 and the BDTI structure 111 can be vertically aligned (e.g., sharing a common centerline 404, which may share a centerline with the doped shallow isolation well 110). In some embodiments, the doped shallow isolation well 110 extends from the front side 122 of the image sensing die 134 to a location within the photodiode doped layer 128 and surrounds the STI structure 402. The doped shallow isolation well 110 can separate the STI structure 402 from the photodiode doped layer 128 and / or the BDTI structure 111. In some further embodiments, the photodiode doped pillar 104a can extend from the back surface 124 of the image sensing die 134 to the lateral portion of the doped pad 114 of the BDTI structure 111. The BDTI structure 111, the doped shallow isolation well 110, and the STI structure 402 together act as isolation portions for the pixel regions 103a and 103b, thereby reducing crosstalk and blurring between the pixel regions 103a and 103b. The doped pad 114 of the BDTI structure 111 and the doped shallow isolation well 110 also jointly promote the depletion of the photodiode 104 during operation, thereby improving the full-well capacity.
[0032] Figure 5 A cross-sectional view of an integrated chip 500 comprising an image sensing die 134 and a logic die 136 joined together, according to some other embodiments, is shown, wherein the image sensing die 134 has a photodiode 104 surrounded by a BDTI structure 111 with a doped pad 114. Figure 1 , Figure 3 and Figure 4The image sensors 100, 300, and 400 shown, as well as components of other image sensors shown in the figures, can be incorporated into the image sensing die 134 where applicable. The image sensing die 134 may also include a composite grid 506 placed between and covering pixel regions 103a and 103b. The composite grid 506 may include a metal layer 502 and a dielectric layer 504 stacked on top of each other at the back surface 124 of the image sensing die 134. A dielectric pad 508 backs the sidewalls and top of the composite grid 506. The metal layer 502 may be one or more layers of tungsten, copper, aluminum copper, or titanium nitride, or composed of one or more layers of tungsten, copper, aluminum copper, or titanium nitride. The thickness of the metal layer 502 may be in the range of about 100 nm to about 500 nm. The dielectric layer 504 may be one or more layers of silicon dioxide, silicon nitride, or a combination thereof, or composed of one or more layers of silicon dioxide, silicon nitride, or a combination thereof. The thickness of dielectric layer 504 can be in the range of about 200 nm to about 800 nm. Dielectric pad 508 can be an oxide (such as silicon dioxide) or composed of an oxide (such as silicon dioxide). The thickness of dielectric pad 508 can be in the range of about 5 nm to about 50 nm. Other suitable metallic materials are also within the scope of this disclosure. A metallization stack 108 can be disposed on the front side 122 of the image sensing die 134. The metallization stack 108 includes a plurality of metal interconnect layers disposed within one or more interlayer dielectric (ILD) layers 106. ILD layer 106 may include one or more of a low-k dielectric layer (i.e., a dielectric with a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide). In some embodiments, BDTI structure 111 may extend through photodiode doped layer 128 and reach ILD layer 106 or gate dielectric layer of transistor device, such as the gate dielectric of transport gate 202.
[0033] The logic die 136 may include a logic device 142 disposed above a logic substrate 140. The logic die 136 may also include a metallization stack 144 disposed within an ILD layer 146 covering the logic device 142. The image sensing die 134 and the logic die 136 may be bonded face-to-face, face-to-back, or back-to-back. As an example, Figure 4 A face-to-face bonding structure is shown, wherein a pair of intermediate bonding dielectric layers 138, 148 and bonding pads 150, 152 are arranged between an image sensing die 134 and a logic die 136, and are bonded to metallized stacks 108, 144 respectively via fusion or eutectic bonding structures.
[0034] Figures 6-20Cross-sectional views 600-2000 illustrate some embodiments of an image sensor having a photodiode surrounded by a BDTI structure with a doped pad. In some embodiments, the formation of the BDTI structure includes etching a deep trench followed by a periodic cleaning process, such that a defect layer is removed and the sidewall surfaces of the deep trench are smoothed. A doped pad is then formed on the smooth sidewall surfaces of the deep trench by an epitaxial deposition process before filling the remaining space of the deep trench. Thus, the sidewall profile of the BDTI structure is formed with a less curved neck, which can improve the performance of the image sensor. Although various doping types are provided for different doping regions, it should be understood that reverse doping types can be used for these doping regions to achieve a reverse image sensor device structure.
[0035] like Figure 6 As shown in cross-sectional view 600, a substrate 102' is provided for the image sensing die 134. In various embodiments, the substrate 102' may include any type of semiconductor body (e.g., silicon / germanium / CMOS block, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, and any other type of semiconductor and / or epitaxial layer formed thereon and / or otherwise associated therewith. For example, a pixel array deep p-type well 132 may be formed on the processing substrate 102. The processing substrate 102 may be a highly doped p-type substrate layer or may be composed of a highly doped p-type substrate layer. A pixel array deep n-type well 130 may be formed on the pixel array deep p-type well 132. The pixel array deep n-type well 130 and the pixel array deep p-type well 132 may be formed by an implantation process. In some embodiments, a photodiode doped layer 128 is formed as the upper portion of the substrate 102'. The photodiode doped layer 128 may be formed by a p-type epitaxial process. In some embodiments, a plurality of shallow trench isolation (STI) structures 402 are formed at the boundary and / or between adjacent pixel regions 103a, 103b, from the front side 122 of the image sensing die 134 to a location within the photodiode doped layer 128. One or more STI structures 402 can be formed by selectively etching the front side 122 of the image sensing die 134 to form shallow trenches, and subsequently forming oxide within the shallow trenches.
[0036] like Figure 7As shown in cross-sectional view 700, dopant material is implanted into the photodiode doped layer 128 to form doped regions. Multiple photodiode doped pillars 104a can be formed by implanting n-type dopant material into pixel regions 103a and 103b, respectively. Multiple doped shallow isolation wells 110 can be formed by implanting p-type dopant material into the photodiode doped layer 128 between adjacent pixel regions 103a and 103b. Multiple doped shallow isolation wells 110 can be formed from the front side 122 of the image sensing die 134 to a location deeper than the STI structure 402. The doped shallow isolation wells 110 can be centered and aligned with the STI structure 402. In some embodiments, the photodiode doped layer 128 can be selectively implanted according to a patterned mask layer (not shown) including photoresist.
[0037] like Figure 8 As shown in cross-sectional view 800, a transmission gate 202 is formed over the front side 122 of the image sensing die 134. The transmission gate 202 can be formed by depositing a gate dielectric layer and a gate electrode layer over a substrate 102'. The gate dielectric layer and the gate electrode layer are then patterned to form a gate dielectric 802 and a gate electrode 804. In some embodiments, an implantation process is performed within the front side 122 of the image sensing die 134 to form a floating diffusion well 204 along one side of the transmission gate 202 or the opposite sides of a pair of transmission gates 202.
[0038] like Figure 9 As shown in cross-sectional view 900, a metallization stack 108 can be formed on the front side 122 of the image sensing die 134. In some embodiments, the metallization stack 108 can be formed by forming an ILD layer 106 on the front side 122 of the image sensing die 134, the ILD layer comprising one or more ILD materials. The ILD layer 106 is then etched to form vias and / or metal trenches. The vias and / or metal trenches are then filled with a conductive material to form a plurality of metal interconnect vias 510 and metal lines 512. In some embodiments, the ILD layer 106 can be deposited using physical vapor deposition techniques (e.g., PVD, CVD, etc.). A plurality of metal interconnect layers can be formed using deposition processes and / or electroplating processes (e.g., electroplating, electroless plating, etc.). In various embodiments, the plurality of metal interconnect layers can include, for example, tungsten, copper, or aluminum-copper.
[0039] like Figure 10As shown in cross-sectional view 1000, the image sensing die 134 can then be bonded to one or more other dies. For example, the image sensing die 134 can be bonded to a logic die 136 having a logic device 142. The image sensing die 134 and the logic die 136 can be bonded face-to-face, face-to-back, or back-to-back. For example, the bonding process can use a pair of intermediate bonding dielectric layers 138, 148 and bonding pads 150, 152 to bond the metallized stacks 108, 144 of the image sensing die 134 and the logic die 136. The bonding process can include fusion or eutectic bonding processes. The bonding process can also include a hybrid bonding process that includes metal-to-metal bonding of bonding pads 150, 152 and dielectric-to-dielectric bonding of intermediate bonding dielectric layers 138, 148. An annealing process can be performed after the hybrid bonding process and can be carried out in a temperature range between about 250°C and about 450°C for a time ranging from about 0.5 hours to about 4 hours.
[0040] like Figure 11 As shown in cross-sectional view 1100, the image sensing die 134 is thinned on the back side 124 opposite to the front side 122. The thinning process can partially or completely remove the processing substrate 102 (see Figure 1100). Figure 10 And allows radiation to reach the photodiode 104 through the back surface 124 of the image sensing die 134. In some embodiments, the image sensing die 134 is thinned to expose the photodiode doped pillar 104a, so that radiation can more easily reach the photodiode. Then, the BDTI structure formed later or the semiconductor layer therein (e.g., see...) Figure 16 The BDTI structure 111 or doped pad 114 in the image sensing die 134 can be formed on the surface of the photodiode doped pillar 104a. The substrate 102' can be thinned by etching the back side 124 of the image sensing die 134. Alternatively, the substrate 102' can be thinned by mechanically grinding the back side 124 of the image sensing die 134. For example, the substrate 102' can be first ground to a thickness between about 17 μm and about 45 μm. Then, an erosive wet etching process can be applied to further thin the substrate 102'. Examples of etchants can include hydrogen fluoride / nitric acid / acetic acid (HNA). Then, a chemical mechanical process and a tetramethylammonium hydroxide (TMAH) wet etching process can be performed to further reduce the thickness to between about 2.8 μm and about 7.2 μm, so that radiation can pass through the back side 124 of the image sensing die 134 to reach the photodiode 104.
[0041] like Figure 12As shown in cross-sectional view 1200, substrate 102' is selectively etched to form a deep trench 1202 laterally separating photodiode 104 within the back surface 124 of image sensing die 134. In some embodiments, substrate 102' can be etched by forming a mask layer on the back surface 124 of image sensing die 134. Substrate 102' is then exposed to an etchant in areas not covered by the mask layer. The etchant etches substrate 102' to form a deep trench 1202 extending into substrate 102'. In some alternative embodiments, when forming the deep trench 1202, substrate 102' or photodiode doped layer 128 is thoroughly etched in depth, and the deep trench 1202 extends through substrate 102' and can reach ILD layer 106, thereby achieving complete isolation. In various embodiments, the mask layer may comprise a nitride (e.g., SiN) or photoresist patterned using a photolithography process. The mask layer may also comprise a thickness ranging from about 200 angstroms. With approximately 1000 Angers The photodiode 1202 is formed by atomic layer deposition (ALD) or plasma-enhanced CVD of oxide layers. In various embodiments, the etchant may include a dry etchant with etching chemicals, including fluorine substances (e.g., CF4, CHF3, C4F8, etc.) or a wet etchant (e.g., hydrofluoric acid (HF) or tetramethylammonium hydroxide (TMAH)). The depth of the deep trench 1202 may range from about 1.5 μm to about 5 μm. The lateral dimension may range from about 0.1 μm to about 0.3 μm. The deep trench 1202 may have an undercut profile and a curved tip at the top of the deep trench 1202. Moreover, as a result of the etching process, the upper portion of the photodiode doped layer 128 forms a defect layer 128' exposed to the deep trench 1202, and may include native oxides and other unwanted impurity layers.
[0042] like Figure 13 As shown in cross-sectional view 1300, a periodic cleaning process is performed on deep trench 1202 to remove the defect layer 128' and smooth the sidewall surface of deep trench 1202. The periodic cleaning process may include multiple cycles using solutions of hydrofluoric acid (HF) and a mixture of ammonia and hydrogen peroxide (APM). For example, the defect layer 128' can be removed by about 21 nanometers (nm), while each cycle removes about 6 angstroms. Therefore, in addition to smoothing the sidewall surface of the deep trench 1202, the bending tip is also reduced. The bending angle θ2 of the resulting bending tip from the upper sidewall of the deep trench 1202 to a vertical line perpendicular to the plane of the photodiode doped layer 128 can be less than 15°. In some embodiments, the bending angle θ2 is less than 8°, allowing for better filling results. In some embodiments, several other cleaning processes can be performed after the periodic cleaning process. Additional wet cleaning processes using HF and remote plasma SiCoNi cleaning can be performed to further improve the dark current and white pixel characteristics of the image sensor. Before the periodic cleaning process, a pre-cleaning process using an HF solution can be used to remove native oxides. As an example, the pre-cleaning process can use an HF solution at a ratio of 130 (water):1 (chemicals) for 90 seconds, with a waiting time of less than two hours.
[0043] like Figure 14 As shown in cross-sectional view 1400, a doped pad precursor 114' is formed on the sidewalls and bottom surface of the deep trench 1202. In some embodiments, the doped pad precursor 114' can be formed by a low-temperature epitaxial growth process, for example, an epitaxial growth process at a temperature below 500°C. The processing gas may include silane (SiH4), dichlorosilane (DCS or H2SiCl2), diborane (B2H6), hydrogen (H2), or other suitable gases. The epitaxial growth process can be performed in a low-pressure chemical vapor deposition epitaxial tool within a pressure range of about 4 Torr to about 200 Torr and a temperature range of about 400°C to about 490°C to form an epitaxial doped layer as the doped pad precursor 114' with a thickness in the range of about 0.5 nm to about 3 nm (e.g., about 2 nm). The thickness of the doped pad precursor 114' may not exceed 10 nm and may also not exceed 3 nm to adequately limit defects and roughness. Because higher formation temperatures result in lower dopant concentrations and increased roughness, the formation temperature should not exceed 490°C. The doped pad precursor 114' is formed on the smooth sidewall surface of the deep trench 1202, leading to better uniformity than conventional beam-injection techniques, which suffer from the masking effect of the three-dimensional structure and cannot achieve the desired uniformity. The doped pad precursor 114' is formed by delta doping. The boron concentration can be approximately 5 × 10⁻⁶. 19 cm -3 Approximately 2×10 20 cm -3 Within the range, and can be no less than 1×10 19 cm -3 Thicker doped pads or lower dopant concentrations adversely affect the number of white pixels and / or dark current in image sensors.
[0044] like Figure 15As shown in the cross-sectional view 1500, a dopant activation process is then performed to facilitate diffusion and form the doped pad 114. In some embodiments, the dopant activation process includes either a laser annealing process or a dynamic surface annealing process. For example, annealing can be performed using a green laser, and the annealing temperature can be in the range of about 800°C to about 1100°C, with a duration in the range of about 10 nanoseconds to about 100 nanoseconds. The dopant activation process is advantageous for low thermal budget products, especially compared to other methods (such as deposition processes followed by thermal drive-in processes) which either cannot provide sufficient junction depth or are unacceptable for low thermal budget products due to the high-temperature junction drive-in and annealing used for damage recovery and dopant activation.
[0045] like Figure 16 As shown in the cross-sectional view 1600, the deep trench 1202 is then filled with a dielectric material. In some embodiments, a high-k dielectric pad 113 is formed within the deep trench 1202 along the doped pad 114. The high-k dielectric pad 113 can be formed by a deposition technique and may include alumina (AlO), hafnium oxide (HfO), tantalum oxide (TaO), or other dielectric materials with a dielectric constant greater than silicon oxide. The doped pad 114 and the high-k dielectric pad 113 line the sidewalls and bottom surface of the deep trench 1202. In some embodiments, the doped pad 114 and the high-k dielectric pad 113 may extend between the deep trenches 1202 over the back surface 124 of the image sensing die 134. A dielectric fill layer 112 is formed to fill the remaining portion of the deep trench 1202. In some embodiments, a planarization process is performed after forming the dielectric fill layer 112 to form a flat surface extending along the upper surface of the high-k dielectric pad 113 and the dielectric fill layer 112. The doped pad 114, high-k dielectric pad 113, and dielectric filling layer 112 can undergo a planarization process that removes the lateral portions of the covering dielectric filling layer 112, high-k dielectric pad 113, and doped pad 114 directly covering pixel regions 103a, 103b. In some embodiments, the high-k dielectric pad 113 and dielectric filling layer 112 can be deposited using physical vapor deposition or chemical vapor deposition. Thus, a BDTI structure 111 is formed in the substrate 102' extending from the back surface 124 into the photodiode doped layer 128. The BDTI structure 111 is formed between adjacent pixel regions 103a, 103b and isolates these adjacent pixel regions.
[0046] The aforementioned cleaning, epitaxial growth, and activation processes provide an improved conformal doped pad with a more conformal thickness, more uniform doping concentration, and a smoother interface with the underlying photodiode doped layer 128. Surface roughness can also be reduced compared to the surface roughness of doped pads formed without periodic cleaning or epitaxial growth processes.
[0047] Figures 17-19 Some embodiments of a method for forming a color filter 116 covering a photodiode-doped pillar 104a are shown. For example... Figure 17 As shown in cross-sectional view 1700, metal layer 502 and dielectric layer 504 are stacked above substrate 102' along the back side 124 of image sensing die 134. Metal layer 502 can be one or more layers of tungsten, copper, aluminum copper, or titanium nitride, or composed of one or more layers of tungsten, copper, aluminum copper, or titanium nitride. Other suitable metallic materials are also within the scope of this disclosure. Dielectric layer 504 can be one or more layers of silicon dioxide, silicon nitride, or combinations thereof, or composed of one or more layers of silicon dioxide, silicon nitride, or combinations thereof. Dielectric layer 504 can be used as a hard mask layer. Figure 18 As shown in cross-sectional view 1800, the metal layer 502 and dielectric layer 504 are etched to form a composite grid 506. The opening 1802 can be centrally aligned with the photodiode-doped pillars 104a, such that the composite grid 506 is arranged around and between the photodiode-doped pillars 104a. Alternatively, the opening 1802 can be laterally displaced or offset from the photodiode-doped pillars 104a in at least one direction, such that the composite grid 506 at least partially covers the photodiode-doped pillars 104a. A dielectric pad 508 is then formed to line the sidewalls and top of the composite grid 506 and to line the opening 1802. The dielectric pad 508 can be formed using conformal deposition techniques (e.g., chemical vapor deposition (CVD) or physical vapor deposition (PVD)). The dielectric pad 508 can be formed, for example, from an oxide (such as silicon dioxide). Figure 19As shown, a color filter 116 for a corresponding pixel sensor is formed in the opening 1802 of the corresponding pixel sensor. The color filter layer is formed of a material that allows light of the corresponding color to pass through while blocking light of other colors. Furthermore, the color filter 116 can be formed using assigned colors. For example, the color filter 116 can be formed using assigned red, green, and blue colors alternately. The color filter 116 can have an upper surface aligned with the upper surface of the composite grid 506. The color filter 116 can be laterally shifted or offset from the photodiode doped pillar 104a of the corresponding pixel sensor in at least one direction. Depending on the degree of shift or offset, the color filter 116 can partially fill the opening of the corresponding pixel sensor and can partially fill the opening of a pixel sensor adjacent to the corresponding pixel sensor. Alternatively, the color filter 116 can be symmetrical about a vertical axis aligned with the center of the photodiode of the corresponding pixel sensor. The process for forming the color filter 116 can include: forming a color filter layer and patterning the color filter layer for each of the different assigned colors. The color filter layer can be planarized after its formation. Patterning can be achieved by forming a patterned photoresist layer over the color filter layer, applying an etchant to the color filter layer according to the pattern of the photoresist layer, and removing the patterned photoresist layer.
[0048] like Figure 20 As shown, a microlens 118 corresponding to a pixel sensor is formed above a color filter 116 of the corresponding pixel sensor. In some embodiments, multiple microlenses can be formed by depositing microlens material over multiple color filters (e.g., by spin coating or deposition process). A microlens template having a curved upper surface is patterned over the microlens material. In some embodiments, the microlens template may include a photoresist material that is exposed using a distributed exposure light dose (e.g., for negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed, and baked to form a circular shape. The microlens 118 is then formed by selectively etching the microlens material according to the microlens template.
[0049] Figure 21 Flowcharts of some embodiments of a method 2100 for forming an image sensor having a photodiode surrounded by a BDTI structure with a doped layer are shown.
[0050] While the disclosed method 2100 is shown and described herein as a series of actions or events, it will be appreciated that the order in which these actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown may be necessary to implement one or more aspects or embodiments described herein. Further, one or more actions in the actions described herein may be performed in one or more separate actions and / or phases.
[0051] At action 2102, a substrate is prepared for the image sensing die. A photodiode and a doped isolation well are formed in the substrate from the front side of the image sensing die. In some embodiments, an epitaxial layer is formed over the processed substrate as a photodiode doped layer, and photodiode doped pillars and / or doped isolation wells can be formed by implanting dopant material into the epitaxial layer. Doped isolation wells can be formed by selective implantation to form a plurality of pillars extending into the photodiode doped layer. In some embodiments, a shallow trench isolation region can be formed within the front side of the image sensing die by selectively etching the substrate to form a shallow trench and subsequently forming a dielectric (e.g., oxide) within the shallow trench. Figure 6-7 Cross-sectional views corresponding to some embodiments of action 2102 are shown.
[0052] At action 2104, a transmission gate is formed on the front side of the image sensing die. Then, a metallization stack is formed over the transmission gate. Figures 8-9 Cross-sectional views corresponding to some embodiments of action 2104 are shown.
[0053] At action 2106, in some embodiments, the image sensor is coupled with one or more other dies (such as logic dies) or other image sensing dies. Figure 10 Cross-sectional views corresponding to some embodiments of action 2106 are shown.
[0054] At action 2108, the substrate is selectively etched to form deep trenches between adjacent sensing pixel regions and extending from the back side of the image sensing die into the substrate. The centerline of the deep trenches may be aligned with the centerline of the doped isolation wells and / or shallow trench isolation regions. In some embodiments, the substrate is thinned before etching to form the deep trenches. The processed substrate may be partially or completely removed from the back side of the image sensing die. Figures 11-12 Cross-sectional views corresponding to some embodiments of action 2108 are shown.
[0055] In step 2110, the deep trench is periodically cleaned. Figure 13Cross-sectional views corresponding to some embodiments of action 2110 are shown.
[0056] At action 2112, a doped pad is formed along the sidewalls and bottom of the deep trench. In some embodiments, the doped pad can be formed by a low-temperature epitaxial process. Figure 14 Cross-sectional views corresponding to some embodiments of action 2112 are shown.
[0057] At step 2114, an annealing process is performed to facilitate the diffusion of dopant from the doped substrate to the underlying photodiode doped layer. Figure 15 Cross-sectional views corresponding to some embodiments of action 2114 are shown.
[0058] At action 2116, the remaining space of the deep trench is filled with dielectric material. A high-k dielectric pad can be formed within the deep trench onto the doped pad. Figure 16 Cross-sectional views corresponding to some embodiments of action 2116 are shown.
[0059] At action 2118, an anti-reflective layer and a composite grid are formed on the back side of the image sensing die. Figures 17-18 Cross-sectional views corresponding to some embodiments of action 2118 are shown.
[0060] At action 2120, a color filter and a microlens are formed on the back side of the image sensing die. Figures 19-20 Cross-sectional views corresponding to some embodiments of action 2120 are shown.
[0061] Therefore, this disclosure relates to an image sensor having a photodiode surrounded by a BDTI structure, and an associated method of forming it. The BDTI structure includes a doped substrate lining the sidewall surfaces of a deep trench and a dielectric layer filling the remaining space of the deep trench. By forming the disclosed BDTI structure, which acts as a doped well and isolation structure, the implantation process from the front side of the image sensing die is simplified, and thus the exposure resolution and full-well capacity of the photodiode are improved, while blurring and crosstalk are reduced. By performing a periodic cleaning process to remove defect layers within the deep trench of the BDTI structure and then forming a thin epitaxial doped pad in the deep trench, a smooth interface is provided between the doped pad and the underlying photodiode doped layer, thus significantly reducing white pixels and dark current. In some other embodiments, the BDTI structure can be used outside of the image sensor, such as in semiconductor devices including deep trench capacitors.
[0062] In some embodiments, this disclosure relates to a method of forming an image sensor. A plurality of photodiodes for multiple pixel regions are formed from the front side of an image sensing die. The photodiodes are formed having photodiode doped pillars of a first doping type surrounded by a photodiode doped layer having a second doping type different from the first doping type. Deep trenches are formed between adjacent pixel regions by etching the photodiode doped layer from the back side of the image sensing die. During the etching of the deep trenches, the upper portion of the photodiode doped layer exposed to the deep trenches is converted into a defect layer. Cyclic cleaning processes using at least two different etchants are performed alternately to remove the defect layer. Doped pads of the second doping type are formed to line the sidewall surfaces of the deep trenches. A dielectric fill layer is formed to fill the interior space of the deep trenches to form a backside deep trench isolation (BDTI) structure.
[0063] In the above method, the cycle cleaning process includes alternating multiple cycles using a solution of hydrofluoric acid and a mixture of ammonia and hydrogen peroxide.
[0064] In the above method, the periodic cleaning process removes at least about 1 nm to 20 nm of the upper portion of the photodiode doped layer.
[0065] In the above method, the doped pad is formed by epitaxial deposition at a temperature below 500°C, followed by a dopant activation process.
[0066] In the above method, the doped pad is formed to have a thickness of less than 10 nm.
[0067] In the above method, the doped pad is formed by delta doping of boron, with a boron doping concentration greater than about 1 × 10⁻⁶. 19 cm -3 .
[0068] In the above method, the dopant activation process is a laser annealing process.
[0069] In the above method, the bending width and bending angle of the deep trench are reduced after the cycle cleaning process.
[0070] In the above method, the BDTI structure is formed through the photodiode doped layer.
[0071] In the above method, the doped pad is formed to reach the surface of the doped pillar of the photodiode.
[0072] In some alternative embodiments, this disclosure relates to a method of forming an image sensor. The method includes forming photodiodes for multiple pixel regions from the front side of an image sensing die. The photodiodes are formed having photodiode doped pillars of a first doping type surrounded by a photodiode doped layer having a second doping type different from the first doping type. Doped isolation wells are formed from the front side of the image sensing die by implanting dopant into the photodiode doped layer via multiple implantation processes. A gate structure and a metallization stack are formed on the front side of the image sensing die, wherein the metallization stack includes multiple metal interconnect layers disposed within one or more interlayer dielectric layers. The image sensing die is bonded to a logic die from the front side, wherein the logic die includes logic devices. Deep trenches are formed between adjacent pixel regions by etching from the back side of the image sensing die. Periodic cleaning processes using at least two different etchants are performed alternately to remove the exposed upper portions of the photodiode doped layer in the deep trenches. Doped pads of a second doping type are formed to line the sidewall surfaces of the deep trenches. An internal space is formed to fill the deep trench to form a dielectric filling layer for a back deep trench isolation (BDTI) structure.
[0073] In the above method, the cleaning process includes alternating multiple cycles using HF and a solution of a mixture of ammonia and hydrogen peroxide (APM).
[0074] The method further includes: forming an STI structure between adjacent pixel regions from the front side of the image sensing die to a position within the photodiode doped layer; wherein the deep trench is formed to expose the STI structure.
[0075] The method described above also includes thinning the back side of the image sensing die before forming the deep trench to expose the photodiode doped pillars.
[0076] In the above method, the deep trench is formed to expose the doped isolation trap.
[0077] In other embodiments, this disclosure relates to an image sensor. The image sensor includes an image sensing die having a front side and a back side opposite the front side. A plurality of pixel regions are disposed within the image sensing die and each includes a photodiode configured to convert radiation entering from the back side of the image sensing die into an electrical signal. The photodiode includes a photodiode doped pillar of a first doping type surrounded by a photodiode doped layer having a second doping type different from the first doping type. A BDTI structure is disposed between adjacent pixel regions and extends from the back side of the image sensing die to a location within the photodiode doped layer. The BDTI structure includes a doped pad of the second doping type and a dielectric filling layer, the doped pad lining the sidewall surfaces of the dielectric filling layer.
[0078] In the aforementioned image sensor, the doped pad and the dielectric filling layer of the BDTI structure extend laterally along the back side of the image sensing die; and wherein the lateral portion of the doped pad is placed on the photodiode doped pillar; wherein the thickness of the doped pad is 1 nm-20 nm, and wherein the boron concentration is approximately 5 × 10⁻⁶. 19 atoms / cm 3 With approximately 2×10 20 atoms / cm 3 Within the range between.
[0079] The image sensor described above further includes: a doped isolation well of the second doping type, placed between the adjacent pixel regions and extending from the front side of the image sensing die to a position within the photodiode doped layer; wherein the doped isolation well is separated from the BDTI structure by the photodiode doped layer.
[0080] The image sensor described above also includes an STI structure placed between adjacent pixel regions from the front side of the image sensing die to a position within the photodiode doped layer; wherein the BDTI structure extends through the STI structure.
[0081] In the aforementioned image sensor, the bending angle of the bent tip at the top corner of the BDTI structure is in the range of approximately 8° to 15°, extending from the upper sidewall of the BDTI structure to a vertical line perpendicular to the transverse plane of the photodiode doped layer.
[0082] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.
Claims
1. A method for forming an image sensor, comprising: Multiple photodiodes for multiple pixel regions are formed from the front side of the image sensing die, wherein the photodiodes are formed as photodiode doped pillars having a first doping type, and the photodiode doped pillars are surrounded by a photodiode doped layer of a second doping type, the second doping type being different from the first doping type; From the front side of the image sensing die, a deep trench is formed between adjacent pixel regions in the photodiode doped layer, wherein the upper portion of the photodiode doped layer exposed in the deep trench is transformed into a defect layer during the etching of the deep trench; The defect layer is removed by alternating cycles of cleaning with at least two different etchants. forming a doped spacer precursor of the second dopant type lining sidewall surfaces of the deep trenches, the doped spacer precursor having a thickness of less than 10 nm and a dopant concentration of greater than 1 x 1019 cm-3 19 -3 ; An annealing process is performed to form a doped pad to facilitate the diffusion of dopant from the doped pad precursor to adjacent portions of the photodiode doped layer; and A dielectric filling layer is formed to fill the internal space of the deep trench, thereby forming a back-side deep trench isolation structure. The periodic cleaning process includes alternating multiple cycles using solutions of hydrofluoric acid and a mixture of ammonia and hydrogen peroxide. The periodic cleaning process reduces the bending angle of the bent tip located at the apex of the deep trench from the upper sidewall of the deep trench to the vertical line perpendicular to the lateral plane of the photodiode doped layer to less than 15°.
2. The method of claim 1, further comprising: A doped isolation trap of the second doping type is formed between the adjacent pixel regions and from the front side of the image sensing die to extend into the photodiode doping layer.
3. The method according to claim 1, wherein, The periodic cleaning process removes at least 1 nm to 20 nm of the upper portion of the doped layer of the photodiode.
4. The method according to claim 1, wherein, The doped pad precursor is formed by an epitaxial deposition process at a temperature below 500°C.
5. The method according to claim 1, wherein, The annealing process includes a multi-round dynamic surface annealing process.
6. The method according to claim 1, wherein, The doped liner is formed to have a surface doping concentration greater than 1 x 1019cm-3 and a depth of 20 nm at which the doping concentration decreases to 1 x 1018cm-3. 20 cm -3 -3 and a depth of 20 nm at which the doping concentration decreases to 1 x 1018cm-3. 15 cm -3 -3 and a depth of 20 nm at which the doping concentration decreases to 1 x 1018cm-3.
7. The method according to claim 4, wherein, The annealing process is a laser annealing process.
8. The method according to claim 1, wherein, The periodic cleaning process reduces the bending width and bending angle of the deep trench.
9. The method according to claim 1, wherein, The back deep trench isolation structure is formed through the doped layer of the photodiode.
10. The method according to claim 1, wherein, The doped pad is formed to reach the surface of the doped pillar of the photodiode.
11. A method for forming an image sensor, comprising: Photodiodes for multiple pixel regions are formed from the front side of an image sensing die, wherein the photodiodes are formed as photodiode doped pillars having a first doping type, the photodiode doped pillars being surrounded by a photodiode doped layer of a second doping type, the second doping type being different from the first doping type; A doped isolation well is formed from the front side of the image sensing die by implanting a dopant into the doped layer of the photodiode via at least one implantation process. A gate structure and a metallization stack are formed on the front side of the image sensing die, wherein the metallization stack includes a plurality of metal interconnect layers disposed within one or more interlayer dielectric layers. The image sensing die is bonded to a logic die from the front side of the image sensing die, wherein the logic die includes logic devices; Deep trenches are formed between adjacent pixel regions on the back side of the image sensing die; A cleaning process is performed to remove the exposed portion of the photodiode doped layer in the upper part of the deep trench; Forming a doped pad of the second doping type to line the sidewall surface of the deep trench; and A dielectric filling layer is formed to fill the internal space of the deep trenches to form a back-side deep trench isolation structure. The cleaning process includes alternating multiple cycles using solutions of hydrofluoric acid and a mixture of ammonia and hydrogen peroxide. The cleaning process reduces the bending angle of the bent tip at the apex of the deep trench from the upper sidewall of the deep trench to the vertical line perpendicular to the transverse plane of the photodiode doped layer to less than 15°.
12. The method according to claim 11, wherein, The doped isolation trap is separated from the deep trench by the photodiode doped layer.
13. The method of claim 11, further comprising: A shallow trench isolation structure is formed between adjacent pixel regions from the front side of the image sensing die to the position within the doped layer of the photodiode; The deep trench is formed to expose the shallow trench isolation structure.
14. The method of claim 11, further comprising thinning the back side of the image sensing die before forming the deep trench to expose the photodiode doped pillar.
15. The method according to claim 11, wherein, The deep trench is formed to expose the doped isolation trap.
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