Spad photodiode

Abstract

Embodiments of this disclosure relate to SPAD photodiodes. The photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a generally hemispherical shape, and a generally hemispherical core having a second conductivity type different from the first conductivity type within the first region. An epitaxial layer covers the semiconductor substrate and embeds the first region and the core.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. 2103040, filed on March 25, 2021, the contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates generally to photodiodes, and more particularly to single-photon avalanche diodes (SPADs) and methods for manufacturing the same. Background Technology

[0004] A photodiode is a semiconductor device with the ability to capture radiation from the optical domain and convert it into an electrical signal. A SPAD photodiode consists of a PN junction reverse-biased to a voltage higher than its avalanche voltage. Under these conditions, photogenerated single carriers in the depletion region can trigger an avalanche caused by impact ionization. The resulting current flows continuously until the avalanche is extinguished. SPAD photodiodes can detect very low intensity light radiation, making them particularly useful for single-photon detection and photon counting.

[0005] In addition to the PN junction, SPAD photodiodes typically include a guard ring surrounding the PN junction. Specifically, the guard ring prevents premature triggering of the photodiode at the junction's periphery. It also reduces the likelihood of minority carriers entering from the junction's periphery.

[0006] Within the plane of the upper surface of a photodiode, the size of the guard ring determines the fill factor (FF) of the photodiode.

[0007] As electronic devices become increasingly smaller, even smaller photodiodes are needed.

[0008] There is a need to improve SPAD photodiodes and their manufacturing methods. Summary of the Invention

[0009] One embodiment addresses all or part of the known drawbacks of SPAD photodiodes.

[0010] One embodiment provides a photodiode having: a first substantially hemispherical buried region of the first conductivity type in a semiconductor substrate; and a substantially hemispherical core of a second conductivity type different from the first conductivity type in the first region.

[0011] One embodiment provides a method of manufacturing a photodiode, comprising forming in a semiconductor substrate of a first conductivity type: a first substantially hemispherical buried region of the first conductivity type; and a substantially hemispherical core having a second conductivity type different from the first conductivity type in the first region.

[0012] According to one embodiment, the core and the first region are formed in a trap separated by peripheral insulating trenches.

[0013] According to one embodiment, the first region and the core are formed from the first side of the substrate.

[0014] According to one embodiment, the core and the first region are located at the center of the well in a plane parallel to a first surface of the substrate.

[0015] According to one embodiment, all or part of the first region is formed by inoculating a dopant of a first conductivity type at an angle greater than 20°, preferably between 25° and 45°, relative to the normal of the first surface of the substrate.

[0016] According to one embodiment, the first region is formed by repeatedly tilting and implanting dopants at different rotation angles of the substrate, the structure rotating about an axis orthogonal to the first surface and passing through the center of the substrate.

[0017] According to one embodiment, on the side opposite to the first surface, the substrate is gradient-doped from the first surface to the second surface of the substrate in an increasing manner.

[0018] According to one embodiment, the diameter of the core is between 400 nm and 800 nm, preferably on the order of 600 nm, in a plane parallel to the first surface of the substrate.

[0019] According to one embodiment, an epitaxial layer is covered on the first surface of the substrate.

[0020] According to one embodiment, the epitaxial layer has a thickness of approximately 500 nm.

[0021] According to one embodiment, the epitaxial layer is formed with a surface parallel to a first surface of the substrate.

[0022] According to one embodiment, the photodiode or method includes: a second region of a second conductivity type aligned with, on, and in contact with the core, the second region of the second conductivity type being flush with the surface of the epitaxial layer.

[0023] According to one embodiment, the method includes a photodiode or the method includes a third annular region for contact recovery located between the second region and the insulating trench, the third region being closer to the insulating trench than to the second region, the third region being of a first conductivity type, and the third region being flush with the surface of the epitaxial layer.

[0024] According to one embodiment, a first electrode (preferably a cathode) is formed on and in contact with a second region, and a second electrode (preferably an anode) is formed on and in contact with a third region.

[0025] According to one embodiment, the maximum height of the core is approximately 500 nm.

[0026] According to one embodiment, the maximum height of the first region is approximately 1µm.

[0027] According to one embodiment, a single mask is used to form the first region and the core.

[0028] According to one embodiment, the method includes the following sequential steps: forming a first region of a first conductivity type in a semiconductor substrate of a first conductivity type by tilting implantation; forming a basic hemispherical core of a second conductivity type different from the first conductivity type in the first region; and epitaxially growing from the substrate to bury the first region and form an epitaxial layer.

[0029] According to one embodiment, the method includes the following sequential steps: forming a basic hemispherical core of a second conductivity type different from the first conductivity type in a semiconductor substrate of a first conductivity type; forming a first region of the first conductivity type under the core by tilting implantation; and epitaxially growing from the substrate to bury the first region and form an epitaxial layer. Attached Figure Description

[0030] The above features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration, and are not limited to the accompanying drawings, wherein:

[0031] Figure 1 This is a partial top view schematic diagram of one embodiment of a photodiode.

[0032] Figure 2 yes Figure 1 A schematic diagram of a partial cross-section in plane AA.

[0033] Figure 3 for Figure 1 and Figure 2 Cross-sectional view of the photodiode manufacturing process.

[0034] Figure 4 yes Figure 1 and Figure 2 A cross-sectional view of another step in the manufacturing process of a photodiode.

[0035] Figure 5 yes Figure 1 and Figure 2 A cross-sectional view of another manufacturing step of a photodiode.

[0036] Figure 6 yes Figure 1 and Figure 2 A cross-sectional view of another manufacturing step of a photodiode.

[0037] Figure 7 yes Figure 1 and Figure 2 A cross-sectional view of another manufacturing step of a photodiode.

[0038] Figure 8 yes Figure 1 and Figure 2 A cross-sectional view of another manufacturing step of a photodiode.

[0039] Figure 9 yes Figure 1 and Figure 2 Cross-sectional view of another manufacturing step of the photodiode; and

[0040] Figure 10 This explains the participation of photons. Figure 1 and Figure 2 The graph shows the probability of photodiode avalanche. Detailed Implementation

[0041] Similar features have been designated by reference to similarity in the various figures. Specifically, structural and / or functional features common in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0042] For clarity, only the operation and elements that help to understand the embodiments described herein are described in detail.

[0043] Unless otherwise stated, when referring to two elements connected together, this means a direct connection without any intermediate elements other than conductors; when referring to two elements coupled together, this means that the two elements can be connected or coupled through one or more other elements.

[0044] In the following disclosure, unless otherwise stated, when referring to absolute positional qualifiers such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative positional qualifiers such as the terms “above,” “below,” “upper,” “lower,” etc., or directional qualifiers such as “horizontal,” “vertical,” etc., refer to the directions shown in the figures.

[0045] Unless otherwise specified, the terms “approximately,” “roughly,” “substantially,” and “on the order of…” are used to indicate less than 10%, preferably less than 5%.

[0046] To miniaturize single-photon avalanche diode (SPAD) type photodiodes, one can consider reducing the size of its various components in the same proportion (proportional), especially within the circuit plane in which the photodiode is integrated. However, for it to function, there is a critical dimension in the width of the guard ring between the active region and the periphery of the photodiode.

[0047] Furthermore, the smaller the surface area of ​​the active region in a plane, the lower the fill factor. However, for efficiency issues related to the active region, a high fill factor is usually sought.

[0048] According to the present invention, the PN junction of the photodiode in the substrate is provided in the form of a first hemispherical region and a core that is also hemispherical, the first hemispherical region of a first conductivity type including the hemispherical core of a second conductivity type. Among other things, this allows for maximizing the size of the active region while miniaturizing the photodiode.

[0049] More specifically, it can be envisioned that a first hemispherical region is formed by obliquely injecting dopants from the substrate surface, then a hemispherical core is formed by normally injecting dopants from the substrate surface, and finally, the PN junction is buried by a layer formed by epitaxially depositing a substrate in which the PN junction is formed.

[0050] Figure 1 and Figure 2 These are a partial top view and a cross-sectional schematic diagram of one embodiment of the photodiode 1. More specifically, Figure 2 It shows that according to Figure 1 The cross-sectional view of photodiode 1 with cross-section AA.

[0051] According to a preferred embodiment, photodiode 1 is a SPAD type photodiode.

[0052] Figure 1 and Figure 2 The photodiode 1 shown includes, in a semiconductor substrate 11 of a first conductivity type (e.g., P-type), a first buried region 13 of the first conductivity type; and a core 15 having a second conductivity type (e.g., N-type) different from the first conductivity type within the first buried region 13.

[0053] The first region 13 and the core 15 are buried to form a PN junction.

[0054] Substrate 11 includes, for example, surfaces 11s, in Figure 2 The upper part in the direction, and surface 11i, opposite surface 11s, in Figure 2 The lower part in the direction.

[0055] The substrate 11 is, for example, topped or covered by the epitaxial layer 12. The epitaxial layer 12 includes a lower surface located on and in contact with the upper surface 11s of the substrate 11, and an upper layer 12s located on the opposite side of and parallel to the lower surface of the epitaxial layer 12.

[0056] The first region 13 and the core 15 are each substantially hemispherical in shape. "Substantially hemispherical" is defined as having at least one circular non-planar outer surface, that is, a shape that is part of a sphere, ellipsoid, geode, or other spherical profile.

[0057] Core 15 has a basic solid hemisphere defined by a non-planar and a planar shape. In other words, core 15 has the shape of a portion of a solid sphere, a portion of a solid ellipsoid, a portion of a solid cavity, or a portion of any other solid sphere. This planar shape corresponds to the upper surface or base of core 15 and is coplanar with face 11s. For example, the base of core 15 has a shape similar to a disk or elliptical disk.

[0058] The first embedded region 13 integrates the core 15 and has a substantially hollow hemispherical shape, i.e., it has the shape of a portion of a hollow sphere, a portion of a hollow ellipsoid, a portion of a hollow cavity, or a portion of any other hollow sphere. The first embedded region 13 has a circular, elliptical (void), or annular base coplanar with the substrate surface 11s. The inner circumference of the circle or annulus at the base of the first embedded region 13 corresponds to the outer circumference of the base of the core 15.

[0059] The diameter of the base of the core 15 is preferably between 400 nm and 800 nm, and more preferably in the range of 600 nm.

[0060] According to one embodiment, the respective bases of the buried first region 13 and the core 15 are flush with the surface 11s of the substrate 11. Therefore, the core 15 and the buried first region 13 are buried at a depth p corresponding to the thickness of the epitaxial layer 12, relative to the surface 12s of the photodiode 1. This depth p is, for example, between 200 nm and 800 nm, preferably around 500 nm.

[0061] The maximum height h1 of the embedded first region 13 is, for example, between 500 nm and 1.5 µm, preferably on the order of 1 µm. The maximum height h2 of the core 15 is, for example, between 200 nm and 800 nm, preferably on the order of 500 nm. The maximum height of the embedded first region 13 of the core 15 refers to the distance between its base and its bottom, the bottom corresponding to the portion of the embedded first region 13 of the core 15 closest to surface 11i.

[0062] For example, the first embedded region 13 has a thickness equal to the difference between heights h1 and h2. If applicable, depending on the manufacturing technique used, the thickness of the first embedded region 13 decreases between its maximum value (perpendicular to the center of its base) and its minimum value at the edge of the base.

[0063] According to one embodiment, the buried first region 13 is lightly doped (i.e., contains less than about 10). 18atoms / cm 3 The doping concentration is [missing information], while the core is heavily doped (i.e., contains approximately more than 10 [missing information] atoms). 19 atoms / cm 3 (doping atom concentration).

[0064] The substrate 11 has a thickness, for example, between 1 µm and 10 µm, preferably about 4.5 µm. The epitaxial layer 12 has a thickness, for example, between 100 nm and 800 nm, preferably about 500 nm.

[0065] The substrate 11 is preferably gradient-doped, increasing from the upper surface 11s to the lower surface 11i on the opposite side. In other words, the dopant concentration in the substrate 11 is non-uniform, with a higher dopant concentration near surface 11i than near surface 11s. For example, the dopant concentration in the substrate 11 near surface 11i is 10. 18 atoms / cm 3 The doping concentration of substrate 11 near surface 11s is 10. 14 atoms / cm 3 This helps to reach beyond the depletion region, that is, away from the PN junction, and the displacement of photons in the vicinity of the depletion region.

[0066] The first region 13 and the core 15 are embedded, for example, in a well 17 extending into the substrate 11 and the epitaxial layer 12, and are defined by a deep trench isolation (DTI) 19. The trench 19 surrounds the well 17. For example, when viewed from above, the trench 19 has the shape of a circular or elliptical ring, a square frame, or a frame with rounded corners (referred to in the art as a squircle) (see, Figure 1 Alternatively, groove 19 can have any closed shape. According to... Figure 1 and Figure 2 In the embodiment shown, the trench 19 extends through the entire thickness of the substrate 11 and the epitaxial layer 12.

[0067] The first region 13 and the core 15 are preferably located in a plane parallel to the surface 11s, at the center of the surface 11s defined by the trench 19.

[0068] according to Figure 1 and Figure 2In the illustrated embodiment, the photodiode 1 includes a second region 21. The second region 21 is preferably of a second conductivity type, such as N-type. The second region 21 is preferably located in the epitaxial layer 12, on and in contact with the core 15. The second region 21 has, for example, a cylindrical shape, with one base coplanar with surface 12s and another base coplanar with surface 11s. For example, the bases of the cylinder correspond to two planes and a parallel plane of the cylinder. The base of the second region 21 coplanar with surface 12s is preferably coplanar with the base of the core 15. The diameters of the two bases of the second region 21 are preferably equal to or substantially equal to the diameter of the base of the core 15. The second region 21 preferably extends from surface 12s to a depth corresponding to depth p.

[0069] according to Figure 1 and Figure 2 In the illustrated embodiment, photodiode 1 includes a contact recovery third region 23. The third region 23 is preferably of a first conductivity type, such as P-type. Preferably, the third region 23 is located in the well 17 and is flush with the surface 12s. The third region 23 has a shape such as a circular or elliptical ring, a square frame, or a frame with rounded corners, similar to the shape of trench 19, and is contained within trench 19. The third region 23 is preferably closer to trench 19 than the second region 21. The third region 23 preferably extends into the well 17 to a depth between 200 nm and 800 nm, for example, on the order of 500 nm.

[0070] according to Figure 1 and Figure 2 In the embodiment shown, photodiode 1 includes two electrodes 25 and 27.

[0071] Electrode 25 (e.g., cathode) is located, for example, opposite the second region 21. For example, electrode 25 is located on and in contact with the contact recovery fourth region 29 in the second region 21, and is flush with surface 12s. Electrode 25 has a shape, for example, parallelepiped, cylindrical, or truncated pyramidal. Alternatively, electrode 25 has any shape that allows the second region 21 to be connected to the overlying metal layer.

[0072] Electrode 27, such as an anode, is located opposite to, for example, above and in contact with, the third region 23. Preferably, in a plan view, electrode 27 has a shape similar to the third region 23. If necessary, an intermediate region is provided between electrode 27 and region 23.

[0073] According to one embodiment, the substrate is made of silicon.

[0074] According to one embodiment, the first conductivity type layer, namely the buried first region 13, substrate 11, and third region 23, is doped with boron (B) atoms. According to one embodiment, the second conductivity type layer, namely the core 15 and the second region 21, is doped with arsenic (As) atoms.

[0075] According to one embodiment, when viewed from above, photodiode 1 is located within a square with a side length of less than 7µm.

[0076] Figures 3 to 9 express Figure 1 and Figure 2 Cross-sectional view of the photodiode manufacturing process.

[0077] Figure 3 It shows Figure 1 and Figure 2 The initial structure of photodiode 1 is shown.

[0078] like Figure 1 and Figure 2 The substrate 11 is gradient-doped, which reduces the phase jitter of the photodiode 1.

[0079] Figure 4 The steps for forming a buried first region 13 in a substrate 11 are shown.

[0080] According to this embodiment, the first region 13 is formed by implanting doped atoms (e.g., boron atoms) into the substrate 11. Figure 4 The dopant injection shown is preferably performed through a mask 31 including an opening 32. Figure 4 The dopant shown is preferably implanted from the upper surface 11s of the substrate 11 in an inclined direction.

[0081] According to one embodiment, the first region 13 is formed at an angle θ, which is calculated relative to a direction perpendicular to the surface 11s and is greater than 20°, for example, between 25° and 45°.

[0082] For example, the oblique injection of dopant into the buried first region 13 gives the buried first region 13 a shape corresponding to a truncated cone near the surface 11s and is substantially hemispherical in depth at the substrate 11.

[0083] According to one embodiment, the buried first region 13 is formed by at least two consecutive implantations of dopant. For example, each implantation is formed at a different angle θ.

[0084] According to one embodiment, the buried first region 13 is formed by at least two consecutive implants, such as four, six, or eight consecutive implants. For example, each implant is formed at a different rotation angle of the structure, with the rotation axis orthogonal to the upper surface of the mask 31 (or the upper surface 11s of the substrate) and passing through the center of the opening 32 of the mask 31 (or the center of the substrate 11).

[0085] According to one embodiment, the implantation energy of the doped atoms is approximately 40 keV.

[0086] The implantation process is performed across the entire wafer to batch all the structures contained in a single semiconductor wafer.

[0087] Figure 5 The steps for forming a core 15 within a buried first region 13 are described. According to one embodiment, the core 15 is formed by injecting dopant atoms (e.g., arsenic atoms) into the buried first region 13. Figure 5 The dopant shown is preferably implanted via a combination of... Figure 4 The same mask 31 used during the injection process is employed. For example, it is performed in a non-tilted orientation in a direction perpendicular to surface 11s. Figure 5 The dopant injection is shown. Because the opening 32 of the mask 31 is narrow, the core 15 is essentially hemispherical.

[0088] According to one embodiment, the injection energy of the doped atoms in core 15 is on the order of 10 keV.

[0089] according to Figure 4 and Figure 5 The embodiments shown, especially the injection type of embedding the first region 13, have a circular or elliptical base.

[0090] According to one embodiment, the core 15 is formed before the first embedded region 13 is formed (i.e., Figure 5 Injection in Figure 4 (Executed before injection).

[0091] Figure 6 The steps for epitaxial growth from substrate 11 to form epitaxial layer 12 are shown.

[0092] according to Figure 6 In the illustrated embodiment, the substrate 11 is epitaxially grown. Epitaxial growth is performed across the entire upper surface 11s. Figure 6 The epitaxial growth shown forms an epitaxial layer 12. The epitaxial layer 12 is located on and in contact with plane 11s. The epitaxial layer 12 includes plane 12s, which... Figure 6 The direction shown is at the top.

[0093] The epitaxial layer 12 preferably has a thickness between 200 nm and 800 nm, for example, on the order of 500 nm.

[0094] exist Figure 6 When the steps shown are completed, the PN junction buried surface 12s formed by the core 15 and the buried first region 13 reaches a depth corresponding to the thickness of the epitaxial layer 12.

[0095] Figure 7 The steps for forming the deep insulating trench 19 are shown.

[0096] According to one embodiment, the insulating trench 19 is formed by a series of etching steps, a step of depositing an insulating coating on the walls of the opening thus formed, and a step of filling the opening. The coating is preferably an oxide, such as silicon oxide. For example, the filling material is polycrystalline silicon.

[0097] According to an exemplary embodiment, in this embodiment, the trench 19 formed in the wafer is through (i.e., completely through the thickness of the substrate 11), and an adhesive wire transfer technique is used to hold the photodiodes that have been etched out until the trench 19 is filled.

[0098] According to another exemplary embodiment, the trench 19 is formed such that it does not extend through the entire thickness of the wafer, and after the trench 19 is formed, a thinning operation is performed on the back side of the substrate 11 such that the lower surface of the trench 19 is eventually flush with the lower surface of the substrate 11.

[0099] A well 17 is formed within a trench 19 by a substrate 11 and an epitaxial layer 12. Figure 7 As shown, the well 17 extends from the upper surface 12s to the base of the substrate 11.

[0100] Then, a protective ring is formed around the PN junction on the substrate 11.

[0101] Figure 8 The steps for forming the second region 21 and the third region 23 are shown.

[0102] According to one embodiment, the second region 21 is formed by implanting doped atoms (e.g., arsenic atoms) into the epitaxial layer 12 opposite to the core 15. To form the second region 21, it is preferable to implant doped atoms (e.g., arsenic atoms) into the epitaxial layer 12 opposite to the core 15. Figure 4 and Figure 5 The same mask 31 used during the injection process is used to perform the injection. For example, the injection is performed with a non-tilted orientation perpendicular to surface 11s.

[0103] According to one embodiment, a third region 23 is formed by implanting dopant atoms (e.g., boron atoms) into epitaxial layer 12. For example, the implantation to form the third region 23 is performed in a non-tilted orientation perpendicular to face 11s.

[0104] According to one embodiment, in order to form the third region 23, the implantation energy of the doped atoms is on the order of 60 keV.

[0105] Figure 9 The steps for forming the contact recovery region 29 and electrodes 25 and 27 are shown.

[0106] The contact recovery region 29 and electrodes 25 and 27 are formed using techniques commonly used in semiconductor device manufacturing in the microelectronics industry.

[0107] Figure 10 This means that the photon arrives Figure 1 and Figure 2 The graph shows the probability of the depletion region of photodiode 1.

[0108] Specifically, the figure illustrates the probability of a photon reaching the depletion region 1 of the photodiode, a probability that is a function of the photon's position in a cross-section orthogonal to surface 11s and passing through the center of core 15. When the voltage applied between the terminals of photodiode 1 corresponds to an avalanche voltage plus an overvoltage, Figure 10 The diagram shown has been implemented. The avalanche voltage is preferably around 17V, while the overvoltage is preferably around 4V. Therefore, the applied voltage is approximately 21V.

[0109] exist Figure 10 In the chart shown, Figure 9 The photodiode 1 in the plane shown is only half illustrated, and in this plane, the photodiode 1 is symmetrical about the central axis.

[0110] Figure 10 The chart shown highlights the protective ring around the PN junction, where the probability of photons participating in the avalanche of photodiode 1 is very low (less than 10%).

[0111] from Figure 10 It is also evident that photons located in the PN junction structure have a high probability of participating in the avalanche of photodiode 1 (probability greater than 50%). Furthermore, it can be seen that photons located in the core structure have a lower probability of participating in the avalanche of photodiode 1 (probability between 10% and 40%).

[0112] One advantage of providing a PN junction with tilted injection is that it maximizes the photosensitive volume, thereby increasing the fill factor and photon detection probability (PDP). Tilted injection also ensures good photon collection throughout the volume. Furthermore, low-energy dopant injection reduces noise and also reduces the size of the well, which in turn reduces the size of the guard ring, resulting in a well diameter of less than 4.48 µm.

[0113] Furthermore, the fact that the PN junction is buried helps to reduce the dark count rate (DCR) by avoiding a large electric field on the surface of the photodiode.

[0114] One advantage of the embodiments and implementation methods described is that they allow avalanche voltages on the order of 20V.

[0115] Another advantage of the embodiments and implementation methods is that they accommodate small photodiodes, for example, with side lengths less than 7µm, such as less than 5µm.

[0116] Another advantage of the embodiments and implementation methods is that they overcome the mask alignment problem for forming the core 15 and embedding the first region 13.

[0117] Furthermore, the gradient doping of the substrate contributes to the reduction of phase jitter in the photodiode.

[0118] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will be readily apparent to them. Specifically, the dopant, doping level, and the thickness or height of layers and regions may vary depending on the application.

[0119] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. A photodiode, comprising: Semiconductor substrate of the first conductivity type; An epitaxial layer covering the top surface of the semiconductor substrate; The first conductivity type has a basic hemispherical buried region in the semiconductor substrate, wherein the basic hemispherical buried region has a top surface that is coplanar with the top surface of the semiconductor substrate; A basic hemispherical core of a second conductivity type, the second conductivity type being different from the first conductivity type, wherein the basic hemispherical core is contained within the basic hemispherical embedment region; and The additional region of the second conductivity type is aligned with the basic hemispherical core and extends through the epitaxial region, and the top surface of the additional region of the second conductivity type is coplanar with the top surface of the epitaxial layer.

2. The photodiode of claim 1, wherein the semiconductor substrate comprises a well defined by a peripheral insulating trench, and wherein the substantially hemispherical core and the substantially hemispherical buried region are formed in the well.

3. The photodiode of claim 2, wherein the basic hemispherical core and the basic hemispherical buried region are positioned at the center of the well in a plane parallel to the top surface of the semiconductor substrate.

4. The photodiode of claim 1, wherein the basic hemispherical buried region and the basic hemispherical core extend from the top surface of the semiconductor substrate into the semiconductor substrate.

5. The photodiode of claim 4, wherein the semiconductor substrate is progressively doped from the top surface to the bottom surface opposite the top surface.

6. The photodiode of claim 4, wherein the basic hemispherical core has a diameter between 400 nm and 800 nm in a plane parallel to the top surface of the semiconductor substrate.

7. The photodiode according to claim 1, wherein the basic hemispherical buried region and the basic hemispherical core form a single-photon avalanche diode (SPAD).

8. The photodiode of claim 1, wherein the epitaxial layer has a thickness of 500 nm.

9. The photodiode of claim 1, wherein the top surface of the epitaxial layer extends parallel to the top surface of the semiconductor substrate.

10. The photodiode according to claim 1, further comprising: In the epitaxial layer, the peripheral region of the first conductivity type surrounds the additional region aligned with the basic hemispherical core in a ring shape.

11. The photodiode of claim 10, wherein the semiconductor substrate includes a well defined by a peripheral insulating trench, and the peripheral region is located between the additional region and the peripheral insulating trench.

12. The photodiode of claim 11, wherein the peripheral region is positioned closer to the peripheral insulating trench rather than closer to the other region.

13. The photodiode of claim 11, wherein the top surface of the peripheral region is coplanar with the top surface of the epitaxial layer.

14. The photodiode according to claim 11, further comprising: A first electrode is formed on and in contact with the other region, which is a cathode; as well as The second electrode is formed as an anode located on and in contact with the peripheral region.

15. The photodiode of claim 1, wherein the basic hemispherical core has a maximum height of 500 nm.

16. The photodiode of claim 1, wherein the basic hemispherical buried region has a maximum height of 1 µm.

17. A method for manufacturing a photodiode, comprising: A first region of the first conductivity type having a generally hemispherical shape is formed in a semiconductor substrate of the first conductivity type; A basic hemispherical core of a second conductivity type, different from the first conductivity type, is formed in the first region; An epitaxial semiconductor layer is grown on the first region and the basic hemispherical core; as well as A second region of the second conductivity type is formed in the epitaxial semiconductor layer, the second region being located at a position aligned with and in contact with the basic hemispherical core.

18. The method of claim 17, further comprising: An insulating trench is formed to define the periphery of the trap, and the basic hemispherical core and the first region are located within the trap.

19. The method of claim 17, wherein forming the first region comprises performing a tilted implantation of a dopant of the first conductivity type at an angle between 20° and 45° relative to a direction perpendicular to the top surface of the semiconductor substrate.

20. The method of claim 19, wherein performing the tilt injection comprises: Multiple successive tilting implantations of dopants are performed at different rotation angles of the semiconductor substrate.

21. The method of claim 17, further comprising: The semiconductor substrate is doped in a gradient manner from the top surface to the bottom surface opposite the top surface.

22. The method of claim 17, further comprising: A third region of the first conductivity type is formed in the epitaxial layer, the third region circumferentially surrounding the second region.

23. The method of claim 22, further comprising: An insulating trench is formed to define the periphery of the trap, wherein the basic hemispherical core and the first region are located within the trap; The third region is positioned closer to the peripheral insulating trench, rather than closer to the second region.

24. The method of claim 22, further comprising: A first electrode is formed to provide a cathode on and in contact with the second region; as well as A second electrode is formed to provide an anode on and in contact with the third region.

25. The method of claim 17, wherein forming the first region and forming the basic hemispherical core comprises performing dopant implantation through the same mask.

26. The method of claim 17, wherein: Forming the first region includes performing tilting implantation in the semiconductor substrate; and Forming the basic hemispherical core involves performing non-tilted implantation in the semiconductor substrate.

27. The method of claim 26, wherein the tilted injection is performed first, and then the non-tilted injection is performed.

28. The method of claim 26, wherein the non-tilted injection is performed first, and then the tilted injection is performed.

29. The method of claim 26, wherein the tilted injection and the non-tilted injection are performed through the same mask opening.

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