Power amplifier package including multipath integrated passive devices

Abstract

The present invention discloses a power amplifier (PA) package, such as a Doherty PA package, that includes a multipath integrated passive device (IPD). In one embodiment, the PA package includes: a package body through which a first signal amplification path and a second signal amplification path extend; a first amplifier die within the package body and positioned in the first signal amplification path; and a second amplifier die within the package body and positioned in the second signal amplification path. A multipath IPD is further included in the package body. The multipath IPD includes: a first IPD region through which the first signal amplification path extends; a second IPD region through which the second signal amplification path extends; and an isolation region formed in the IPD substrate at a location intermediate the first and second IPD regions.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to microelectronics, and more particularly to power amplifier (PA) packages, such as a small footprint Doherty PA package, that include multipath integrated passives.

[0002] abbreviation

[0003] Abbreviations that occur less frequently in this document are qualified upon first use, while abbreviations that occur more frequently in this document are qualified as follows:

[0004] FET—field effect transistor;

[0005] IPD—integrated passive device;

[0006] MN—matching network;

[0007] PA—power amplifier; and

[0008] PCB—printed circuit board. Background Art

[0009] According to a common design, a Doherty PA package contains a peaking amplifier die and a carrier amplifier die. The peaking and carrier amplifier dies are mounted to a package substrate, such as a conductive base flange, which can serve as the package ground when the power amplifier is implemented using FETs. The Doherty PA package also typically includes a carrier input impedance MN, a carrier output impedance MN, a peaking input impedance MN, and a peaking output impedance MN, interconnected with adjacent circuit components within the package body. As the industry trend continues toward miniaturization, device designers are challenged to include all necessary MN circuitry within a single device package. Summary of the Invention

[0010] According to one aspect of the present invention, there is provided a power amplifier (PA) package, comprising:

[0011] a package body through which the first signal amplification path and the second signal amplification path extend;

[0012] a first amplifier die contained within the package body and positioned in the first signal amplification path;

[0013] a second amplifier die contained within the package body and positioned in the second signal amplification path, the second amplifier die being spaced apart from the first amplifier die along a first axis; and

[0014] a multipath integrated passive device (IPD), the multipath IPD additionally contained within the package body, the multipath IPD comprising:

[0015] IPD substrate;

[0016] a first IPD region, the first signal amplification path extending through the first IPD region, the first IPD region being formed in the IPD substrate at a first position;

[0017] a second IPD region through which the second signal amplification path extends, the second IPD region being formed in the IPD substrate at a second location spaced apart from the first location along a second axis perpendicular to the first axis; and

[0018] An isolation region is formed in the IPD substrate at a third position between the first position and the second position.

[0019] According to one or more embodiments, the first signal amplification path, the first amplifier die and the first IPD region respectively include a carrier signal amplification path, a carrier amplifier die and a carrier IPD region; and wherein the second signal amplification path, the second amplifier die and the second IPD region respectively include a peaking signal amplification path, a peaking amplifier die and a peaking amplifier region.

[0020] According to one or more embodiments, the IPD substrate spans the space between the carrier signal amplification path and the peaking signal amplification path.

[0021] In accordance with one or more embodiments, the PA package further includes an electromagnetic (EM) isolation structure coupled to the isolation region and extending from the multipath IPD to over an area between the first amplifier die and the second amplifier die.

[0022] In accordance with one or more embodiments, the EM isolation structure includes a wire fence including a plurality of bond wires contacting one or more bond pads located in the isolation region of the multi-path IPD.

[0023] According to one or more embodiments, the PA package further includes a conductive flange to which the first amplifier die, the second amplifier die, and the IPD substrate are attached; wherein the wire fence is electrically coupled to the conductive flange through the multi-path IPD.

[0024] According to one or more embodiments, the first amplifier die has a gate terminal and a drain terminal; wherein the PA package further includes: a gate bond wire, the gate bond wire contacting the gate terminal and having a gate bond wire profile; and a drain bond wire, the drain bond wire contacting the drain terminal and having a drain bond wire profile; and the plurality of bond wires included in the wire fence include: a first bond wire, the first bond wire having a first bond wire profile that follows at least a portion of the gate bond wire profile as seen along the second axis; and a second bond wire having a second bond wire profile that is different from the first bond wire profile and follows at least a portion of the drain bond wire profile as seen along the second axis.

[0025] According to one or more embodiments, the PA package further includes: a first plurality of bond wires, wherein the first plurality of bond wires contacts the first IPD region; and a second plurality of bond wires, wherein the second plurality of bond wires contacts the second IPD region; wherein the first IPD region includes a circuit system that is combined with the first plurality of bond wires to form a first impedance matching network electrically coupled to an end of the first amplifier die; and wherein the second IPD region includes a circuit system that is combined with the second plurality of bond wires to form a second impedance matching network electrically coupled to an end of the second amplifier die.

[0026] According to one or more embodiments, the PA package further includes a packaging substrate, to which the first amplifier die, the second amplifier die and the IPD substrate are attached; the circuit system included in the first IPD area includes a first parallel capacitor, which is electrically coupled to the packaging substrate; and the circuit system included in the second IPD area includes a second parallel capacitor, which is electrically coupled to the packaging substrate.

[0027] According to one or more embodiments, the package substrate includes a conductive base flange, which serves as a ground terminal of the PA package.

[0028] According to one or more embodiments, the PA package additionally includes:

[0029] a first bonding wire contacting the first IPD region; and

[0030] a second bonding wire contacting the second IPD region;

[0031] wherein the first IPD region includes circuitry that combines with the first bond wire to form a first harmonic termination circuit electrically coupled to a terminal of the first amplifier die; and

[0032] Wherein the second IPD region includes circuitry that combines with the second bond wire to form a second harmonic termination circuit electrically coupled to a terminal of the second amplifier die.

[0033] In accordance with one or more embodiments, the circuitry of the first IPD region includes a shunt capacitor that combines with the first bond wire to form an LC circuit that is tuned to resonate at a harmonic frequency during operation of the PA package.

[0034] In accordance with one or more embodiments, the IPD substrate includes a multi-path IPD semiconductor die positioned adjacent to and extending substantially parallel to the first and second amplifier dies.

[0035] According to one or more embodiments, the IPD substrate includes a printed circuit board (PCB), and the PCB is embedded in the package body.

[0036] According to one or more embodiments, the PA package further includes a package substrate, to which the first amplifier die, the second amplifier die, and the PCB substrate are attached; wherein the PCB further includes an opening, through which the first amplifier die and the second amplifier die are bonded to the upper surface of the package substrate.

[0037] According to another aspect of the present invention, there is provided a power amplifier (PA) package, comprising:

[0038] Package substrate;

[0039] a first amplifier die bonded to the front side of the package substrate;

[0040] a second amplifier die bonded to the front side of the packaging substrate and spaced apart from the first amplifier die by an amplifier die gap as viewed along a first axis extending parallel to the front side of the packaging substrate;

[0041] an input multipath integrated passive device (IPD) having a first input IPD region, a second input IPD region, and a first isolation region between the first input IPD region and the second input IPD region;

[0042] an output multipath IPD having a first output IPD region, a second output IPD region, and a second isolation region between the first output IPD region and the second output IPD region; and

[0043] An isolation structure extends from the first isolation region to over the amplifier die gap and to the second isolation region, the isolation structure being electrically coupled to the package substrate through at least one of the first multipath IPD and the second multipath IPD.

[0044] According to one or more embodiments, the input multipath IPD includes an input multipath IPD die, the first input IPD region, the second input IPD region, and the first isolation region being formed in the input multipath IPD die; and

[0045] The output multi-path IPD includes an output multi-path IPD die, and the first output IPD region, the second output IPD region, and the second isolation region are formed in the output multi-path IPD die.

[0046] In accordance with one or more embodiments, an input multipath IPD die extends substantially parallel to the output multipath IPD die to define an inter-IPD gap, and the second amplifier die and the first amplifier die are located in the inter-IPD gap.

[0047] According to one or more embodiments, the PA package additionally includes:

[0048] a package body formed in part by the package substrate, the package body containing the second amplifier die, the first amplifier die, the input multipath IPD, and the output multipath IPD; and

[0049] A printed circuit board (PCB), wherein the PCB is embedded in the package body, and the PCB comprises:

[0050] a first PCB section, the input multipath IPD being formed on the first PCB section;

[0051] a second PCB section, the output multipath IPD being formed on the second PCB section; and

[0052] An opening is located between the first PCB section and the second PCB section, and the first amplifier die and the second amplifier die are bonded to the package substrate within the opening.

[0053] According to one or more embodiments, the first input IPD region, the first amplifier die, and the first output IPD region are aligned along a second axis, which is perpendicular to the first axis and extends parallel to the front side of the packaging substrate; and wherein the second input IPD region, the second amplifier die, and the first output IPD region are aligned along a third axis parallel to the second axis. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] At least one example of the present invention will be described below with reference to the accompanying drawings, wherein like reference numerals represent like elements, and:

[0055] Figure 1 is a simplified schematic diagram of a Doherty PA package implemented with an input multipath IPD and an output multipath IPD as shown in an example embodiment according to the present disclosure;

[0056] Figure 2 is a top-down or plan view of a Doherty PA package containing an input multipath IPD (implemented using a first IPD die), an output multipath IPD (implemented using a second IPD die), and an IPD-to-IPD isolation structure (here, a ground rail), the top-down or plan view showing how a Dowty PA package may be implemented. Figure 1 An example embodiment of a Doherty PA package is schematically shown in FIG.

[0057] Figure 3 yes Figure 2 a detailed view of a center portion of the Doherty PA package shown in , depicting in greater detail the multipath IPD die, IPD-to-IPD bond wire fence, power amplifier die, and various bond wire interconnects;

[0058] Figure 4 and 5 is included in Figure 2 and 3 An example of a simplified cross-sectional view of a multi-path IPD die in a Doherty PA package, as shown along Figure 3 The cross-sectional planes 4-4 and 5-5 are cut in FIG.

[0059] Figure 6 yes Figure 2-5 a simplified cross-sectional schematic diagram of a Doherty PA package shown in , which illustrates how, in at least some embodiments, bond wires contained within an IPD-to-IPD bond wire fence may have a range of bond wire profiles to enhance isolation performance; and

[0060] Figure 7 is a top view of the central region of an example Doherty PA package similar to Figure 2-5The Doherty PA package is similar to the one shown in , but contains two multipath IPDs implemented using circuitry formed on different sections of a PCB embedded in the package body (rather than on discrete dies or other discrete substrates).

[0061] For the sake of simplicity and clarity, descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the present invention described in the subsequent detailed descriptions. It should be further understood that unless otherwise indicated, the features or elements shown in the accompanying drawings are not necessarily drawn to scale. For example, the dimensions of certain elements or regions in the drawings may be exaggerated relative to other elements or regions to facilitate understanding of the embodiments of the present invention. DETAILED DESCRIPTION

[0062] Embodiments of the present disclosure are illustrated in the drawings of the drawings briefly described above. Various modifications to the example embodiments may be contemplated by those skilled in the art without departing from the scope of the present invention as set forth in the appended claims.

[0063] As used herein, the term "multipath IPD" refers to an integrated passive device (IPD) structure that includes circuitry in distinct regions or blocks formed within a common substrate. At least two electrically isolated signal amplification paths extend in parallel through the multipath IPD: a carrier signal amplification path and a peaking signal amplification path (note that signal amplification is implemented external to the multipath IPD). The substrate of the multipath IPD spans the space between the carrier signal amplification path and the peaking signal amplification path. When integrated into a dual-way Doherty PA package, a given multipath IPD may include a first electrically isolated circuit region and a second electrically isolated circuit region, with the carrier signal amplification path and the peaking signal amplification path extending through the first and second electrically isolated circuit regions, respectively. In this case, the multipath IPD may be more specifically referred to as a "dual-path IPD." In other embodiments, such as when a given multipath IPD is contained within an N-way Doherty PA package (N>2), the multipath IPD may include three or more electrically isolated circuit regions or blocks, with an equal number of signal amplification paths extending through each of the circuit regions or blocks.

[0064] Overview

[0065] The following describes a PA package that includes a multipath IPD and other unique structural features, which, in various embodiments, achieves reduced package footprint, lower manufacturing costs, and enhanced isolation performance. In many cases, the PA package described herein is implemented as a Doherty PA package and is therefore primarily described below. However, it should be emphasized that the following disclosure is equally applicable to other types of PA packages, including, for example, push-pull PA packages. In addition, although primarily described below as including two multipath IPDs (i.e., one input multipath IPD and one output multipath IPD), the PA package described below does not need to include two multipath IPDs in all embodiments. In fact, in embodiments, the PA package may include a single multipath input IPD, which is combined with a discrete (single-path) carrier output IPD and a discrete (single-path) peaking output IPD. Conversely, other embodiments of the PA package may include a single multipath output IPD, which is combined with a discrete (single-path) carrier input IPD and a discrete (single-path) peaking output IPD. In other cases, embodiments of a PA package may include a single multipath IPD on a first side (either the output side or the input side) of the amplifier die without in-package impedance MN circuitry on a second side of the amplifier die—in which case the desired impedance matching may be achieved by circuitry external to the PA package, which is on a PCB included in a larger PA circuit or system in which the PA package is integrated.

[0066] In various implementations, the Doherty PA package includes an input multipath IPD comprising a carrier IPD region or block and a peaking IPD region or block. As noted above, the carrier IPD region is electrically isolated from the peaking IPD region and, in particular, may be separated by an intermediate isolation region. Each IPD region includes circuitry that supports impedance matching on either the input or output side of the power amplifier die. For example, in the case of an input multipath IPD, the input carrier IPD region includes circuitry that, in combination with corresponding bond wires (or other electrical interconnects), forms a carrier input impedance MN for raising the impedance of a carrier signal applied to the input (e.g., gate) of the carrier amplifier to a desired level. Similarly, the input peaking IPD region includes circuitry that, in combination with other circuit elements (e.g., bond wires or other inductive elements), forms a peaking input impedance MN for raising the impedance of a peaking signal applied to the input of the peaking amplifier. The circuitry defining the input carrier IPD region and the circuitry defining the input peaking IPD region are formed at different locations in a common substrate, such as a semiconductor die, a PCB, a ceramic substrate, or another type of substrate. The same is true for an intermediate isolation region formed in the common substrate at a location between the carrier IPD region and the peaking IPD region. When the input carrier IPD region, the input peaking IPD region, and the intermediate isolation region are formed in a semiconductor die, the semiconductor die may be referred to herein as an "input multipath IPD die."

[0067] In addition to or in lieu of an input multipath IPD, a Doherty PA package may include an output multipath IPD. Similarly, this output multipath IPD may include: (i) a first circuit block or IPD region that, in combination with bond wires (or other circuit elements), forms a carrier output impedance MN; (ii) a second circuit block or IPD region that, in combination with bond wires (or other circuit elements), forms a peaking output impedance MN; and (iii) an isolation region between the IPD regions. The carrier output impedance MN and the peaking output impedance MN serve to raise the output impedances of the carrier amplifier and the peaking amplifier, respectively, to levels that more closely match the impedance of an electrical load, such as an antenna, coupled to the output of a larger Doherty PA circuit or system that includes the Doherty PA package. The output carrier IPD region and the output peaking IPD region, along with an intermediate isolation region, are formed in a common substrate, such as a semiconductor die, a ceramic substrate, or a PCB. When these regions are formed in a common semiconductor die, the semiconductor die may be referred to as an "output multipath IPD die," in accordance with the terminology introduced above. In contrast, when implemented using a PCB, the output carrier IPD region and the peaking IPD region may be formed in a different PCB than the PCB in which the input carrier IPD region and the peaking IPD region (when present) are formed; or alternatively, the output carrier IPD region and the peaking IPD region may be formed in a first section of the PCB, while the input carrier IPD region and the peaking IPD region are formed in a second section of the same PCB. In the latter case, in embodiments, the PCB may be shaped to avoid interfering with direct mounting of the power amplifier die to the package substrate; for example, the PCB may have a generally U-shaped or annular planar geometry defining a central opening within which the power amplifier die is attached to the package substrate in the form of a conductive base flange.

[0068] In embodiments of the Doherty PA package, the input multipath IPD and / or the output multipath IPD can be fabricated to include circuitry that supports other functions in addition to the impedance matching functions described above. For example, in at least some embodiments, when implementing the amplifier using FETs, either or both of the multipath IPDs can be fabricated to include circuit elements that support harmonic termination, baseband decoupling, and / or amplifier biasing, such as biasing at the gate or drain terminals of the transistors. With respect to harmonic termination, specifically, termination of the second harmonic on the input side of the carrier amplifier, on the output side of the carrier amplifier, on the input side of the peaking amplifier, and / or on the output side of the peaking amplifier can be advantageously achieved by fabricating appropriate IPD regions to include circuitry for this purpose; such circuitry can be formed in or disposed on one or more multipath IPD substrates and electrically coupled to a shunt capacitor of an inductive element in the form of one or more bond wires. One or more shunt capacitors and one or more bond wires can then be tuned by design to dissipate excess energy generated at the target (e.g., second) harmonic to ground during operation of the Doherty PA package. Baseband decoupling or amplifier bias circuitry can also be formed in the multipath IPD and cooperate with other circuit components (e.g., bond wires or bias leads, as appropriate) to provide the desired functionality.

[0069] As a significant benefit, incorporating multiple IPD regions or circuit blocks into a common substrate generally enables reduced spacing between IPD regions, relative to conventional approaches that form each instance of IPD circuitry on a discrete semiconductor die. However, as a corollary, when a Doherty PA package is fabricated to include one or more multipath IPDs, each including an IPD region formed in relatively close proximity within a common substrate, electromagnetic (EM) interference, coupling, or crosstalk, between the carrier signal path and the peaking signal path tends to increase. Therefore, to address this secondary technical issue, embodiments of the PA package are advantageously produced to additionally include at least one IPD isolation structure that improves signal isolation between the carrier IPD region and the peaking IPD region formed on a given multipath IPD, and more generally, improves signal isolation between the carrier signal path and the peaking signal path of the PA package. In embodiments where the PA package includes both an input multipath IPD and an output multipath IPD, this isolation structure may extend from the input multipath IPD to above the region between the amplifier dies (as viewed looking down on the package substrate), and to the output multipath IPD. In such cases, the isolation structure may be referred to as an IPD-to-IPD isolation structure. Additionally, in embodiments, such an IPD-to-IPD isolation structure may be electrically coupled to the ground of the PA package via one or both of the multi-path IPDs; for example, in embodiments where the PA package includes a conductive flange that acts as a ground, the IPD-to-IPD isolation structure may be electrically coupled to the flange via a conductive via or other metal structure formed in the IPD substrate. In various embodiments, such electrically grounded IPD-to-IPD isolation structures are implemented using one or more bond wires that contact bonding pads or bonding pads disposed on the multi-path IPD. For example, a bond wire array or ground wire fence may be bonded between the IPDs, possibly while giving the bond wires within the array different profiles, thereby enhancing the isolation capabilities of the bond wire array, as described more fully below.

[0070] Using one or more multipath IPDs instead of multiple discrete IPDs offers several advantages. For example, in a PA package containing two multipath IPDs with two amplifier dies positioned between them, the number of dies that need to be precisely positioned and attached during package manufacturing can be reduced by one-third. That is, in this case, four dies need to be mounted within a PA package comprising an input multipath IPD and an output multipath IPD, whereas a comparable PA package containing six dies conventionally manufactured as single-path IPDs implemented on four discrete dies would minimize manufacturing variation and increase manufacturing throughput, which in turn reduces overall manufacturing costs. Specifically, using multipath IPDs instead of multiple discrete single-path IPDs can reduce not only variations in bond wire lengths but also variations in performance parameters of the peaking and carrier IPD regions formed on the multipath IPDs. For example, this can be achieved by making buildup layer thicknesses more uniform, such as the thickness of dielectric (e.g., nitride) layers used to form metal-insulator-metal (MIM) capacitors, which provide highly reliable and predictable relationships between capacitance values, or other such circuit element characteristics. This, in turn, eliminates or reduces the need for IPD die pairing during Doherty package fabrication, helping to simplify the manufacturing process. Additionally, and as previously noted, the PA package footprint can be reduced by using such multipath IPDs, further saving space and reducing costs. At the same time, in embodiments where at least one in-package isolation structure (e.g., a ground bond fence connected between the input multipath IPD and the output multipath IPD) is additionally integrated into the PA package, isolation between the peaking and carrier paths can be improved, despite the space-constrained environment within the PA package.

[0071] Turning now to the accompanying drawings, Figure 2-7 A description of two example PA packages (specifically, Doherty PA packages) including multipath IPDs and in-package isolation structures is provided. However, first, in conjunction with Figure 1 A general description of a Doherty PA package as included in a larger Doherty PA circuit or system is discussed to establish an example, but the example is a non-limiting context in which embodiments of the present disclosure may be better understood.

[0072] Discussion of a general example Doherty PA package containing multipath integrated passives and included in a Doherty PA system

[0073] Figure 1is a simplified schematic diagram of a Doherty PA package 10 including two multipath IPDs 12, 14, as shown in accordance with an example embodiment of the present disclosure. For descriptive purposes, the Doherty PA package 10 is depicted as being contained within a larger Doherty PA circuit or system 16, which includes an input node 18 and an output node 20. The output node 20 is electrically coupled to an electrical load 22, which is driven during operation of the Doherty PA system 16. In embodiments employing the Doherty PA system 16 in a base station or other wireless communication system, the electrical load 22 may include or take the form of, for example, one or more antennas. In embodiments, an impedance transformer, not shown, may be coupled between the output node 20 and the electrical load 22. Similarly, embodiments of the Doherty PA system 16 may include various other circuit components not shown. Figure 1 shown or described herein to avoid obscuring the teachings of the present invention.

[0074] A power splitter 24, a carrier (or primary) signal amplification path 26, a peaking (or auxiliary) signal amplification path 28, and a combining node 30 are disposed between the input node 18 and the output node 20 of the Doherty PA system 16. When a radio frequency (RF) input signal is applied to the input node 18, a splitter input node 32 included in the power splitter 24 splits the RF input signal into a carrier signal and a peaking signal that appear at splitter output nodes 34 and 36, respectively. The carrier signal and the peaking signal are then applied from the power splitter output nodes 34 and 36 to a carrier input terminal 38 (e.g., a carrier input lead) and a peaking input terminal 40 (e.g., a peaking input lead) of the Doherty PA package 10. Thus, the carrier signal and the peaking signal are transmitted in parallel along the carrier signal amplification path 26 and the peaking signal amplification path 28, respectively, to be individually amplified within the Doherty PA package 10. Various additional components or circuit elements are also positioned within the carrier signal amplification path 26 and the peaking signal amplification path 28, specifically including a carrier amplifier 42 and a peaking amplifier 44. Specifically, the carrier amplifier 42 and the peaking amplifier 44 are positioned within the carrier signal amplification path 26 and the peaking signal amplification path 28, respectively, between the power divider 24 and the combining node 30. Whether single-stage or multi-stage amplifiers, the amplifiers 42 and 44 can be implemented in a variety of different ways, as discussed in greater detail below. After signal amplification by the carrier amplifier 42 and the peaking amplifier 44, the carrier signal and the peaking signal are further conducted along the signal amplification paths 26 and 28, output from the Doherty PA package 10, and ultimately combined at the combining node 30 to produce a combined RF output signal.

[0075] In the example shown, the Doherty PA system 16 has a standard load network configuration. Thus, a first phase delay element 46 applies a controlled phase delay to the peaking signal transmitted along the peaking signal amplification path 28. The phase delay element 46 can take any form suitable for applying a desired phase delay (a quarter wavelength (λ / 4) or a 90° phase delay) to the peaking signal relative to the carrier signal at the center operating frequency (fo). In various embodiments, the phase delay element 46 takes the form of a quarter wavelength (λ / 4) transmission line. A second phase delay element 48 is also provided on the output side of the carrier signal amplification path 28 to compensate for the resulting 90° phase delay difference between the carrier amplification path 26 and the peaking amplification path 28 at the inputs of the amplifiers 42 and 44. The output phase delay element 48 introduces an appropriate signal delay into the carrier signal, thereby ensuring that the amplified signals arrive in phase for recombining into the amplified RF output signal at the combining node 30. Likewise, in an embodiment, the output phase delay element 48 may take the form of a quarter-wavelength (λ / 4) transmission line sized to provide an appropriate electrical length between the output of the carrier amplifier 42 and the combining node 30 to achieve a desired (e.g., 90°) phase delay. In other embodiments, the Doherty PA system 16 may alternatively have an inverted load network configuration such that a controlled phase delay is applied to the carrier input signal prior to amplification at the carrier amplifier 42, and a corresponding phase delay is applied to the peaking output signal prior to signal recombination at the combining node 30.

[0076] As indicated by the first cross-hatched pattern (by the presence of Figure 1 50 ), the input multipath IPD 12 includes two IPD regions 52, 54. As used herein, the term "IPD region" refers to a first region or block of passive circuitry formed in and / or on a substrate, together with at least a second region or block of passive circuitry (another IPD region), wherein the regions or blocks of passive circuitry (IPD regions) are electrically isolated from one another. The IPD regions 52, 54 may be more fully referred to as "electrically isolated IPD regions 52, 54" to indicate that the circuitry defining the IPD regions 52, 54 is electrically isolated, for example, by an intermediate isolation region, which may include circuitry that assists in EM shielding the IPD regions 52, 54, as described more fully below. As further indicated by the second cross-hatching pattern identified in the legend 50, the electrically isolated IPD regions 52, 54 are formed in a common substrate 56 (e.g., a die body, PCB, ceramic substrate, or similar structure) that is also included in the multipath IPD 12. In a similar aspect, and as indicated by the third cross-hatched pattern identified in legend 50, the multi-path IPD 14 includes two electrically isolated IPD regions 58, 60 (identified by a fourth cross-hatched pattern) formed in a common substrate 62. In various embodiments, and generally as shown in Figure 1 As indicated in FIG, the IPD substrates 56, 62 may be produced as separate structures, such as in conjunction with Figure 2-6 In other cases, the IPD substrates 56, 62 may be joined as a single substrate, such as a PCB embedded within the Doherty PA package 10, as described below in conjunction with Figure 7 Discussed.

[0077] Describing the input multipath IPD 12 in greater detail, the circuitry that forms (or helps form) a carrier input impedance MN 64 is disposed in the IPD region 52, while the circuitry that forms (or helps form) a peaking input impedance MN 66 is disposed in the IPD region 54. The carrier input impedance MN 64 is electrically coupled between the carrier input terminal or lead 38 of the Doherty PA package 10 and the end of the carrier amplifier 42. In contrast, the peaking input impedance MN 66 is electrically coupled between the peaking input terminal or lead 40 of the Doherty PA package 10 and the end of the peaking amplifier 44. During operation of the Doherty PA system 16, the input impedances MN 64, 66 serve to gradually increase the circuit impedance of the Doherty PA package 10 toward the source impedance. The specific manner in which the input impedances MN 64, 66 are implemented will vary between embodiments, provided that the MNs provide the desired impedance matching before the carrier and peaking signals are transmitted to the amplifiers 42, 44. In one embodiment, and by way of non-limiting example only, the input impedances MN 64, 66 each have a T-type matching configuration, an example of which is present in FIG. Figure 1 6. Although in this figure, detail bubble 68 is visually associated or correlated with carrier input impedance MN 64, in embodiments, the T-type matching circuit topology shown in detail bubble 68 may be equally applicable to peaking input impedance MN 66. As shown, input impedances MN 64, 66 may each include a plurality of inductive elements 70, 72, 74 and at least one shunt capacitive element 76. In embodiments, inductive elements 70, 72, 74 may be implemented as bond wires or integrated spiral inductors, while shunt capacitive element 76 may be a grounded (e.g., MIM) capacitor structure formed in or supported by substrate 56. Figure 2 and 3 Additional description of example ways in which this T-matching circuit configuration may be implemented is provided.Other embodiments may include input impedances MN 64, 66 having other circuit topologies and / or forming other filter types.

[0078] In addition to the MNs 64, 66, the IPD regions 52, 54 of the multipath IPD 12 may also include circuitry 78, 80 for performing or supporting other circuit functions. Such other functions may include baseband decoupling, harmonic termination, transistor (e.g., FET gate) biasing, and other signal filtering functions. To explore harmonic termination in more detail, Figure 1 Example harmonic termination structures or circuits 82, 84 are shown in detail bubble 86 appearing in the lower left corner of FIG. Although visually associated with circuitry 80 included in carrier input IPD region 54, example circuits 82, 84 can also be implemented for circuitry 78 included in peaking input IPD region 52. In this example, input harmonic termination circuits 82, 84 comprise resonant inductor / capacitor (LC) circuits, wherein inductive element 82 is electrically coupled to ground (or another reference voltage) via capacitive element 84 (thereby providing a parallel capacitance). By varying the inductance and capacitance values ​​of inductive element 82 and capacitive element 84, as appropriate, input harmonic termination circuits 82, 84 can be tuned to resonate at a target harmonic frequency (e.g., 2fo) to terminate signal energy at the target harmonic frequency before the signal is transmitted to carrier amplifier 42 or peaking amplifier 44. Thus, amplifier performance is enhanced. In further embodiments, such harmonic termination circuitry 78, 80 within the IPD regions 52, 54 may have different configurations for eliminating or minimizing signal energy at a target harmonic frequency, which is typically the second harmonic frequency (2fo) of the carrier signal and the peaking signal. Additionally or alternatively, such additional IPD circuitry 78, 80 may be configured for another purpose (e.g., baseband decoupling, gate biasing, drain biasing, etc.), or may be omitted entirely from the multipath IPD 12.

[0079] The foregoing description of the input multipath IPD 12 is generally equally applicable to the output multipath IPD 14, with the slight caveat that the input multipath IPD 12 and the output multipath IPD 14 will be tuned differently and may perform different functions or the same function. Figure 1As further indicated in FIG. , the electrically isolated output IPD regions 58, 60 may include circuitry for forming a carrier output impedance MN 88 and a peaking output impedance MN 90, respectively, which may be employed in combination with other, not-illustrated, circuit elements (e.g., bond wires) otherwise included in the Doherty PA package 10, as described below. The output impedances MN 88, 90 may each have a T-type matching topology similar to or identical to the topology described above in connection with detail bubble 68 and carrier input impedance MN 64. In other embodiments, the output impedances 88, 90 may have other topologies suitable for increasing the circuit impedance of the Doherty PA package 10 toward the load impedance of the electrical load 22. It should be noted that, in embodiments, additional impedance transformation may also be provided external to the Doherty PA package 10. Furthermore, as before, the output IPD regions 58, 60 may include other circuitry 92, 94 that provides harmonic termination, baseband decoupling, transistor (e.g., FET drain) biasing, and other such functionality. In an embodiment, circuitry 92 of output carrier IPD region 58 and circuitry 94 of output peaking IPD region 60 provide second (2fo) harmonic termination of the carrier signal and the peaking signal, respectively; and may each have a topology similar to or identical to the topology described above in conjunction with detail bubble 86 and circuitry 80 of input peaking IPD region 54.

[0080] exist Figure 1 In the example of FIG. 1 , the Doherty PA package 10 further includes an IPD-to-IPD isolation structure 96, wherein the isolation structure 96 extends from the multipath IPD 12 to the multipath IPD 14. In this regard, the IPD-to-IPD isolation structure 96 may extend generally along a first axis (corresponding to the X-axis of the graph 98) along which the multipath IPDs 12, 14 are spaced apart. Additionally, as viewed along a second axis (corresponding to the Y-axis of the graph 98) perpendicular to the first axis, the IPD-to-IPD isolation structure 96 may also extend through or over the region or space 100 of the separation amplifiers 42, 44. In an embodiment, one or both ends of the IPD-to-IPD isolation structure 96 may be electrically coupled to a ground terminal of the Doherty PA package 10. For example, and as described below in conjunction with FIG. Figure 2-6 More fully described, the IPD to IPD isolation structure 96 may be electrically coupled to a base flange (not shown) through electrical features (eg, bond pads and conductive vias or metal plugs) formed in the IPD substrates 56, 62. Although generally shown as Figure 1, but using the example of such a wire fence discussed below, in embodiments, the IPD-to-IPD isolation structure 96 can be fabricated as a wire fence. In other cases, the IPD-to-IPD isolation structure 96 can be replaced by one or more isolation structures of another type; for example, in another embodiment, the multi-path IPDs 12, 14 can be fabricated to include grounded conductive structures and / or magnetically permeable structures (e.g., walls, fins, or wire bonds) extending upward from the isolation region of the multi-path IPDs 12, 14, but the conductive structures and / or magnetically permeable structures do not extend completely between the IPDs 12, 14, as shown.

[0081] Continue to refer Figure 1As schematically indicated by symbols 102 and 104, carrier amplifier 42 and peaking amplifier 44 each include at least one power transistor integrated circuit (IC) for amplifying RF signals conducted through amplifiers 42 and 44. Each power transistor IC 102 and 104 can be fabricated on discrete semiconductor dies 106 and 108 and have a single-stage configuration or a multi-stage configuration. In an embodiment, all amplifier stages (or the final amplifier stage) of one or both of carrier amplifier 42 and peaking amplifier 44 can be implemented using any of the following transistor technologies: silicon-based FETs (e.g., laterally diffused metal oxide semiconductor FETs or LDMOS FETs) or III-V FETs (e.g., gallium nitride (GaN) FETs, gallium arsenide (GaAs) FETs, gallium phosphide (GaP) FETs, indium phosphide (InP) FETs, or indium antimonide (InSb) FETs, or another type of III-V transistor). When, for example, Doherty PA package 10 has a symmetrical Doherty configuration, the carrier transistor IC and the peaking transistor IC can be of equal size. Alternatively, the carrier transistor IC and the peaking transistor IC may be unequally sized in various asymmetric Doherty configurations; it should be understood that the term "size" as used in this context refers to the active periphery or total active gate width of the power transistor IC. In an asymmetric Doherty configuration, the peaking transistor IC may be larger than the carrier transistor IC, specifically by a multiplier. For example, the peaking transistor IC may be twice the size of the carrier transistor IC, resulting in a current carrying capacity of the peaking transistor IC that is twice that of the carrier transistor IC. Peaking to carrier amplifier IC size ratios other than a 2:1 ratio may also be utilized. Additionally, in more complex embodiments, either or both power amplifiers 42, 44 may be implemented with multiple parallel amplification paths (rather than a single amplification path). For example, in the example asymmetric Doherty configuration, the carrier amplifier 42 may be implemented with two (or a greater number) of parallel amplification paths, while the peaking amplifier 44 may be implemented with three (or some other number) of parallel amplification paths. Additionally, in the case of an N-way Doherty amplifier (N>2), the Doherty PA package 10 may include multiple peaking amplifiers of different configurations or levels.

[0082] For ease of explanation, and to reflect that FETs are currently primarily used to produce Doherty PA devices, the preceding paragraphs, and this document as a whole, focus primarily on embodiments of (e.g., Doherty) PA devices implemented using FETs. However, it should be emphasized that alternative embodiments of the present disclosure may be implemented using other transistor technologies, including but not limited to bipolar transistors. Thus, in Figure 1In the embodiment of the Doherty PA package 10 shown in , and in all other PA device embodiments described herein, any and all amplifier stages may be implemented using any suitable transistor technology, such as FETs, bipolar transistors, or combinations thereof. Figure 1 An example of a single-stage FET is shown in detail in detail bubble 110 in FIG. Here, an input carrier signal fed to carrier transistor IC 102 may be applied to a gate manifold or control terminal 112 of the illustrated FET, which further includes a drain terminal 116 (typically an output terminal or pad) and a source terminal 114 electrically coupled to ground or another reference voltage (e.g., via a base flange not shown). In this example, drain terminal 116 serves as the output of carrier amplifier 42, with the amplifier carrier signal appearing at terminal 116 and subsequently transmitted to carrier IPD region 58 of multipath IPD 14. In an embodiment, peaking transistor IC 104 may likewise be implemented as a single-stage FET, with the control terminal of the FET receiving the output signal from peaking IPD region 54 of multipath IPD 12, the drain terminal of the FET providing the amplified output signal to peaking IPD region 60 of multipath IPD 14, and the source terminal of the FET electrically coupled to a reference voltage (e.g., ground) via a flange not shown that is also included in Doherty PA package 10.

[0083] During circuit operation, the carrier amplifier 42 of the Doherty PA package 10 can be biased to operate in Class AB mode, while the peaking amplifier 44 is biased to operate in Class C mode. At low power levels (e.g., when the power of the input signal is less than the turn-on threshold level of the peaking amplifier 44), the Doherty PA package 10 operates in a low-power or back-off mode. In the low-power (back-off) mode, the carrier amplifier 42 is typically the only amplifier supplying current to the load 22. Conversely, when the power of the input signal exceeds the threshold level of the peaking amplifier 102, the Doherty PA package 10 transitions to operate in a high-power mode, in which both the carrier amplifier 42 and the peaking amplifier 44 simultaneously supply current to the load 22. At this point, the peaking amplifier 44 provides active load modulation at the combining node 30, thereby allowing the current of the carrier amplifier 42 to continue to increase linearly. After transmitting through the circuitry formed in the multipath IPD regions 58, 60, the amplified output signals of the power amplifiers 42, 44 appear at output nodes or terminals 118, 120 of the Doherty PA package 10. Thus, output terminal 118 may be a peaking output lead of the Doherty PA package 10, while output terminal 120 is a carrier output lead. The amplified output signals are then combined at combining node 30 and applied to the electrical load 22, with an appropriate phase delay applied to the amplified carrier output signal as previously described. By including the Doherty PA package 10, the overall size and cost of the Doherty PA circuit or system 16 may be reduced while enhancing the system 16 (e.g., isolation and efficiency). Having now provided a general description of the functionality of the Doherty circuit, the following description will be made in conjunction with Figure 2-7 Potential ways in which embodiments of the Doherty PA package 10 may be physically implemented are described.

[0084] Example of a Doherty PA package containing multipath integrated passives

[0085] Now refer to Figure 2 and 3, according to another example embodiment of the present disclosure, a Doherty PA package 122 is shown that includes two multipath IPDs 124, 126. In this particular example, the multipath IPDs 124, 126 are implemented using discrete semiconductor dies and are therefore referred to hereinafter as "multipath IPD die 124" and "multipath IPD die 126," respectively. In other embodiments, the multipath IPDs 124, 126 may be produced using other types of discrete substrates, such as ceramic substrates. In addition to the multipath IPD dies 124, 126, the Doherty PA package 122 also includes a carrier amplifier die 128 and a peaking amplifier die 130. Thus, the Doherty PA package 122 includes a total of four IC dies 124, 126, 128, 130 attached to the top surface or front side of the package substrate 132. The package substrate 132 forms part or portion of a larger package body 134 of the Doherty PA package 122 within which the dies 124 , 126 , 128 , 130 are contained.

[0086] A plurality of leads 136, 138, 140, 142, 144 extend from the package body 134. In this example, the package leads include a carrier input lead 136, a peaking input lead 138, a carrier output lead 140, a peaking output lead 142, and two bias leads 144. Inner end portions of the package leads 136, 138, 140, 142, 144 are attached to the upper surface of a peripheral package sidewall extending around the upper perimeter of the package substrate 132 using a metallization layer 146. The peripheral package sidewall is constructed of a dielectric (e.g., molding) material to provide electrical isolation between the package leads 136, 138, 140, 142, 144 and the underlying package substrate 132, which, in embodiments of the Doherty PA package 122, can serve as conductive (e.g., ground) terminals. Arrows 121 and 123 represent the carrier input signal applied to carrier input lead 136 and the amplified carrier output signal appearing at carrier output lead 140, respectively; while arrows 125 and 127 represent the peaking input signal applied to peaking input lead 138 and the amplified peaking output signal appearing at peaking output lead 142, respectively. Arrows 121 and 123 can also be collectively considered to represent the carrier signal amplification path extending through Doherty PA package 122, while arrows 125 and 127 can be considered to represent the peaking signal amplification path extending through package 122.

[0087] The specific manner in which the package body 134 of the Doherty PA package 122 is constructed may vary between embodiments. For example, in embodiments in which the Doherty PA package 122 is fabricated as an air cavity package, the Doherty PA package 122 may additionally include a lid or cover (not shown) bonded over the upper peripheral package sidewalls to enclose the gas-containing cavity (containing air or another inert gas) housing the IC dies 124, 126, 128, 130. The peripheral package sidewalls may be formed around the package substrate 132 to bond the periphery of the air cavity using, for example, a molding process or by assembling the package sidewalls from one or more dielectric members (often referred to as a "window frame"). In embodiments where a molded package body is formed, the molded package body can extend downwardly beyond the sidewalls of the package substrate 132 to cover the sidewalls (e.g., base flange) of the package sub-state 132, thereby leaving the lower surface of the substrate 132 exposed for electrical connection when the substrate 132 serves as the conductive end of the Doherty PA package 122. In other embodiments, the Doherty PA package 122 can take other forms, such as an overmold or encapsulated package without a gas-containing cavity. However, generally speaking, embodiments of the present disclosure are open to implementations having a variety of different package configurations.

[0088] exist Figure 2 and 3 In the example of the embodiment of the present invention, and as briefly indicated above, the package substrate 132 takes the form of a conductive base flange and, therefore, will be referred to hereinafter as "base flange 132" or "flange 132." The base flange 132 of the Doherty PA package 122 can be implemented as a body of material, a layered or laminated structure, or other substrate suitable for supporting the IC dies 124, 126, 128, 130. In addition, the base flange 132 can serve as a heat sink and / or conductive end for the Doherty PA package 122. In certain embodiments, by way of example, the base flange 132 can take the form of a unitary metal structure, plate, or block. In other embodiments, the base flange 132 can have a multi-layer metal construction; for example, the base flange 132 can include multiple thermally conductive layers bonded in a stacked or laminated arrangement. Typically, the base flange 132 will be primarily composed of one or more metals having a relatively high thermal conductivity, such as copper (Cu). As a more specific example, in embodiments where the base flange 132 is a layered or laminated structure, the base flange 132 may include at least one Cu layer combined with at least one dissimilar metal layer having a coefficient of thermal expansion (CTE) less than that of the Cu layer. The dissimilar metal layer may be composed of, for example, molybdenum (Mo), a Mo-Cu alloy, or a Mo-Cu composite material. In this manner, the base flange 132 may have a relatively high thermal conductivity and a low effective CTE.

[0089] The base flange 132 has an upper major surface or front side 148 to which the IC dies 124, 126, 128, 130 are attached or bonded. In an embodiment, the IC dies 124, 126, 128, 130 may be bonded to the front side 148 of the base flange 132 using a conductive material such as a metal-filled epoxy, a sintered metal material, or another conductive die attach material. Figure 1 In the manner of the Doherty PA package 10 shown in FIG. 1 , the power amplifier dies 124 , 126 are spaced apart along a first axis of the package 10 , which extends parallel to the front side 148 of the base flange 132 and corresponds to Figure 2 and 3 In embodiments, this axis may also be referred to as the longitudinal axis of the Doherty PA package 122, provided that the IC dies 124, 126, 128, 130 and possibly the package 122 itself may (but need not) be elongated along this axis. Figure 3 In addition, through Figure 3 Reference numeral 152 in the graph 150 identifies the region separating the power amplifier dies 124, 126, referred to herein as the "amplifier die offset" or "amplifier die gap." In contrast, the multipath IPD dies 124, 126 are spaced apart along a second axis that is perpendicular to the first axis and extends parallel to the front side 148 of the base flange 132 (corresponding to the X-axis of the graph 150). As viewed along the X-axis of the graph 150, the spacing between the multipath IPD dies 124, 126 (also referred to herein as constituting the "inter-IPD gap") is sufficient to contain the power amplifier dies 128, 130 positioned therebetween. In the example shown, the multipath IPD dies 124, 126 have a length such that the dies 124, 126 extend beyond the outer edges of the amplifier dies 128, 130, as viewed along the Y-axis. In other embodiments, the planar shape, arrangement size, and relative positioning of the IC dies 124 , 126 , 128 , 130 may vary.

[0090] As in Figure 3As shown in FIG1 , the input multipath IPD die 124 includes two electrically isolated IPD regions: (i) an input carrier IPD region 154, and (ii) an output carrier IPD region 156. Additionally, an intermediate isolation region 158 is disposed between the IPD regions 154, 156, as viewed along the Y-axis of the graph 150 (also referred to herein as the "longitudinal axis" of the Doherty PA package 122). Regardless of whether the isolation region 150 contains circuit elements (e.g., conductive vias or metal plugs that provide signal conduction through the body of the die 124), the isolation region 150 may also be referred to herein as an "IPD region," given that the region 150 is included within the multipath IPD die 124. At least the IPD regions 154, 156 are defined by conductive circuit features formed in a common substrate, an IPD substrate 160, which in this example takes the form of a semiconductor die. The IPD substrate 160 spans the space between the signal amplification paths extending through the multipath IPD die 124. The IPD regions 154, 156 include elongated input-side bond pads or bonding pads 162, 164 and a plurality of smaller output-side bond pads or bonding pads 166, 168 (only a few of which are labeled to avoid cluttering the diagram). The bonding pads 162, 164, 166, 168 are included in or electrically coupled to a grounded capacitor (e.g., the bonding pads 162, 164, 166, 168 may form or be connected to the upper metal plate of a metal-insulator-metal (MIM) capacitor formed in the IPD substrate 160), which is electrically coupled to the base flange 132 through the IPD substrate or the die body 160 of the multi-path IPD die 124. Therefore, the elements 162, 164, 166, 168 may also be referred to herein as forming part of or being connected to a "shunt capacitor" or "capacitive element." The die body 160 of the input multipath IPD die 124 can be constructed in whole or in part from various semiconductor materials, as listed above in connection with the power amplifier dies 124 and 126. For example, in one embodiment, the die body 160 can be constructed from a bulk silicon (Si) wafer or a multilayer semiconductor substrate including a buried oxide layer. The die body 188 described below can also be constructed in whole or in part from Si or another semiconductor material (e.g., in the case of a layered semiconductor structure).

[0091] A plurality of bond wires 170, 172, 174, 176 electrically interconnect the bond pads 162, 164, 166, 168 (and more generally, the multipath IPD 124) between the package input leads 136, 138 and the inputs of the power amplifier dies 128, 130. Specifically, a first bond wire array 170 electrically connects the inner edge of the carrier input lead 136 to the elongated bond pad 162 located within the input carrier IPD region 154. Second bond wire array 172 includes longer bond wires (also referred to as "double-humped" bond wires, given the common contact point on elongated bond pad 162) that electrically connect bond pad 162 to the input (here, the gate contact) of a single-stage amplifier or FET 178 formed on carrier amplifier die 128, and shorter bond wires that electrically connect bond pad 164 to the input of FET 178. Similarly, third bond wire array 174 electrically connects the inner edge of peaking input lead 138 to bond pad 164, while the longer bond wires within fourth bond wire array 176 electrically connect bond pad 164 to the input (here, the gate contact) of a single-stage amplifier or FET 180 formed on peaking amplifier die 130, and the shorter bond wires within array 176 electrically connect bond pad 168 to the input of FET 180.

[0092] exist Figure 3 In the example of FIG. 1 , the carrier input impedance MN 162, 170, 172 having a T-matching configuration is formed by the combination of the bond wire 170 (providing the first bulk inductance), the parallel capacitor coupled to the bond pad 162, and the bond wire 172. This circuit structure generally corresponds to Figure 1 68, wherein bond wire 170 corresponds to inductive element 70, a shunt capacitor coupled in part to bond pad 162 corresponds to shunt capacitor element 76, and bond wire 172 corresponds to inductive element 72. By configuring bond wires 170, 172 (e.g., by selecting appropriate dimensions) to provide an inductance at the center operating frequency of Doherty PA package 122 and configuring the shunt capacitor coupled to bond pad 162 to provide a desired capacitance (by appropriately sizing the conductive and dielectric layers of the MIM capacitor), carrier input impedance MN 162, 170, 172 can raise the source impedance of the carrier input signal to a desired level before being applied to one or more inputs of FET 178. In a similar manner, peaking input impedances MN 164, 174, 176 are provided by the combination of bond wires 174, 176 and the parallel capacitance coupled to bond pad 162; wherein the peaking input impedances MN 164, 174, 176 are also tuned as necessary to provide the desired impedance matching function of the peaking input signal before being applied to the input of FET 180.

[0093] In many respects, the output multipath IPD die 126 is similar to the input multipath IPD die 124. The output multipath IPD die 126 includes an output carrier IPD region 182, an output peaking IPD region 184, and an intermediate isolation region 186 formed between the IPD regions 182, 184. Regions 182, 184, 186 are formed at different locations in a common substrate 188; here, the body of the semiconductor die spans the space between the signal amplification paths that extend through the multipath IPD die 124. The IPD region 184, in turn, includes bonding pads or bond pads 190, 192, 194, 196. Various bond wires 198, 200 interconnect the bond pads 190, 192, 194, 196 to the FETs 178, 180 carried by the power amplifier dies 128, 130, as well as the output leads 140, 142. In addition, in this example, additional bond wires 202 electrically couple bond pads 192 and 196 to two additional leads 144 of the Doherty PA package 122. When the Doherty PA package 122 is mounted in a larger Doherty PA circuit or system, the package leads 144 provide electrical connections to circuitry within the larger system (e.g., package-external circuit elements formed on or mounted to a PCB, such as a chip cap), where such circuitry assists with FET biasing and / or baseband decoupling. Certain of the bond wires 198 and 200 thus cooperate with the bond pads 190 and 192 and the ground bond pad 204 to form the desired output impedance MN, bias circuitry, and / or harmonic termination circuitry. Consider, for example, a medium-length bond wire included in the bond wire array 198 that is bonded between an output terminal (here, the drain manifold 206 of the FET 178) and an elongated bond pad 190 within the output carrier IPD region 182. Here, the first portion of the mid-length bond wires of array 198 (in other words, the first bond wire segment in the bimodal bond wire bond on bond pad 190) collectively provides a first inductance value, while the MIM capacitor coupled to bond pad 190 provides a shunt capacitance with a selected capacitance value. The mid-length bond wires of array 198 further provide a second inductance value when extending to bond pad 192 (that is, the second bond wire segment in the bimodal bond wire) to complete the T-matched MN configuration. Harmonic termination can also be provided by shorter bond wires within array 198 (sized to provide the desired inductance), which terminate at bond pad 190. Bond pad 190, in turn, is electrically coupled to the shunt capacitor providing the desired capacitance to complete the LC circuit. Finally, the longer bond wires in array 198 extend completely from the output end 206 of carrier FET 178 to the inner edge portion of carrier output lead 140 to transfer the amplified carrier signal from FET 178 to carrier output lead 140 .A similar topology is also provided for the bond wires 200 and the peaking output IPD region 184 , where the bond wires 200 electrically interconnect the output (here, the drain manifold) of the peaking FET 180 to the bond pad regions 194 , 196 and the peaking output lead 142 in a similar manner.

[0094] With the construction of the Doherty PA package 122, several benefits are achieved. Due to the use of multipath IPD dies 124, 126 instead of a conventional four IPD die arrangement, the package footprint is minimized. Additionally, package assembly is simplified by reducing the number of dies that need to be positioned within the Doherty PA package from six dies to four dies. This not only reduces the duration of package assembly, but also facilitates precise angular positioning of the multipath IPD dies 124, 126 due, at least in part, to the larger size (primarily, the larger longitudinal dimension) of the dies 124, 126. By using multipath IPD dies 124, 126 instead of a conventional four IPD die arrangement, manufacturing variations are also advantageously reduced. By manufacturing a given multipath IPD die to include two IPD regions formed on a common substrate, uniformity of layer thickness across the substrate is better maintained to enhance consistency in device performance. For example, integrated (e.g., MIM) capacitors formed in different IPD regions can more predictably provide expected or predicted capacitance values ​​for the thickness uniformity of the conductive (e.g., Cu or other metal) layer and the dielectric (e.g., nitride) layer between the plates of the MIM capacitor. In contrast, in conventional manufacturing methods where the peaking IPD (input or output) and the carrier IPD (input or output) are formed on discrete dies, the layer thicknesses, and therefore the performance parameters (e.g., capacitance values), can vary significantly, requiring more thorough testing and die pairing procedures.

[0095] The aforementioned advantages ultimately improve the manufacturing of the entire Doherty PA package 122 and reduce the manufacturing cost of the Doherty PA package 122. At the same time, and as noted above, the Doherty PA package 122 advantageously (though not substantially) has a reduced footprint, at least in part because the longitudinal spacing between the input IPD regions is reduced and the longitudinal spacing between the output IPD regions of the multipath IPD dies 124, 126 is correspondingly reduced. As a corollary, electromagnetic (EM) interference, or crosstalk, between the carrier signal path and the peaking signal path also tends to increase in the absence of temporary additional in-package isolation or shielding. For this reason, in an embodiment, the Doherty PA package 122 is produced to additionally include an isolation structure 212 extending from the multipath IPD die 124 to the multipath IPD die 126 and extending above the amplifier die gap 152 to enhance the isolation or EM shielding between the input IPD regions 154, 156 and the output IPD regions 182, 184. Additionally, the IPD-to-IPD isolation structure may further provide isolation between the carrier amplifier die 128 and the peaking amplifier die 130, as well as the various bond wires interconnecting the power amplifier dies 128, 130 with the multipath IPD dies 124, 126, as described below.

[0096] In some cases, the IPD-to-IPD isolation structure 212 may take the form of a wall, fin, or partition extending between the intermediate isolation regions 158, 186 of the multipath IPD dies 124, 126. Such an isolation wall (or similar structure) may be a single-layer or multi-layer structure composed of one or more conductive materials, and in some embodiments, one or more magnetically conductive materials. Additionally, such an isolation wall may be electrically grounded (or otherwise coupled to a reference voltage) through one or both of the multipath IPD dies 124, 126 (e.g., by electrically connecting to conductive vias extending through the IPD dies 124, 126 to the underlying conductive base flange 132) or through additional leads extending from the body of the Doherty PA package 122. In such embodiments, the isolation wall may be bonded in place during package assembly and, in embodiments where the Doherty PA package 122 takes the form of an air cavity package, may be embedded in a lid positioned above the package body. In other cases, the IPD-to-IPD isolation structure 212 may take a different form suitable for providing the desired isolation between the carrier signal amplification path and the peaking signal amplification path, particularly between those sections of the signal amplification path that extend through adjacent IPD regions of the multipath IPD dies 124, 126 formed with impedance matching (and other such) circuitry. For example, as in Figure 2 and 3As indicated in , the IPD-to-IPD isolation structure 212 may include a bond wire array 214 bonded between a first bond pad 216 located in the intermediate isolation region 158 of the input multipath IPD die 124 and a second bond pad 218 located in the intermediate isolation region 186 of the output multipath IPD die 126.

[0097] The bond wire array 214 may be electrically coupled to a ground terminal of the Doherty PA package 122 (here, the base flange 132) via an electrical routing feature (e.g., a conductive via or metal plug) formed through one or both of the multi-path IPD dies 124, 126. This may be accomplished by referring to Figure 4 and 5 Also understand, Figure 4 and 5 The multi-path IPD dies 124 and 126 are respectively along Figure 3 The cross-sectional views are taken along the planes 4-4 and 5-5 identified in FIG. Figure 4 , the middle isolation region 158 of the multi-path IPD die 124 is shown in a cross-section taken along a cross-sectional plane of the IPD substrate 160 (here, the die body) of the semiconductor die 124. As can be seen, the bond pads 216 are defined by openings in the outer dielectric (e.g., solder mask) layer 222, which expose regions of the underlying conductive (e.g., Cu or other metal) layer 226. A cluster or group 230 of through substrate vias (TSVs) are additionally formed through the die substrate 160, extending from a front side 232 to a back side 234 of the die substrate 160. The back side 232 of the multi-path IPD substrate or die body 160 is in turn placed in electrical contact with the base flange 132 (of course, it should be noted that conductive bonding material will typically be present at the interface between the back side 232 of the die body 160 and the base flange 132). In this manner, when the Doherty PA package 122 is mounted on, for example, the substrate 160 in combination with the die body 160 described above, the substrate 160 can be electrically bonded to the die. Figure 1 When within a larger Doherty PA circuit or system, such as the described Doherty PA system 16, the bond wire array 214 is electrically coupled to the ground terminal of the Doherty PA package 122 (here, the base flange 132), and is therefore electrically coupled to ground (or another reference voltage). Such a grounded bond wire array 214 used for isolation purposes may alternatively be referred to as a "wire fence 214," wherein this term is also utilized hereinafter.

[0098] Steering Figure 5, the cross section shown is taken through the middle isolation region 186 of the substrate or die body 188 of the multi-path IPD die 126, which has an upper major surface or front side 236 and a lower major surface or back side 238. As before, the bond pad 210 is defined by an opening formed in an outer dielectric (e.g., solder mask) layer 240, which exposes an area of ​​patterned features 242 formed in a conductive (e.g., metal) layer 244. TSVs 246 extending from the front side 236 to the back side 238 are also formed through the die body 188 to electrically connect the features 242 to the base flange 132 during operation of the Doherty PA package 122, and thus, electrically ground the bond pad 218. In embodiments, various other features may also be formed in the middle isolation region 186 of the multi-path IPD die 126 and extend longitudinally therethrough. Such features may not be necessary for the functionality of wire fence 214, but are formed in both IPD regions 182, 184 and therefore conveniently extend through or across intermediate isolation region 186. In the example shown, these features include a shunt (e.g., high value) capacitor 248 and a shunt metal oxide semiconductor (MOS) capacitor structure 250. Shunt capacitor 248 is defined by a patterned metal feature (upper plate) 252 formed as part of upper metal layer 244, an intermediate dielectric region 254, a lower metal feature (lower plate) 256 formed as part of patterned metal layer 258, and a plurality of TSVs 260. In contrast, MOS capacitor structure 250 is defined by a patterned metal feature (upper plate) 262 formed as part of upper metal layer 244, an intermediate dielectric region 264, a lower metal feature (lower plate grid) 266 formed as part of patterned metal level 258, and a cluster or group of TSVs 268. Likewise, shunt capacitor 248 and MOS capacitor structure 250 may be omitted from multipath IPD die 126, or, in alternative embodiments, may be formed so as not to extend through intermediate isolation region 186 of die 126. In other implementations, any or all of the aforementioned capacitors (e.g., capacitors 248, 250) may be discrete capacitors coupled to the top surface of a multipath IPD (e.g., multipath IPD 124, 126). More generally, the circuit features formed in multipath IPD dies 124, 126 may also vary in embodiments in conjunction with variations in wire fence 214.

[0099] In an embodiment, the isolation performance of the ground wire fence 214 can be enhanced by giving the bond wires of the fence 214 different profiles. This can be achieved by referring to Figure 6 To understand more fully, Figure 61 is a cross-sectional view of the Doherty PA package 122 (shown in simplified form with various components hidden from view). In this view, the package sidewall 270 (e.g., a molded wall or window frame portion) can be seen extending vertically between the package leads 138, 142 and the base flange 132. In this example, at least three bond wires 272, 274, 276 are included in the ground wire fence 214, with each bond wire following a different bond wire profile as viewed along an axis (corresponding to the Y-axis of the graph 150) that is parallel to the front side 148 of the base flange 132 and perpendicular to the axis (corresponding to the X-axis of the graph 150) along which the multi-path IPD dies 124, 126 are spaced apart. Specifically, the bond wires 272, 276 are formed such that the apex of the bond wire 272 is positioned closer to the input multipath IPD die 124 than to the output multipath IPD die 126, while the apex of the bond wire 276 is positioned closer to the output multipath IPD die 126 than to the input multipath IPD die 124. The bond wire 274 follows a hybrid or intermediate path such that the apex of the wire 274 is located between the apexes of the bond wires 272, 276. In an embodiment, the bond wire 272 may follow at least a portion of the general shape profile of a gate bond wire connected to the input (gate) terminal of one or both of the FETs 178, 180 (e.g., in FIG. 1 ). Figure 3 172, 176), while the bond wire 276 follows at least a portion of the shape contour of the drain bond wire connected to the input (gate) terminal of one or both of the FETs 178, 180 (as shown in FIG. Figure 3 ). Shaping the bond wires 272, 274, 276 in this manner can advantageously optimize or enhance the shielding capabilities of the ground wire fence 214. Nevertheless, in other embodiments of the Doherty PA package 122, the bond wires 272, 274, 276 can have similar or identical bond wire profiles.

[0100] Thus, an example embodiment of a small footprint Doherty PA package including two multipath IPD dies and an IPD-to-IPD isolation structure in the form of a ground wire fence has been described. In further embodiments, a Doherty PA package may be produced that includes one or more multipath IPDs that differ in various respects from the conventional Dowry PA package. Figure 2-6. For example, as described above, in alternative embodiments, the Doherty PA package may include only a single multipath IPD die located on the output side or the input side of the package. Additionally or alternatively, in embodiments where the Doherty PA package has an N-way Doherty amplifier topology (N>2), the multipath IPD die may be fabricated to include three or more electrically isolated IPD regions. In other embodiments, the multipath IPD may be produced on a discrete substrate, which may be a semiconductor die, a ceramic substrate, or other substrate. As yet another possibility, in an alternative embodiment, the two multipath IPDs may be formed in a common substrate, rather than in discrete semiconductor dies as is the case in the example embodiment just described. In the latter case, the input multipath IPD and the output multipath IPD may be fabricated on different sections of a PCB embedded in the Doherty PA package. To further emphasize this point, the following will now be combined with the Figure 7 An example of such a Doherty PA package is described that includes a PCB on which the input multipath IPD and the output multipath IPD are generated.

[0101] Finally, advance to Figure 7 , shows the central region of an example Doherty PA package 278. In many respects, the Doherty PA package 278 is similar to the one described above in conjunction with Figure 2-6 The Doherty PA package 122 is described (if not identical), with particular attention to Figure 3The center portion of the Doherty PA package 122 is shown for comparison purposes. Therefore, the aforementioned structural features shared by the Doherty PA packages 122 and 278 will not be discussed in detail to avoid redundancy. As before, the Doherty PA package 278 includes an input multipath IPD 280 and an output multipath IPD 282. The input multipath IPD 280 further includes a carrier input IPD region 284, a peaking input IPD region 286, and an intermediate isolation region 288 between the IPD regions 284 and 286. The output multipath IPD 282 also includes a carrier output IPD region 288, a peaking output IPD region 290, and an intermediate isolation region 292 between the regions 288 and 290. Various bond wires (not labeled) interconnect the circuitry elements formed in the IPD regions 284, 286, 288, 290 to the FETs carried by the carrier amplifier die 294 and the peaking amplifier die 296 in a manner similar to (if not substantially identical to) that previously described. Similarly, the circuitry formed in the IPD regions 284, 286, 288, 290 effectively (though not essentially) provides input and output impedance matching, as well as other functions such as harmonic termination, baseband decoupling (e.g., provided by the circuitry formed in the IPD regions 288, 290 in combination with additional circuitry external to the Doherty PA package 278), and / or gate or drain biasing (only drain bias circuitry is shown in the illustrated example). The amplifier dies 294, 296 are attached to the front side 298 of the base flange 300, which can serve as a conductive (e.g., ground) terminal and / or heat sink for the Doherty PA package 278.

[0102] The input IPD regions 154, 156 and output IPD regions 182, 184 ( Figure 2-6 ) In contrast, the input IPD regions 284, 286 and the output IPD regions 290, 292 of the Doherty PA package 278 are not implemented using separate or discrete substrates (e.g., separate semiconductor dies or ceramic substrates). Instead, the input IPD regions 284, 286 and the output IPD regions 290, 292 are formed in different portions or sections of a PCB 302 that is embedded in the body of the Doherty PA package 122. More specifically, the input IPD regions 284, 286 are formed in a first elongated section or wing 304 of the PCB 302, while the output IPD regions 290, 292 are formed in a second elongated section or wing 306 of the PCB 302. The PCB wings 304, 306 are joined by a middle section 308 and are separated or spaced apart by an opening 310 formed in the PCB 302. This gives the PCB 302 a generally U-shaped geometry, as shown along the package centerline (parallel to the centerline). Figure 7312 as viewed looking down at PCB 302. Opening 310 further enables the power amplifier dies 294, 296 to be attached or bonded directly to the front side 298 of base flange 300. Simultaneously, forming IPD regions 284, 286 and regions 290, 292 on PCB wings 304, 306 achieves desired alignment with the power amplifier dies 294, 296; that is, aligning carrier input IPD region 284 and carrier output IPD region 290 with carrier amplifier die 294, while aligning peaking input IPD region 286 and peaking output IPD region 292 with peaking amplifier die 296, as viewed along an axis parallel to the Z-axis of graph 312. With this arrangement, the die count of Doherty PA package 278 is further reduced (to two), while still achieving the aforementioned benefits associated with reduced manufacturing costs, improved isolation performance, and reduced package size in embodiments. In yet other embodiments, PCB 302 may have different planar shapes (e.g., Figure 7 PCB 302 may be formed by repeating middle section 308 of PCB 302 near the lower area of ​​the PCB to give PCB 302 a toroidal shape); or PCB 302 may be divided into two separate PCBs by removing middle section 308. In other embodiments, the aforementioned circuit elements (e.g., capacitors) in such PCB-based multi-path IPDs may be implemented using surface mount devices (SMDs), such as SMD capacitors or "chip caps" coupled to the top surface of the PCB.

[0103] in conclusion

[0104] Therefore, PA packages such as the Doherty PA package and other PA packages (e.g., push-pull power amplifier packages) have been provided that include multipath IPDs and other associated structural features. By incorporating such multipath IPDs, the PA packages described above can increase manufacturing throughput while reducing manufacturing variations to lower overall production costs. At the same time, embodiments of the PA package can have a reduced footprint while further improving isolation characteristics in embodiments where the intra-package isolation features are incorporated into the PA package and coupled to one or more multipath IPDs. For example, EM isolation or shielding between signal paths can be improved by providing a ground wire fence that extends between the input multipath IPD and the output multipath IPD (and can be electrically coupled to the ground terminal of the package), passing through the input multipath IPD and the output multipath IPD. In such embodiments, the wire bonds of the wire fence can have different wire profiles to further enhance EM isolation. When including two or more multipath IPDs, the Doherty PA package can additionally include a PCB on which the multipath IPDs are formed. Alternatively, each multipath IPD can be formed on a discrete substrate (e.g., a ceramic substrate or a semiconductor die) that is attached to a base flange or other package substrate adjacent to the power amplifier die, resulting in a compact, economical, high-performance Doherty PA package.

[0105] Various embodiments of the above-described (e.g., Doherty) PA packages include a package body through which a first (e.g., carrier) signal amplification path and a second (e.g., peaking) signal amplification path extend, a first (e.g., carrier) amplifier die within the package body and positioned in the first signal amplification path, and a second (e.g., peaking) amplifier die within the package body and positioned in the second signal amplification path. A multipath IPD is further included in the package body and includes: (i) a first (e.g., carrier) IPD region through which the first signal amplification path extends, the first IPD region being formed in an IPD substrate at a first location and a second IPD region through which the second signal amplification path extends; (ii) a second (e.g., peaking) IPD region being formed in the IPD substrate at a second location, the second location being spaced apart from the first location along a second axis perpendicular to the first axis; and (iii) an isolation region formed in the IPD substrate at a third location between or intermediate the first and second locations.

[0106] In another embodiment, the PA package includes a package substrate, a first (e.g., carrier) amplifier die bonded to a front side of the package substrate, and a second (e.g., peaking) amplifier die bonded to the front side of the package substrate and separated from the first amplifier die by an amplifier die gap, as viewed along a first axis extending parallel to the front side of the package substrate. An input multipath IPD is provided, having a first (e.g., carrier) input IPD region, a second (e.g., peaking) input IPD region, and a first isolation region between the first and second input IPD regions. Similarly, an output multipath IPD is provided, having a first (e.g., carrier) output IPD region, a second (e.g., peaking) output IPD region, and a second isolation region between the first and second output IPD regions. An isolation structure extends from the first isolation region over the amplifier die gap and to the second isolation region. The isolation structure is electrically coupled to the package substrate via at least one of the first and second multipath IPDs.

[0107] Although at least one example embodiment has been presented in the foregoing embodiments, it should be understood that there are a large number of changes. It should also be understood that one or more example embodiments are merely examples and are not intended to limit the scope, applicability or configuration of the present invention in any way. Specifically, the foregoing embodiments will provide a convenient roadmap for implementing the example embodiments of the present invention to those skilled in the art. It should be understood that various changes can be made in terms of the function and arrangement of the elements described in the example embodiments without departing from the scope of the present invention as set forth in the appended claims. Numerical identifiers such as "first", "second", "third" have been used according to the order in which certain elements (e.g., package leads, transistors, and transistor-carrying dies) are introduced during the foregoing embodiments. Such numerical identifiers can also be used in subsequent claims to indicate the order of introduction in the claims. Therefore, such numerical identifiers can change between the embodiments and subsequent claims to reflect the difference in the order of introduction of the elements.

Claims

1. A power amplifier PA package, characterized in that: include: a package body through which the first signal amplification path and the second signal amplification path extend; a first amplifier die contained within the package body and positioned in the first signal amplification path; a second amplifier die contained within the package body and positioned in the second signal amplification path, the second amplifier die being spaced apart from the first amplifier die along a first axis; as well as a multipath integrated passive device (IPD), the multipath IPD being further contained within the package body, the multipath IPD comprising: IPD substrate; a first electrically isolated IPD region, the first signal amplification path extending through the first IPD region, the first IPD region being formed in the IPD substrate at a first location; a second electrically isolated IPD region, the second signal amplification path extending through the second IPD region, the second IPD region being formed in the IPD substrate at a second location spaced apart from the first location along a second axis parallel to the first axis; and an isolation region formed in the IPD substrate at a third position intermediate the first position and the second position; The PA package further comprises: an electromagnetic (EM) isolation structure coupled to the isolation region and extending from the multipath IPD to over a region between the first amplifier die and the second amplifier die, wherein the EM isolation structure comprises a wire fence including a plurality of bond wires contacting one or more bond pads located in the isolation region of the multipath IPD; a conductive flange to which the first amplifier die, the second amplifier die, and the IPD substrate are attached; wherein the wire fence is electrically coupled to the conductive flange through the multi-path IPD.

2. The PA package according to claim 1, characterized in that The first signal amplification path, the first amplifier die, and the first IPD region include a carrier signal amplification path, a carrier amplifier die, and a carrier IPD region, respectively; and The second signal amplification path, the second amplifier die and the second IPD region respectively include a peaking signal amplification path, a peaking amplifier die and a peaking amplifier region.

3. The PA package according to claim 2, characterized in that: The IPD substrate spans the space between the carrier signal amplification path and the peaking signal amplification path.

4. The PA package according to claim 1, characterized in that The first amplifier die has a gate terminal and a drain terminal; The PA package further comprises: a gate bonding wire contacting the gate terminal and having a gate bonding wire profile; and a drain bond wire contacting the drain terminal and having a drain bond wire profile; and wherein the plurality of bonding wires included in the wire fence include: a first bond wire having a first bond wire profile that follows at least a portion of the gate bond wire profile as viewed along a third axis perpendicular to the second axis; and A second bond wire having a second bond wire profile, as viewed along the third axis, that is different from the first bond wire profile and follows at least a portion of the drain bond wire profile.

5. The PA package according to claim 1, wherein: Also includes: a first plurality of bond wires contacting the first IPD region; as well as a second plurality of bond wires contacting the second IPD region; wherein the first IPD region includes circuitry that combines with the first plurality of bond wires to form a first impedance matching network electrically coupled to a terminal of the first amplifier die; and Wherein the second IPD region includes circuitry that combines with the second plurality of bond wires to form a second impedance matching network electrically coupled to a terminal of the second amplifier die.

6. The PA package according to claim 5, wherein: wherein the circuitry included in the first IPD region includes a first shunt capacitor; and The circuitry included in the second IPD region includes a second shunt capacitor.

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