Memory device and method of manufacturing the same

Abstract

The memory device includes: a substrate; an active layer spaced apart from the substrate and oriented laterally; a word line spaced apart from the substrate and oriented laterally along one side of the active layer in parallel to the active layer; an active body spaced apart from the substrate by passing through the active layer; a bit line spaced apart from the substrate by passing through the active layer; and a capacitor spaced apart from the other side of the active body by passing through the active layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0178427, filed on December 30, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0004] Recently, in order to increase the net die size of a memory device, the size of a memory cell continues to decrease.

[0005] As the memory cell size is miniaturized, the parasitic capacitance Cb decreases and the capacitance increases. However, due to the structural limitations of the memory cell, it is difficult to increase the net die. Summary of the invention

[0006] Embodiments of the present invention relate to a highly integrated memory cell, a memory device including the integrated memory cell, and a method of manufacturing the memory device.

[0007] According to one embodiment of the present invention, a memory device includes: a substrate; an active layer spaced apart from the substrate and oriented laterally; a word line spaced apart from the substrate and oriented laterally along one side of the active layer in parallel to the active layer; an active body spaced apart from the other side of the active body by vertically oriented through the active layer; a bit line spaced apart from the other side of the active body by vertically oriented through the active layer.

[0008] According to another embodiment of the present invention, a memory device includes memory cells arranged in a vertical direction, wherein each of the memory cells includes: an active layer including a first source / drain region, a second source / drain region and a channel body, wherein the channel body is laterally oriented between the first source / drain region and the second source / drain region; a word line laterally oriented parallel to one side of the active layer; an active body running through the channel body; a bit line vertically oriented to couple with the first source / drain region by running through the active layer; and a capacitor vertically oriented to couple with the second source / drain region by running through the active layer.

[0009] According to yet another embodiment of the present invention, a method for manufacturing a memory device includes: forming a plurality of active layers arranged in a vertical direction relative to a substrate; forming vertically oriented active bodies that penetrate the active layers to interconnect the active layers to each other; forming vertically oriented bit lines that are spaced apart from one side of the active bodies and penetrate the active layers; forming vertically oriented capacitors that are spaced apart from another side of the active bodies and penetrate the active layers; and forming a plurality of word lines that are laterally oriented adjacent to one side of each of the active layers.

[0010] These and other features and advantages of the present invention will become apparent to those of ordinary skill in the art from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a perspective view schematically showing the structure of a memory device according to an embodiment of the present invention.

[0012] Figure 1B is a plan view of the memory device taken along line AA′ of FIG. 1 .

[0013] Figure 1C It is along Figure 1B A cross-sectional view of the memory device taken along line BB'.

[0014] Figure 2A and Figure 2B is a cross-sectional view showing a memory device according to another embodiment of the present invention.

[0015] FIG. 3A to FIG. 26B is a cross-sectional view illustrating a method of manufacturing a memory device according to an embodiment of the present invention.

[0016] Fig.27A and Fig.27B A stepped wordline structure is shown.

[0017] Figures 28 to 30 A method for manufacturing a memory device according to another embodiment of the present invention is shown.

[0018] Figure 31 to Figure 33 Memory devices according to other embodiments of the present invention are shown. DETAILED DESCRIPTION

[0019] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, in the various drawings and embodiments of the present invention, the same reference numerals refer to the same parts.

[0020] The drawings are not necessarily drawn to scale, and in some cases, the scale may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as "on a second layer" or "on a substrate", it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0021] According to one embodiment of the present invention, a memory device may include: at least one laterally extending active layer (also referred to as a lateral active layer); at least one single word line WL; a vertical bit line BL that runs through the at least one active layer; and a vertical capacitor that also runs through the at least one active layer. The at least one single word line WL may be at the same distance (level) from the substrate as the at least one lateral active layer.

[0022] Figure 1A is a perspective view schematically showing the structure of a memory device 100M according to an embodiment of the present invention. Figure 1B is along Figure 1A A plan view of the memory device 100M taken along the line AA', and Figure 1C is along Figure 1B 1 is a cross-sectional view of the memory device 100M taken along line BB′.

[0023] refer to Figures 1A to 1C , the memory device 100M may include: a substrate SS; an active layer ACT, which is laterally oriented and spaced apart from the substrate SS; a word line WL, which is laterally oriented along one side of the active layer ACT and parallel to the active layer ACT; an active body ACB, which is vertically oriented and penetrates the active layer ACT; a bit line BL, which is vertically oriented and penetrates the active layer ACT and is spaced apart from one side of the active body ACB; and a capacitor CAP, which is vertically oriented and penetrates the active layer ACT and is spaced apart from the other side of the active body ACB.

[0024] The substrate SS may provide a plane extending in the first direction D1 and the third direction D3. The memory cell array MCA may be vertically positioned above the substrate SS in the second direction D2. The second direction D2 may be perpendicular to the first direction D1 and the third direction D3. The second direction D2 may be simply referred to as a vertical direction or a vertical orientation. The memory cell array MCA may include a plurality of memory cells MC vertically arranged in the second direction D2. The memory cell array MCA may be located above the substrate SS. The memory cells MC may be located above the substrate SS. For example, the memory cell array MCA may be or may include a dynamic random access memory (DRAM) memory cell array.

[0025] Each memory cell MC may include an active layer ACT, a word line WL, a bit line BL, and a capacitor CAP. A plurality of active layers ACT may be arranged vertically in the second direction D2. The active layers ACT may overlap vertically in the second direction D2. Each active layer ACT may have a plate shape, and its cross section may have a plurality of fingers. In other words, each active layer ACT may have a first elongated portion extending laterally in the first direction D1 and a plurality of fingers extending from the elongated portion in the third direction D3. The fingers may be spaced apart from each other at regular intervals. The fingers may have the same shape and size, but the present invention is not limited thereto. The first finger of each active layer ACT may be a portion of the active layer ACT penetrated by the active body ACB. The second finger of each active layer ACT may be a portion of the active layer ACT penetrated by the bit line BL, and the third finger of each active layer ACT may be a portion of the active layer ACT penetrated by the capacitor CAP. The active body ACB, the bit line BL, and the capacitor CAP may pass through the respective first, second, and third fingers along the center so that each finger leaves an equal portion on any of their respective sides in the first direction D1 and the third direction D3.

[0026] Each active layer ACT may include a first source / drain region FSD, a second source / drain region SSD, and a channel body CHB arranged between the first source / drain region FSD and the second source / drain region SSD in the first direction D1. The first source / drain region FSD, the second source / drain region SSD, and the channel body CHB may be located at the same distance.

[0027] The laterally oriented word line WL may be positioned parallel to one side of each active layer ACT. The active body ACB may penetrate a plurality of active layers ACT arranged in the second direction D2. The active body ACB may be oriented vertically in the second direction D2. The active body ACB may be referred to as an "active pillar". When viewed from above, the active body ACB may have a rectangular cross-section. The active body ACB may pass through the channel body CHB of each active layer while extending along the second direction D2. The channel body CHB of each active layer ACT may surround the active body ACB passing through it. Therefore, each channel body CHB may be located at the same distance as the corresponding active layer ACT. Multiple channel bodies CHB may overlap vertically in the second direction D2. The word lines WL may overlap vertically in the second direction D2. For example, as Figure 1A As shown in the embodiment of FIG. 4 , the ends of the word lines WL may form a stepped structure, and their lengths in the first direction gradually decrease from the bottom word line next to the substrate SS toward the top word line along the second direction.

[0028] The bit line BL may be vertically oriented in the second direction D2 and may run through each active layer ACT. The bit line BL may be coupled to the first source / drain region FSD. The bit line BL may also have a rectangular cross-section when viewed from above. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN may be formed in each active layer ACT to be coupled to the corresponding second source / drain region SSD. The dielectric layer DE and the plate node PN may extend in the second direction D2 and run through the active layer ACT.

[0029] The memory device 100M may further include a plurality of bit line contact nodes BLC ( Figure 1C ), which are formed in each active layer ACT. Each contact node BLC is coupled to the first source / drain region FSD and the bit line BL of the corresponding active layer ACT. The memory device 100M may further include: a contact liner layer CL, which is vertically oriented (i.e., extends in the second direction D2) so as to penetrate the bit line contact node BLC in the second direction D2 while surrounding the sidewall of the bit line BL. The bit line contact node BLC may also surround the bottom of the bit line BL. The bit line contact node BLC may not surround the top of the bit line BL.

[0030] The bit line BL, the active body ACB, and the capacitor CAP may extend vertically upward from the substrate SS. Each of the plurality of active layers ACT may be located at the same distance from one word line WL. The active layer ACT may be parallel to the plane of the substrate SS.

[0031] like Figure 1B As shown, the gate dielectric layer GD may be formed between one side of the channel body CHB and the word line WL. Each word line WL having a generally elongated shape extending in the first direction D1 may also include a protrusion WLP extending laterally in the third direction D3 to directly contact the gate dielectric layer GD. The portion of each word line WL extending in the first direction D1 may be referred to herein as a line portion WLL of the word line WL. The line portion WLL of each word line WL may be spaced apart from the first source / drain region FSD and the second source / drain region SSD of the corresponding active layer ACT.

[0032] The plate node PN and the dielectric layer DE may each be oriented perpendicularly to the substrate SS in the second direction D2, and the dielectric layer DE may surround the sidewalls of the plate node PN. The dielectric layer DE may also surround the bottom of the plate node PN. Multiple storage nodes SN may be arranged perpendicularly to the substrate SS in the second direction D2. The storage node SN may be formed in the corresponding active layer ACT and shaped to surround the dielectric layer DE and the plate node PN. The storage node SN and the word line WL may be located at the same distance in the second direction D3. The storage node SN may contact the capacitor contact node SNC. The capacitor contact node SNC may contact the second source / drain region SSD. The capacitor contact node SNC may surround the storage node SN. The storage node SN and the capacitor contact node SNC may be located at the same distance. From a plan view, the storage node SN may have a rectangular ring shape (see Figure 1B ).

[0033] Figure 2A and Figure 2B is a cross-sectional view showing a memory device 100 according to another embodiment of the present invention.

[0034] refer to Figure 2A and Figure 2B The memory device 100 may include a peripheral circuit 110 , a lower structure 120 , and a memory cell array 130M, and the lower structure 120 and the memory cell array 130M are sequentially formed above the peripheral circuit 110 .

[0035] The peripheral circuit 110 may include a plurality of control circuits. At least one control circuit in the peripheral circuit 110 may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuit 110 may include an address decoder circuit, a read circuit, and a write circuit, etc. At least one control circuit in the peripheral circuit 110 may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.

[0036] The memory cell array 130M may include a DRAM memory cell array, and the peripheral circuit 110 may include a sense amplifier SA. The sense amplifier SA may be coupled to the multi-level metal wiring MLM.

[0037] The lower structure 120 may include a stop layer 121 and a lower interlayer dielectric layer ILD122. The stop layer 121 may include a material having an etching selectivity in a series of etching processes for forming the subsequent memory cell array 130M. For example, the stop layer 121 may include a polysilicon layer. The stop layer 121 may be formed by depositing a polysilicon layer and etching the polysilicon layer. The stop layer 121 may be formed in the shape of a plurality of stop layer islands spaced apart from each other above the lower structure 120. A protective layer 123 may be formed on the surface of the stop layer 121.

[0038] The lower structure 120 may provide a plane extending in the first direction D1 and the third direction D3, and the memory cell array 130M may be vertically positioned above the lower structure 120 in the second direction D2. The second direction D2 may be perpendicular to the first direction D1 and the third direction D3. The memory cell array 130M may include a plurality of memory cells MC arranged vertically in the second direction D2. The first dielectric material 131 may be formed between the memory cells MC to be arranged vertically in the second direction D2. The first dielectric material 131 and the memory cells MC may be vertically formed alternately in the second direction D2. The second dielectric material 132 surrounding the memory cells MC may be formed between the first dielectric materials 131 located in the vertical direction. In one embodiment, the first dielectric material 131 may, for example, include silicon oxide, and the second dielectric material 132 may, for example, include silicon nitride.

[0039] Each memory cell MC may include an active layer 151, a word line 173, a bit line 184, and a capacitor 195. These active layers 151 may be arranged vertically in the second direction D2. Each active layer 151 may include a first source / drain region 163, a second source / drain region 164, and a channel body 157, which is laterally oriented in the direction D1 between the first source / drain region 163 and the second source / drain region 164. The first source / drain region 163, the second source / drain region 164, and the channel body 157 may be located at the same distance. The word line 173 may be positioned to be parallel to one side of each active layer 151 and laterally oriented. The active body 156 may be formed to penetrate the active layer 151. The active body 156 may penetrate the channel body 157 in the second direction D2. The bit line 184 may be vertically oriented in the second direction D2 and may penetrate the active layer 151 to be coupled to the first source / drain region 163. The capacitor 195 may include a storage node 192, a dielectric layer 193, and a plate node 194. The storage node 192 may be formed in the active layer 151 to be coupled to the second source / drain region 164. The dielectric layer 193 and the plate node 194 may penetrate the active layer 151.

[0040] The memory device 100M may further include a bit line contact node 183 formed in the active layer 151 and coupled to the first source / drain region 163 and the bit line 184. The memory device 100 may further include a contact liner layer 182 vertically oriented in the second direction D2 to penetrate the bit line contact node 183 while surrounding the sidewall of the bit line 184.

[0041] The side of the active layer 151 may be covered by the protective layer 134. A portion of the protective layer 134 may be cut, and one side of the active layer 151 may be partially exposed by the cut protective layer 134. Here, the exposed side may be a portion of the first source / drain region 163, the second source / drain region 164, and the channel body 157.

[0042] A gate dielectric layer 172 may be formed between one side of the channel body 157 and the word line 173. An isolation dielectric layer 165 may be formed between the first and second source / drain regions 163 and 164 and the word line 173. The word line 173 may contact a slit dielectric layer 174. As will be described later, a plurality of word lines 173 may be isolated from one another by the slit dielectric layer 174.

[0043] The plate node 194 and the dielectric layer 193 may be oriented vertically relative to the lower structure 120 in the second direction D2, and the dielectric layer 193 may surround the sidewall of the plate node 194. A plurality of storage nodes 192 may be arranged vertically relative to the lower structure 120 in the second direction D2. The storage node 192 may be formed in the active layer 151. The storage node 192 may be shaped to surround the dielectric layer 193 and the plate node 194. The storage node 192 and the word line 173 may be located at the same distance from the peripheral circuit 110 along the second direction D2. The storage node 192 may contact the capacitor contact node 192C. The capacitor contact node 192C may contact the second source / drain region 164. The capacitor contact node 192C may surround the storage node 192. The storage node 192 and the capacitor contact node 192C may be located at the same distance. The storage node 192 may have a transverse annular shape.

[0044] The bit line contact node 183 may be coupled to the first source / drain region 163, and the storage node 192 may be coupled to the second source / drain region 164. The bit line contact node 183, the storage node 192, and the channel body 157 may be laterally arranged in the first direction D1.

[0045] Each active layer 151 may be oriented laterally in the first direction D1. The word line 173 may be oriented laterally in the first direction D1. The active layer 151 may be vertically stacked in the second direction D2. The word line 173 may be vertically stacked in the second direction D2. The active layer 151 and the word line 173 may be parallel to each other. The active layer 151 and the word line 173 may be located at the same lateral distance. The end of the word line 173 may have a step shape in the second direction D2. In other words, the word lines 173 stacked in the second direction D2 may have different lengths. The bit line 184 and the capacitor 195 may be vertically oriented in the second direction D2. The bit line contact node 183 may extend in the third direction D3 from the first source / drain region 163. The storage node 192 may extend in the third direction D3 from the second source / drain region 164.

[0046] FIG. 3A to FIG. 26B is a cross-sectional view illustrating a method of manufacturing a memory device according to an embodiment of the present invention. FIG. 3A to FIG. 26A is a plan view, and FIG. 3B to FIG. 26B It is a cross-sectional view.

[0047] Figure 3B is along Figure 3A A cross-sectional view taken along line AA'.

[0048] refer to Figure 3A and Figure 3B , the lower structure 120 and the upper structure 130 may be sequentially formed above the peripheral circuit 110 .

[0049] The peripheral circuit 110 may be made of a material suitable for semiconductor processing. The peripheral circuit 110 may include at least one of a conductive material, a dielectric material, and a semiconductor material. Various materials may be formed in the peripheral circuit 110. The peripheral circuit 110 may include a semiconductor substrate, and the semiconductor substrate may be formed of a material containing silicon. For example, the peripheral circuit 110 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The peripheral circuit 110 may include other semiconductor materials, such as germanium. The peripheral circuit 110 may include a III / V semiconductor substrate, such as a compound semiconductor substrate, for example, GaAs. The peripheral circuit 110 may include a silicon on insulator (SOI) substrate.

[0050] According to another embodiment of the present invention, the peripheral circuit 110 may include a semiconductor substrate and a plurality of integrated circuits formed on the semiconductor substrate. For example, the peripheral circuit 110 may include a plurality of control circuits. The control circuit of the peripheral circuit 110 may include at least one of the following: an N-channel transistor, a P-channel transistor, a CMOS circuit, an address decoder circuit, a read circuit, a write circuit, a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin channel transistor (FinFET), etc. In one embodiment, at least one control circuit in the peripheral circuit 110 may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof, at least one control circuit in the peripheral circuit 110 may include an address decoder circuit, a read circuit, and a write circuit, etc., and at least one control circuit in the peripheral circuit 110 may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin channel transistor (FinFET), etc.

[0051] Although not shown, the peripheral circuit 110 may include a sense amplifier SA, and the sense amplifier SA may be coupled to a multi-level metal wiring (MLM).

[0052] The lower structure 120 may include a stop layer 121 and a lower interlayer dielectric layer 122. The stop layer 121 may include a material having an etching selectivity during a subsequent etching process of the upper structure 130. For example, the stop layer 121 may include a polysilicon layer. The stop layer 121 may be formed by depositing a polysilicon layer and etching the polysilicon layer to form a plurality of stop layer islands (i.e., spaced-apart regions) that are spaced apart from each other and formed above the peripheral circuit 110.

[0053] After forming the etch stop layer 121 having a plurality of islands over the peripheral circuit 110, a lower interlayer dielectric layer 122 may be formed to fill spaces between the islands of the etch stop layer 121. The lower interlayer dielectric layer 122 may be formed by depositing a dielectric material on the peripheral circuit 110 including the etch stop layer 121 and then performing planarization.

[0054] The lower interlayer dielectric layer 122 may include, for example, oxide.

[0055] The upper structure 130 may include a first material layer 131 and a second material layer 132. The upper structure 130 may include a plurality of first material layers 131 and a plurality of second material layers 132. The upper structure 130 may be an alternating stack, wherein the first material layer 131 and the second material layer 132 are alternately stacked. The first material layer 131 and the second material layer 132 may be different materials. The first material layer 131 and the second material layer 132 may have different etching selectivities.

[0056] In one embodiment, the first material layer 131 may include silicon oxide, and the second material layer 132 may include silicon nitride. The stack of the first material layer 131 and the second material layer 132 may be referred to as an "oxide-nitride (ON) stack", and the upper structure 130 may include at least one ON stack. The number of ON stacks may be set to correspond to the number of memory cells.

[0057] The first material layers 131 may be respectively located at the lowermost portion and the uppermost portion of the upper structure 130. The lowermost first material layer 131 and the uppermost first material layer 131 may be thicker than the remaining first material layers 131. Except for the lowermost first material layer 131 and the uppermost first material layer 131, the first material layers 131 and the second material layers 132 may have the same thickness.

[0058] Hereinafter, in a plan view, reference numerals of the lower structure 120 between the peripheral circuit 110 and the upper structure 130 will be omitted.

[0059] Figure 4B is along Figure 4A A cross-sectional view taken along the line A-A'. Figure 4A and Figure 4B , a portion (i.e., the first region) of the upper structure 130 may be etched using the first mask M1. The etching process of the first region of the upper structure 130 may be performed until it ends at the stop layer 121. As a result, a plurality of unit openings 140 may be formed that penetrate the upper structure 130. The first region of the upper structure 130 may be dry-etched to form the unit openings 140.

[0060] The first mask M1 may be an etch barrier layer during the process of etching the upper structure 130. The first mask M1 may include a photoresist pattern. According to another embodiment of the present invention, the first mask M1 may include a hard mask material. The first mask M1 may include amorphous carbon or polysilicon.

[0061] To prevent the cell opening 140 from not opening, the process of etching the cell opening 140 may include over-etching. As a result, the bottom of the cell opening 140 may partially extend into the island of the etch stop layer 121. In other words, a concave surface may be formed on the surface of each island of the etch stop layer 121.

[0062] The cell opening 140 is a vertical opening that is vertically oriented starting from the lower structure 120 and may vertically extend to the upper surface of the etch stop layer 121 and pass through the upper structure 130. The sidewall of the cell opening 140 may have a vertical profile. The cell opening 140 may refer to a region where a portion of a plurality of memory cells are to be formed.

[0063] From the perspective of the top view, the unit opening 140 may include a plurality of fingers. The unit opening 140 may be a finger-shaped opening. For example, the unit opening 140 may include a first finger 141, a second finger 142, and a third finger 143. Hereinafter, the first finger 141 may be referred to as a first unit opening 141, the second finger 142 may be referred to as a second unit opening 142, and the third finger 143 may be referred to as a third unit opening 143.

[0064] like Figure 4A As shown, the first cell opening 141, the second cell opening 142, and the third cell opening 143 may be coupled to each other. The first cell opening 141 may provide a space in which an active body is to be formed, the second cell opening 142 may provide a space in which a bit line is to be formed, and the third cell opening 143 may define a space in which a capacitor is to be formed. The first cell opening 141 may be referred to as an "active body opening", and the second cell opening 142 may be referred to as a "bit line opening". The third cell opening 143 may be referred to as a "capacitor opening".

[0065] From the perspective of the top view, the first unit opening 141 may be located at the center, the second unit opening 142 may be located at one side (or left side) of the first unit opening 141, and the third unit opening 143 may be located at the other side (or right side) of the first unit opening 141. The opening area of ​​the third unit opening 143 may be larger than the first unit opening 141 and the second unit opening 142. Since the third unit opening 143 is made larger, the size of the capacitor formed subsequently can be increased. As a result, the capacitance can be sufficiently ensured.

[0066] As described above, the cross section of the unit opening 140 may have a multi-finger shape. The first unit opening 141, the second unit opening 142, and the third unit opening 143 may be arranged side by side in the shape of a multi-finger. From a top view, the unit opening 140 may have an elongated portion extending in the first direction D1, and three fingers 141, 142, and 143 protrude laterally from the elongated portion in the third direction D3.

[0067] The second material layer 132 may be replaced with the active layer 151 through the following series of processes: A portion of the active layer 151 may be replaced with the channel body 157 , the bit line contact node 183 , and the storage node 192 .

[0068] Figure 5B is along Figure 5A A cross-sectional view taken along the line A-A'. Figure 5A and Figure 5B, the protective layer 123 may be formed by oxidizing the recessed surface of the etch stop layer 121. The protective layer 123 may be formed by exposing the recessed surface of the etch stop layer 121 to a thermal oxidation process. For example, when the etch stop layer 121 includes polysilicon, the protective layer 123 may be formed of silicon oxide. The protective layer 123 may protect the etch stop layer 121 in subsequent processes. Moreover, the protective layer 123 may electrically insulate the subsequent bit line and capacitor from the etch stop layer 121.

[0069] The protection layer 123 may not fill the bottom of the cell opening 140, that is, the recessed surface of the etch-stop layer 121. The protection layer 123 may be conformally formed on the recessed surface of the etch-stop layer 121.

[0070] Figure 6B is along Fig. 6A A cross-sectional view taken along the line A-A'. Fig. 6A and Figure 6B , through the unit opening 140, a portion of the upper structure 130 may be selectively recessed. For example, the second material layer 132 of the upper structure 130 may be selectively recessed laterally. A plurality of lateral recesses 133 may be formed in the upper structure 130 by recessing (e.g., etching) the second material layer 132 laterally. The lateral recesses 133 may be formed between the vertically stacked first material layers 131. The lateral recessing of the second material layer 132 may be performed by wet etching or dry etching. For example, when the second material layer 132 includes silicon nitride, the lateral recesses 133 may be formed by wet etching of silicon nitride.

[0071] The lateral recesses 133 may extend laterally from the sides of the first to third cell openings 141, 142, and 143 into the upper structure 130. As a result, the lateral recesses 133 may extend from the sides of the first, second, and third cell openings 141, 142, and 143, respectively.

[0072] Figure 7B is along Fig. 7A A cross-sectional view taken along the line A-A'. Fig. 7A and Figure 7B , the side of the second material layer 132 may be selectively oxidized. As a result, the sidewall of the lateral recess 133 may be covered by selective oxides 134. For example, when the second material layer 132 includes silicon nitride, the selective oxide 134 may include silicon oxynitride.

[0073] Subsequently, an active material 150 may be deposited. The active material 150 may fill the lateral recess 133. The active material 150 may cover the sidewalls of the first to third unit openings 141, 142, and 143, but may not fill the first to third unit openings 141, 142, and 143. In other words, the active material 150 may conformally cover the sidewalls of the first to third unit openings 141, 142, and 143 while filling the lateral recess 133. Each selective oxide 134 may be located between the active material 150 and the second material layer 132. The active material 150 may include a semiconductor material. The active material 150 may include polysilicon. The active material 150 may include P-type polysilicon or undoped polysilicon. The thickness of the active material 150 may be adjusted to fill the lateral recess 133 without a gap.

[0074] Figure 8B is along Fig. 8A A cross-sectional view taken along the line A-A'. Fig. 8A and Figure 8B , an active isolation process may be performed. For example, the active material 150 may be selectively etched to form active layers 151 in the lateral recesses 133, respectively. The active layers 151 respectively formed in the lateral recesses 133 may be isolated from each other in the vertical direction. The sidewalls of the active layers 151 may be covered by selective oxides 134, respectively. The selective oxides 134 may be respectively located between the active layers 151 and the second material layer 132.

[0075] From the perspective of the top view, the active layer 151 may have a closed ring shape. Therefore, the first cell opening 141, the second cell opening 142, and the third cell opening 143 may be formed to penetrate the vertically stacked active layer 151. The active layer 151 may include a plurality of fingers. Each finger may be penetrated by the first cell opening 141 to the third cell opening 143 located therein.

[0076] Fig. 9B is along Fig. 9A A cross-sectional view taken along the line A-A'. Fig. 9A and Fig. 9B , a sacrificial liner layer 152 may be formed to protect the active layer 151. The sacrificial liner layer 152 may include a dielectric material. For example, the sacrificial liner layer 152 may be formed of silicon nitride or silicon oxide.

[0077] A sacrificial material 153 may be formed on the sacrificial liner layer 152. The sacrificial material 153 may fill the first to third cell openings 141, 142, and 143 on the sacrificial liner layer 152. The sacrificial material 153 may include a metal-based material. The sacrificial material 153 may include a metal and a metal nitride. The sacrificial material 153 may include tungsten. The sacrificial material 153 may be planarized so as to remain only inside the first to third cell openings 141, 142, and 143.

[0078] An upper interlayer dielectric layer (ILD) 154 may be formed over the sacrificial material 153. The upper interlayer dielectric layer 154 may include silicon oxide.

[0079] As described above, a plurality of active layers 151 may be formed in the upper structure 130. The active layers 151 and the first material layers 131 may be alternately stacked in a vertical direction. Sides of the active layers 151 may be respectively surrounded by the second material layers 132. The upper structure 130 may be referred to as a mold structure, and the mold structure may include: an alternating stack in which the active layers 151 and the first material layers 131 are alternately stacked in a vertical direction.

[0080] Fig. 10B is along Fig. 10A A cross-sectional view taken along the line A-A'. Fig. 10A and Fig. 10B , the first cell opening 141 can be exposed again. To this end, the sacrificial liner layer 152 and the sacrificial material 153 filling the first cell opening 141 can be selectively removed. For example, by using the second mask M2, a portion of the upper interlayer dielectric layer 154 can be etched to expose a portion corresponding to the first cell opening 141, and then the sacrificial liner layer 152 and the sacrificial material 153 filling the first cell opening 141 can be etched.

[0081] As described above, the exposed first cell opening 141 may be simply referred to as an “active body opening 155 .” A portion of each active layer 151 may be exposed through the active body opening 155 .

[0082] The active body opening 155 may be oriented vertically relative to the lower structure 120 .

[0083] Fig. 11B is along Fig.11A A cross-sectional view taken along the line A-A'. Fig.11A and Fig. 11B, after removing the second mask M2, the active body opening 155 may be filled with an active body 156. The active body 156 may include P-type polysilicon. The active body 156 may be formed by depositing P-type polysilicon to fill the active body opening 155 and performing planarization. During the planarization of the P-type polysilicon, a portion of the sacrificial material 153 and the sacrificial liner layer 152 may be planarized.

[0084] The active body 156 may interconnect the active layers 151 positioned in a vertical direction. A body bias may be applied to the active body 156. The active body 156 may be a columnar shape. The active body 156 may penetrate the active layers 151 stacked in a vertical direction.

[0085] Fig. 12B is along Fig. 12A A cross-sectional view taken along the line A-A'. Fig. 12A and Fig. 12B , when the active layer 151 includes undoped polysilicon, a heat treatment process may be subsequently performed to diffuse the P-type impurities from the active body 156. Therefore, a portion of the active layer 151 in contact with the active body 156 may be doped with the P-type impurities. The portion of the active layer 151 doped with the P-type impurities may be the channel body 157. The channel body 157 may be stacked in a vertical direction. At one level, the channel body 157 and the active layer 151 may be located at the same distance.

[0086] From a top view perspective, the channel body 157 may have a surrounding shape surrounding the active body 156. The active body 156 may be shaped to penetrate the channel body 157 stacked in a vertical direction.

[0087] Fig. 13B is along Fig.13A A cross-sectional view taken along line C-C' of Fig. 13C is along Fig.13A A cross-sectional view taken along line D-D'.

[0088] refer to FIG. 13A to FIG. 13C, an isolation opening 161 may be formed at a position spaced apart from the active layer 151. For example, after forming a third mask (not shown) above the upper structure 130, the second region of the upper structure 130 (here, a portion where the first to third unit openings 141, 142, and 143 are not formed) may be etched using the third mask. As a result, when the upper interlayer dielectric layer 154, the plurality of first material layers 131, and the plurality of second material layers 132 are etched, a pair of isolation openings 161 isolated from each other may be formed. When the isolation opening 161 is formed to be spaced apart from the active layer 151 laterally, the second material layer 132 may be selectively recessed from the sidewall of the isolation opening 161, thereby exposing one side of the active layer 151. According to another embodiment of the present invention, the etching process for forming the isolation opening 161 may be performed such that the sidewall of the isolation opening 161 exposes one side of the active layer 151. The isolation opening 161 may be vertically oriented in the stacking direction of the memory cell.

[0089] Subsequently, an impurity doping process 162 may be performed. Impurities may be doped onto the exposed portion of the active layer 151 through the isolation opening 161. As a result, a first source / drain region 163 and a second source / drain region 164 may be formed. The impurity doping process 162 may include an N-type impurity doping process. The first source / drain region 163 and the second source / drain region 164 may be N-type source / drain regions.

[0090] The first source / drain region 163 may be a portion to be subsequently coupled to a bit line, and the second source / drain region 164 may be a portion to be subsequently coupled to a capacitor.

[0091] The impurity doping process 162 may be performed by tilt implantation. According to another embodiment of the present invention, the impurity doping process 162 may be performed by a plasma doping process.

[0092] The first source / drain region 163 and the second source / drain region 164 may be laterally spaced apart from each other by the channel body 157 therebetween. Thus, a lateral channel may be defined in the channel body 157 between the first source / drain region 163 and the second source / drain region 164.

[0093] Fig. 14B is along Fig.14A A cross-sectional view taken along line CC' of Fig. 14C is along Fig.14A A cross-sectional view taken along line D-D'.

[0094] refer to FIG. 14A to FIG. 14C, the isolation opening 161 may be filled with an isolation dielectric layer 165. The isolation dielectric layer 165 may include silicon oxide. The isolation dielectric layer 165 may be vertically oriented relative to the lower structure 120. The isolation dielectric layer 165 may be referred to as a bonding isolation layer. The isolation dielectric layer 165 may face the first source / drain region 163 and the second source / drain region 164. The isolation dielectric layer 165 may be vertically oriented in the stacking direction of the memory cell.

[0095] Fig. 15B is along Fig.15A A cross-sectional view taken along line CC' of Fig. 15C is along Fig.15A A cross-sectional view taken along line D-D'. Fig.15D is along Fig.15A A cross-sectional view taken along the line BB' of FIG. FIG. 15A to FIG. 15D , a slit 166 may be formed. The slit 166 may be formed around the isolation dielectric layer 165. The isolation dielectric layer 165 may be located between the active layer 151 and the slit 166. The slit 166 may be laterally spaced apart from the active layer 151.

[0096] The slit 166 may be formed by etching the third region of the upper structure 130. For example, the slit 166 may be formed in the third region of the upper structure 130 by etching the alternating stack of the upper interlayer dielectric layer 154, the first material layer 131, and the second material layer 132. The bottom of the slit 166 may be located on the top surface of the lower structure 120.

[0097] Fig. 16B is along Fig.16A A cross-sectional view taken along line C-C', Fig. 16C is along Fig.16A A cross-sectional view taken along line D-D' of Fig.16D is along Fig.16A A cross-sectional view taken along line BB'.

[0098] refer to FIG. 16A to FIG. 16D , the second material layer 132 can be selectively peeled off through the slit 166. As a result, the second material layer 132 can be selectively removed between the lateral isolation dielectric layers 165 located in the lateral direction. Moreover, the second material layer 132 can be selectively removed between the slit 166 and the isolation dielectric layer 165.

[0099] As described above, through the selective removal process of the second material layer 132 , a lateral gate recess 171 may be formed between the first material layers 131 stacked in the vertical direction in a self-aligned manner.

[0100] The lateral gate recess 171 may expose a portion of the protection layer 134. After the second material layer 132 is stripped, a portion of the protection layer 134 may be removed to expose the channel body 157.

[0101] Fig. 17B is along Fig.17A A cross-sectional view taken along line CC' of Fig. 17C is along Fig.17A A cross-sectional view taken along line D-D'. Fig.17D is along Fig.17A A cross-sectional view taken along line BB'.

[0102] refer to FIG. 17A to FIG. 17D , a gate dielectric layer 172 may be formed. The gate dielectric layer 172 may be formed by selectively oxidizing the surface of the channel body 157 exposed by the lateral gate recess 171 .

[0103] A word line 173 may be formed over the gate dielectric layer 172 to fill the lateral gate recess 171. The word line 173 may be formed of a metal-based material. The word line 173 may be formed by stacking titanium nitride and tungsten. For example, after conformally forming titanium nitride on the lateral gate recess 171, the lateral gate recess 171 may be gap-filled with tungsten. Subsequently, the titanium nitride and tungsten may be etched back to form a word line 173 isolated in the vertical direction. This may be referred to as a word line isolation process, and the edge of the word line 173 may be located inside the lateral gate recess 171. That is, the edge of the word line 173 may be formed using an undercut between the first material layers 131. According to another embodiment of the present invention, the word line 173 may include polysilicon doped with impurities.

[0104] As described above, a plurality of word lines 173 may be stacked in a vertical direction. The first material layer 131 may be located between the word lines 173 stacked in the vertical direction. The plurality of first material layers 131 and the plurality of word lines 173 may be alternately stacked in a direction perpendicular to the lower structure 120. The word lines 173 and the active layer 151 may be located at the same distance.

[0105] Fig.18B is along Fig.18A A cross-sectional view taken along line CC' of Fig. 18C is along Fig.18A A cross-sectional view taken along line D-D'. Fig.18D is along Fig.18A A cross-sectional view taken along line BB'.

[0106] refer to 18A to 18D , after forming the word line 173, the slit 166 may be filled with a slit dielectric layer 174. For example, the slit dielectric layer 174 may include an oxide, such as silicon oxide.

[0107] Fig.19B is along Fig.19A A cross-sectional view taken along the line A-A'. Fig.19A and Fig.19B , a top interlayer dielectric layer 180 may be formed over the slit dielectric layer 174 and the upper structure 130. For example, the top interlayer dielectric layer 180 may include silicon oxide.

[0108] Subsequently, the sacrificial material 153 and the sacrificial protection layer 152 filling the second cell opening 142 may be removed to form a bit line opening 181. For example, after etching the top interlayer dielectric layer 180 of a portion corresponding to the second cell opening 142, the sacrificial material 153 and the sacrificial protection layer 152 filling the second cell opening 142 may be etched.

[0109] The protection layer 123 may be exposed on the bottom of the bit line opening 181. The bit line opening 181 may be vertically oriented with respect to the lower structure 120. The bit line opening 181 may have a shape vertically penetrating the active layer 151.

[0110] Fig. 20B is along Fig. 20A A cross-sectional view taken along the line A-A'. Fig. 20A and Fig. 20B , a first contact liner layer 182 may be formed, which covers the bit line opening 181. The first contact liner layer 182 may include impurities. For example, the first contact liner layer 182 may include N-type polysilicon.

[0111] Fig.21B is along Fig.21A A cross-sectional view taken along the line A-A'. Fig.21A and Fig.21B , a heat treatment may be performed to diffuse the N-type impurities from the first contact pad layer 182. As a result, the N-type impurities may be doped in a portion of the active layer 151 that contacts the first contact pad layer 182. The first contact pad layer 182 and the portion of the active layer 151 doped with the N-type impurities may form a bit line contact node 183. From a top view perspective, the bit line contact node 183 may be shaped to penetrate the upper structure 130 and may extend laterally to be located between the first material layers 131 while covering the sidewalls of the bit line opening 181. In this way, a portion of the bit line contact node 183 may be a portion of the active layer 151 doped with the N-type impurities.

[0112] According to another embodiment of the present invention, after the heat treatment, the first contact liner layer 182 may be removed. In this way, the bit line contact node 183 may not cover the sidewall of the bit line opening 181, but may be located only between the first material layers 131. The bit line contact node 183 may be located at the same distance as the active layer 151, and may also be located at the same distance as the word line 173.

[0113] Fig. 22B is along Fig.22A A cross-sectional view taken along the line A-A'. Fig.22A and Fig. 22B , a bit line 184 may be formed on the bit line contact node 183 to fill the bit line opening 181. The bit line 184 may be formed by forming a bit line conductive material to fill the bit line opening 181 and then performing planarization. The bit line 184 may include a metal-based material. The bit line 184 may include a stack of metal nitride and metal. For example, the bit line 184 may be formed by stacking titanium nitride and tungsten. According to another embodiment of the present invention, an ohmic contact layer (not shown) may be further formed between the bit line 184 and the bit line contact node 183. For example, the ohmic contact layer may include a metal silicide.

[0114] As described above, the bit line 184 may be vertically oriented with respect to the lower structure 120. From a top view perspective, the bit line 184 may have a shape penetrating the bit line contact node 183. The bit line contact node 183 may have a shape surrounding the bit line 184.

[0115] Fig. 23B is along Fig.23A A cross-sectional view taken along the line A-A'. Fig.23A and Fig. 23B , the sacrificial material 153 and the sacrificial protection layer 152 filling the third unit opening 143 may be removed to form the capacitor opening 190. For example, after etching the top interlayer dielectric layer 180 and the upper interlayer dielectric layer 154 of the portion corresponding to the third unit opening 143, the sacrificial material 153 and the sacrificial protection layer 152 filling the second unit opening 143 may be etched. Although not shown, an additional hard mask layer may be further formed over the top interlayer dielectric layer 180, and by using the additional hard mask layer, the sacrificial material 153 and the sacrificial protection layer 152 may be removed.

[0116] The protective layer 123 may be exposed on the bottom surface of the capacitor opening 190. The capacitor opening 190 may be vertically oriented with respect to the lower structure 120. The capacitor opening 190 may be shaped to vertically penetrate the active layer 151.

[0117] Fig. 24B is along Fig.24AA cross-sectional view taken along the line A-A'. Fig.24A and Fig. 24B , a second contact liner layer 191 may be formed to cover the capacitor opening 190. The second contact liner layer 191 may include impurities. For example, the second contact liner layer 191 may include N-type polysilicon.

[0118] Fig.25B is along Fig.25A A cross-sectional view taken along the line A-A'. Fig.25A and Fig.25B , heat treatment may be performed to diffuse N-type impurities from the second contact pad layer 191. As a result, N-type impurities may be doped in a portion of the active layer 151 that contacts the second contact pad layer 191. A portion of the active layer 151 doped with N-type impurities may be a storage node 192 of a capacitor. From a top view perspective, the storage node 192 may extend laterally to be located between the first material layers 131 while covering the sidewalls of the capacitor opening 190. In this way, the storage node 192 may be a portion in which a portion of the active layer 151 is doped with N-type impurities. The storage node 192 may be stacked in a vertical direction with the first material layer 131 interposed therebetween. The storage node 192 may be alternately stacked with the first material layer 131.

[0119] Fig.26B is along Fig.26A A cross-sectional view taken along the line A-A'. Fig.26A and Fig.26B , after removing the second contact liner layer 191 , a dielectric layer 193 and a plate node 194 may be formed on the storage node 192 to fill the capacitor opening 190 .

[0120] Dielectric layer 193 may conformally cover capacitor opening 190 , and plate node 194 may completely fill capacitor opening 190 above dielectric layer 193 .

[0121] Dielectric layer 193 and plate node 194 may be formed by depositing a dielectric material and plate node layer over capacitor opening 190 and then planarizing the dielectric material and plate node layer to remain in capacitor opening 190 .

[0122] The dielectric layer 193 may include a single layer material, a multilayer material, a laminated material, a mixed material, or a combination thereof. The dielectric layer 193 may include a high-k material. The dielectric layer 193 may have a dielectric constant higher than that of silicon oxide (SiO2). Silicon oxide may have a dielectric constant of about 3.9, and the dielectric layer 193 may include a material having a dielectric constant of about 4 or greater. The high-k material may have a dielectric constant of about 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof. The dielectric layer 193 may be formed by atomic layer deposition (ALD).

[0123] The dielectric layer 193 may be formed of an oxide based on zirconium. The dielectric layer 193 may have a laminated structure including zirconium oxide (ZrO2). The laminated structure including zirconium oxide (ZrO2) may include ZA (ZrO2 / Al2O3) or ZAZ (ZrO2 / Al2O3 / ZrO2). ZA may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). ZAZ may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked sequentially. ZrO2, ZA and ZAZ may be referred to as zirconium oxide-based layers. According to another embodiment of the present invention, the dielectric layer 193 may be formed of an oxide based on hafnium. The dielectric layer 193 may have a laminated structure including hafnium oxide (HfO2). The stacked structure including hafnium oxide (HfO 2 ) may include HA (HfO 2 / Al 2 O 3 ) or HAH (HfO 2 / Al 2 O 3 / HfO 2 ). HA may have a structure in which aluminum oxide (Al 2 O 3 ) is stacked on hafnium oxide (HfO 2 ).

[0124] HAH may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are sequentially stacked. HfO2, HA and HAH may be referred to as hafnium oxide-based layers. In ZA, ZAZ, HA and HAH, aluminum oxide (Al2O3) may have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of aluminum oxide (Al2O3) may be lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, dielectric layer 193 may include a stack of a high-k material and a high-bandgap material having a bandgap energy greater than that of the high-k material. In addition to aluminum oxide (Al2O3), dielectric layer 193 may also include silicon oxide (SiO2) as another high-bandgap material. Dielectric layer 193 may include a high-bandgap material, thereby suppressing leakage current. The high-bandgap material may be very thin. The high-bandgap material may be thinner than the high-k material.

[0125] According to another embodiment of the present invention, the dielectric layer 193 may include a laminated structure in which a high-k material and a high bandgap material are alternately stacked, such as ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3). In the above laminated structure, aluminum oxide (Al2O3) may be very thin.

[0126] According to another embodiment of the present invention, the dielectric layer 193 may include hafnium oxide having a tetragonal phase or zirconium oxide having a tetragonal phase.

[0127] According to another embodiment of the present invention, the dielectric layer 193 may have a stacked structure including hafnium oxide having a tetragonal phase and zirconium oxide having a tetragonal phase.

[0128] Plate nodes 194 may include metal-based materials. Plate nodes 194 may include metal nitrides. Plate nodes 194 may include metals, metal nitrides, metal carbides, conductive metal nitrides, conductive metal oxides, or combinations thereof. Plate nodes 194 may be formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), or combinations thereof.

[0129] As a result of the above series of processes, capacitor 195 may be formed, and capacitor 195 may include storage node 192, dielectric layer 193, and plate node 194. Dielectric layer 193 and plate node 194 may be vertically oriented relative to lower structure 120, and each storage node 192 may surround dielectric layer 193 and plate node 194. Storage node 192 may have a transverse annular shape.

[0130] Fig.27A and Fig.27B A method for forming a stepped wordline structure is shown. The stepped wordline structure may be stepped on two opposite ends of the wordline.

[0131] refer to Fig.27A , the stepped structure ST may be formed by selectively etching the first material layer 131 and the second material layer 132 of the upper structure 130. The process for forming the stepped structure ST may be referred to as a slimming process. FIG. 13A to FIG. 13CThe isolation openings 161 shown are formed simultaneously.

[0132] refer to FIG. 16A to FIG. 16D , the second material layer 132 may be selectively removed to form a gate recess 171 between the first material layers 131 .

[0133] Then, if Fig.27B As shown, the gate recess 171 may be filled with a word line 173 .

[0134] As described above, when the stepped structure ST is formed in the upper structure 130 , at least one end of the word line 173 may be formed in the stepped structure ST.

[0135] Figures 28 to 30 A method for manufacturing a memory device according to another embodiment of the present invention is shown. The method of forming other constituent elements other than the capacitor will be referred to in detail. FIG. 3A to FIG. 22B The method shown.

[0136] First, refer to Fig.23A and Fig. 23B , a capacitor opening 190 may be formed.

[0137] Then, if Fig.28 As shown, the side surface of the active layer 151 exposed by the capacitor opening 190 may be selectively removed to form a storage node recess 191 ′. The storage node recess 191 ′ may be located between the first material layers 131 .

[0138] Subsequently, a capacitor contact node 192C may be formed in the active layer 151 remaining due to the storage node recess 191 ′.

[0139] For example, refer to FIG. 24A to FIG. 25B, a second contact pad layer 191 may be formed to cover the capacitor opening 190. The second contact pad layer 191 may contain impurities. The second contact pad layer 191 may include N-type polysilicon. Subsequently, the N-type impurities may be diffused from the second contact pad layer 191 by performing a heat treatment. As a result, a portion of the active layer 151 in contact with the second contact pad layer 191 may be doped with N-type impurities. The portion of the active layer 151 doped with N-type impurities may be a capacitor contact node 192C. From a top view perspective, the capacitor contact node 192C may extend laterally to be located between the first material layers 131 while covering the sidewalls of the capacitor opening 190. In this way, the capacitor contact node 192C may be a portion in which a portion of the active layer 151 is doped with N-type impurities. The capacitor contact node 192C may partially fill the storage node 191', respectively. According to another embodiment of the present invention, a metal silicide may be further formed on the capacitor contact node 192C. In order to form the metal silicide, a deposition process of titanium / titanium nitride and an annealing process may be performed, and unreacted titanium / titanium nitride may be removed.

[0140] refer to Fig.29 , a storage node 192' may be formed in the storage node recess 191'. After depositing a conductive material to fill the storage node recess 191', the conductive material may be selectively etched. For example, by etching back the conductive material, the storage node 192' may be formed to be isolated from each other while filling the storage node recess 191'. The storage node 192' may include a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The storage node 192' may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir) and ruthenium oxide (RuO2), iridium oxide (IrO2), or a combination thereof. The storage node 192' may have a lateral annular shape.

[0141] refer to Fig.30 , a dielectric layer 193 and a plate node 194 may be formed on the storage node 192' to fill the capacitor opening 190. Fig.26A and Fig.26BDepicting dielectric layer 193 and plate node 194. Dielectric layer 193 may conformally cover capacitor opening 190, and plate node 194 may completely fill capacitor opening 190 above dielectric layer 193. Dielectric layer 193 and plate node 194 may be formed by stacking a dielectric material and a plate node layer over capacitor opening 190, and then planarizing the dielectric material and plate node layer so that the dielectric material and plate node layer may remain in capacitor opening 190. Storage node 192' may surround dielectric layer 193 plate node 194. Capacitor contact node 192C may surround storage node 192'.

[0142] Fig.31 is a cross-sectional view showing a memory device according to another embodiment of the present invention. Fig.31 The memory device 200 may be similar to Figure 1A Memory device 100M.

[0143] refer to Fig.31 , the memory device 200 may include: a substrate SS; an active layer ACT, which is spaced apart from the substrate SS and laterally oriented in a first direction D1; a word line WL, which is laterally oriented along one side of the active layer ACT and parallel to the active layer ACT; an active body ACB, which is vertically oriented in a second direction D2 by penetrating the active layer ACT; a bit line BL, which is vertically oriented in the second direction D2 by penetrating the active layer ACT and spaced apart from one side of the active body ACB; and a capacitor CAP, which is vertically oriented in the second direction D2 by penetrating the active layer ACT and spaced apart from the other side of the active body ACB.

[0144] exist Fig.31 In the memory device 200, the memory cell array MCA may be located below the substrate SS. The substrate SS may include a substrate structure including a peripheral circuit, and the peripheral circuit may include at least one control circuit for controlling the memory cell array MCA. The bit line BL, the active body ACB, and the capacitor CAP may extend vertically downward from the substrate SS. The active layer ACT and the word line WL may be located at the same distance and may be parallel to the plane of the substrate SS.

[0145] Fig.32 A memory device according to another embodiment of the present invention is shown. Fig.32 The storage device can be similar to Figure 1A The storage device has 100M.

[0146] refer to Fig.32 , adjacent memory cells MCU and MCL may be symmetrical to each other in the third direction D3 with respect to the word line WL therebetween.

[0147] Fig.33 A memory device according to another embodiment of the present invention is shown. Fig.33 The memory device 400 may be similar to Figure 1A Memory device 100M.

[0148] refer to Fig.33 , adjacent memory cells MC1, MC2, and MC3 may share one word line WL. The word line WL may extend along a first direction D1.

[0149] According to an embodiment of the present invention, by stacking memory cells in a three-dimensional structure in a vertical direction, the cell density can be increased and the parasitic capacitance can be reduced.

[0150] According to the embodiments of the present invention, it is also possible to realize a highly integrated memory device in a limited area by stacking memory cells in a vertical direction relative to a peripheral circuit portion.

[0151] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A storage device, comprising: substrate; an active layer spaced apart from and laterally oriented from the substrate; a word line oriented laterally parallel to the active layer along a side of the active layer; an active body vertically oriented by penetrating the active layer; a bit line vertically oriented to be spaced apart from one side of the active body by penetrating the active layer; and A capacitor is vertically oriented through the active layer to be spaced apart from another side of the active body.

2. The memory device according to claim 1, wherein: The active layer and the word lines are located at the same distance from the substrate.

3. The memory device according to claim 1, wherein: The active layer comprises: a first source / drain region coupled to the bit line; a second source / drain region coupled to the capacitor; and A channel body is coupled to the active body and is laterally oriented between the first source / drain region and the second source / drain region.

4. The memory device according to claim 3, wherein: The channel body has a shape surrounding the active body.

5. The memory device according to claim 1, wherein: The capacitor comprises: a storage node oriented laterally parallel to the substrate; a dielectric layer overlying the storage node; and a plate node on the dielectric layer; Wherein, the dielectric layer and the plate node are vertically oriented by penetrating the storage node.

6. The memory device according to claim 5, wherein: The storage nodes are located at the same distance from the active layer.

7. The memory device according to claim 1, further comprising: A bit line contact node is formed in the active layer and surrounds the bit line.

8. The memory device according to claim 1, wherein: At least one end of the word line has a stepped portion.

9. A storage device comprising: Storage units, which are arranged in a vertical direction, Wherein, each of the storage units comprises: an active layer comprising a first source / drain region, a second source / drain region, and a channel body, the channel body being laterally oriented between the first source / drain region and the second source / drain region; a word line oriented laterally parallel to a side of the active layer; an active body extending through the channel body; a bit line coupled to the first source / drain region by being vertically oriented through the active layer; and A capacitor is vertically oriented to be coupled to the second source / drain region by penetrating the active layer.

10. The memory device according to claim 9, wherein: The word line is parallel to the first source / drain region, the second source / drain region, and the channel body.

11. The memory device according to claim 9, further comprising: A gate dielectric layer is formed between one side of the channel body and the word line.

12. The memory device according to claim 9, further comprising: an isolation dielectric layer between the first source / drain region and the second source / drain region and the word line, The isolation dielectric layer is vertically oriented in a stacking direction of the memory cell.

13. The memory device according to claim 9, further comprising: a bit line contact node formed in the active layer and coupled to the first source / drain region and the bit line, The bit line contact node surrounds the bit line.

14. The memory device according to claim 9, wherein: At least one end of the word line has a stepped portion.

15. The memory device according to claim 9, wherein: The capacitor comprises: a storage node formed in the active layer and coupled to the second source / drain region; a dielectric layer overlying the storage node; and A plate node is above the dielectric layer.

16. The memory device according to claim 15, wherein: The storage nodes are located at the same distance from the active layer.

17. The memory device according to claim 15, wherein: The dielectric layer and the plate node are vertically oriented to penetrate the active layer.

18. The memory device according to claim 9, further comprising: A dielectric material is located between the memory cells.

19. The memory device according to claim 9, further comprising: The peripheral circuit is located below the memory cell.

20. The memory device according to claim 9, further comprising: The peripheral circuit is located above the memory cell.

21. A method for manufacturing a memory device, comprising: forming a plurality of active layers arranged in a vertical direction relative to the substrate; forming a vertically oriented active body that penetrates the active layers to interconnect the active layers to each other; forming a vertically oriented bit line spaced apart from one side of the active body and extending through the active layer; forming a vertically oriented capacitor spaced apart from another side of the active body and extending through the active layer; as well as A plurality of word lines are formed and oriented laterally adjacent to one side of each of the active layers.

22. The method according to claim 21, wherein: The step of forming a plurality of active layers arranged in a vertical direction relative to the substrate comprises: forming an alternating stack in which dielectric materials and sacrificial materials are alternately stacked; forming vertically oriented cell openings extending through the alternating stack of layers; forming a recess extending laterally from the cell opening by selectively recessing the sacrificial material through the cell opening; and The active layers are formed so as to fill the recesses respectively.

23. The method according to claim 21, wherein: Each of the active layers includes a plurality of fingers.

24. The method according to claim 21, wherein: The step of forming a vertically oriented active body that penetrates the active layers and interconnects the active layers to each other comprises: forming an alternating stack in which dielectric materials and sacrificial materials are alternately stacked; replacing a portion of the sacrificial material with the active body; and A vertically oriented active body is formed through a channel body of the active layer.

25. The method according to claim 24, wherein: The step of forming a vertically oriented active body that penetrates the active layers and interconnects the active layers to each other comprises: forming an alternating stack in which dielectric materials and sacrificial materials are alternately stacked; forming a first unit opening vertically oriented through the alternating stack of layers; forming a recess extending laterally from the first cell opening by selectively recessing the sacrificial material through the first cell opening; filling the first cell opening from which the sacrificial material has been removed with a silicon material; forming the active body doped with impurities when filling the first cell opening above the silicon material; and The impurities are diffused from the active body to form the channel body.

26. The method according to claim 21, wherein: The step of forming a vertically oriented bit line spaced apart from one side of the active body and penetrating the active layer comprises: forming an alternating stack of layers over the substrate, wherein dielectric materials and sacrificial materials are alternately stacked; replacing a portion of the sacrificial material with a bit line contact node; and A conductive material is formed through the bit line contact node to form the vertically oriented bit line.

27. The method according to claim 26, wherein: The step of forming a vertically oriented bit line spaced apart from one side of the active body and penetrating the active layer comprises: forming an alternating stack of layers over the substrate, wherein dielectric materials and sacrificial materials are alternately stacked; forming a second unit opening vertically oriented through the alternating stack of layers; forming a recess extending laterally from the cell opening by selectively recessing the sacrificial material through the second cell opening; filling the second cell opening from which the sacrificial material has been removed with the bit line contact node; and A vertically oriented bit line is formed filling the second cell opening over the bit line contact node.

28. The method of claim 21, wherein: The step of forming a vertically oriented capacitor spaced apart from another side of the active body and extending through the active layer comprises: forming an alternating stack of layers over the substrate, wherein dielectric materials and sacrificial materials are alternately stacked; replacing a portion of the sacrificial material with a storage node; and A dielectric layer and a plate node are formed, both oriented vertically to penetrate the storage node.

29. The method according to claim 28, wherein: The step of forming a vertically oriented capacitor spaced apart from another side of the active body and extending through the active layer comprises: forming an alternating stack of layers over the substrate, wherein dielectric materials and sacrificial materials are alternately stacked; forming a third unit opening vertically oriented through the alternating stack of layers; forming a recess extending laterally from the third cell opening by selectively recessing the sacrificial material through the third cell opening; filling the third cell opening from which the sacrificial material has been removed with a capacitor contact node; and forming a storage node over and surrounded by the capacitor contact node; and The dielectric layer and the plate node are formed, filling the third cell opening above the storage node.

30. The method of claim 21, wherein: In the step of forming a plurality of active layers arranged in a vertical direction relative to the substrate, Each of the active layers includes a first unit opening, a second unit opening, and a third unit opening, and The first cell opening, the second cell opening, and the third cell opening are vertically oriented relative to each other.

31. The method according to claim 30, wherein: filling the first cell opening with the vertically oriented active body, and filling the second cell opening with the vertically-oriented bit line, The third cell opening is filled with the vertically-oriented capacitor.

32. The method of claim 21, further comprising: forming a first source / drain region in each of the active layers; forming a second source / drain region in each of the active layers, the second source / drain region being laterally spaced apart from the first source / drain region; as well as A channel body is formed that is laterally oriented between the first source / drain region and the second source / drain region.

33. The method of claim 32, wherein: The steps of forming the first source / drain region and forming the second source / drain region include: forming an opening that exposes one side of each of the active layers; and Impurities are doped on one side of each of the active layers through the openings.

34. The method of claim 32, wherein: The step of forming a channel body laterally oriented between the first source / drain region and the second source / drain region comprises: forming an opening vertically oriented through each of said active layers; forming an active body doped with impurities that fills the opening; and The impurities are diffused from the impurity-doped active body to form the channel body.

35. The method of claim 21, wherein: The step of forming a plurality of word lines oriented laterally adjacent to one side of each of the active layers comprises: forming an opening vertically oriented parallel to a side of the active layer; forming a gate recess extending laterally from the opening; and The gate recess is filled with a conductive material to form the word line.

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