Display Devices

Abstract

A display device includes: a substrate divided into a central area and a peripheral area arranged adjacent to the central area, the central area including a display area; a first insulating layer corresponding to the peripheral area of ​​the substrate; at least one cutout corresponding to an area of ​​the first insulating layer; and a covering layer covering the at least one cutout and located on the first insulating layer.

Description

Technical Field

[0001] One or more embodiments relate to a display device. Background Art

[0002] In recent years, display devices have been used for various purposes. As display devices become thinner and lighter, their use range becomes wider.

[0003] Particularly, in recent years, flat panel display devices have been further studied and manufactured.

[0004] A display device, more specifically, a flat panel display device, has a variety of different films. When an external force is applied to the flat panel display device or due to process conditions during the manufacture of the flat panel display device, the different films may be damaged or a path for crack propagation may be generated.

[0005] When the display device is formed from one mother substrate, the manufacturing may include a process of cutting the mother substrate to separate the display devices.

[0006] During the cutting process, cracks may occur on the film of the display device, and the film may create a path for the cracks to propagate.

[0007] Therefore, the durability of the display device is affected. Summary of the invention

[0008] One or more embodiments include a display device and a method of manufacturing the display device.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0010] According to one or more embodiments, a display device includes: a substrate divided into a central area and a peripheral area arranged adjacent to the central area, the central area including a display area; a first insulating layer corresponding to the peripheral area of ​​the substrate; at least one cutout corresponding to an area of ​​the first insulating layer; and a covering layer located on the first insulating layer and covering the at least one cutout.

[0011] The display device may further include one or more insulating layers in the display area, and the cover layer may include the same material as that of the one or more insulating layers.

[0012] The depth of the at least one cutout may be less than or equal to the thickness of the first insulating layer.

[0013] The capping layer may extend in one direction and may be parallel to the edge of the substrate.

[0014] The width of the coating may be greater than the width of the at least one cutout.

[0015] The length of the coating may be longer than the length of the at least one cutout.

[0016] The first insulating layer may extend to the display area.

[0017] The first insulating layer may extend to an edge of the substrate.

[0018] The display device may further include a barrier layer between the substrate and the first insulating layer.

[0019] The barrier layer may extend to the display area.

[0020] The display device may further include a second insulating layer on the first insulating layer, and the at least one cutout may extend through the second insulating layer.

[0021] The second insulating layer may extend to the display area.

[0022] The at least one cutout may be spaced apart from at least one edge of the substrate.

[0023] At least one cutout may overlap at least one edge of the substrate.

[0024] The cover layer may be spaced apart from at least one edge of the substrate.

[0025] The capping layer may overlap at least one of the edges of the substrate.

[0026] The plurality of cutouts may be spaced apart from one another in one direction.

[0027] A plurality of cutouts may be provided in a direction intersecting the one direction.

[0028] Among the plurality of cutouts, a width of a cutout closest to an edge of the substrate may be greater than a width of each of the cutouts except for the cutout closest to the edge of the substrate.

[0029] Among the plurality of cutouts, a width of a cutout farthest from the edge of the substrate may be greater than a width of each of the cutouts except for the cutout farthest from the edge of the substrate.

[0030] Among the plurality of cutouts, a middle cutout between a cutout farthest from an edge of the substrate and a cutout closest to the edge of the substrate may have a width greater than a width of each of the cutouts except the middle cutout.

[0031] At least one edge among the edges of the substrate may be defined as a cutting line.

[0032] The substrate may include a flexible material.

[0033] The substrate may include an organic material.

[0034] The substrate may include multiple layers.

[0035] The substrate may further include a first layer, a second layer, and an intervening layer between the first layer and the second layer, wherein the first layer includes an organic material and the second layer includes an organic material.

[0036] The display device may further include particles remaining in the at least one cutout, and the covering layer may be formed to cover the particles.

[0037] The display device may further include at least one encapsulation layer in the display area.

[0038] At least one encapsulation layer may extend to the peripheral region.

[0039] At least one encapsulation layer may be separated from the cover layer.

[0040] The at least one encapsulation layer may include one or more inorganic encapsulation layers or one or more organic encapsulation layers.

[0041] The display device may further include a plurality of thin film transistors (TFTs) in a central area of ​​the substrate, each of the plurality of TFTs including an active layer, a gate electrode, a source electrode, and a drain electrode, wherein one or more insulating layers may be adjacent to at least one of the active layer, the gate electrode, the source electrode, and the drain electrode, and the capping layer and the one or more insulating layers may include the same material.

[0042] The first insulating layer may extend to the central region and may be disposed between the substrate and the plurality of TFTs.

[0043] The display device may further include a passivation layer on the source electrode and the drain electrode, and the overcoat layer and the passivation layer may be formed of the same material.

[0044] The display device may further include a second insulating layer between the gate electrode and the active layer, and the second insulating layer may be located on the first insulating layer and may extend to the peripheral region to correspond to the at least one cutout.

[0045] The display device may further include an interlayer insulating layer between the gate electrode and the source and drain electrodes, and the interlayer insulating layer may be on the first insulating layer and may extend to the peripheral region to correspond to the at least one cutout.

[0046] The display device may further include a first electrode electrically connected to at least one of the plurality of TFTs, and a pixel defining layer covering a portion of the first electrode and defining the pixel area.

[0047] The display device may further include a second electrode facing the first electrode; and an intermediate layer between the first electrode and the second electrode and including the organic emission layer.

[0048] The capping layer and the pixel defining layer may include the same material.

[0049] A cover may surround the display area.

[0050] The cover layer may correspond to an edge of the display area except for one of the edges.

[0051] The cladding may include one or more main portions corresponding to the edges of the substrate, and may include a corner portion connecting two adjacent main portions.

[0052] The display device may further include a pad area in the peripheral area of ​​the substrate, wherein the cover layer is adjacent to the pad area and includes a bent portion corresponding to the pad area, and the bent portion is bent toward or away from the display area.

[0053] According to one or more embodiments, a method for manufacturing a display device is provided, the display device including a substrate divided into a central area and a peripheral area adjacent to the central area, the central area including a display area, the method including: forming a first insulating layer corresponding to the peripheral area of ​​the substrate; forming at least one incision by partially removing a vertical portion of the first insulating layer, wherein at least one incision corresponds to an area of ​​the first insulating layer; and forming a covering layer on the first insulating layer, wherein the covering layer covers at least one incision.

[0054] The method may further include forming one or more insulating layers in the display area, and the overcoat layer may include the same material as the one or more insulating layers formed in the display area.

[0055] The method may further include forming a plurality of thin film transistors (TFTs) in a central region of the substrate, wherein each of the plurality of TFTs includes an active layer, a gate electrode, a source electrode, and a drain electrode.

[0056] The method may further include forming a passivation layer on the source electrode and the drain electrode, wherein the step of forming the passivation layer may include forming a through hole in the passivation layer to expose a region of at least one of the source electrode and the drain electrode, and the capping layer may include the same material as the passivation layer, and the capping layer may be simultaneously patterned by forming the through hole.

[0057] According to one or more embodiments, a method for manufacturing a display device by using a mother substrate is provided, the display device including a central area and a peripheral area adjacent to the central area, the method including: cutting the mother substrate along a cutting line to form a first insulating layer corresponding to the peripheral area; forming at least one incision by partially removing a vertical portion of the first insulating layer, wherein the incision corresponds to an area of ​​the first insulating layer; forming a covering layer on the first insulating layer, wherein the covering layer covers at least one incision; and performing a cutting process along the cutting line, thereby separating one or more display devices formed on the mother substrate.

[0058] During the cutting process, the cutting line may be separated from the coating.

[0059] During the cutting process, the cutting line may overlap the coating. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] These and / or other aspects will become apparent and more easily understood through the following description of some embodiments in conjunction with the accompanying drawings, in which:

[0061] Figure 1 shows a plan view of a display device according to an embodiment;

[0062] Figure 2 Shows Figure 1 An enlarged view of part D;

[0063] Figure 3 Shown along Figure 2 A cross-sectional view of portion D taken along line III-III;

[0064] Figures 4 to 12 Shows Figures 1 to 3 Variations of cutouts and coatings;

[0065] Fig.13 An example in which particles remain in a cutout of a display device according to an embodiment is shown;

[0066] Fig.14 shows a plan view of a display device according to another embodiment;

[0067] Fig.15 Shows Fig.14 An enlarged view of part D;

[0068] Fig.16 Shown along Fig.15 A cross-sectional view of portion D taken along line XVI-XVI of FIG.

[0069] Fig.17 Shows Fig.15 and Fig.16 Variations of the cutouts and coatings shown in ;

[0070] Fig.18 shows a plan view of a display device according to another embodiment;

[0071] Fig.19 Shows Fig.18 An enlarged view of part D;

[0072] Fig. 20 Shown along Fig.19 A cross-sectional view of portion D taken along line IXX-IXX of FIG.

[0073] Fig.21 Shows Figures 18 to 20 Variations of the cutouts and coatings shown in ;

[0074] Fig. 22 shows a plan view of a display device according to another embodiment;

[0075] Fig.23 Shown along Fig. 22 A cross-sectional view taken along line XXII-XXII;

[0076] Fig.24 Shows Fig. 22 and Fig.23 A variation of the display device;

[0077] Fig.25 shows a plan view of a display device according to another embodiment;

[0078] Fig.26 Shown along Fig.25 A cross-sectional view of the display device taken along lines XXVA-XXVA and XXVB-XXVB;

[0079] Fig. 27 Shows Fig.25 and Fig.26 A variation of the display device shown in ;

[0080] Fig.28 shows a plan view of a display device according to another embodiment;

[0081] Fig.29 Shown along Fig.28 A cross-sectional view taken along the XXXA-XXXA and XXXB-XXXB lines;

[0082] Figure 30 to Figure 33 shows a plan view of a display device according to another embodiment;

[0083] Fig.34 A plan view showing a mother substrate for manufacturing a display device according to an embodiment;

[0084] Fig.35 Shows Fig.34 An enlarged plan view of section M;

[0085] Fig.36 Shown along Fig.35 A cross-sectional view of the M portion taken along the XXX-XXX line; and

[0086] Fig.37 Shows Fig.36 A modification of the structure shown in . DETAILED DESCRIPTION

[0087] Because the inventive concept allows for various changes and multiple embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. The effects and features of the inventive concept and the methods for implementing the inventive concept can be more easily understood by referring to the following detailed description of the embodiments and the drawings. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0088] In one or more embodiments, terms such as “first”, “second”, etc. may be used, but these components should not be limited to the above terms, and the above terms are only used to distinguish one component from another.

[0089] In one or more embodiments, unless there is a specific description to the contrary, a singular form may include a plural form.

[0090] In one or more embodiments, terms such as “include” or “comprising” are used to specify the presence of a specified feature or component and do not exclude the presence of one or more other specified features or one or more other components.

[0091] In one or more embodiments, it will also be understood that when an element such as a layer, region, area, or component is referred to as being “on” another element, it can be directly on the other element or intervening elements such as layers, regions, areas, or components may be interposed between the two.

[0092] In the drawings, for ease of description, the sizes of layers and regions may be exaggerated for clarity. For example, for ease of description, the size and thickness of each element may be arbitrary, and therefore, one or more embodiments are not limited thereto.

[0093] In one or more embodiments, the X-axis, Y-axis, and Z-axis may not be limited to the three axes on the rectangular coordinate system, but may be interpreted as a broad meaning including the three axes. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may indicate different directions that are not perpendicular to each other.

[0094] In one or more embodiments, the order of the processes may be different from that described. For example, two processes described sequentially may be performed substantially simultaneously, or may be performed in the reverse order of the described order.

[0095] Hereinafter, one or more embodiments will be described in more detail with reference to the accompanying drawings. Those components that are the same or correspond to each other are generally marked with the same reference numerals regardless of the figure numbers, and redundant explanations are omitted.

[0096] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Phrases such as "at least one of...", when preceding a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0097] Figure 1 A plan view of a display device 1000 according to an embodiment is shown. Figure 2 Shows Figure 1 An enlarged view of part D of Figure 3 Shown along Figure 2 A cross-sectional view of portion D taken along line III-III.

[0098] Reference Figures 1 to 3 , the display device 1000 includes a substrate 101. The substrate 101 may include various materials. In some embodiments, the substrate 101 may include a glass material, a metal material, or other organic materials.

[0099] In some embodiments, substrate 101 may include a flexible material. For example, substrate 101 may be substantially bent, curved, folded, or rolled.

[0100] In some embodiments, the substrate 101 may include ultra-thin glass, metal, or plastic. For example, when plastic is used, the substrate 101 may include polyimide (PI), but the embodiment is not limited thereto, and thus various materials may be used.

[0101] A plurality of display devices 1000 may be formed on the mother substrate, and the plurality of display devices 1000 may be separated into individual display devices 1000 in a manner of cutting the mother substrate along a cutting line CL of the substrate 101 . Figure 1 One display device 1000 is shown cut along a cutting line CL and thus separated. Thus, the edge of the substrate 101 is defined by the cutting line CL.

[0102] All edges of the substrate 101, such as Figure 1 The four edges of the substrate 101 shown in FIG. 1 may all be cutting lines CL. In an embodiment, one, two or three of the four edges of the substrate 101 may be cutting lines CL.

[0103] According to the size or shape of the mother substrate, the position or number of edges determined as the cutting line CL among all the edges of the display device 1000 may vary.

[0104] The substrate 101 is divided into a peripheral area PA and a central area CA. The peripheral area PA includes an area around the cutting line CL, that is, an area adjacent to the cutting line CL, and the central area CA indicates an area arranged inside compared to the peripheral area PA.

[0105] Embodiments are not limited thereto. The cutting line CL may not exist. One display device 1000 may be formed on a mother substrate, and in this case, the substrate 101 may correspond to the mother substrate, so that the cutting line CL may not exist. In this case, the peripheral area PA may indicate an area adjacent to an edge of the substrate 101, and the central area CA may indicate an area arranged inside compared to the peripheral area PA. For ease of description, it is assumed that the cutting line CL exists in the following embodiments.

[0106] The central area CA may include at least one display area DA.

[0107] The display area DA may include at least one display device (not shown), such as an organic light emitting device (OLED) for displaying an image. In addition, a plurality of pixels (not shown) may be provided in the display area DA, and at least one display device (not shown) may be provided in each of the plurality of pixels.

[0108] A non-display area (not shown) may be formed around the display area DA. The non-display area may be formed to surround the display area DA. In some embodiments, the non-display area may be formed to be adjacent to multiple sides of the display area DA. In some embodiments, the non-display area may be formed to be adjacent to one side of the display area DA.

[0109] In some embodiments, only the display area DA may be disposed in the central area CA, and the non-display area may be formed only in the peripheral area PA.

[0110] A pad area (not shown) may be formed in the non-display area, and a driver or a plurality of pad units (not shown) may be disposed in the pad area.

[0111] In some embodiments, at least one insulating layer (not shown) may be formed in the display area DA of the central area CA. The insulating layer may include an organic material or an inorganic material.

[0112] The peripheral area PA indicates an area adjacent to the cutting line CL, and the peripheral area PA is arranged in an edge of the substrate 101 along the cutting line CL.

[0113] In the peripheral area PA, a first insulating layer 111 is formed on the substrate 101. A slit SL is formed on the first insulating layer 111. The slit SL is formed in the peripheral area PA so as to be spaced apart from the display area DA.

[0114] The first insulating layer 111 may include various insulating materials. In some embodiments, the first insulating layer 111 may include an inorganic material. For example, the first insulating layer 111 may include an oxide, a nitride, or a nitride oxide. The first insulating layer 111 may include, for example, silicon nitride (SiNx), silicon oxide (SiO 2 ), or silicon oxynitride (SiOx N y ).

[0115] In some embodiments, the first insulating layer 111 may be formed while extending to the central area CA or the display area DA. In some embodiments, the first insulating layer 111 may be formed jointly on the central area CA and the peripheral area PA of the substrate 101. The first insulating layer 111 may be formed on the entire top surface of the substrate 101.

[0116] The first insulating layer 111 may reduce or prevent moisture or impurities from penetrating into the display device 1000 via the substrate 101 , and may provide a flat surface on a top surface of the substrate 101 .

[0117] In some embodiments, the first insulating layer 111 may extend to the cutting line CL of the substrate 101 .

[0118] The embodiment is not limited thereto, and the first insulating layer 111 may not cover the top surface of the substrate 101 in the region of the peripheral area PA.

[0119] The slit SL is formed from the first insulating layer 111 by removing a vertical portion of the first insulating layer 111. However, the method of forming the slit SL is not limited to the etching method.

[0120] The slit SL may be formed by not completely removing but partially removing a vertical portion of the first insulating layer 111 so that a region of the substrate 101 may not be exposed. The depth of the slit SL may be less than the thickness of the first insulating layer 111.

[0121] The slit SL may have various shapes including, for example, a shape extending in one direction.

[0122] In some embodiments, Figure 2 As shown, the slit SL may be formed in such a manner that the slit SL may have a side parallel to the edge of the substrate 101 or the cutting line CL.

[0123] Here, the length of the cutout SL may vary and thus may be smaller or larger than the length of the display area DA.

[0124] In some embodiments, the cutout SL may be spaced apart from the central area CA, and for example, the cutout SL may be spaced apart from the display area DA.

[0125] A capping layer CLL is formed on the first insulating layer 111 to cover the slit SL.

[0126] In some embodiments, the width of the cover layer CLL may be greater than the width of the slit SL, and the length of the cover layer CLL may be greater than the length of the slit SL. In this way, the cover layer CLL may completely cover the slit SL to prevent the slit SL from being exposed.

[0127] The cladding layer CLL may include various materials. The cladding layer CLL may include inorganic or organic materials.

[0128] In some embodiments, the cover layer CLL may include an organic material. In this way, an appropriate thickness and an appropriate width of the cover layer CLL may be ensured, and as a result, the cover layer CLL may cover the slit SL.

[0129] In some embodiments, the overcoat layer CLL may include the same material as an insulating layer (not shown) that may be formed in the display area DA of the substrate 101. In addition, the overcoat layer CLL and the insulating layer (not shown) that may be formed in the display area DA of the substrate 101 may be formed simultaneously.

[0130] The capping layer CLL may be formed in the peripheral area PA.

[0131] In some embodiments, the capping layer CLL may be disposed between an edge of the substrate 101 and a boundary of the central area CA.

[0132] In some embodiments, the capping layer CLL may be disposed between the cutting line CL and a boundary of the central area CA.

[0133] The cladding CLL may extend longitudinally. Figure 2 As shown in FIG. 1 , the overcoat layer CLL may have a shape extending longitudinally in parallel with the cutting line CL of the substrate 101. The length of the overcoat layer CLL may vary and thus may be greater than or less than the length of the display area DA.

[0134] The cutouts SL in the first insulating layer 111 arranged in the peripheral area PA of the display device 1000 prevent cracks from extending from the edge of the substrate 101. For example, the cutouts SL adjacent to the cutting lines CL of the substrate 101 mainly prevent the extension of cracks that may occur on the substrate 101 when each display device 1000 is cut and then separated from the mother substrate.

[0135] Specifically, the first insulating layer 111 may be formed in the peripheral area PA of the substrate 101, and may selectively extend to the cutting line CL, thereby protecting the top surface of the substrate 101. In addition, the cutout SL may prevent or reduce cracks that may occur on the first insulating layer 111 due to pressure applied to the first insulating layer 111 or the expansion of the cracks.

[0136] The cover layer CLL is formed on the slit SL. Due to the cover layer CLL, movement of foreign substances or particles that may be generated in the slit SL may be prevented. In some embodiments, the cover layer CLL may cover the slit SL, and thus may not expose foreign substances or particles in the slit SL.

[0137] When manufacturing the display device 1000, foreign substances or particles may be generated in the cutout SL. For example, a conductive material used to form an electrode (not shown) in the manufacturing process of the display device 1000 may remain in the cutout SL. The conductive material remaining in the cutout SL may cause defects of the display device 1000 in subsequent processes, for example, the residual conductive material may move to the display area DA and may cause electrical defects in the display area DA, which leads to deterioration of electrical characteristics and image quality.

[0138] However, the capping layer CLL is formed on the cutout SL, and thus movement of remaining foreign substances and particles may be prevented, so that defects that may occur in the display area DA may be reduced and prevented.

[0139] In addition, due to the first insulating layer 111 , the cap layer CLL can be prevented from being delaminated from the substrate 101 .

[0140] Figures 4 to 12 Shows Figures 1 to 3 For convenience of description, the modification will be described considering only the features different from those of the above-described embodiment.

[0141] Reference Figure 4 , a first insulating layer 111 is formed on the substrate 101, and a slit SL is formed by partially removing the first insulating layer 111. The depth of the slit SL corresponds to the thickness of the first insulating layer 111.

[0142] Some embodiments may have the following structure, where Figure 4 As shown, the cutout SL has a depth corresponding to the thickness of the first insulating layer 111 .

[0143] Reference Figure 5 , a barrier layer 102 is disposed between the substrate 101 and the first insulating layer 111. A slit SL is formed in the first insulating layer 111.

[0144] The slit SL is not formed in the barrier layer 102, and is formed only in the first insulating layer 111. The barrier layer 102 may reduce or prevent moisture or foreign substances from penetrating into the display device 1000 via the substrate 101. Since the slit SL is not formed in the barrier layer 102, the barrier layer 102 may reduce or prevent moisture or foreign substances from penetrating toward the slit SL.

[0145] In some embodiments, the cutout SL may have a size greater than Figure 5 The depth of the quartz crystal is less than the depth shown in FIG. 1 and thus may even be formed in the barrier layer 102 .

[0146] The barrier layer 102 may include, for example, silicon nitride (SiNx), silicon oxide (SiO 2 ), or silicon oxynitride (SiO x N y ).

[0147] Reference Figure 6 , a second insulating layer 121 is formed on the first insulating layer 111. The second insulating layer 121 may include various insulating materials. In some embodiments, the second insulating layer 121 may include the same material as the first insulating layer 111.

[0148] In some embodiments, the second insulating layer 121 may include an inorganic material.

[0149] For example, the second insulating layer 121 may include oxide, nitride, or oxynitride. The second insulating layer 121 may include, for example, silicon nitride (SiN x ), silicon oxide (SiO 2 ), or silicon oxynitride (SiO x N y ).

[0150] In some embodiments, the second insulating layer 121 may extend to the central area CA and may be formed in the display area DA. In some embodiments, the second insulating layer 121 may be completely formed in the central area CA and the peripheral area PA of the substrate 101 .

[0151] In some embodiments, the second insulating layer 121 may extend to the cutting line CL of the substrate 101 .

[0152] The embodiment is not limited thereto, and the second insulating layer 121 may not cover the top surface of the substrate 101 in the region of the peripheral area PA.

[0153] The slit SL is formed in the second insulating layer 121. The slit SL is formed in the second insulating layer 121 and the first insulating layer 111. The slit SL may extend through the second insulating layer 121. In this way, the slit SL may have a thickness equal to or greater than a predetermined value, so that when the capping layer CLL is formed in the slit SL, the capping layer CLL is deeply buried in the slit SL, and thus the capping layer CLL is firmly disposed in the slit SL. In this way, delamination of the capping layer CLL and the slit SL can be reduced or prevented.

[0154] Although not shown, at least one insulating layer (not shown) may be additionally formed on the second insulating layer 121 , and the slit SL may extend through the at least one insulating layer.

[0155] In addition, a barrier layer 102 may be formed between the substrate 101 and the first insulating layer 111. In some embodiments, Figure 6 The barrier layer 102 may be omitted.

[0156] Reference Figure 7 , the substrate 101 is not a single layer, but a multilayer including a first layer 101a, a second layer 101b, and an insertion layer 101c. The first layer 101a and the second layer 101b may include an organic material, and the insertion layer 101c may include an inorganic material. In some embodiments, the first layer 101a and the second layer 101b may include a plastic material, such as polyimide, and the insertion layer 101c may include, for example, silicon oxide.

[0157] The embodiment is not limited thereto, and the first layer 101a and the second layer 101b may include various types of the same or different organic materials. The insertion layer 101c may include various materials capable of functioning as a barrier, and may not have a single layer structure but may have a multi-layer structure.

[0158] Although not shown, Figure 7 The multilayer structure of the substrate 101 shown in FIG. 1 may be applied to the above embodiments, their modifications, and one or more embodiments described below.

[0159] Reference Figure 8 , a plurality of cutouts SL are formed in the first insulating layer 111. Figure 8 Two slits SL are shown, but the embodiment is not limited thereto. In other embodiments, more slits SL may be formed, for example, three or more than three slits SL.

[0160] In some embodiments, the plurality of slits SL may be spaced apart from each other. The plurality of slits SL may be arranged in one direction, for example, in the width direction of the plurality of slits SL (see Figure 8 in the X-axis direction).

[0161] Fig. 9 Shown along Figure 8 The cross-sectional view taken along the IX-IX line. Fig. 9 As shown in FIG. 1 , the cover layer CLL may cover all of the plurality of slits SL. Although not shown, in some embodiments, the cover layer CLL may be formed as a plurality of cover layers CLL spaced apart from each other to correspond to the plurality of slits SL, respectively.

[0162] In some embodiments, the plurality of slits SL may be formed in parallel with each other and may have a fixed width. Although not shown, the widths of the plurality of slits SL may be different from each other. Fig. 9 The structure of the plurality of cutouts SL shown in FIG. 4 may be applied to the above embodiment and one or more embodiments described below.

[0163] The plurality of slits SL and the spaces formed between the plurality of slits SL can effectively prevent cracks from extending to the substrate 101 via the cutting line CL of the substrate 101. Due to the slit SL closest to the cutting line CL or the edge of the substrate 101 among the plurality of slits SL, the occurrence of cracks can be minimized, and due to another slit SL next closest to the cutting line CL, the effect of preventing another crack from occurring and extending can be improved.

[0164] Reference Fig.10 , a plurality of slits SL are formed. Among the slits SL, the width W1 of the slit SL closest to the edge or cutting line CL of the substrate 101 may be different from the widths W2 of the other slits SL. Among the slits SL, the width W1 of the slit SL closest to the edge or cutting line CL of the substrate 101 is greater than each of the widths W2 of the other slits SL. By doing so, the effect of mainly preventing the expansion of cracks that have already appeared at the cutting line CL of the substrate 101 can be increased.

[0165] The embodiment is not limited thereto, and the widths of the plurality of slits SL may be set differently. Fig.11 As shown, among the slits SL, the width W1 of the slit SL farthest from the edge of the substrate 101 or the cutting line CL may be greater than each of the widths W2 of the other slits SL. Fig.12 As shown, among the plurality of slits SL, a width W1 of a slit SL located between a slit SL closest to the edge of the substrate 101 or the cutting line CL and a slit SL farthest from the edge of the substrate 101 or the cutting line CL may be greater than a width W2 of the other slits SL.

[0166] Fig.13 An example in which the particles MR according to the embodiment remain in the cutout SL of the display device 1000 is shown.

[0167] Reference Fig.13 , the particle MR remains in the reference Figures 1 to 3 The particles MR may be, for example, metal particles, metal layer waste, or other metal residues. The particles MR may be generated from an external source or may be residues of materials used to form elements of the display device 1000 during the manufacturing process of the display device 1000.

[0168] When the cap layer CLL is formed on the slit SL, the cap layer CLL covers the particles MR, and thus, the movement of the particles MR can be prevented or the possibility of the movement of the particles MR can be reduced. The cap layer CLL can prevent the particles MR from moving to the display area DA of the display device 1000. By doing so, defects in the display area DA of the display device 1000 can be prevented, so that the display device 1000 can have improved electrical characteristics and / or improved image quality.

[0169] Fig.14 A plan view of a display device 2000 according to another embodiment is shown. Fig.15 Shows Fig.14 An enlarged view of part D of Fig.16 Shown along Fig.15 A cross-sectional view of portion D taken along line XVI-XVI.

[0170] Reference Figures 14 to 16 , the display device 2000 includes a substrate 201. The substrate 201 may include various materials. Detailed examples of various materials of the substrate 201 are the same as those described in the above embodiment, and thus a detailed description thereof is omitted here.

[0171] A plurality of display devices 2000 may be formed on a mother substrate, and may be separated into each display device 2000 in a manner of cutting the mother substrate along a cutting line CL of the substrate 201 . Fig.14 One display device 2000 is shown cut along a cutting line CL and thus separated. Thus, the edge of the substrate 201 is defined by the cutting line CL.

[0172] All edges of the substrate 201, such as Fig.14 The four edges of the substrate 201 shown in FIG. 2 may all be cutting lines CL. In other embodiments, one, two or three of the four edges of the substrate 201 may be cutting lines CL.

[0173] According to the size or shape of the mother substrate, the position or number of edges determined as the cutting line CL among all the edges of the display device 2000 may vary.

[0174] The substrate 201 is divided into a peripheral area PA and a central area CA. The peripheral area PA includes an area around the cutting line CL, that is, an area adjacent to the cutting line CL, and the central area CA indicates an area arranged inside compared to the peripheral area PA.

[0175] Embodiments are not limited thereto. The cutting line CL may not exist. One display device 2000 may be formed on a mother substrate, and in this case, the substrate 201 may correspond to the mother substrate, so that the cutting line CL may not exist. In this case, the peripheral area PA may indicate an area adjacent to an edge of the substrate 201, and the central area CA may indicate an area arranged inside compared to the peripheral area PA. For ease of description, it is assumed that the cutting line CL exists in the following embodiments.

[0176] The central area CA may include at least one display area DA.

[0177] The display area DA may have at least one display device (not shown), such as an OLED for displaying an image. In addition, a plurality of pixels may be arranged in the display area DA.

[0178] A non-display area (not shown) may be formed around the display area DA. The non-display area may be formed to surround the display area DA. In some embodiments, the non-display area may be formed to be adjacent to multiple sides of the display area DA. In some embodiments, the non-display area may be formed to be adjacent to one side of the display area DA.

[0179] In another embodiment, only the display area DA may be arranged in the central area CA, and the non-display area may be formed only in the peripheral area PA.

[0180] A pad area (not shown) may be formed in the non-display area, and a driver or a plurality of pad units (not shown) may be disposed in the pad area.

[0181] In some embodiments, at least one insulating layer (not shown) may be formed in the display area DA of the central area CA. The insulating layer may include an organic material or an inorganic material.

[0182] The peripheral area PA indicates an area adjacent to the cutting line CL, and the peripheral area PA is arranged in an edge of the substrate 201 along the cutting line CL.

[0183] In the peripheral area PA, a first insulating layer 211 is formed on the substrate 201. A slit SL is formed in the first insulating layer 211. The slit SL is formed in the peripheral area PA to be spaced apart from the display area DA.

[0184] The first insulating layer 211 may include various insulating materials. In some embodiments, the first insulating layer 211 may include an inorganic material. For example, the first insulating layer 211 may include an oxide, a nitride, or a nitride oxide. The first insulating layer 211 may include, for example, silicon nitride (SiNx), silicon oxide (SiO 2 ), or silicon oxynitride (SiO x N y ).

[0185] In some embodiments, the first insulating layer 211 may be formed while extending to the central area CA or the display area DA. In some embodiments, the first insulating layer 211 may be formed jointly on the central area CA and the peripheral area PA of the substrate 201. The first insulating layer 211 may be formed on the entire top surface of the substrate 201.

[0186] In some embodiments, the first insulating layer 211 may extend to the cutting line CL of the substrate 201 .

[0187] The embodiment is not limited thereto, and the first insulating layer 211 may not cover the top surface of the substrate 201 in the region of the peripheral area PA.

[0188] A capping layer CLL is formed on the first insulating layer 211 to cover the slit SL.

[0189] In some embodiments, the width of the cover layer CLL may be greater than the width of the slit SL, and the length of the cover layer CLL may be greater than the length of the slit SL. In this way, the cover layer CLL may completely cover the slit SL to prevent the slit SL from being exposed.

[0190] The cladding layer CLL may include various materials. The cladding layer CLL may include inorganic or organic materials.

[0191] In some embodiments, the cover layer CLL may include an organic material. In this way, an appropriate thickness and an appropriate width of the cover layer CLL may be ensured, and as a result, the cover layer CLL may cover the slit SL.

[0192] In some embodiments, the capping layer CLL may include the same material as an insulating layer (not shown) that may be formed in the central area CA of the substrate 201. In addition, the capping layer CLL and the insulating layer (not shown) that may be formed in the display area DA of the substrate 201 may be formed simultaneously.

[0193] In some embodiments, the capping layer CLL may be formed adjacent to an edge or a cutting line CL of the substrate 201 .

[0194] One side of the cover layer CLL adjacent to the edge of the substrate 201 or the cutting line CL, and the other side of the cover layer CLL facing the side may have different shapes. For example, one side of the cover layer CLL adjacent to the edge of the substrate 201 or the cutting line CL may be a plane almost perpendicular to the ground, and the other side of the cover layer CLL facing the side may be an inclined surface or a curved surface.

[0195] When the mother substrate is cut along the cutting line CL, the display device 2000 may be obtained by performing a cutting process on the capping layer CLL disposed at the cutting line CL, and as a result, a side surface of the capping layer CLL may have a cross-section caused by the cutting process.

[0196] Fig.17 Shows Fig.15 and Fig.16 A modification of the cutout SL and the cover CLL shown in FIG.

[0197] Reference Fig.17 , a plurality of slits SL are formed. Although not shown, one of the plurality of slits SL may overlap with the cutting line CL.

[0198] Fig.18 A plan view of a display device 3000 according to another embodiment is shown. Fig.19 Shows Fig.18 An enlarged view of part D of Fig. 20 Shown along Fig.19 A cross-sectional view of portion D taken along line IXX-IXX.

[0199] Reference Figures 18 to 20 , the display device 3000 includes a substrate 301. The substrate 301 may include various materials. Detailed examples of various materials of the substrate 301 are the same as those described in the above embodiment, and thus a detailed description thereof is omitted here.

[0200] A plurality of display devices 3000 may be formed on a mother substrate, and may be separated into each display device 3000 in a manner of cutting the mother substrate along a cutting line CL of the substrate 301 . Fig.18 One display device 3000 is shown cut along a cutting line CL and thus separated. Thus, the edge of the substrate 301 is defined by the cutting line CL.

[0201] All edges of the substrate 301, such as Fig.18 All four edges of the substrate 301 shown in FIG. 3 may be cutting lines CL. In some embodiments, one, two or three of the four edges of the substrate 301 may be cutting lines CL.

[0202] According to the size or shape of the mother substrate, the position or number of edges determined as the cutting line CL among all the edges of the display device 3000 may vary.

[0203] The substrate 301 is divided into a peripheral area PA and a central area CA. The peripheral area PA indicates an area around the cutting line CL, and the central area CA indicates an area arranged inside compared with the peripheral area PA.

[0204] Embodiments are not limited thereto. The cutting line CL may not exist. One display device 3000 may be formed on a mother substrate, and in this case, the substrate 301 may correspond to the mother substrate, so that the cutting line CL may not exist. In this case, the peripheral area PA may indicate an area adjacent to an edge of the substrate 301, and the central area CA may indicate an area arranged inside compared to the peripheral area PA. For ease of description, it is assumed that the cutting line CL exists in the embodiments described below.

[0205] The central area CA may include at least one display area DA.

[0206] The display area DA may include at least one display device (not shown), such as an OLED for displaying an image. In addition, a plurality of pixels may be provided in the display area DA.

[0207] A non-display area (not shown) may be formed around the display area DA. The non-display area may be formed to surround the display area DA. In some embodiments, the non-display area may be formed to be adjacent to multiple sides of the display area DA. In some embodiments, the non-display area may be formed to be adjacent to one side of the display area DA.

[0208] In some embodiments, only the display area DA may be disposed in the central area CA, and the non-display area may be formed only in the peripheral area PA.

[0209] A pad area (not shown) may be formed in the non-display area, and a driver or a plurality of pad units (not shown) may be disposed in the pad area.

[0210] In some embodiments, at least one insulating layer (not shown) may be formed in the display area DA of the central area CA. The insulating layer may include an organic material or an inorganic material.

[0211] In the peripheral area PA, a first insulating layer 311 is formed in the substrate 301. A plurality of slits SL are formed in the first insulating layer 311. The plurality of slits SL may be spaced apart from each other.

[0212] The plurality of slits SL may be arranged in one direction intersecting another direction from the edge of the substrate 301 or the cutting line CL to the display area DA.

[0213] In addition, if Fig.21 As shown, multiple cutouts SL can be formed in one direction (see Fig.21 Y-axis direction) and another direction intersecting with this direction (see Fig.21 in the X-axis direction).

[0214] The cover layer CLL may be formed to cover all of the plurality of cutouts SL.

[0215] Fig. 22A plan view of a display device 4000 according to another embodiment is shown. Fig.23 Shown along Fig. 22 A cross-sectional view taken along line XXII-XXII.

[0216] Reference Fig. 22 and Fig.23 , the display device 4000 includes a substrate 401. The substrate 401 may include various materials. Detailed examples of various materials of the substrate 401 are the same as those described in the above embodiment, and thus a detailed description thereof is omitted here.

[0217] The cutting line CL of the display device 4000 is the same as in the above embodiment, and thus a detailed description thereof is omitted here.

[0218] The substrate 401 is divided into a peripheral area PA and a central area CA. The peripheral area PA indicates an area around the cutting line CL, and the central area CA indicates an area arranged inside compared to the peripheral area PA. Since this is described in the above embodiment, a detailed description thereof is omitted here.

[0219] In some embodiments, at least one insulating layer (not shown) is formed in the display area DA of the central area CA. The insulating layer may include an organic material or an inorganic material.

[0220] In the peripheral area PA, a first insulating layer 411 is formed on the substrate 401. A slit SL is formed on the first insulating layer 411. The slit SL is formed in the peripheral area PA to be spaced apart from the display area DA.

[0221] In the display area DA of the central area CA, at least one encapsulation layer may be formed to reduce or prevent moisture or foreign substances from penetrating into a display device (not shown) in the display area DA. Fig.23 Two encapsulation layers 461 and 462 are shown, a first inorganic encapsulation layer 461 and a second inorganic encapsulation layer 462. Fig.23 The first inorganic encapsulation layer 461 and the second inorganic encapsulation layer 462 extend from the display area DA to the peripheral area PA. The first inorganic encapsulation layer 461 is formed on the first insulating layer 411 , and the second inorganic encapsulation layer 462 is formed on the first inorganic encapsulation layer 461 .

[0222] The first and second inorganic encapsulating layers 461 and 462 may be spaced apart from the overlayer CLL and the cutout SL.

[0223] Although not shown, the first and second inorganic encapsulating layers 461 and 462 may not extend to the peripheral area PA and may not overlap the peripheral area PA.

[0224] In some embodiments, one of the first inorganic encapsulating layer 461 and the second inorganic encapsulating layer 462 may be provided. In some embodiments, an encapsulating layer (not shown) including an organic material instead of an inorganic material may be formed.

[0225] Fig.24 Shows Fig. 22 and Fig.23 A variation of the display device 4000.

[0226] Fig.24 Four encapsulation layers are shown: a first inorganic encapsulation layer 461 , a second inorganic encapsulation layer 462 , a first organic encapsulation layer 471 , and a second organic encapsulation layer 472 .

[0227] Reference Fig.24 , four encapsulation layers 461, 462, 471, and 472 extend from the display area DA to the peripheral area PA. The first inorganic encapsulation layer 461 may be formed on the first insulating layer 411, the first organic encapsulation layer 471 may be formed between the first insulating layer 411 and the first inorganic encapsulation layer 461, the second inorganic encapsulation layer 462 may be formed on the first inorganic encapsulation layer 461, and the second organic encapsulation layer 472 may be disposed between the first inorganic encapsulation layer 461 and the second inorganic encapsulation layer 462.

[0228] A region of a top surface of the first inorganic encapsulating layer 461 close to the peripheral area PA may be in contact with a region of a bottom surface of the second inorganic encapsulating layer 462 close to the peripheral area PA.

[0229] The four encapsulation layers 461 , 462 , 471 , and 472 may be separated from the cover layer CLL and the cutout SL.

[0230] Since the four encapsulation layers 461, 462, 471 and 472 are separated from the covering layer CLL and the cut SL, cracks that may appear in the cut SL can be prevented from extending through one of the four encapsulation layers 461, 462, 471 and 472, and particles that may remain in the cut SL can be prevented from moving through one of the four encapsulation layers 461, 462, 471 and 472.

[0231] Although not shown, the four encapsulation layers 461 , 462 , 471 , and 472 may not extend to the peripheral area PA and may not overlap the peripheral area PA.

[0232] Fig.25 A plan view of a display device 5000 according to another embodiment is shown. Fig.26 Shown along Fig.25 A cross-sectional view of the display device 5000 taken along lines XXVA-XXVA and XXVB-XXVB.

[0233] Reference Fig.25 and Fig.26 , the display device 5000 includes a substrate 501. The substrate 501 may include various materials. Detailed examples of various materials of the substrate 501 are the same as those described in the above embodiment, and thus a detailed description thereof is omitted here.

[0234] The cutting line CL of the display device 5000 is the same as in the above embodiment, and thus a detailed description thereof is omitted here.

[0235] The substrate 501 is divided into a peripheral area PA and a central area CA. The peripheral area PA indicates an area around the cutting line CL, and the central area CA indicates an area arranged inside compared to the peripheral area PA. Since this is described in the above embodiment, a detailed description thereof is omitted here.

[0236] A first insulating layer 511 is formed on the substrate 501. The first insulating layer 511 may include various insulating materials. For example, the first insulating layer 511 may include an inorganic material.

[0237] The first insulating layer 511 may be formed in the central area CA and the peripheral area PA. In some embodiments, the first insulating layer 511 may be formed on the substrate 501 without a separate patterning process.

[0238] The first insulating layer 511 may include various insulating materials. In some embodiments, the first insulating layer 511 may include an inorganic material. For example, the first insulating layer 511 may include an oxide, a nitride, or a nitride oxide. The first insulating layer 511 may include, for example, silicon nitride (SiNx), silicon oxide (SiO 2 ) or silicon oxynitride (SiO x N y ). In addition, the first insulating layer 511 may be formed by using various deposition methods including a plasma enhanced chemical vapor deposition (PECVD) method, an atmospheric pressure CVD (APCVD) method, a low pressure CVD (LPCVD) method, and the like.

[0239] On the first insulating layer 511, a thin film transistor (TFT) may be formed in the display area DA. The TFT formed in the display area DA serves as a part of the pixel circuit. In addition, the TFT may be formed in the non-display area. The TFT formed in the non-display area serves as a part of the circuit included in the driver.

[0240] In some embodiments, the TFT corresponds to a top gate type TFT in which an active layer 513, a gate electrode 515, a source electrode 517, and a drain electrode 518 are sequentially formed. In other embodiments, various types of TFTs including a bottom gate type TFT may be used as the TFT.

[0241] The active layer 513 is formed on the first insulating layer 511. The active layer 513 may include a semiconductor material, such as amorphous silicon or polycrystalline silicon. In some embodiments, the active layer 513 may include various materials. In some embodiments, the active layer 513 may include an organic semiconductor material.

[0242] In some embodiments, the active layer 513 may include an oxide semiconductor material. For example, the active layer 513 may include an oxide including a material selected from Group 12, 13, and 14 metal elements, such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), and hafnium (Hf), or a combination thereof.

[0243] As described above, one embodiment may include a bottom gate type TFT. If the active layer 513 includes oxide or amorphous silicon, the embodiment may include a bottom gate type TFT.

[0244] The bottom gate TFT may have various structures. For one example, a gate electrode may be formed on the first insulating layer 511, an active layer may be formed on the gate electrode, and a source electrode and a drain electrode may be provided on the active layer. As another example, a gate electrode may be formed on a substrate, a source electrode and a drain electrode may be formed on the gate electrode, and an active layer may be formed on the source electrode and the drain electrode. In this case, an insulating layer, such as an inorganic layer, may be formed adjacent to the gate electrode, the active layer, and at least one of the source electrode and the drain electrode.

[0245] A second insulating layer 521 is formed on the active layer 513 . The second insulating layer 521 may be formed as a multi-layer or single-layer including an inorganic material such as silicon oxide and / or silicon nitride. The second insulating layer 521 insulates the active layer 513 from the gate electrode 515 .

[0246] The second insulating layer 521 may be formed in the central area CA and the peripheral area PA. In some embodiments, the second insulating layer 521 may be formed between the active layer 513 and the gate electrode 515 without a separate patterning process.

[0247] A gate electrode 515 is disposed on the second insulating layer 521. The gate electrode 515 may be connected to a gate line (not shown) that applies an ON signal or an OFF signal to the TFT.

[0248] The gate electrode 515 may include a low resistance metal material. For example, the gate electrode 515 may be formed as a multi-layer or single-layer including a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti).

[0249] An interlayer insulating layer 522 is formed on the gate electrode 515. The interlayer insulating layer 522 insulates the gate electrode 515 from the source electrode 517 and the drain electrode 518.

[0250] The interlayer insulating layer 522 may be formed in the central area CA and the peripheral area PA. In some embodiments, the interlayer insulating layer 522 may be formed between the source and drain electrodes 517 and 518 and the gate electrode 515 without a separate patterning process.

[0251] The interlayer insulating layer 522 may be formed as a multilayer or single layer including an inorganic material. For example, the inorganic material may be a metal oxide or a metal nitride. In some embodiments, the inorganic material may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zirconium oxide (ZrO 2 ).

[0252] Before the source electrode 517 and the drain electrode 518 are formed on the interlayer insulating layer 522, a process of forming contact holes is performed so that the source electrode 517 and the drain electrode 518 respectively contact regions of the active layer 513. Regions of the second insulating layer 521 and the interlayer insulating layer 522 formed on the active layer 513 are removed.

[0253] In some embodiments, when the process of forming the contact hole is performed, the process of forming the slit SL in the peripheral area PA may be performed. The process of removing the second insulating layer 521 and the interlayer insulating layer 522 on the active layer 513 and the process of forming the slit SL may be performed simultaneously.

[0254] Each of the slits SL extends through the second insulating layer 521 and the interlayer insulating layer 522 , and corresponds to a predetermined thickness of the first insulating layer 511 .

[0255] In some embodiments, each slit SL may extend through the interlayer insulating layer 522 and may correspond to a portion of the thickness of the second insulating layer 521. In some embodiments, each slit SL may correspond to a portion of the thickness of the interlayer insulating layer 522.

[0256] Fig.26 A plurality of slits SL are shown, but one slit SL may be formed in other embodiments.

[0257] A source electrode 517 and a drain electrode 518 are formed on the interlayer insulating layer 522. Each of the source electrode 517 and the drain electrode 518 may be formed as a single layer or a multilayer including a highly conductive material.

[0258] The source electrode 517 and the drain electrode 518 are formed to contact the active layer 513. Some of the metal material used to form the source electrode 517 and the drain electrode 518 may remain in the cutout SL.

[0259] A passivation layer 530 is formed on the source electrode 517 and the drain electrode 518 to cover the TFT.

[0260] The passivation layer 530 can remove the steps caused by the TFT, provide a flat layer above the TFT, and thus prevent the unevenness caused by the TFT from causing defects in the OLED 540. The passivation layer 530 can be formed as a single layer or multiple layers including an organic material. The organic material can include a polymer derivative with a commercial polymer, such as polymethyl methacrylate (PMMA) or polystyrene (PS), as well as a phenol-based polymer, an propylene-based polymer, an imide-based polymer, an aryl ether-based polymer, an amino polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a combination thereof. In addition, the passivation layer 530 can be formed as a multi-stack including an inorganic insulating layer and an organic insulating layer.

[0261] In some embodiments, the capping layer CLL may include the same material as the passivation layer 530. The capping layer CLL may include an organic material.

[0262] In some embodiments, the passivation layer 530 and the capping layer CLL may be formed simultaneously. When the passivation layer 530 is formed, a through-hole forming process is performed to expose the surface of one of the source electrode 517 and the drain electrode 518, and a through-hole forming process may be performed and the capping layer CLL may be patterned at the same time. The capping layer CLL may be easily formed without using an additional mask.

[0263] The overcoat layer CLL may cover the cutout SL and thus may reduce or prevent movement of particles that may remain in the cutout SL. By doing so, electrical defects including short circuit defects of the OLED 540 in the display area DA may be reduced.

[0264] An OLED 540 is formed on the passivation layer 530. The OLED 540 is electrically connected to the TFT.

[0265] The OLED 540 includes a first electrode 541 , a second electrode 542 , and an intermediate layer 543 disposed between the first electrode 541 and the second electrode 542 .

[0266] The first electrode 541 is electrically connected to one of the source electrode 517 and the drain electrode 518. Fig.26 , the first electrode 541 may be electrically connected to the drain electrode 518 .

[0267] The first electrode 541 may have one of various forms. For example, the first electrode 541 may be patterned in the form of an island.

[0268] The first electrode 541 may include various materials. The first electrode 541 may include at least one transparent conductive oxide material, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The first electrode 541 may include a metal having high reflectivity, for example, silver (Ag).

[0269] The intermediate layer 543 may include an organic emission layer including a small molecule organic material or a polymer molecule organic material. In some embodiments, the intermediate layer 543 includes an organic emission layer and may further include one or more of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0270] An organic emission layer may be formed in each OLED. In this case, the OLED may emit red light, green light, and blue light, respectively. In some embodiments, the organic emission layer may be formed together in the OLED. For example, a plurality of organic emission layers emitting red light, green light, and blue light may be vertically stacked or mixed, and thus may emit white light. The color combination for emitting white light is not limited to the above description. A color conversion layer or a color filter may be separately arranged to convert the emitted white light into a predetermined color.

[0271] The second electrode 542 may include various conductive materials. For example, the second electrode 542 may be formed as a multilayer or single layer including at least one of lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), silver (Ag), or an alloy including at least two of these materials.

[0272] A pixel defining layer 535 is formed on the passivation layer 530. The pixel defining layer 535 is formed but does not cover a predetermined region of the first electrode 541, an intermediate layer 543 is formed on a predetermined region of the first electrode 541 not covered by the pixel defining layer 535, and a second electrode 542 is formed on the intermediate layer 543.

[0273] The pixel defining layer 535 may include at least one inorganic insulating material, such as polyimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin, and the pixel defining layer 535 may be formed by using a spin coating method.

[0274] In some embodiments, the capping layer CLL may include the same material as the pixel defining layer 535 .

[0275] Although not shown on the second electrode 542, in some embodiments, a functional layer (not shown) may be further formed on the second electrode 542. The functional layer may include a plurality of layers formed on the second electrode 542. At least one layer of the functional layer may prevent the second electrode 542 from being contaminated in subsequent processing, and another layer of the functional layer may improve the efficiency of visible light emitted from the intermediate layer 543 to the second electrode 542.

[0276] The cutouts SL arranged in the first insulating layer 511 in the peripheral area PA of the display device 5000 prevent cracks from extending from the edge of the substrate 501. For example, the cutouts SL adjacent to the cutting lines CL of the substrate 501 mainly prevent the extension of cracks that may occur on the substrate 501 when each display device 5000 is cut and separated from the mother substrate.

[0277] When the substrate 501 includes a flexible material and thus the display device 5000 has flexibility, the cutout SL may effectively reduce or prevent occurrence and extension of cracks in the peripheral area PA when a bending or flexing action occurs at the peripheral area PA.

[0278] The cover layer CLL is formed on the slit SL. Due to the cover layer CLL, movement of foreign substances or particles that may remain in the slit SL may be prevented. In some embodiments, the cover layer CLL may cover the slit SL so that foreign substances or particles that may remain in the slit SL may not be exposed.

[0279] Due to the first insulating layer 511 , the capping layer CLL may not be delaminated from the substrate 501 .

[0280] The capping layer CLL may include the same material as the passivation layer 530 in the central area CA, and in some embodiments, a via forming process and a capping layer forming process may be simultaneously performed when forming the passivation layer 530. Therefore, the capping layer CLL may be easily formed without increasing a patterning process using a separate mask.

[0281] The embodiment may include one of a plurality of types of TFTs, and in some embodiments, the overlayer CLL may include the same material as an insulating layer of the TFT, the insulating layer being adjacent to one of the active layer, the gate electrode, the source electrode, and the drain electrode. In some embodiments, the overlayer CLL and the insulating layer of the TFT may be formed simultaneously.

[0282] Fig. 27 Shows Fig.25 and Fig.26 A variation of the display device 5000 shown in FIG.

[0283] For convenience of description, the present embodiment will be described focusing on differences from the above embodiments.

[0284] Reference Fig. 27 , the display device 5000 includes a barrier layer 502 located between a substrate 501 and a first insulating layer 511 .

[0285] The barrier layer 502 may reduce or prevent moisture or foreign substances from penetrating into the display device 5000 via the substrate 501. Since the slit SL is not formed in the barrier layer 502, the barrier layer 502 may reduce or prevent moisture or foreign substances from penetrating toward the slit SL.

[0286] In some embodiments, each cutout SL may have a size greater than Fig. 27 The depth of the depth shown in FIG. 5 and thus each cutout SL may be formed even in the barrier layer 502 .

[0287] The barrier layer 502 may include silicon nitride (SiN x ), silicon oxide (SiO 2 ) or silicon oxynitride (SiO x N y ).

[0288] Fig.28 A plan view of a display device 6000 according to another embodiment is shown. Fig.29 Shown along Fig.28 A cross-sectional view taken along lines XXXA-XXXA and XXXB-XXXB.

[0289] Reference Fig.28 and Fig.29 , the display device 6000 includes a substrate 601. The substrate 601 may include various materials. Detailed examples of various materials of the substrate 601 are the same as those described in the above embodiment, and thus detailed descriptions thereof are omitted here.

[0290] The cutting line CL of the display device 6000 is the same as in the above embodiment, and thus, a detailed description thereof is omitted herein.

[0291] The substrate 601 is divided into a peripheral area PA and a central area CA. The peripheral area PA indicates an area adjacent to the cutting line CL, and the central area CA indicates an area arranged inside compared to the peripheral area PA. Since this is described in the above embodiment, a detailed description thereof is omitted here.

[0292] A barrier layer 602 is formed between the substrate 601 and the first insulating layer 611 .

[0293] The barrier layer 602 may reduce or prevent moisture or foreign substances from penetrating into the display device 6000 via the substrate 601. Since the slit SL is not formed in the barrier layer 602, the barrier layer 602 may reduce or prevent moisture or foreign substances from penetrating toward the slit SL.

[0294] In some embodiments, each cutout SL may have a size greater than Fig.29 The depth of the depth shown in FIG. 6A and thus each cutout SL can be formed even in the barrier layer 602 .

[0295] The barrier layer 602 may include silicon nitride (SiN x ), silicon oxide (SiO 2 ) or silicon oxynitride (SiO x N y ).

[0296] A first insulating layer 611 is formed on the barrier layer 602. The first insulating layer 611 may include various insulating materials. For example, the first insulating layer 611 may include an inorganic material.

[0297] The first insulating layer 611 may be formed in the central area CA and the peripheral area PA. In some embodiments, the first insulating layer 611 may be formed on the substrate 601 without a separate patterning process.

[0298] The first insulating layer 611 may include various insulating materials. For example, the first insulating layer 611 may include an inorganic material. For example, the first insulating layer 611 may include an oxide, a nitride, or a nitride oxide. The first insulating layer 611 may include, for example, silicon nitride (SiNx), silicon oxide (SiO 2 ) or silicon oxynitride (SiO x N y ). In addition, the first insulating layer 611 may be formed by using various deposition methods including a PECVD method, an APCVD method, an LPCVD method, and the like.

[0299] On the first insulating layer 611, a TFT may be formed in the display area DA. The TFT formed in the display area DA serves as a part of the pixel circuit. In addition, a TFT may be formed in the non-display area. The TFT formed in the non-display area serves as a part of the circuit included in the driver.

[0300] In some embodiments, the TFT corresponds to a top gate type TFT in which an active layer 613, a gate electrode 615, a source electrode 617, and a drain electrode 618 are sequentially formed. In other embodiments, various types of TFTs including a bottom gate type TFT may be applied to the TFT.

[0301] The active layer 613 is formed on the first insulating layer 611. The material for forming the first insulating layer 611 is described in the above embodiment, and thus a detailed description thereof is omitted here.

[0302] A second insulating layer 621 is formed on the active layer 613. The second insulating layer 621 may be formed as a multilayer or single layer including an inorganic material such as silicon oxide and / or silicon nitride. The second insulating layer 621 may be formed in the central area CA and the peripheral area PA. In some embodiments, the second insulating layer 621 may be formed between the active layer 613 and the gate electrode 615 without a separate patterning process.

[0303] A gate electrode 615 is disposed on the second insulating layer 621. The gate electrode 615 may be connected to a gate line (not shown) that applies an ON signal or an OFF signal to the TFT.

[0304] An interlayer insulating layer 622 is formed on the gate electrode 615. The interlayer insulating layer 622 insulates the gate electrode 615 from the source electrode 617 and the drain electrode 618.

[0305] The interlayer insulating layer 622 may be formed in the central area CA and the peripheral area PA. In some embodiments, the interlayer insulating layer 622 may be formed between the source and drain electrodes 617 and 618 and the gate electrode 615 without a separate patterning process.

[0306] The interlayer insulating layer 622 may be formed as a multilayer or single layer including an inorganic material. For example, the inorganic material may be a metal oxide or a metal nitride. The inorganic material may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zirconium oxide (ZrO 2 ).

[0307] Before the source electrode 617 and the drain electrode 618 are formed on the interlayer insulating layer 622, a process of forming contact holes is performed so that the source electrode 617 and the drain electrode 618 respectively contact regions of the active layer 613. The regions of the second insulating layer 621 and the interlayer insulating layer 622 formed on the active layer 613 are removed.

[0308] In some embodiments, when the process of forming the contact hole is performed, the process of forming the slit SL in the peripheral area PA may be performed. The process of removing the second insulating layer 621 and the interlayer insulating layer 622 on the active layer 613 and the process of forming the slit SL may be performed simultaneously.

[0309] Each of the slits SL extends through the second insulating layer 621 and the interlayer insulating layer 622 , and corresponds to a predetermined thickness of the first insulating layer 611 .

[0310] In some embodiments, each slit SL may extend through the interlayer insulating layer 622 and may correspond to a portion of the thickness of the second insulating layer 621. In some embodiments, each slit SL may correspond to a portion of the thickness of the interlayer insulating layer 622.

[0311] Fig.29 A plurality of slits SL are shown, but in some embodiments, one slit SL may be formed.

[0312] A source electrode 617 and a drain electrode 618 are formed on the interlayer insulating layer 622. Each of the source electrode 617 and the drain electrode 618 may be formed as a single layer or a multilayer including a highly conductive material.

[0313] The source electrode 617 and the drain electrode 618 are formed to be in contact with the active layer 613. Some of the metal material used to form the source electrode 617 and the drain electrode 618 may remain in the cutout SL.

[0314] A passivation layer 630 is formed on the source electrode 617 and the drain electrode 618 to cover the TFT.

[0315] The passivation layer 630 can remove the steps caused by the TFT, provide a flat layer above the TFT, and thus prevent the unevenness caused by the TFT from causing defects in the OLED 640. The passivation layer 630 can be formed as a single layer or multiple layers including an organic material. The organic material can include a polymer derivative with a commercial polymer, such as polymethyl methacrylate (PMMA) or polystyrene (PS), and an aromatic, acrylic polymer, an imide polymer, an aromatic ether polymer, an amino polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a combination thereof. The passivation layer 630 can be formed as a multi-stack including an inorganic insulating layer and an organic insulating layer.

[0316] In some embodiments, the capping layer CLL may include the same material as the passivation layer 630. The capping layer CLL may include an organic material.

[0317] In some embodiments, the passivation layer 630 and the capping layer CLL may be formed simultaneously. When the passivation layer 630 is formed, a through-hole forming process is performed to expose the surface of one of the source electrode 617 and the drain electrode 618, and a through-hole forming process may be performed and the capping layer CLL may be patterned at the same time. The capping layer CLL may be easily formed without using an additional mask.

[0318] An OLED 640 is formed on the passivation layer 630. The OLED 640 is electrically connected to the TFT.

[0319] The OLED 640 includes a first electrode 641 , a second electrode 642 , and an intermediate layer 643 disposed between the first electrode 641 and the second electrode 642 .

[0320] The first electrode 641 is electrically connected to one of the source electrode 617 and the drain electrode 618. Fig.29 , the first electrode 641 may be electrically connected to the drain electrode 618 .

[0321] The first electrode 641 may have one of various forms. For example, the first electrode 641 may be patterned in the form of an island.

[0322] The first electrode 641 may include various materials. The first electrode 641 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In addition, the first electrode 641 may include a metal having high reflectivity, such as silver (Ag).

[0323] The intermediate layer 643 may include an organic emission layer including a small molecule organic material or a polymer molecule organic material. In some embodiments, the intermediate layer 643 includes an organic emission layer and may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer.

[0324] An organic emission layer may be formed in each OLED. The OLED may emit red light, green light, and blue light, respectively. In other embodiments, the organic emission layer may be formed together in the OLED. For example, a plurality of organic emission layers emitting red light, green light, and blue light may be vertically stacked or mixed, and thus may emit white light. The color combination for emitting white light is not limited to the above description. A color conversion layer or a color filter may be arranged separately to convert the emitted white light into a predetermined color.

[0325] The second electrode 642 may include various conductive materials. For example, the second electrode 642 may be formed as a multilayer or single layer including at least one of lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), silver (Ag), or an alloy including at least two of these materials.

[0326] A pixel defining layer 635 is formed on the passivation layer 630. The pixel defining layer 635 is formed but does not cover a predetermined region of the first electrode 641, an intermediate layer 643 is formed on a predetermined region of the first electrode 641 not covered by the pixel defining layer 635, and a second electrode 642 is formed on the intermediate layer 643.

[0327] The pixel defining layer 635 may include at least one inorganic insulating material, such as polyimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin, and the pixel defining layer 635 may be formed by using a spin coating method.

[0328] In some embodiments, the capping layer CLL may include the same material as the pixel defining layer 635 .

[0329] Although not shown on the second electrode 642, in some embodiments, a functional layer (not shown) may be further formed on the second electrode 642. The functional layer may include a plurality of layers formed on the second electrode 642. At least one layer of the functional layer may prevent the second electrode 642 from being contaminated in subsequent processing, and another layer of the functional layer may improve the efficiency of visible light emitted from the intermediate layer 643 to the second electrode 642.

[0330] One or more encapsulation layers 661 , 662 , 671 , and 672 may be formed on the second electrode 642 to reduce or prevent moisture or foreign substances from penetrating into the OLED 640 .

[0331] Fig.29 Four encapsulation layers are shown: a first inorganic encapsulation layer 661 , a second inorganic encapsulation layer 662 , a first organic encapsulation layer 671 , and a second organic encapsulation layer 672 .

[0332] The first inorganic encapsulating layer 661 is formed on the first organic encapsulating layer 671 , the second organic encapsulating layer 672 is formed on the first inorganic encapsulating layer 661 , and the second inorganic encapsulating layer 662 is formed on the second organic encapsulating layer 672 .

[0333] The area of ​​the first inorganic encapsulation layer 661 and the area of ​​the second inorganic encapsulation layer 662 may contact each other. The width of the first inorganic encapsulation layer 661 and the second inorganic encapsulation layer 662 may extend in one direction so as to be greater than the width of the first organic encapsulation layer 671 and the second organic encapsulation layer 672. In some embodiments, the entire area of ​​the first inorganic encapsulation layer 661 and the second inorganic encapsulation layer 662 may be greater than the entire area of ​​the first organic encapsulation layer 671 and the second organic encapsulation layer 672.

[0334] In some embodiments, at least one of the four encapsulation layers 661 , 662 , 671 , and 672 may be omitted, and in some embodiments, the display device 6000 may further include at least an additional organic encapsulation layer or an additional inorganic encapsulation layer.

[0335] The first organic encapsulating layer 671 and the second organic encapsulating layer 672 may include various organic materials including an acryl-based material, an epoxy-based material, a PI-based material, and the like.

[0336] The first inorganic encapsulation layer 661 and the second inorganic encapsulation layer 662 may include various inorganic materials, including metal oxides, for example, Al 2 O 3 、TiO 2 , MgO or CrO. In some embodiments, the first inorganic encapsulation layer 661 and the second inorganic encapsulation layer 662 may include a silicon-based material, such as SiN x , SiON or SiO 2 or other ceramic materials.

[0337] The four encapsulation layers 661 , 662 , 671 , and 672 may extend from the display area DA to the peripheral area PA.

[0338] The four encapsulation layers 661 , 662 , 671 , and 672 may be separated from the cover layer CLL and the cutout SL.

[0339] In some embodiments, the four encapsulation layers 661 , 662 , 671 , and 672 may not extend toward the peripheral area PA and may not overlap the peripheral area PA.

[0340] In some embodiments, the capping layer CLL and at least one of the four encapsulation layers 661 , 662 , 671 , and 672 may include the same material.

[0341] Figure 30 to Figure 33 A plan view of a display device 7000 according to another embodiment is shown.

[0342] Reference Figure 30 to Figure 33 , the display device 7000 includes a display area DA and a cover layer CLL on a substrate 701 . Figure 30 to Figure 33The structure of the display device 7000 shown in FIG. 7 may be applied to the above embodiments and one or more embodiments described below.

[0343] For convenience of description, detailed description of elements other than the overlay layer CLL is omitted herein.

[0344] Reference Fig.30 The overcoat layer CLL may surround the display area DA and may have an edge parallel to an edge of the substrate 701 .

[0345] Reference Fig.31 , an edge of the cover layer CLL may correspond to an edge of the display area DA except for one edge of the display area DA.

[0346] Reference Fig.32 , an edge of the cover layer CLL may correspond to an edge of the display area DA except for one edge of the display area DA.

[0347] like Fig.32 As shown, the cladding layer CLL may include one or more main portions CLLm corresponding to the edge of the substrate 701, and may include at least one corner portion CLLa connected to two adjacent main portions CLLm. In some embodiments, the corner portion CLLa may correspond to a corner of the substrate 701.

[0348] In addition, if Fig.33 As shown, when the pad area PDA is formed in the area outside the display area DA of the substrate 701, the overcoat CLL may be formed near the pad area PDA, and at the same time the overcoat CLL is separated from the pad area PDA. The overcoat CLL may include a bent portion CLLt according to the shape of the pad area PDA. Fig.33 , the curved portion CLLt is bent toward the display area DA. However, in some embodiments, the curved portion CLLt may be bent away from the display area DA.

[0349] Fig.34 A plan view illustrating a mother substrate MSU used in manufacturing a display device according to an embodiment. Fig.35 Shows Fig.34 An enlarged plan view of section M, and Fig.36 Shown along Fig.35 A cross-sectional view of portion M taken along line XXX-XXX.

[0350] Reference Fig.34 A plurality of units C1, C2, C3 and C4 are provided on the mother substrate MSU. The plurality of units C1, C2, C3 and C4 correspond to a plurality of display devices, respectively.

[0351] The mother substrate MSU is cut along the cutting line CL, and thus the plurality of cells C1, C2, C3, and C4 are separated. Thereafter, four display devices are manufactured through subsequent processes. Each of the manufactured four display devices may be one of the display devices according to the above-described embodiments.

[0352] The mother substrate MSU includes a substrate 101 .

[0353] The substrate 101 may include various materials. Detailed examples of various materials of the substrate 101 are the same as those described in the above embodiment, and thus a detailed description thereof is omitted here.

[0354] Each of the plurality of cells C1, C2, C3 and C4 of the mother substrate MSU is divided into a peripheral area PA and a central area CA. The peripheral area PA indicates an area adjacent to the cutting line CL, and the central area CA indicates an area disposed inside compared to the peripheral area PA.

[0355] The central area CA may include at least one display area DA.

[0356] The display area DA may have at least one display device (not shown) for displaying an image, such as an OLED. In addition, a plurality of pixels may be arranged in the display area DA.

[0357] A non-display area (not shown) may be formed around the display area DA. The non-display area may be formed to surround the display area DA. In some embodiments, the non-display area may be formed to be adjacent to multiple sides of the display area DA. In some embodiments, the non-display area may be formed to be adjacent to one side of the display area DA.

[0358] In some embodiments, only the display area DA may be disposed in the central area CA, and the non-display area may be formed only in the peripheral area PA.

[0359] A pad area (not shown) may be formed in the non-display area, and a driver or a plurality of pad units (not shown) may be disposed in the pad area.

[0360] The peripheral area PA indicates a region around the cutting line CL, and the peripheral area PA may be arranged in a side end of the mother substrate MSU along the cutting line CL.

[0361] In the peripheral area PA, a first insulating layer 111 is formed on the substrate 101. A slit SL is formed on the first insulating layer 111. The slit SL is formed in the peripheral area PA to be spaced apart from the display area DA.

[0362] The slit SL may be spaced apart from the cutting line CL. A capping layer CLL is formed on the first insulating layer 111 to cover the slit SL. The capping layer CLL may be spaced apart from the cutting line CL.

[0363] Due to the cutout SL, the movement of cracks that may occur on the first insulating layer 111 during the cutting process performed along the cutting line CL can be prevented or reduced. In addition, due to the capping layer CLL, the movement of particles that may remain in the cutout SL can be prevented or reduced, so that electrical defects that may occur in the display device can be prevented.

[0364] Since the first insulating layer 111 and the cap layer CLL are in contact with each other, it is possible to prevent the cap layer CLL from being delaminated from the substrate 101 .

[0365] For ease of description, Figure 1 The structure of the display device 1000 shown in FIG. 1 is applied to this embodiment mode, and the structure of any one of the above embodiments may be applied to this embodiment mode.

[0366] Fig.37 Shows Fig.36 A modification of the structure shown in .

[0367] Reference Fig.37 , in the peripheral area PA, a first insulating layer 111 is formed on the substrate 101. A plurality of cutouts SL are formed on the first insulating layer 111. The plurality of cutouts SL are formed in the peripheral area PA to be separated from the display area DA.

[0368] In addition, the cutout SLC among the plurality of cutouts SL may overlap the cutting line CL. The cutout SLC overlapping the cutting line CL may increase the effect of preventing cracks from occurring on the first insulating layer 111 during a cutting process performed along the cutting line CL.

[0369] A capping layer CLL is formed on the first insulating layer 111 to cover the plurality of slits SL. The capping layer CLL may overlap the cutting lines CL. After the cutting process is performed, the capping layer CLL may have a cross section parallel to the cutting lines CL.

[0370] As described above, according to one or more of the above embodiments, the display device may have improved durability and improved image quality.

[0371] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for a limiting purpose. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments.

[0372] Although one or more embodiments have been described with reference to the drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display device, comprising: A display area, which displays images and includes at least one display device disposed on a substrate; A peripheral area, arranged outside the display area and adjacent to an edge of the substrate; A thin film transistor, disposed in the display area and connected to the display device, the thin film transistor comprising an active layer, a gate electrode, a source electrode and a drain electrode; A first insulating layer, disposed in the display area and the peripheral area; a second insulating layer, disposed in the display area and the peripheral area and disposed on the first insulating layer; a third insulating layer, disposed in the display area and the peripheral area and disposed on the second insulating layer; a passivation layer, disposed on the third insulating layer in the display area and covering the thin film transistor; at least one cutout formed by removing the first insulating layer, the second insulating layer, and the third insulating layer in a thickness direction in the peripheral region; a coating disposed in the peripheral region and covering the at least one cutout, wherein a width of the coating is greater than a width of the at least one cutout; as well as The encapsulation layer encapsulates the display device.

2. The display device according to claim 1, wherein: The second insulating layer is disposed between the active layer and the gate electrode.

3. The display device according to claim 2, wherein: The third insulating layer is disposed between the gate electrode and the source and drain electrodes.

4. The display device according to claim 3, wherein: A height from one surface of the substrate to a top surface of the third insulating layer in which the cutout is arranged is smaller than a height from the one surface of the substrate to top surfaces of the source electrode and the drain electrode.

5. The display device according to claim 3, wherein: A height from one surface of the substrate to a top surface of the third insulating layer in which the cutout is arranged is smaller than a height from the one surface of the substrate to a top surface of the passivation layer.

6. The display device according to claim 1, wherein: The encapsulation layer is separated from the cover layer.

7. The display device according to claim 1, wherein: The capping layer includes the same material as the passivation layer.

8. The display device according to claim 1, wherein: The encapsulation layer includes at least one inorganic encapsulation layer and at least one organic encapsulation layer.

9. The display device according to claim 1, wherein: The at least one cut is obtained by removing a portion of the thickness of the first insulating layer through the second insulating layer and the third insulating layer.

10. The display device according to claim 1, wherein: The capping layer is spaced apart from an edge of the substrate.

11. A method for manufacturing a display device, the display device comprising a display area and a peripheral area, the display area being arranged on a substrate and displaying an image, the peripheral area being arranged outside the display area and adjacent to an edge of the substrate, the method comprising: forming a first insulating layer on the substrate in the display area and the peripheral area; forming an active layer on the first insulating layer in the display area; forming a second insulating layer on the first insulating layer in the display area and the peripheral area; forming a gate electrode on the second insulating layer in the display area; forming a third insulating layer on the second insulating layer in the display area and the peripheral area; forming a source electrode and a drain electrode on the third insulating layer in the display area; forming at least one cutout by removing the first insulating layer, the second insulating layer, and the third insulating layer in the peripheral region along a thickness direction; forming a capping layer and a passivation layer, wherein the capping layer covers the at least one cutout in the peripheral area, and the passivation layer covers the source electrode and the drain electrode in the display area, wherein a width of the capping layer is greater than a width of the at least one cutout; forming at least one display device on the passivation layer in the display area; and An encapsulation layer encapsulating the display device is formed.

12. The method according to claim 11, in, forming the passivation layer includes forming a through hole in the passivation layer to expose a region of at least one of the source electrode and the drain electrode, and The capping layer comprises the same material as the passivation layer and is patterned at the same time as the through hole is formed.

13. The method according to claim 11, wherein: The encapsulation layer is formed to be separated from the capping layer.

14. The method according to claim 11, wherein: The encapsulation layer is formed to include at least one inorganic encapsulation layer and at least one organic encapsulation layer.

15. The method according to claim 11, wherein: The capping layer is formed to be spaced apart from an edge of the substrate.

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