Display device and method of manufacturing the same

Abstract

A display device and a method for manufacturing the same are provided. The display device includes: a base substrate; a thin-film transistor and a power supply line located on the base substrate; a first electrode located on the base substrate and electrically connected to the thin-film transistor; a light-emitting layer and a common layer located on the first electrode; and a second electrode located on the common layer. The power supply line includes: a first conductive layer; a second conductive layer located on the first conductive layer; and a third conductive layer located on the second conductive layer. The third conductive layer protrudes further from a side surface of the power supply line than the second conductive layer, and the second electrode contacts a side surface of the second conductive layer.

Description

Technical Field

[0001] Various aspects of exemplary embodiments of the present disclosure generally relate to display devices and methods of manufacturing display devices. More particularly, various aspects of exemplary embodiments of the present disclosure relate to display devices with improved display quality and methods of manufacturing the same. Background Art

[0002] Recently, with the advancement of display technology, display products with smaller size, lighter weight and excellent performance have been produced. Cathode ray tube (CRT) televisions have been widely used as display devices due to their many desirable characteristics in terms of performance and price. However, recently, display devices such as plasma display devices, liquid crystal display devices and organic light emitting diode display devices that overcome the shortcomings of CRT in terms of miniaturization and / or portability and have light weight and low power consumption have attracted attention.

[0003] An organic light-emitting diode (OLED) display device may include a first electrode serving as an anode, a second electrode serving as a cathode, and a light-emitting layer disposed between the first and second electrodes. In this case, as the OLED display device becomes larger, display quality may deteriorate due to IR drop at the second electrode.

[0004] The above information disclosed in this Background section is for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0005] One or more example embodiments of the present disclosure relate to a display device capable of preventing or reducing IR drop of a cathode to improve display quality while reducing manufacturing costs.

[0006] One or more example embodiments of the present disclosure relate to a method of manufacturing a display device.

[0007] According to one or more exemplary embodiments of the present disclosure, a display device includes: a base substrate; a thin film transistor and a power supply line located on the base substrate; a first electrode located on the base substrate and electrically connected to the thin film transistor; a light-emitting layer and a common layer located on the first electrode; and a second electrode located on the common layer. The power supply line includes: a first conductive layer; a second conductive layer located on the first conductive layer; and a third conductive layer located on the second conductive layer. The third conductive layer protrudes further from a side surface of the power supply line than the second conductive layer, and the second electrode contacts a side surface of the second conductive layer.

[0008] In some embodiments, the common layer may contact side surfaces of the second conductive layer.

[0009] In some embodiments, a first covering portion including a material that is the same as that of the common layer may be located on a third conductive layer of the power line, a second covering portion including a material that is the same as that of the second electrode may be located on the first covering portion that may be on the third conductive layer, and the second covering portion on the third conductive layer may be spaced apart from the second electrode that may be connected to a side surface of the second conductive layer.

[0010] In some embodiments, the common layer may include a hole injection layer and a hole transport layer between the first electrode and the light emitting layer, and an electron transport layer and an electron injection layer between the light emitting layer and the second electrode.

[0011] In some embodiments, the display device may further include a lower shielding electrode between the base substrate and the thin film transistor, and the lower shielding electrode and the power line may be located on the same layer.

[0012] In some embodiments, the thin film transistor may include a gate electrode, and the power supply line may be located at the same layer as that of the gate electrode.

[0013] In some embodiments, the power supply line may extend in a first direction from a display area for displaying an image to a peripheral area, the peripheral area being a non-display area adjacent to the display area.

[0014] In some embodiments, the side surface of the second conductive layer of the power line may include a first side surface and a second side surface opposite to the first side surface, and when measured along a length direction intersecting the width direction of the power line in a cross-section extending through the first side surface and the second side surface, the contact length of a portion of the second electrode in contact with the first side surface of the second conductive layer may be greater than the contact length of a portion of the second electrode in contact with the second side surface of the second conductive layer.

[0015] In some embodiments, the power line may extend in a first direction, the power line may include a contact portion protruding in a second direction crossing the first direction, and the second electrode may contact a side surface of the second conductive layer in the contact portion.

[0016] In some embodiments, the contact portion may have a semicircular shape in a plan view.

[0017] In some embodiments, the second conductive layer of the power line may include aluminum or copper.

[0018] According to one or more exemplary embodiments of the present disclosure, a display device includes: a base substrate; a first electrode located on the base substrate; a common layer located on the first electrode; a second electrode located on the common layer; and a power supply line located on the base substrate. In a cross-sectional view of the power supply line, the power supply line includes a recessed portion on a side surface of the power supply line, and the second electrode contacts the side surface of the power supply line at the recessed portion.

[0019] In some embodiments, the common layer may contact side surfaces of the power lines.

[0020] According to one or more example embodiments of the present disclosure, a method for manufacturing a display device includes: sequentially forming a first conductive layer, a second conductive layer, and a third conductive layer on a base substrate; forming a power line by patterning the third conductive layer, the second conductive layer, and the first conductive layer; forming a through-hole insulating layer on the base substrate having the power line formed thereon; forming a first electrode on the through-hole insulating layer; forming a common layer on the through-hole insulating layer having the first electrode formed thereon; and forming a second electrode on the common layer. The third conductive layer protrudes further from a side surface of the power line than the second conductive layer, and when the second electrode is formed, the second electrode contacts the side surface of the second conductive layer.

[0021] In some embodiments, the first conductive layer may include titanium, the second conductive layer may include aluminum, and the third conductive layer may include titanium, and when forming the power line, the first conductive layer, the second conductive layer, and the third conductive layer may be patterned by dry etching to form an undercut.

[0022] In some embodiments, the first conductive layer may include titanium, the second conductive layer may include aluminum, and the third conductive layer may include titanium, and when forming the first electrode, the first electrode may be patterned by wet etching, and a portion of the second conductive layer may be etched to form an undercut at the side surfaces of the third conductive layer and the second conductive layer.

[0023] In some embodiments, the first conductive layer may include titanium, the second conductive layer may include copper, and the third conductive layer may include titanium, and when forming the power line, the first conductive layer, the second conductive layer, and the third conductive layer may be patterned by wet etching to form an undercut at the side surfaces of the third conductive layer and the second conductive layer.

[0024] In some embodiments, when forming the second electrode, the second electrode may be formed by depositing a conductive material in a direction tilted at an angle with respect to a direction perpendicular to the base substrate.

[0025] In some embodiments, the common layer may contact side surfaces of the second conductive layer.

[0026] In some embodiments, the common layer may include a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, and the method may further include forming a light-emitting layer on the hole transport layer to overlap with the first electrode before forming the electron transport layer of the common layer.

[0027] A display device according to one or more example embodiments of the present disclosure may include a base substrate and a thin film transistor and a power line that may be provided on the base substrate. A first electrode may be provided on the base substrate and may be electrically connected to the thin film transistor. A light emitting layer and a common layer may be provided on the first electrode, and a second electrode may be provided on the common layer. The power line may include a first conductive layer, a second conductive layer provided on the first conductive layer, and a third conductive layer provided on the second conductive layer. The third conductive layer may protrude more than the side surface of the second conductive layer to form an undercut. The second electrode may contact (e.g., directly contact) the side surface of the second conductive layer. Therefore, in the display device, the power line that may serve as an auxiliary line may be connected to the second electrode without the need for a separate laser drilling process or a separate optical process using a mask, so that a display device that can prevent or reduce IR drop while reducing manufacturing costs and having a simplified structure can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art from the following detailed description of example embodiments with reference to the accompanying drawings.

[0029] Figure 1 is a plan view illustrating a display device according to one or more example embodiments.

[0030] Figure 2 It shows Figure 1 A cross-sectional view of a display area of a display device.

[0031] Figure 3 yes Figure 2 An enlarged view of portion “A” of the display device is shown.

[0032] Figure 4 It shows Figure 2 An enlarged view of the stacked structure of the light-emitting structure of the display device.

[0033] Figure 5 is a cross-sectional view illustrating a display region of a display device according to one or more example embodiments.

[0034] Figure 6 is a cross-sectional view illustrating a display region of a display device according to one or more example embodiments.

[0035] Figure 7 is an enlarged view illustrating a power supply line of a display device according to one or more example embodiments.

[0036] Figure 8 is a plan view illustrating power supply lines in a display area of a display device according to one or more example embodiments.

[0037] Figure 9It is along Figure 8 A cross-sectional view taken along line II' in FIG.

[0038] Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A and Figure 15B is a cross-sectional view illustrating a method of manufacturing a display device according to one or more example embodiments.

[0039] Figure 16 is a block diagram illustrating an electronic device according to one or more example embodiments.

[0040] Figure 17A It shows Figure 16 FIG. 1 is a diagram of an example in which the electronic device is implemented as a television.

[0041] Figure 17B It shows Figure 16 FIG2 is a diagram of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0042] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout. However, the present disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the various aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the various aspects and features of the present disclosure may not be described. Unless otherwise stated, similar reference numerals refer to similar elements throughout the drawings and written description, and therefore, their descriptions may not be repeated.

[0043] In the accompanying drawings, the relative sizes of elements, layers and regions may be exaggerated and / or simplified for clarity. For ease of explanation, spatial relative terms such as "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship between an element or feature and another (multiple) element or another (multiple) feature as shown in the figure. It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to also cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, the element described as being "below" or "below" or "below" other elements or features will subsequently be oriented to be "above" other elements or features. Therefore, the example terms "below" and "below" can cover both the above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0044] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, areas, layers, and / or cross-sections, these elements, components, areas, layers, and / or cross-sections should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or cross-section from another element, component, area, layer, or cross-section. Therefore, a first element, component, area, layer, or cross-section described below may be referred to as a second element, component, area, layer, or cross-section without departing from the spirit and scope of the present disclosure.

[0045] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0046] The wording used herein is for the purpose of describing specific embodiments and is not intended to be a limitation of the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, except where the context clearly indicates otherwise. It will also be understood that, when used in this specification, the terms "comprise," "comprising," "include," and "including," "has," "have," and "having" indicate the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. When a statement such as "at least one of..." follows a series of elements, it modifies the elements of the entire series and does not modify the individual elements in the series.

[0047] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "in use," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly rigid sense, unless explicitly defined as such herein.

[0049] Figure 1 is a plan view illustrating a display device according to one or more example embodiments.

[0050] Reference Figure 1 , the display device may include a display area DA and a peripheral area PA.

[0051] A plurality of pixels PX for displaying an image may be disposed in the display area DA (e.g., disposed in or on the display area DA). The pixels PX may be arranged in a matrix in a first direction D1 and in a second direction D2 that intersects the first direction D1 (e.g., perpendicular to or substantially perpendicular to the first direction D1). Each of the plurality of pixels PX may include a thin film transistor and a light emitting structure. The light emitting structure may include a first electrode electrically connected to the thin film transistor, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer.

[0052] The display device may include a plurality of scan lines SL electrically connected to the pixels PX to apply scan signals thereto and a plurality of data lines DL electrically connected to the pixels PX to apply data signals thereto.

[0053] The display device may further include a plurality of power lines VL. The power lines VL may extend in the first direction D1 and may be disposed at (eg, in or on) the display area DA. Figure 1 Only one power line VL is shown in FIG. 4 , however, a plurality of power lines VL may be arranged along the second direction D2 , and each of the plurality of power lines VL may extend in the first direction D1 , but the present disclosure is not limited thereto.

[0054] In this case, in order to drive the pixel PX, a first power voltage ELVDD, a second power voltage ELVSS, an initialization voltage VINT, etc. may be applied to the pixel PX. For example, the second power voltage ELVSS may be applied to the power line VL.

[0055] The peripheral area PA may be a non-display area where no image is displayed (e.g., in or on the non-display area), and the peripheral area PA may be adjacent to the display area DA so as to surround the display area DA (e.g., around the periphery of the display area DA). A driving circuit for driving the display device and / or an inspection circuit for inspecting the display device may be provided at the peripheral area PA (e.g., in or on the peripheral area PA). For example, the power line VL may extend in a first direction D1 from the display area DA for displaying an image to the peripheral area PA corresponding to the non-display area adjacent to the display area DA, and may be connected to a test pad formed at the peripheral area PA (e.g., in or on the peripheral area PA).

[0056] Generally, when a large organic light-emitting diode display device (e.g., such as a television) has a front-emitting structure, display quality may be degraded due to IR drop of the second electrode serving as the cathode, and in order to prevent or reduce such IR drop, an auxiliary line may be formed. In this case, a separate laser drilling process, a separate contact hole formation process using a mask, etc. may be additionally performed to electrically connect the auxiliary line to the cathode.

[0057] According to one or more example embodiments of the present disclosure, the power line VL, which can serve as an auxiliary line, can be connected to the second electrode without performing a separate laser drilling process or a separate optical process using a mask, so that a display device can be provided that can prevent or reduce IR drop while reducing manufacturing costs and has a simplified structure.

[0058] Figure 2 It shows Figure 1 a cross-sectional view of a display area of a display device, Figure 3 yes Figure 2 An enlarged view of portion "A" of the display device is shown, and Figure 4 It shows Figure 2 An enlarged view of the stacked structure of the light-emitting structure of the display device.

[0059] Reference Figures 1 to 4 The display device may include a base substrate 100, a lower shielding electrode BML, a first insulating layer 110, an active pattern ACT, a gate insulating layer 120, a gate electrode GE, an interlayer insulating layer 130, a source electrode SE, a drain electrode DE, a power line VL, a through-hole insulating layer 140, a pixel defining layer PDL, a light emitting structure 180, a common layer CL, and a thin film encapsulation layer TFE. The light emitting structure 180 may include a first electrode 181, a light emitting layer EL, and a second electrode 183.

[0060] The base substrate 100 may be formed of a transparent or opaque material. For example, the base substrate 100 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (e.g., an F-doped quartz substrate), a soda-lime glass substrate, an alkali-free glass substrate, etc. In some embodiments, the base substrate 100 may be a flexible transparent resin substrate. Examples of transparent resin substrates that can be used as the base substrate 100 include polyimide substrates.

[0061] A lower shielding electrode BML may be provided on the base substrate 100. The lower shielding electrode BML may overlap the active pattern ACT to function as a protective layer for preventing or substantially preventing degradation of the electrical characteristics of the active pattern ACT constituting the thin film transistor TFT. More specifically, the lower shielding electrode BML may minimize or reduce fluctuations in the threshold voltage of the thin film transistor TFT that may be caused by the influx of a laser beam irradiated from the lower portion of the base substrate 100 onto (e.g., into) the active pattern ACT of the thin film transistor TFT. The lower shielding electrode BML may be formed of a metal having low light transmittance.

[0062] The first insulating layer 110 may be disposed on the base substrate 100 on which the lower shielding electrode BML is disposed. For example, the first insulating layer 110 may be disposed on the base substrate 100 to cover the lower shielding electrode BML. The first insulating layer 110 may prevent or substantially prevent metal atoms and / or impurities from diffusing from the base substrate 100 into the active pattern ACT, and may control a heat transfer rate during a crystallization process for forming the active pattern ACT to obtain a uniform or substantially uniform active pattern ACT.

[0063] The active pattern ACT of the thin film transistor TFT may be disposed on the first insulating layer 110. The active pattern ACT may include amorphous silicon or polycrystalline silicon. In another embodiment, the active pattern ACT may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The active pattern ACT may include a drain region and a source region doped with impurities, and a channel region disposed between the drain region and the source region.

[0064] The gate insulating layer 120 may be disposed on the channel region of the active pattern ACT. The gate insulating layer 120 may include an inorganic insulating material, for example, such as a silicon compound and a metal oxide. The gate insulating layer 120 may include a plurality of layers.

[0065] The gate electrode GE of the thin film transistor TFT may be disposed on the gate insulating layer 120. The gate electrode GE may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like.

[0066] The interlayer insulating layer 130 may be disposed on the active pattern ACT having the gate electrode GE disposed thereon, and on the first insulating layer 110. For example, the interlayer insulating layer 130 may cover (e.g., substantially cover) the active pattern ACT and the gate electrode GE on the first insulating layer 110, and may have a flat or substantially flat top surface without creating gaps around the active pattern ACT and the gate electrode GE. In another embodiment, the interlayer insulating layer 130 may be disposed with the same or substantially the same thickness along the contours of the active pattern ACT and the gate electrode GE to cover the active pattern ACT and the gate electrode GE on the first insulating layer 110. The interlayer insulating layer 130 may include a plurality of layers.

[0067] The source electrode SE and drain electrode DE of the thin film transistor TFT and the power line VL may be disposed on the interlayer insulating layer 130. The source electrode SE may be electrically connected to the source region of the active pattern ACT via a contact hole formed through the interlayer insulating layer 130. The drain electrode DE may be electrically connected to the drain region of the active pattern ACT via a contact hole formed through the interlayer insulating layer 130. The drain electrode DE may be electrically connected to the lower shielding electrode BML via a contact hole formed through the interlayer insulating layer 130 and the first insulating layer 110.

[0068] The source electrode SE, the drain electrode DE, and the power line VL may be formed in the same layer (e.g., in the same layer or on the same layer). The power line VL may include a first conductive layer VL1, a second conductive layer VL2 disposed on the first conductive layer VL1, and a third conductive layer VL3 disposed on the second conductive layer VL2.

[0069] In this case, the third conductive layer VL3 may protrude more than the side surface of the second conductive layer VL2 to form an undercut (eg, see Figure 3 ). In other words, when measured in the width direction of the power line VL from a cross section of the power line VL, the width of the second conductive layer VL2 may be smaller than (e.g., less than) the width of the third conductive layer VL3 and the width of the first conductive layer VL1. Therefore, on the side surface of the power line VL, the third conductive layer VL3 may protrude more than the second conductive layer VL2, so that the recess RS may be formed on the side surface of the power line VL. The undercut may be formed by a process of uniformly etching and patterning the third conductive layer VL3, the second conductive layer VL2, and the first conductive layer VL1, or by a process of separately etching only the side surface of the second conductive layer VL2, and the undercut may be formed by taking into account that the second conductive layer VL2 may include a material different from those of the first conductive layer VL1 and the third conductive layer VL3.

[0070] For example, in an embodiment, the first conductive layer VL1 may include titanium, the second conductive layer VL2 may include aluminum, and the third conductive layer VL3 may include titanium. According to another embodiment, for example, the first conductive layer VL1 may include titanium, the second conductive layer VL2 may include copper, and the third conductive layer VL3 may include titanium. However, the present disclosure is not limited thereto.

[0071] The via insulating layer 140 may be disposed on the interlayer insulating layer 130 on which the source electrode SE, the drain electrode DE, and the power line VL are disposed. The via insulating layer 140 may have an opening exposing the power line VL to allow the power line VL to be electrically connected to the second electrode 183 .

[0072] The first electrode 181 may be disposed on the through-hole insulating layer 140. The first electrode 181 may be electrically connected to the thin film transistor TFT through a contact hole formed through the through-hole insulating layer 140. For example, in some embodiments, the first electrode 181 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the contact hole, but the present disclosure is not limited thereto.

[0073] Depending on the light-emitting scheme of the display device, the first electrode 181 may be formed using a reflective material or a transmissive material. For example, the first electrode 181 may include aluminum, an aluminum-containing alloy, aluminum nitride, silver, a silver-containing alloy, tungsten, tungsten nitride, copper, a copper-containing alloy, nickel, chromium, chromium nitride, molybdenum, a molybdenum-containing alloy, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. These materials may be used alone or in combination with each other. In some example embodiments, the first electrode 181 may have a single-layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive material film.

[0074] The pixel defining layer PDL may be provided on the through-hole insulating layer 140 on which the first electrode 181 is provided. The pixel defining layer PDL may be formed by using an organic material, an inorganic material, or the like. For example, the pixel defining layer PDL may be formed by using a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, a silicone compound, or the like. According to some example embodiments, the pixel defining layer PDL may be etched to form an opening partially exposing the first electrode 181. The emission area and the non-emission area of the display device may be defined by the opening of the pixel defining layer PDL. For example, the portion where the opening of the pixel defining layer PDL is located may correspond to the emission area, and the non-emission area may correspond to the portion adjacent to the opening of the pixel defining layer PDL.

[0075] The common layer CL and the light emitting layer EL may be disposed on the first electrode 181 exposed through the opening of the pixel defining layer PDL.

[0076] In some example embodiments, the common layer CL may have a multilayer structure including a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, an electron injection layer EIL, and the like. In addition to the light-emitting layer EL, the hole injection layer HIL, the hole transport layer HTL, the electron transport layer ETL, and the electron injection layer EIL may be commonly formed to correspond to a plurality of pixels. The common layer CL may contact (e.g., directly contact) the side surface of the second conductive layer VL2 of the power line VL. A first cover portion CLa including the same material as that of the common layer CL may be provided on the third conductive layer VL3.

[0077] The organic emission layer of the light-emitting layer EL can be formed by using an appropriate light-emitting material for generating light of different colors (e.g., such as red light, green light, and blue light) according to each pixel of the display device. According to other example embodiments, the organic emission layer of the light-emitting layer EL may have a structure in which a plurality of light-emitting materials for realizing light of different colors (e.g., such as red light, green light, and blue light) can be stacked on each other to emit white light. In this case, the above-mentioned light-emitting structure can be commonly formed to correspond to a plurality of pixels, and these pixels can be distinguished by a color filter layer.

[0078] The second electrode 183 may be disposed on the pixel defining layer PDL, the light-emitting layer EL, and the common layer CL. Depending on the light-emitting scheme of the display device, the second electrode 183 may include a transmissive material or a reflective material. For example, the second electrode 183 may include aluminum, an aluminum-containing alloy, aluminum nitride, silver, a silver-containing alloy, tungsten, tungsten nitride, copper, a copper-containing alloy, nickel, chromium, chromium nitride, molybdenum, a molybdenum-containing alloy, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. These materials may be used alone or in combination with each other. In some example embodiments, the second electrode 183 may have a single-layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive material film.

[0079] The second electrode 183 may contact (e.g., directly contact) the side surface of the second conductive layer VL2 of the power line VL. A second covering portion 183a including the same material as the second electrode 183 may be provided on the first covering portion CLa, which is provided on the third conductive layer VL3. The second covering portion 183a provided over the third conductive layer VL3 may be spaced apart from the second electrode 183 connected to the side surface of the second conductive layer VL2.

[0080] The thin film encapsulation layer TFE may be provided on the second electrode 183. The thin film encapsulation layer TFE may prevent or substantially prevent moisture and / or oxygen from penetrating from the outside. The thin film encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. The at least one organic layer and the at least one inorganic layer may be alternately stacked with each other. For example, the thin film encapsulation layer TFE may include a first inorganic layer, a second inorganic layer, and an organic layer provided between the first inorganic layer and the second inorganic layer, but the present disclosure is not limited thereto. In another embodiment, instead of the thin film encapsulation layer, a sealing substrate may be provided to block or substantially block external air and / or moisture from penetrating into the display device.

[0081] Generally, for contact between conductive layers, a process of forming a contact hole by drilling using a laser or forming a contact hole by using a separate mask is performed.

[0082] According to this embodiment, the power line VL can be connected to the second electrode 183 without a separate laser drilling process or a separate optical process using a mask, so that a display device capable of preventing or reducing IR drop while reducing manufacturing costs and having a simplified structure can be provided.

[0083] In more detail, when the common layer CL is formed and the second electrode 183 is formed, when the conditions of the incident angle when providing the deposition material from the end of the third conductive layer VL3 toward the side surface of the second conductive layer VL2 are appropriately adjusted, the second electrode 183 can be formed on the side surface of the second conductive layer VL2 at a position higher than that of the common layer CL, so that the second electrode 183 and the power line VL can be electrically connected to each other.

[0084] Figure 5 is a cross-sectional view illustrating a display region of a display device according to one or more example embodiments.

[0085] Except that the power supply line VL is formed in the same layer as that of the gate electrode GE (eg, formed in the same layer as that of the gate electrode GE or formed on the same layer as that of the gate electrode GE), Figure 5 The display device shown in Figures 1 to 4 The display device shown in FIG. 1 is the same or substantially the same as that shown in FIG. Therefore, a redundant description thereof may not be repeated.

[0086] Reference Figure 5 The display device may include a base substrate 100, a lower shielding electrode BML, a first insulating layer 110, an active pattern ACT, a gate insulating layer 120, a gate electrode GE, an interlayer insulating layer 130, a source electrode SE, a drain electrode DE, a power line VL, a through-hole insulating layer 140, a pixel defining layer PDL, a light emitting structure 180, a common layer CL, and a thin film encapsulation layer TFE. The light emitting structure 180 may include a first electrode 181, a light emitting layer EL, and a second electrode 183.

[0087] The interlayer insulating layer 130 and the via insulating layer 140 may have an opening exposing the power line VL to allow the power line VL to be electrically connected to the second electrode 183 .

[0088] The power line VL may include a first conductive layer VL1, a second conductive layer VL2, and a third conductive layer VL3 (eg, see Figure 3 ). The second electrode 183 may contact (eg, directly contact) a side surface of the second conductive layer VL2 of the power line VL.

[0089] Figure 6 is a cross-sectional view illustrating a display region of a display device according to one or more example embodiments.

[0090] Except that the power supply line VL is formed in the same layer as that of the lower shielding electrode BML (eg, formed in the same layer as that of the lower shielding electrode BML or formed on the same layer as that of the lower shielding electrode BML), Figure 6 The display device shown in Figures 1 to 4 The display device shown in FIG. 1 is the same or substantially the same as that shown in FIG. Therefore, a redundant description thereof may not be repeated.

[0091] Reference Figure 6 The display device may include a base substrate 100, a lower shielding electrode BML, a first insulating layer 110, an active pattern ACT, a gate insulating layer 120, a gate electrode GE, an interlayer insulating layer 130, a source electrode SE, a drain electrode DE, a power line VL, a through-hole insulating layer 140, a pixel defining layer PDL, a light emitting structure 180, a common layer CL, and a thin film encapsulation layer TFE. The light emitting structure 180 may include a first electrode 181, a light emitting layer EL, and a second electrode 183.

[0092] The first insulating layer 110 , the interlayer insulating layer 130 , and the via insulating layer 140 may have openings exposing the power line VL to allow the power line VL to be electrically connected to the second electrode 183 .

[0093] The power line VL may include a first conductive layer VL1, a second conductive layer VL2, and a third conductive layer VL3 (eg, see Figure 3 ). The second electrode 183 may contact (eg, directly contact) a side surface of the second conductive layer VL2 of the power line VL.

[0094] Figure 7 is an enlarged view illustrating a power supply line of a display device according to one or more example embodiments.

[0095] Except that the shapes of the first and second side surfaces of the second electrode 183 contacting (eg, directly contacting) the second conductive layer VL2 of the power line VL may be different, Figure 7The display device shown in Figures 1 to 4 The display device shown in FIG. 1 is the same or substantially the same as that shown in FIG. Therefore, a redundant description thereof may not be repeated.

[0096] Reference Figure 7 The display device may include a base substrate 100, a lower shielding electrode BML, a first insulating layer 110, an active pattern ACT, a gate insulating layer 120, a gate electrode GE, an interlayer insulating layer 130, a source electrode SE, a drain electrode DE, a power line VL, a through-hole insulating layer 140, a pixel defining layer PDL, a light emitting structure 180, a common layer CL, a first covering portion CLa, a second covering portion 183a, and a thin film encapsulation layer TFE (for example, see Figure 2 and Figures 4 to 7 ). The light emitting structure 180 may include a first electrode 181, a light emitting layer EL, and a second electrode 183 (eg, see Figure 2 and Figures 4 to 6 ).

[0097] The power line VL may include a first conductive layer VL1, a second conductive layer VL2, and a third conductive layer VL3. The second conductive layer VL2 of the power line VL may include a first side surface (eg, Figure 7 the right side of the second conductive layer VL2 in the middle) and the second side surface opposite to the first side surface (eg, Figure 7 The recess RS formed by the undercut may be formed at (e.g., in or on) the first and second side surfaces of the second conductive layer VL2.

[0098] When measured in a length direction intersecting the width direction of the power line VL in a cross section extending through the first and second side surfaces, a contact length W1 between the second conductive layer VL2 and the second electrode 183 on the first side surface of the second conductive layer VL2 may be greater than a contact length W2 between the second conductive layer VL2 and the second electrode 183 on the second side surface of the second conductive layer VL2. In other words, a contact length W1 of a portion of the second electrode 183 in contact with the first side surface of the second conductive layer VL2 may be greater than a contact length W2 of a portion of the second electrode 183 in contact with the second side surface of the second conductive layer VL2.

[0099] This can be achieved by forming the second electrode 183 in a direction tilted at a suitable angle (eg, a predetermined angle) relative to a direction perpendicular or substantially perpendicular to the base substrate 100 (eg, see FIG. Figure 7 This is achieved by supplying deposition material (arrow in the figure).

[0100] Therefore, a contact area for electrically connecting the second electrode 183 to the power line VL may be secured on the first side surface of the second conductive layer VL2 .

[0101] Figure 8 is a plan view illustrating power supply lines in a display area of a display device according to one or more example embodiments, and Figure 9 It is along Figure 8 A cross-sectional view taken along line II' in FIG.

[0102] In addition to the power line VL, it also includes a contact portion VLC. Figure 8 and Figure 9 The display device shown is Figures 1 to 4 The display device shown in FIG. 1 is the same or substantially the same as that shown in FIG. Therefore, a redundant description thereof may not be repeated.

[0103] The display device may include a base substrate 100, a lower shielding electrode BML, a first insulating layer 110, an active pattern ACT, a gate insulating layer 120, a gate electrode GE, an interlayer insulating layer 130, a source electrode SE, a drain electrode DE, a power line VL, a via insulating layer 140, a pixel defining layer PDL, a light emitting structure 180, a common layer CL, a first covering portion CLa, a second covering portion 183a, and a thin film encapsulation layer TFE (e.g., see Figures 2 to 7 ). The light emitting structure 180 may include a first electrode 181, a light emitting layer EL, and a second electrode 183 (eg, see Figure 2 and Figures 4 to 6 ).

[0104] The power line VL may include a first conductive layer VL1, a second conductive layer VL2, and a third conductive layer VL3 (eg, see Figures 2 to 3 and Figures 5 to 7 ).

[0105] The power line VL may extend in a first direction D1. The power line VL may include a contact portion VLC that protrudes in a second direction D2 that intersects the first direction D1 (e.g., perpendicular to or substantially perpendicular to the first direction D1). In other words, when viewed in a plane (e.g., when viewed in a plan view), the contact portion VLC may have a semicircular shape and may be formed on multiple sides (e.g., two sides or opposite sides) of the power line VL in the second direction D2 to form a circular shape as a whole. However, the present disclosure is not limited thereto, and in some embodiments, the contact portion VLC may be formed only on one side (e.g., in the second direction D2) of the power line VL to have a semicircular shape.

[0106] In the contact portion VLC, the second electrode 183 may contact (e.g., directly contact) the side surface of the second conductive layer VL2. When viewed in a plan view, the contact portion VLC may have a circular shape. Therefore, the area in which the second electrode 183 can make contact with the second conductive layer VL2 can be sufficiently ensured.

[0107] Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A and Figure 15B is a cross-sectional view illustrating a method of manufacturing a display device according to one or more example embodiments.

[0108] In summary, a method for manufacturing a display device may include: sequentially forming a first conductive layer, a second conductive layer, and a third conductive layer on a base substrate; forming a power line by patterning the third conductive layer, the second conductive layer, and the first conductive layer; forming a through-hole insulating layer on the base substrate having the power line formed thereon; forming a first electrode on the through-hole insulating layer; forming a common layer on the through-hole insulating layer having the first electrode formed thereon; and forming a second electrode on the common layer. The third conductive layer of the power line may protrude further than the side surface of the second conductive layer to form an undercut. During the formation of the second electrode, the second electrode may contact (e.g., may directly contact) the side surface of the second conductive layer.

[0109] For more details, refer to Figure 10A and Figure 10B , a lower shielding electrode BML, a first insulating layer 110 , an active pattern ACT, a gate insulating layer 120 , a gate electrode GE, and an interlayer insulating layer 130 may be formed on the base substrate 100 .

[0110] A preliminary conductive layer CON may be formed on the interlayer insulating layer 130 .

[0111] The preliminary conductive layer CON may include a first preliminary conductive layer CON1 , a second preliminary conductive layer CON2 disposed on the first preliminary conductive layer CON1 , and a third preliminary conductive layer CON3 disposed on the second preliminary conductive layer CON2 .

[0112] Reference Figure 11A and Figure 11B The preliminary conductive layer CON may be patterned to form a source electrode SE, a drain electrode DE, and a power line VL. The power line VL may include a first conductive layer VL1 formed from the first preliminary conductive layer CON1, a second conductive layer VL2 formed from the second preliminary conductive layer CON2, and a third conductive layer VL3 formed from the third preliminary conductive layer CON3.

[0113] In this case, for example, when the first conductive layer VL1 includes titanium, the second conductive layer VL2 includes aluminum, and the third conductive layer VL3 includes titanium, during formation of the power line VL, the first conductive layer VL1, the second conductive layer VL2, and the third conductive layer VL3 may be patterned by dry etching to form an undercut. Consequently, a recess RS may be formed on the side surface of the power line VL. For example, the recess RS may be formed at the side surface of the second conductive layer VL2 (e.g., formed in or on the side surface of the second conductive layer VL2) such that the width of the second conductive layer VL2 is smaller than the widths of the first conductive layer VL1 and the third conductive layer VL3.

[0114] However, the present disclosure is not limited thereto, and according to another embodiment, for example, when the first conductive layer VL1 includes titanium, the second conductive layer VL2 includes copper, and the third conductive layer VL3 includes titanium, during the formation of the power line VL, the first conductive layer VL1, the second conductive layer VL2, and the third conductive layer VL3 may be patterned by wet etching, and an undercut may be formed by selective etching of the second conductive layer VL2 to form the recess RS.

[0115] According to another embodiment, for example, when the first conductive layer VL1 includes titanium, the second conductive layer VL2 includes aluminum and the third conductive layer VL3 includes titanium, during the formation of the first electrode 181, which will be described in more detail below, the first electrode can be patterned by wet etching and an undercut can be formed by selective etching of the second conductive layer VL2.

[0116] Reference Figure 12 A through-hole insulating layer 140 having an opening exposing the power line VL may be formed on the interlayer insulating layer 130 on which the source electrode SE, the drain electrode DE, and the power line VL are formed. A first electrode 181 may be formed on the through-hole insulating layer 140. A pixel defining layer PDL may be formed on the through-hole insulating layer 140 on which the first electrode 181 is formed.

[0117] Reference Figure 13A and Figure 13B , the common layer CL and the light emitting layer EL may be formed on the through hole insulating layer 140 on which the pixel defining layer PDL is formed.

[0118] The common layer CL may be formed over the entire base substrate 100 (eg, formed over the entire base substrate 100). The common layer CL may have a multi-layer structure including a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like.

[0119] Because the common layer CL is formed over the entire base substrate 100 (e.g., formed over the entire base substrate 100), the common layer CL may be formed on the top surface of the third conductive layer VL3 of the power line VL (e.g., see the first cover portion CLa). Because an undercut is formed between the third conductive layer VL3 and the second conductive layer VL2 of the power line VL, a portion of the side surface of the second conductive layer VL2 may be exposed without being covered by the first cover portion CLa and the common layer CL (e.g., see OP).

[0120] Before forming the electron transport layer of the common layer CL, the light emitting layer EL may be formed on the hole transport layer to overlap with the first electrode 181 .

[0121] Reference Figure 14A and Figure 14B , the second electrode 183 may be formed on the common layer CL. The second electrode 183 may be formed over the entire base substrate 100 (eg, over the entire base substrate 100). In other words, in some embodiments, the second electrode 183 may be formed using an open mask.

[0122] In this case, the second electrode 183 may contact (e.g., directly contact) the side surface of the second conductive layer VL2 of the power line VL. When forming the second electrode 183, the second electrode 183 may be formed by a process having suitable step coverage (e.g., having excellent step coverage), so that the deposition material can be deposited on the undercut between the third conductive layer VL3 and the second conductive layer VL2 of the power line VL. Therefore, the second cover portion 183a may be formed on the first cover portion CLa.

[0123] For example, the second electrode 183 may be formed by using a (thermal) atomic layer deposition (ALD) process, etc. and / or a general deposition process.

[0124] Reference Figure 15A and Figure 15B A thin film encapsulation layer TFE may be formed on the second electrode 183 so that a display device can be manufactured. In some embodiments, each component of the display device may be formed by various suitable processes known to those skilled in the art.

[0125] Figure 16 is a block diagram illustrating an electronic device according to one or more example embodiments, Figure 17A It shows Figure 16 The electronic device is implemented as an example of a television, and Figure 17B It shows Figure 16 FIG2 is a diagram of an example in which the electronic device is implemented as a smart phone.

[0126] Reference Figures 16 to 17B, the electronic device 500 may include a processor 510, a memory device 520, a storage device 530, an input / output (I / O) device 540, a power supply 550, and a display device 560. Here, the display device 560 may be Figure 1 In addition, the electronic device 500 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. In an embodiment, as shown in FIG. Figure 17A As shown in , the electronic device 500 may be implemented as a television. In another embodiment, as Figure 17B , the electronic device 500 may be implemented as a smartphone. However, the present disclosure is not limited thereto, and the electronic device 500 may be implemented as any suitable device using or including the display device 560. For example, the electronic device 500 may be implemented as a cellular phone, a video phone, a smart pad, a smart watch, a tablet PC, a car navigation system, a computer monitor, a notebook computer, a head-mounted display (HMD) device, etc.

[0127] The processor 510 can perform various computing functions. The processor 510 can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 510 can be connected to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 510 can be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. The memory device 520 can store data used for the operation of the electronic device 500. For example, memory device 520 may include at least one non-volatile memory device, such as, for example, an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.; and / or at least one volatile memory device, such as, for example, a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc. Storage device 530 may include a solid-state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. I / O device 540 may include input devices, such as, for example, a keyboard, a keypad, a mouse device, a touchpad, a touch screen, etc.; and output devices, such as, for example, a printer, a speaker, etc. Power supply 550 may provide power for the operation of electronic device 500.

[0128] The display device 560 can be connected to other components via a bus and / or other communication links. In some embodiments, the I / O device 540 may include a display device 560. As described above, the display device 560 may include a base substrate, a thin film transistor and a power line disposed on the base substrate, a first electrode disposed on the base substrate and electrically connected to the thin film transistor, a light-emitting layer and a common layer disposed on the first electrode, and a second electrode disposed on the common layer. The power line may include a first conductive layer, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The third conductive layer may protrude further than the side surface of the second conductive layer to form an undercut. The second electrode may contact (e.g., directly contact) the side surface of the second conductive layer. Therefore, in the display device 560, the power line, which can serve as an auxiliary line, can be connected to the second electrode without a separate laser drilling process or a separate optical process using a mask, so that a display device with a simplified structure can be provided that can prevent or reduce IR drop while reducing manufacturing costs. Because these aspects and features of the present disclosure are described above, redundant descriptions will not be repeated.

[0129] The exemplary embodiments of the present disclosure may be applied to display devices and electronic devices including display devices. For example, one or more exemplary embodiments of the present disclosure may be applied to smartphones, cellular phones, video phones, smart pads, smart watches, tablet PCs, car navigation systems, televisions, computer monitors, notebook computers, head-mounted display devices, and the like.

[0130] The foregoing is an illustration of example embodiments and is not to be construed as limiting thereof. Although a number of example embodiments have been described, it will be readily apparent to those skilled in the art that various modifications are possible in the example embodiments without materially departing from the spirit and scope of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims and their equivalents. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and is not to be construed as being limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments and other embodiments are intended to be included within the spirit and scope of the appended claims and their equivalents.

Claims

1. A display device comprising: base substrate; Thin film transistors and power lines are both located on the base substrate; a first electrode located on the base substrate and electrically connected to the thin film transistor; The light-emitting layer and the common layer are both located on the first electrode; as well as a second electrode, located on the common layer, Wherein, the power cord includes: a first conductive layer; a second conductive layer located on the first conductive layer; and a third conductive layer, located on the second conductive layer, wherein the third conductive layer protrudes further on the side surface of the power line than the second conductive layer, and The second electrode contacts a side surface of the second conductive layer.

2. The display device according to claim 1, wherein The common layer contacts the side surface of the second conductive layer.

3. The display device according to claim 1, wherein a first covering portion including the same material as that of the common layer is located on the third conductive layer of the power line, wherein a second covering portion including the same material as that of the second electrode is located on the first covering portion, and The second covering portion on the third conductive layer is spaced apart from the second electrode connected to the side surface of the second conductive layer.

4. The display device according to claim 1, wherein The common layer includes a hole injection layer and a hole transport layer located between the first electrode and the light emitting layer, and an electron transport layer and an electron injection layer located between the light emitting layer and the second electrode.

5. The display device according to claim 1, further comprising: a lower shielding electrode, located between the base substrate and the thin film transistor, Wherein, the lower shielding electrode and the power line are located in the same layer. The display device according to claim 1 , wherein: The thin film transistor includes a gate electrode, and the power supply line is located at the same layer as that of the gate electrode.

7. The display device according to claim 1, wherein The power supply line extends in a first direction from a display area for displaying an image to a peripheral area that is a non-display area adjacent to the display area.

8. The display device according to claim 1, wherein The side surface of the second conductive layer of the power line includes a first side surface and a second side surface opposite to the first side surface, and Wherein, when measured along the length direction intersecting the width direction of the power line in a cross section extending through the first side surface and the second side surface, the contact length of a portion of the second electrode in contact with the first side surface of the second conductive layer is greater than the contact length of a portion of the second electrode in contact with the second side surface of the second conductive layer.

9. The display device according to claim 1, wherein The power line extends in a first direction, wherein the power line includes a contact portion protruding in a second direction intersecting the first direction, and The second electrode contacts the side surface of the second conductive layer in the contact portion.

10. The display device according to claim 9, wherein The contact portion has a semicircular shape in a plan view.

11. The display device according to claim 1, wherein The second conductive layer of the power line includes aluminum or copper.

12. A display device comprising: base substrate; a first electrode, located on the base substrate; a common layer, located on the first electrode; a second electrode, located on the common layer; as well as a power line, located on the base substrate, wherein, in a cross-sectional view of the power cord, the power cord includes a recessed portion at a side surface of the power cord, and The second electrode contacts the side surface of the power line at the recessed portion of the power line.

13. The display device according to claim 12, wherein: The common layer contacts the side surface of the power line.

14. A method for manufacturing a display device, the method comprising: sequentially forming a first conductive layer, a second conductive layer, and a third conductive layer on a base substrate; forming a power line by patterning the third conductive layer, the second conductive layer, and the first conductive layer; forming a through-hole insulating layer having an opening exposing the power line on the base substrate on which the power line is formed; forming a first electrode on the through-hole insulating layer; forming a common layer on the through-hole insulating layer having the first electrode formed thereon; as well as forming a second electrode on the common layer, wherein the third conductive layer protrudes further than the second conductive layer at the side surface of the power line, and When the second electrode is formed, the second electrode contacts a side surface of the second conductive layer.

15. The method according to claim 14, wherein The first conductive layer comprises titanium, the second conductive layer comprises aluminum, and the third conductive layer comprises titanium, and When forming the power line, the first conductive layer, the second conductive layer and the third conductive layer are patterned by dry etching to form an undercut.

16. The method according to claim 14, wherein The first conductive layer comprises titanium, the second conductive layer comprises aluminum, and the third conductive layer comprises titanium, and When forming the first electrode, the first electrode is patterned by wet etching, and a portion of the second conductive layer is etched to form undercuts at side surfaces of the third conductive layer and the second conductive layer.

17. The method according to claim 14, wherein: The first conductive layer comprises titanium, the second conductive layer comprises copper, and the third conductive layer comprises titanium, and When forming the power line, the first conductive layer, the second conductive layer, and the third conductive layer are patterned by wet etching to form undercuts at side surfaces of the third conductive layer and the second conductive layer.

18. The method according to claim 14, wherein When forming the second electrode, the second electrode is formed by depositing a conductive material in a direction tilted at an angle with respect to a direction perpendicular to the base substrate.

19. The method according to claim 14, wherein The common layer contacts side surfaces of the second conductive layer.

20. The method according to claim 14, wherein The common layer includes a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer, and The method further includes forming a light-emitting layer on the hole transport layer to overlap with the first electrode before forming the electron transport layer of the common layer.

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