Component carrier, method for producing the same, and method for using the component carrier

Abstract

The present invention relates to a component carrier, a method for manufacturing a component carrier, and a method for using a component carrier for high frequency applications. The component carrier (100) comprises a stack (102) comprising a plurality of electrically conductive layer structures (104) and at least one electrically insulating layer structure (106); the electrically conductive layer structure (104) comprising an electrically conductive vertical through-connector (108) and a horizontally extending electrically conductive trace (110), the horizontally extending electrically conductive trace (110) being electrically connected to an end portion (116) of the vertical through-connector (108); a back-drilled hole (112) extending through at least a portion of the at least one electrically insulating layer structure (106) toward the end portion (116); and an etched neck (114) connecting the back-drilled hole (112) to the end portion (116) of the vertical through-connector (108).

Description

Technical Field

[0001] This disclosure relates to a component carrier, a method for manufacturing the component carrier, and a method for using it. Background Art

[0002] With the increasing functionality of products equipped with component carriers containing one or more electronic components, the gradual miniaturization of these electronic components, and the growing number of electronic components to be mounted on component carriers such as printed circuit boards, increasingly robust array-shaped components or packages with multiple electronic components and multiple contacts or connections with increasingly smaller spacing between them are being adopted. During operation, heat removal generated by these electronic components and the component carrier itself becomes an increasingly serious problem. Simultaneously, the component carrier must possess mechanical strength and electrical reliability to operate even under harsh conditions.

[0003] Furthermore, when high-frequency signals propagate along the wiring structure of the component carrier, parasitic effects (such as insertion loss and distortion) may occur. This can significantly reduce the overall performance of the mobile communication system. Summary of the Invention

[0004] The purpose of this invention is to provide a component carrier with high performance in signal transmission.

[0005] To achieve the above objectives, a component carrier according to the independent claims, a method for manufacturing the component carrier, and a method of using the component carrier are provided.

[0006] According to an exemplary embodiment of the present invention, a component carrier is provided, wherein the component carrier includes: a stacked member comprising a plurality of electrically conductive layer structures and at least one electrically insulating layer structure, wherein the electrically conductive layer structure includes an electrically conductive vertical through-connector and a horizontally extending electrically conductive trace, the horizontally extending electrically conductive trace being electrically connected to an end portion of the vertical through-connector; a back-drilled hole extending toward the end portion through at least a portion of the at least one electrically insulating layer structure; and an etched neck connecting the back-drilled hole to the end portion of the vertical through-connector.

[0007] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein the method includes providing a stack comprising a plurality of electrically conductive layer structures and at least one electrically insulating layer structure; forming an electrically conductive layer structure having an electrically conductive vertical through-connector and a horizontally extending electrically conductive trace, the electrically conductive trace being electrically connected to the vertical through-connector; drilling a back-drilled hole through at least a portion of the at least one electrically insulating layer structure and into the vertical through-connector; and etching an etch neck between the back-drilled hole and an end portion of the vertical through-connector.

[0008] According to another exemplary embodiment of the present invention, the electrically conductive wiring structure of the component carrier having the above-described features is used for high-frequency applications, particularly for conducting radio frequency (RF) signals, especially for conducting RF signals with frequencies higher than 1 GHz.

[0009] According to another exemplary embodiment of the present invention, a component carrier is provided, wherein the component carrier includes a stack, the stack including a plurality of electrically conductive layer structures and at least one electrically insulating layer structure; wherein the electrically conductive layer structure includes an electrically conductive vertical through-connector and a horizontally extending electrically conductive trace, the horizontally extending electrically conductive trace being electrically connected to an end portion of the vertical through-connector; a back-drilled hole extending toward the end portion through at least a portion of the at least one electrically insulating layer structure; and a test structure including at least one horizontally extending electrically conductive virtual trace located at the vertical height of the back-drilled hole and connected to the back-drilled hole, and / or the electrically conductive virtual trace located at the vertical height of an optional etched neck and connected to an optional etched neck, the optional etched neck connecting the back-drilled hole to the end portion of the vertical through-connector.

[0010] In the context of this application, the term "component carrier" can specifically refer to any support structure capable of accommodating one or more components on and / or within the support structure for providing mechanical support and / or electrical connection. In other words, a component carrier can be configured as a mechanical and / or electronic carrier for a component. Specifically, a component carrier can be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier can also be a hybrid board combining different component carriers of the types described above.

[0011] In the context of this application, the term "layer structure" may specifically refer to a continuous layer, a patterned layer, or a plurality of discontinuous islands in the same plane.

[0012] In the context of this application, the term "high-frequency application" may specifically refer to a task performed by or contributed to by a component carrier, wherein the task may relate to the processing of radio frequency signals. Such radio signals or high-frequency signals can be electrical or electromagnetic signals propagating along a wiring structure (which may include traces and vertical through-connectors) in a frequency range used for communication or other signals. In particular, radio frequency (RF) signals may, for example, have frequencies in the range between 3 kHz and 300 GHz.

[0013] In the context of this application, the term "vertical through-connector" may specifically refer to an electrically conductive structure extending along the stacking direction of the layered structure of a component carrier. Such a component carrier may be a flat body, and the vertical through-connector may extend along the thinnest direction of such component carrier. For example, such a vertical through-connector may be a plated via. The corresponding through-hole may be formed, for example, by mechanical drilling or by laser drilling.

[0014] In the context of this application, the term "horizontally extending electrical conductive trace" may specifically refer to an electrical conductive structure extending in a horizontal plane perpendicular to a vertical through-connector or in a stacked sequence of layers of a component carrier. For example, at least one electrical conductive trace may be electrically connected within a component carrier to carry current or electrical signals in a horizontal plane, particularly high-frequency signals. To form such a horizontal trace, a metal layer (e.g., a copper sheet) forming part of the stack may be patterned.

[0015] In the context of this application, the term "back-drilled hole" can specifically refer to a hole drilled in a stack of component carriers and extending from the main surface of the component carrier (e.g., the rear main surface) into the interior of the stack. Specifically, a back-drilled hole can be formed by drilling, particularly by mechanically drilling through a portion of the stack. The back-drilled hole can extend from the outer main surface of the component carrier to the end or end portion of a vertically penetrating connector. It has been shown that the formation of such a back-drilled hole can improve the performance of the component carrier, particularly in handling high-frequency signals, such as radio frequency signals, because the formation of the back-drilled hole can reduce the length of the parasitic piling portion extending vertically beyond the vertical connection position of the vertically penetrating connector and the horizontal trace.

[0016] In the context of this application, the term "etched neck" may specifically refer to a laterally narrowed portion or extension of a back-drilled hole, which has a smaller diameter (particularly a smaller maximum diameter) in the horizontal plane compared to the back-drilled hole. Specifically, the etched neck may be formed and sized to be formed by etching or by etching. Descriptively, a partially narrowed etched neck may provide a vertical extension of the back-drilled hole that partially or wholly bridges the space between the end portion of the back-drilled hole and the vertical position of at least one electrically conductive trace.

[0017] According to an exemplary embodiment of the present invention, a component carrier can be provided that exhibits excellent characteristics in processing high-frequency signals. According to the exemplary embodiment, this can be achieved not only by forming a back-drilled hole in a stack of component carriers with improved high-frequency characteristics, but also by further extending the drilled back-drilled hole through a locally narrowed portion. The locally narrowed portion can be suitably formed by etching, which can extend the length of the hole extending into the stack to further reduce the length of the parasitic piling portion of the conductive material at the junction between the vertical through-connector and the horizontal conductive trace. Conventionally, such a piling portion can remain quite long in the stack because the back-drilled hole may not extend vertically completely upwards into the trace to ensure the maintenance of the electrical connection between the conductive trace and the vertical through-connector. Since it is difficult to precisely define the length of the back-drilled hole during drilling, corresponding errors should generally be considered, which may result in a relatively long residual piling portion. However, because the etching process can be appropriately controlled, a precisely controlled etching process performed after drilling the back hole can reduce the length of the piling portion by forming a locally narrowed extension of the back hole. This can further reduce the length of the piling portion, which can significantly improve high-frequency characteristics. Simultaneously, due to the high precision and controllability of the etching process used to form the etch neck, undesirable disconnection of the traces from the vertical through-connector caused by excessively long back holes can be safely prevented. Described as such, by forming a locally narrowed etch neck, the length of the copper-filled blind hole that extends vertically beyond the target end of the vertical through-connector due to parasitic effects can be shortened or even eliminated. Advantageously, this can be achieved without the risk of unintentionally separating the electrically conductive structure of the connection between the vertical through-connector and the horizontal trace-like connection. Thus, high electrical reliability can be combined with excellent high-frequency characteristics of the component carrier. Simultaneously, one or more back holes can be created for the HF (high-frequency) board without burrs inside the holes. Removing any residual burrs after the drilling process is another characteristic advantage of the etching process implemented for forming the etch neck. Similarly, the additional etching process mentioned above can prevent unwanted inner layer connections that might conventionally result from excessively short back drill holes. In this process, the additional etching creates an etch neck and helps to separate the unwanted inner layer connections.

[0018] According to another exemplary embodiment of the invention, a component carrier having an integrally formed test structure can be provided. When a back-drilled hole is correctly formed, the dummy trace connected to the back-drilled hole will not receive electrical signals applied to the electrically conductive traces or the vertical through-connector (or applied in the opposite direction) because the back-drilled hole disconnects the corresponding electrical path. Accordingly, when an etched neck is correctly formed, the dummy trace connected to the etched neck will not receive electrical signals applied to the electrically conductive traces or the vertical through-connector (or applied in the opposite direction) because the etched neck disconnects the corresponding electrical path. However, applying a test signal to the trace connected to the vertical through-connector or between traces (e.g., at the top and bottom sides) should allow the detection of a response signal when the connection between the vertical through-connector and the trace is properly established. Therefore, the described test structure allows for reliable testing of the function of the back-drilled hole (and, in the presence of an etched neck, reliably testing the connected etched neck) by performing a non-destructive testing process using the described hardware test structure.

[0019] Other exemplary embodiments of the component carrier and method will be explained below.

[0020] A key aspect of exemplary embodiments is back-drilling to remove unused portions (also known as pilings) of copper cylindrical sections from plated through-holes in printed circuit boards (PCBs) or other types of component carriers. Highly advantageously, an additional etching process can be performed after the drilling process for removing such unused portions. High-speed signals can be distorted as they travel through paths between layers. If the use of signal layers causes pilings, and the pilings are too long, the distortion becomes significant. Furthermore, drill burrs are typically generated within the holes due to the inability to control burrs, which can potentially impact performance. On the other hand, tolerances for deep drilling must be considered, so the remaining pilings may still have a considerable length after drilling. To avoid such problems, exemplary embodiments of the invention add an etching process (e.g., alkaline etching, acid etching, or dry etching step) after back-drilling to partially or completely remove burrs and additionally reduce the remaining piling length without damaging the functional portion of the hole. Advantageously, according to the exemplary embodiment, uncontrolled burrs can be prevented from forming in the back drill hole. Additionally, reducing the length of the remaining pile portion ensures more stable and repeatable performance of the HF feature.

[0021] In this embodiment, the vertical through-hole is a plated via. Therefore, a vertical through-hole can be formed by drilling via mechanical processing, laser drilling, or even etching, followed by at least partially filling the formed via with an electrically conductive filling medium, such as copper, by electroplating. For example, plating may include the formation of a seed layer lining that forms, for example, the generally cylindrical sidewalls of the resulting hole. This seed layer can be formed, for example, by chemical deposition or sputtering. Optionally, at least one additional plating process, such as electroplating, can then be performed after this process. Electroplating allows a large amount of electrically conductive filling medium to be filled into the hole.

[0022] In one embodiment, the component carrier includes a disc or pad that electrically connects the conductive trace to the vertical through-connector. Described as such, this disc or pad can balance the tolerances between the conductive trace and the vertical through-connector. If, for example, such a tolerance results in an insufficient match between the relative positions of the vertical through-connector and the conductive trace, the physical contact establishing the electrical connection between the trace and the vertical through-connector may be absent or only partially present. However, this tolerance can be compensated for by providing a disc as a horizontally extending pad portion connected to the vertical through-connector of the conductive trace. For example, such a disc may be a circular, rectangular, or annular conductive sheet portion connected to both the trace and the vertical through-connector.

[0023] In one embodiment, the vertical through-connector includes an electrically conductive peg between the etched neck and the electrically conductive trace. Such a peg can be a short electrically conductive extension of the vertical through-connector that protrudes beyond the vertical horizontal portion of the trace. This parasitic peg constitutes a loss mechanism for high-frequency signals that propagate along the trace and the vertical through-connector and partially into the blind hole formed by the peg. Therefore, this peg is a parasitic effect, and the peg degrades the RF performance of the component carrier; thus, the peg should be kept as short as possible. According to an exemplary embodiment of the invention, forming the etched neck to allow the back-drilled hole to extend at a precisely controllable size can reduce the size of the remaining peg to a small value. Preferably, the vertical length of the peg remaining after etching the etched neck may not exceed 0.2 mm, particularly not more than 0.1 mm. Descriptively, the etched neck may etch away a portion of the peg. This can significantly improve the RF characteristics of the component carrier.

[0024] In another embodiment, the component carrier has no conductive peg between the etched neck and the conductive trace. In such a preferred embodiment, the extension of the etched neck is so long that there is no neck residue in the manufactured component carrier. This can be achieved by controlling the length of the etched neck so that the length of the etched neck corresponds to the distance between the end portion of the back drill hole and the vertical position of the conductive trace.

[0025] In this embodiment, the end portion of the vertical through-connector is burr-free. In the context of this application, the term "burr" can specifically refer to a raised edge or small piece of electrically conductive material that remains attached to the end of the vertical through-connector after the drilling process used to form a back-drilled hole. Such burrs are undesirable material elements for high-frequency application to component carriers and can be partially or completely removed by an etching process that forms an etch neck, thereby deburring the vertical through-connector. It has been shown that deburring the vertical through-connector after etching the subsequent formation of the back-drilled hole can significantly reduce signal loss and improve signal quality for RF tasks.

[0026] In this embodiment, the back-drilled hole includes a cylindrical portion. The back-drilled hole can be formed, for example, by laser drilling or mechanical drilling. In both manufacturing processes, a generally cylindrical extension of the back-drilled hole can be obtained. In the case of mechanical drilling, this may be a result of the shape of the drill bit's rotation axis.

[0027] In an embodiment, the back-drilled hole includes a tapered or truncated tapered portion between the cylindrical portion and the etched neck. When formed by mechanical drilling, the aforementioned cylindrical portion can be connected to a truncated tapered or even tapered end portion obtained from a tapered end portion of a drill bit used to form the back-drilled hole. However, even when the truncated tapered end portion has a tapered geometry, the narrowest portion of the blind hole formed in the stack can be defined by the etched neck.

[0028] In implementations, the etched neck has one of a cylindrical shape and a truncated conical shape. Since the neck is preferably formed by etching, its shape is also defined by the etching process. In the case of a substantially anisotropic etching process, the sidewalls of the etched neck can be generally vertical, and the shape of the etched neck can be generally cylindrical. However, when the etching process involves some anisotropic contribution, the etching may not be able to proceed completely in the vertical direction, and thus the sidewalls of the etched neck may taper slightly.

[0029] In this embodiment, the diameter of the etched neck (particularly the maximum diameter) is smaller than the diameter of the back-drilled hole (particularly the minimum diameter). Therefore, even the maximum diameter of the etched neck can be smaller than the minimum diameter of the back-drilled hole. For example, a stack can be formed at the vertical joint between the back-drilled hole and the etched neck.

[0030] Specifically, the hole formed in the main surface of the stacked component by back-drilling and etching the neck may include an outer cylindrical portion having a first diameter, followed by a directly connected truncated tapered extension that in turn connects to an inner cylindrical portion having a second diameter smaller than the first diameter. For example, Figure 3 This geometry is shown in the image.

[0031] In one embodiment, the vertical through-connector is constructed as either a cylindrical electrically conductive structure or a hollow cylindrical electrically conductive structure. For example, the sidewalls of the blind hole formed only in the stacked member for creating the vertical through-connector may be covered with an electrically conductive material such as copper. In such an embodiment, the interior of the vertical through-connector may remain hollow. In another embodiment, the entire blind hole formed for creating the vertical through-connector may be completely filled with an electrically conductive filling medium such as copper.

[0032] In this embodiment, the component carrier is configured for high-frequency applications. Specifically, the component carrier may include at least one electronic component, particularly at least one radio frequency (RF) semiconductor chip configured to transmit and / or receive RF signals, mounted on and / or embedded in the stack, and electrically connected to conductive traces and vertical through-connectors.

[0033] In this implementation, the method includes etching the etch neck by wet etching. Wet etching has proven to be a simple and well-defined process, allowing for precise definition of the etch neck size by adjusting etching parameters. Therefore, wet etching is a highly preferred method for forming the etch neck because it ensures both reliable improvement in the high-frequency characteristics of the component carrier and reliable electrical connection between the trace and the vertical through-connector.

[0034] In this embodiment, the method includes etching the etch neck using alkaline etching, acidic etching, or the like. Therefore, etching with either acidic or alkaline etchants can be a method to form a etch neck with a suitable height through wet etching. Wet etching can be performed using both acids and alkalis; both methods can be referred to as wet etching (wet alkaline or wet acidic etching).

[0035] In another embodiment, the method includes etching the etch neck by dry etching. Specifically, the method may include etching the etch neck by plasma etching. As an alternative to wet etching, a dry etching process can also be used to form the etch neck to keep the impact on the stack minimal. In particular, plasma etching, i.e., treating the stack with plasma to form the etch neck, is ideally suited for defining the etch neck to improve RF performance while ensuring appropriate electrical reliability of the resulting component carrier. Dry etching can be performed using plasma. Other possible dry etching methods include reactive ion etching (RIE) or laser ablation.

[0036] In one implementation, the method includes cleaning the back-drilled hole by rinsing, for example, high-pressure rinsing. Cleaning the back-drilled hole by rinsing, particularly before forming the etched neck, can improve the high-frequency performance of the resulting component carrier. This can further reduce burrs at the piling portion and thus can cooperate synergistically with the etching of the neck.

[0037] In one embodiment, the component carrier includes a test structure comprising at least one horizontally extending electrical conductive virtual trace, which is located at and connected to the vertical height of the back drill hole, and / or connected to the horizontal plane of the etched neck. Specifically, the test structure can be configured such that an electrical test signal is applied to one of the electrical conductive trace and the at least one horizontally extending electrical conductive virtual trace, and a response signal is detected at the other of the electrical conductive trace and the at least one horizontally extending electrical conductive virtual trace to indicate the function of the back drill hole and / or the etched neck. Correspondingly, the method may include applying an electrical test signal to one of an electrically conductive trace and at least one horizontally extending electrically conductive virtual trace, the at least one horizontally extending electrically conductive virtual trace being positioned at the vertical height of the back drill hole and / or etch neck and connected to the back drill hole and / or etch neck; detecting a response signal at the other of the electrically conductive trace and at least one horizontally extending electrically conductive virtual trace; and determining information indicative of the function of the back drill hole and / or etch neck based on the detected response signal. Described in writing, when a back drill hole is correctly formed, the virtual trace connected to the back drill hole will not receive an electrical signal applied to the electrically conductive trace or the vertical through-connector (or applied in the opposite direction) because the back drill hole disconnects the corresponding electrical path. Correspondingly, when an etch neck is correctly formed, the virtual trace connected to the etch neck will not receive an electrical signal applied to the electrically conductive trace or the vertical through-connector (or applied in the opposite direction) because the etch neck disconnects the corresponding electrical path. However, applying a test signal to a trace connected by a vertical through-connector (e.g., at the top or bottom side) or between traces should allow for detection of the response signal when the connection between the vertical through-connector and the trace is properly established. Therefore, the described embodiment allows for reliable testing of the functionality of back-drilled holes and connected etched necks using a non-destructive testing process performed with the described hardware test structure.

[0038] In one embodiment, the stack includes a central electrical insulating layer structure that is covered on its two opposite main surfaces by a corresponding electrically conductive layer structure of at least one of at least one electrically conductive layer structure. For example, the stack may be a core. Such a core may have a central dielectric layer that may comprise a resin, optionally including reinforcing particles such as glass fiber. For example, the central dielectric layer may be a prepreg layer. The central dielectric layer may be covered on its two opposite main surfaces by corresponding copper foils, etc.

[0039] In one embodiment, the stack includes at least one through-hole, which is at least partially filled with an electrically conductive filler medium (e.g., copper plating) for electrically connecting opposite main surfaces of the stack. For example, the through-hole can be formed by laser processing or by mechanical drilling. The filler medium can be copper, which can be inserted into the through-hole, for example, by chemical deposition and / or plating. Such plated through-holes provide a short vertical connection path between the two opposite main surfaces of the component carrier, thus suppressing signal loss.

[0040] In this implementation, the component carrier is used for 5G (or higher, such as 6G). Mobile wireless communication according to the 5G standard involves high-frequency transmission with a high amount of data transmitted per unit time, and therefore requires good performance in terms of high-frequency behavior. The component carrier according to an exemplary embodiment of the invention meets these demanding requirements. Fifth-generation (5G) networks have higher mobile data rates, particularly significantly higher than 100 Mb / s. When the component carrier according to an exemplary embodiment of the invention is implemented, fifth-generation communication networks can experience excellent network transmission fidelity.

[0041] In this embodiment, the component carrier is used for high-frequency applications above 1 GHz, particularly around 100 GHz. Especially at such high frequencies, signal transmission is particularly sensitive to the parasitic effects caused by the pile shape. The high RF performance of the component carrier according to an exemplary embodiment of the invention allows for low-loss signal transmission even at such high frequency values.

[0042] In embodiments, the component carrier includes a stack comprising at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the aforementioned electrically insulating and electrically conductive layer structures, specifically formed by applying mechanical pressure and / or thermal energy. The aforementioned stack can provide a plate-like component carrier capable of providing a large mounting surface for other components while remaining very thin and compact. The term "layer structure" may specifically refer to a continuous layer, a patterned layer, or multiple discontinuous island-like elements within a common plane.

[0043] In this implementation, the component carrier is shaped as a plate. This contributes to a compact design, whereby the component carrier still provides a large base for mounting components on the component carrier. Furthermore, in particular, bare wafers, as examples of embedded electronic components, can be conveniently embedded in thin plates such as printed circuit boards due to their small thickness.

[0044] In one embodiment, the component carrier is constructed as one of a printed circuit board, a substrate (especially an IC substrate), and an interposer.

[0045] In the context of this application, the term "printed circuit board" (PCB) can specifically refer to a sheet-like component carrier formed by laminating multiple electrically conductive layer structures with multiple electrically insulating layer structures, for example, by applying pressure and / or supplying heat. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fiber, so-called prepreg, or FR4 material. The electrically conductive layer structures can be connected to each other in a desired manner by forming through-holes through the laminate, for example, by laser drilling or mechanical drilling, and by filling the through-holes with an electrically conductive material (particularly copper) to form vias serving as through-hole connections. In addition to one or more components that can be embedded in the PCB, the PCB is generally configured to accommodate one or more components on one or both opposite surfaces of the sheet-like PCB. The one or more components can be soldered to the respective main surfaces. The dielectric portion of the PCB may include resin with reinforcing fibers (such as glass fiber).

[0046] In the context of this application, the term "substrate" can specifically refer to a small component carrier. A substrate can be a relatively small component carrier, on which one or more components can be mounted, and which can serve as a connection medium between one or more chips and another PCB. For example, a substrate can have approximately the same dimensions as the components (particularly electronic components) to be mounted on it (e.g., in the case of chip-scale packages (CSP)). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks and a component carrier with a considerably higher density of lateral and / or vertically arranged connections, comparable to a printed circuit board (PCB). Lateral connections are, for example, conductive channels, while vertical connections can be, for example, drilled holes. These lateral and / or vertical connections are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodating or non-accommodating components (such as bare wafers)—particularly IC chips—and the printed circuit board or intermediate printed circuit board. Therefore, the term "substrate" also includes "IC substrate." The dielectric portion of the substrate may include a resin with reinforcing particles (such as reinforcing spheres, particularly glass spheres).

[0047] The substrate or interlayer may include or be composed of the following: at least one layer of glass, silicon (Si), photo-imageable or dry-etchable organic material such as epoxy-based laminated material (e.g., epoxy-based laminated film), or polymer compound such as polyimide, polybenzoxazole or benzocyclobutene-functionalized polymer.

[0048] In embodiments, at least one electrically insulating layer structure comprises at least one of the following: resin (e.g., reinforced or unreinforced resins, such as epoxy resins or bismaleimide-triazine resins), cyanate esters, polyphenylene derivatives, glass (particularly glass fiber, multilayer glass, glassy materials), prepreg materials (e.g., FR-4 or FR-5), polyimide, polyamide, liquid crystal polymer (LCP), epoxy-based laminated films, polytetrafluoroethylene (PTFE, Teflon), ceramics, and metal oxides. Reinforcing structures made of glass (multilayer glass), such as meshes, fibers, or spheres, may also be used. While prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials, particularly epoxy-based laminated films or photoemissive dielectric materials, may also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate ester resins, low-temperature co-fired ceramics (LTCC), or other low, very low, or ultra-low DK materials can be implemented as electrically insulating layer structures in component carriers.

[0049] In an embodiment, at least one of the electrically conductive layer structures comprises at least one of copper, aluminum, nickel, silver, gold, palladium, and tungsten. While copper is generally preferred, other materials or other types of coatings thereof are also possible, particularly coatings with superconducting materials such as graphene.

[0050] At least one component, optionally surface-mounted in and / or embedded in the stack, may be selected from non-conductive inlays, conductive inlays (e.g., metallic inlays, preferably copper or aluminum), heat transfer units (e.g., heat pipes), light guiding elements (e.g., optical waveguides or optical conductor connectors), optical elements (e.g., lenses), electronic components, or combinations thereof. For example, the component may be an active electronic component, a passive electronic component, an electronic chip, a storage device (e.g., DRAM or other data memory), a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a light-emitting diode, an optocoupler, a voltage converter (e.g., a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or receiver, an electromechanical converter, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may also be embedded in a component carrier. For example, a magnetic element may be used as a component. Such magnetic components can be permanent magnetic components (such as ferromagnetic, antiferromagnetic, multiferroic, or ferrimagnetic components, e.g., ferrite cores) or paramagnetic components. However, the component can also be, for example, a substrate in a plate-in-plate configuration, an interlayer, or other component carrier. The component can be surface-mounted on the component carrier and / or embedded within the component carrier. Furthermore, other components can be used as components, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment.

[0051] In one embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a multilayered compound that is stacked and connected together by applying pressure and / or heat.

[0052] After the internal layer structure of the component carrier has been treated, one or more additional electrically insulating and / or electrically conductive layer structures can be used to symmetrically or asymmetrically cover (particularly by lamination) one of the main surfaces of the treated layer structure or two opposite main surfaces. In other words, the layers can be continuously stacked until the desired number of layers is achieved.

[0053] After the stack of electrical insulation layer structure and electrical conductivity layer structure is formed, the surface treatment of the obtained layer structure or component carrier can be carried out.

[0054] Specifically, in terms of surface treatment, an electrically insulating solder resist can be applied to one or both opposing main surfaces of the laminate or component carrier. For example, the solder resist can be formed over the entire main surface and the resist layer can then be patterned to expose one or more electrically conductive surface portions that will be used to electrically couple the component carrier to electronic peripherals. The solder resist-covered surfaces of the component carrier, particularly those containing copper, can be effectively protected from oxidation or corrosion.

[0055] Regarding surface treatment, surface trimmings can also be selectively applied to exposed electrically conductive surface portions of component carriers. Such surface trimmings can be electrically conductive covering materials on exposed electrically conductive covering structures (such as pads, conductive traces, etc., particularly including or made of copper) on the surface of the component carrier. Without protecting such exposed electrically conductive layer structures, the exposed electrically conductive component carrier material (especially copper) may oxidize, resulting in lower reliability of the component carrier. The surface trimmings can then be formed as, for example, a joint between a surface-mounted component and the component carrier. The surface trimmings function to protect the exposed electrically conductive layer structures (especially copper circuitry) and, for example, to achieve a bonding process with one or more components via soldering. Examples of suitable materials for surface trimmings are organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), gold (especially hard gold), electroless tin, nickel-gold, nickel-palladium, electroless nickel-palladium immersion gold (ENIPIG), etc.

[0056] The above-defined aspects and other aspects of the invention will become apparent from the examples of embodiments described below, and will be illustrated with reference to these examples of embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figures 1 to 3 The following describes the manufacturing process in accordance with an exemplary embodiment of the invention. Figure 3 A three-dimensional view of the structure obtained during the method of supporting the component shown.

[0058] Figure 4 A flowchart illustrating a method for manufacturing a component carrier according to an exemplary embodiment of the present invention is shown.

[0059] Figure 5 A component carrier without any pile-shaped portion is shown according to another exemplary embodiment of the present invention.

[0060] Figure 6 A component carrier according to yet another exemplary embodiment of the present invention is shown, the component carrier including a test structure for non-destructive testing of the integrity of the component carrier.

[0061] Figure 7 A component carrier according to yet another exemplary embodiment of the present invention is shown, the component carrier including a test structure for performing electrical tests to test the integrity of the component carrier.

[0062] The illustrations in the accompanying drawings are schematic. In different drawings, similar or identical elements have the same reference numerals. Detailed Implementation

[0063] Before referring to the accompanying drawings, exemplary embodiments will be described in more detail, summarizing some basic considerations that have led to the development of exemplary embodiments of the present invention.

[0064] According to an exemplary embodiment of the present invention, back-drilled holes can be created for HF boards (high-frequency boards) without burrs inside the holes. This can be achieved by forming a neck-shaped extension of the back-drilled hole, particularly by etching.

[0065] The pile portion can significantly impact the high-frequency performance of the component's load-bearing parts. To reduce the pile portion length and improve performance, back-drilling the remaining pile portion is advantageous. However, uncontrolled copper burrs can occur within the hole due to the (particularly mechanical) back-drilling process, which can have additional undesirable effects on performance. According to an exemplary embodiment of the invention, the etched neck is formed to extend the back-drilled hole to reduce the length of the pile portion, preferably to zero.

[0066] Back-drilling is a technique for removing unused portions (so-called pilings) from plated through-holes in component carriers such as printed circuit boards (PCBs). High-speed signals can be distorted as they travel through paths between layers. This distortion can become significant if the use of signal layers creates pilings that are too long. In conventional processes, drill burrs can appear inside the hole, which can impact performance because these burrs cannot be properly controlled. On the other hand, the remaining pilings may be longer on one side due to the need to consider tolerances in depth drilling. To avoid this problem, exemplary embodiments of the present invention additionally create etched necks, which can be formed by, for example, an alkaline etching process. Such an additional etching process can be performed as a separate stage after mechanical back-drilling. Highly advantageously, this can partially or completely remove burrs, further reduce the remaining piling length, and safely prevent undesirable damage to the functional parts of the hole itself.

[0067] Additionally, high-pressure flushing can be used to clean the back drilled hole, which can also reduce burrs. However, for optimal results, this cleaning process can be combined with or replaced by the etching process used to form the etch neck. In particular, exemplary embodiments of the invention allow for the removal of at least a majority of the piling portion and burrs. Therefore, the presence of highly undesirable, uncontrolled excessive burrs in the back drilled hole can be safely prevented. Furthermore, the length of the remaining piling portion can be reduced, resulting in a more stable and repeatable HF feature.

[0068] An exemplary application of an exemplary embodiment of the present invention is a component carrier with high-frequency applications, wherein back drilling is advantageous, the back drill hole can be flushed, and the length of the pile portion can be reduced and burrs removed by forming an etched neck.

[0069] For example, a component carrier according to an exemplary embodiment of the present invention can be operated using a signal with a frequency of at least 20 GHz. In particular, interference typically occurs in laser vias in this frequency domain.

[0070] According to an exemplary embodiment of the present invention, burr-free back drilling of HF boards can be achieved. Driven by a steady increase in bandwidth requirements and the amount of data that must be processed, the transmission channel within the PCB can be improved or even optimized according to an exemplary embodiment of the present invention.

[0071] Specifically, three key parameters of the component carrier can be considered to reduce insertion loss. These parameters relate to the use of materials (preferably low-k materials), copper loss (through the use of low-processed foil), and via structure. Via structure can have a significant negative impact on the insertion loss profile, especially if the via extends significantly beyond the layers that need to be electrically connected. Back-drilling is a technique for removing unused portions (perhaps represented as pilings) of copper cylindrical sections from plated through-holes in PCBs or other component carriers. High-speed signals can be distorted as they travel through paths between layers. If the use of signal layers creates pilings, and these pilings are too long, the distortion becomes significant.

[0072] In view of the foregoing, an exemplary embodiment of the present invention provides a manufacturing method that allows (partial or preferably complete) removal of burrs within the plated through-hole of a back drill.

[0073] In existing processes, drilling burrs can form inside the hole, which can adversely affect performance because these burrs cannot be properly controlled. Furthermore, due to the need to account for depth drilling tolerances, residual pile portion may be present on the longer side. Cross-sections of conventional component carriers show undesirable inner layer connections and significant drilling burrs.

[0074] According to an exemplary embodiment of the invention, an etching process (particularly alkaline) can be performed to at least reduce the aforementioned disadvantages. To avoid these and / or other problems, an etching step (e.g., alkaline) can be performed after back drilling to partially or completely remove burrs and at least additionally reduce the remaining post length without damaging the functional portion of the hole itself.

[0075] The process flow for an exemplary embodiment of the present invention, which utilizes an additional alkaline etching process to perform the back drilling, can be as follows: After the final pressing cycle forming the stack, mechanical drilling can be performed, followed by copper processing. Subsequently, optical processing (potentially involving lamination, exposure, and development) and tin plating deposition processes can be performed. The back drilling can then be completed. An alkaline etching process can then be performed to form the etched neck. Afterward, the component carrier can continue to be manufactured in a conventional manner.

[0076] Figures 1 to 3 The manufacturing process according to an exemplary embodiment of the present invention is illustrated. Figure 3 A three-dimensional view of the structure obtained during the method of the component carrier 100 shown.

[0077] Reference Figure 1 The diagram illustrates a laminated stack 102 comprising an electrically conductive layer structure 104 and an electrically insulating layer structure 106. For example, the electrically conductive layer structure 104 may include patterned copper foil and vertical through-connectors, such as copper-filled laser vias. The electrically insulating layer structure 106 may include a resin (e.g., epoxy resin), and optionally include reinforcing particles (e.g., glass fibers or glass beads). For example, the electrically insulating layer structure 106 may be made of prepreg or FR4. The layers 104 and 106 may be joined by lamination, i.e., by applying pressure and / or heat.

[0078] As shown, the conductive layer structure 104 includes a vertically extending conductive connector 108 and a horizontally extending conductive trace 110, the conductive trace 110 being electrically connected to the vertically extending connector 108 at different vertical heights. Furthermore, pads 118 are disposed at different vertical heights, and the pads 118 are electrically connected to a corresponding trace of the vertically extending connector 108 and the trace 110. Therefore, Figure 1The diagram illustrates a laterally stacked arrangement of the various portions of the vertical through-connector 108 traversed by a disc or pad 118. Corresponding traces 110 are connected to the corresponding portions of the vertical through-connector 108 via allocated discs or pads 118. Figure 3 In the readily manufactured component carrier 100 shown, electrical signals (particularly high-frequency signals, preferably having a frequency of 20 GHz or higher) should be conducted between the two electrical conduction traces 110 via a vertical through-connector 108 between the two electrical conduction traces 110. According to... Figure 1 Below the lower trace 110, on the bottom side of the vertical through connector 108, a parasitic portion of the vertical through connector 108 is shown, which has a vertical extension H. If Figure 1 The structure shown is used to transmit high-frequency signals, and the parasitic portion will significantly reduce signal quality due to the creation of a parasitic propagation path indicated by reference numeral 138 in the figure.

[0079] Reference Figure 2 The back-drilled hole 112 can penetrate a portion of the electrically insulating layer structure 106 from the back side of the stacked member 102 toward the end portion 116 of the vertically penetrating connector 108, and can also remove a portion of the material (particularly copper) of the vertically penetrating connector 108. Thus, the length of the parasitic portion of the vertically penetrating connector 108 can be reduced to the length h of the remaining metal peg-shaped portion 120, where H > h. This back-drilling can improve the high-frequency performance of the currently manufactured component carrier 100. For example, the back-drilled hole 112 can be mechanically drilled using a rotary drill bit having a generally cylindrical shaft and a tapered or truncated tapered tip (not shown). If the back-drilled hole 112 is formed by mechanical drilling, it can have the shape shown, i.e., having a large cylindrical portion 122 and a smaller vertically tapered or truncated tapered extension 124. Forming a back-drilled hole 112 extending from the back side of the stacked member 102 to the aforementioned through-hole pile portion 120 can improve the high-frequency performance of the component carrier 100 to be manufactured, because... Figure 1 In comparison, the vertical extension h of the remaining peg portion 120 can be significantly reduced. However, as indicated by reference numeral 132, mechanically drilling the back drill hole 112 may produce undesirable copper burrs at the junction between the remaining peg portion 120 and the back drill hole 112. Both the burrs 132 and the remaining peg portion 120 of length h may degrade RF performance because they may interfere with signal propagation along the desired path between the traces 110 connected by the vertical through connector 108.

[0080] Subsequently, optionally, the back drill hole 112 can be cleaned using high-pressure flushing. This may have already had a positive impact on the high-frequency characteristics.

[0081] Reference Figure 3 An etch neck 114 is formed between the back drill hole 112 and the end portion 116 of the vertical through connector 108 by an additional etching process performed after back drilling (and optionally after rinsing). More specifically, the etch neck 114 can be formed by wet etching, for example by alkaline etching.

[0082] As shown in the figure, the hole formed in the stack 102 by back drilling and neck etching may include an outer cylindrical portion 122 having a first diameter D, followed by a directly connected truncated tapered extension 124, which in turn is directly connected to an inner cylindrical portion, which takes the form of an etched neck 114 having a second diameter d, which is smaller than the first diameter D, i.e., d < D.

[0083] Optionally, component 126 (e.g., a high-frequency semiconductor chip) may be embedded in stack 102 and may be electrically connected to trace 110 and vertical through connector 108. For example, component 126 with embedded RF component carrier 100 may be used for wireless communication according to 5G (or higher, such as 6G).

[0084] As a result of this manufacturing method, one can obtain Figure 3 The component carrier 100 shown is a component carrier 100. The component carrier 100 includes a stack 102 consisting of an electrically conductive layer structure 104 and an electrically insulating layer structure 106. As shown, the electrically conductive layer structure 104 includes an electrically conductive vertical through-connector 108 and a horizontally extending electrically conductive trace 110, one of which is electrically connected to an end portion 116 of the vertical through-connector 108. A back-drilled hole 112 extends through a portion of the stack 102. An etched neck 114 is formed to connect the back-drilled hole 112 to the end portion 116 of the vertical through-connector 108. The vertical through-connector 108 is a plated via. The vertical through-connector 108 can be constructed as a cylindrical electrically conductive structure or as a hollow cylindrical electrically conductive structure, the hollow cylindrical electrically conductive structure preferably being made of copper. The disc or pad 118 electrically connects the conductive trace 110 to the vertical through connector 108.

[0085] Furthermore, the vertical through-connector 108 includes a shortened conductive post 120 now located between the etched neck 114 and the lower disc or pad 118. The shortened post 120 is a result of forming the etched neck 114. Additionally, the etched neck 114 is formed by partially or completely removing the burrs 132, see reference. Figure 3Reference numeral 134 in the accompanying drawings. Given this configuration, the component carrier 100 is ideally suited for high-frequency applications with signal frequencies above 1 GHz. (See attached figure 134.) Figure 3 As indicated by reference numeral 136 in the accompanying drawings, the high-frequency signal propagating along the vertical through connector 108 between traces 110 can now be conducted, essentially unaffected by reference. Figure 1 and Figure 2 The interference described by parasitic effects.

[0086] according to Figure 3 The component carrier 100 can be obtained by first flushing the back drill hole 112, and then performing an alkaline etching process starting from the lower side of the stack 102, thereby forming a narrow upward extension of the back drill hole 112 in the form of an etched neck 114. The advantages of this component carrier are twofold: firstly, Figure 2 The burr 132 shown can be removed, as... Figure 3 The figure is schematically indicated by reference numeral 134. Furthermore, the vertical dimension of the remaining pile portion 120 can optionally be further reduced to a value b < h. Therefore, the RF performance of the component carrier 100 is very good because it substantially prevents RF signals from undesirably propagating to undesirable portions of the component carrier 100. Thus, the RF signal essentially travels along... Figure 3 The intended propagation path 136 is schematically indicated in the diagram. Therefore, it is possible to prevent propagation such as... Figure 1 The figure below, denoted by reference numeral 138, schematically indicates an unwanted signal path. In description, Figure 1 The parasitic part of medium length H and Figure 2 A pile-shaped section of medium length h may act as a parasitic antenna, and therefore could significantly interfere with the signal. Figure 3 In the embodiment shown, the remaining length b of the pile portion 120 can be, for example, less than 0.2 mm, particularly less than 0.1 mm. When the etching process is controlled in a corresponding manner, the remaining length b can even be substantially zero (e.g., with...). Figure 5 (in comparison)

[0087] although Figure 3 Not shown, but at least a portion of the back drilled hole 112, which optionally includes at least a portion of the etched neck 114, can also be filled with a plug preferably made of an electrically insulating plugging material. This prevents undesirable material from entering the interior of the component carrier 100.

[0088] Figure 4 A flowchart of a method for manufacturing a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0089] As shown by reference numeral 200, the stack 102 of the layer structures 104, 106 may have undergone a final pressing cycle. As shown by reference numeral 202, a mechanical drilling process can then be performed. As shown by reference numeral 204, a copper deposition process can then be performed to form the vertical through connector 108. This can be followed by an optical process, see reference numeral 210, which may involve lamination, exposure, and development. Subsequently, an electroplated tin deposition process can be performed, see reference numeral 212. As shown by box 214, a back-drilling process can then be performed to form the back-drilled hole 112 by mechanical drilling. Subsequently, an alkaline etching process (see box 216) can be performed to form the etched neck 114. The fabrication of the component carrier can then proceed in a conventional manner according to box 218.

[0090] Figure 5 A component carrier 100 without any pile-shaped portion is shown according to another exemplary embodiment of the invention. As indicated by reference numeral 140, the lower portion of the back-drilled hole 112 may have vertical sidewalls. The upper portion of the back-drilled hole 112 may have inwardly tapering inclined sidewall portions, see reference numeral 142. This creates a truncated conical extension 124 of the back-drilled hole 112. The etched neck 114 may have vertical sidewalls, see reference numeral 144. However, when the etching process is not ideally anisotropic, the sidewalls of the etched neck 114 may also taper inward, see reference numeral 146. Accordingly, when the back-drilled hole 112 is not formed by mechanical drilling, but rather, for example, by laser drilling, the back-drilled hole may also have inclined sidewalls, see reference numeral 148. In the case where the back-drilled hole 112 is formed by laser drilling, it is also possible that the back-drilled hole 112 has an overall truncated conical shape.

[0091] Figure 6 A component carrier 100 according to another exemplary embodiment of the present invention is shown, the component carrier 100 including a test structure 150 for non-destructive testing of the integrity of the component carrier 100.

[0092] In the illustrated embodiment, the test structure 150 has two horizontally extending electrical conduction virtual traces 130. The lower virtual trace 130 is positioned at the vertical height of the back drill hole 112 and connected to the back drill hole 112. The other upper virtual trace 130 is positioned at the vertical height of the etched neck 114 and connected to the etched neck 114. Furthermore, the test structure 150 is configured to apply an electrical test signal to one of the electrical conduction traces 110 and to detect the response signal at the corresponding virtual trace 130. The measured response signal indicates the function of the back drill hole 112 and the etched neck 114. Information indicating the function of the back drill hole 112 and / or the etched neck 114 can then be determined based on the detected response signal. For example, if the back drill hole 112 is properly formed, no signal will be detected at the virtual trace 130 connected to the back drill hole 112. If the etched neck 114 is properly formed, no signal will be detected at the virtual trace 130 connected to the etched neck 114.

[0093] therefore, Figure 6 The PCB component carrier 100, which has high-frequency capability, can undergo functional testing. As shown, in addition to the functional trace 110, multiple test traces or dummy traces 130 can be provided at different vertical heights of the stack 102, including at the back drill hole 112, in the embodiment shown above. Performing electrical tests using the test traces 130 or dummy traces ensures the correct formation of the back drill hole 112 or the correct formation of the etched neck 114 without damaging the component carrier 100. In the illustrated embodiment, test signals may not be transmitted between the lower test trace or dummy trace 130 and the functional trace 110, as the lower test trace or dummy trace 130 terminates at the back drill hole 112, thus the aforementioned electrical test path cannot be used. Accordingly, since the upper test or dummy trace 130 terminates at the etched neck 114, and because the etched neck 114 is properly formed and thereby disables the described electrical test path, the test signal may not be transmitted between the upper test trace or dummy trace 130 and the functional trace 110. Therefore, a reference can be used... Figure 6 The described test structure 150 tests the correct formation of the back drill hole 112 and the etched neck 114 in a non-destructive manner, and in particular tests the height of the back drill hole 112 and the etched neck 114.

[0094] Figure 7 A component carrier 100 including a test structure 150 is shown according to another exemplary embodiment of the present invention, the test structure 150 being used to perform electrical tests to test the integrity of the component carrier 100.

[0095] Also refer to Figure 6In a similar embodiment, the test structure 150 shown allows testing whether a proper electrical connection has been established between the reference drilled structure 230 with the back drill hole 112 and the forced connection structure 200. The component carrier 100 can be considered to be functioning correctly only if current flows along trace 110. Furthermore, the test structure 150 shown allows testing whether an electrical connection is missing between the non-connection-permitted structure 220 and the reference drilled structure 230. The component carrier 100 can only be considered to be functioning correctly if no current flows along the first dummy trace 130a. Furthermore, current should not flow along the second dummy trace 130b between the reference drilled structure 230 and the target layer structure 210. Therefore, according to... Figure 7 The component carrier 100 allows for the provision of electrical test references for the rear / deep borehole structure.

[0096] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude multiple. Moreover, elements described in association with different embodiments can be combined.

[0097] It should also be noted that the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0098] The implementation of this invention is not limited to the preferred embodiments shown in the accompanying drawings and described above. Instead, it is possible to use the illustrated solutions and various modifications according to the principles of the invention, even in fundamentally different implementations.

Claims

1. A component carrier (100), wherein: The component carrier (100) comprises: A stack (102) comprising a plurality of electrically conductive layer structures (104) and at least one electrically insulating layer structure (106); wherein the electrically conductive layer structure (104) comprises an electrically conductive vertical through-connector (108) and a horizontally extending electrically conductive trace (110), wherein the horizontally extending electrically conductive trace (110) is electrically connected at an end portion (116) of the vertical through-connector (108); a back-drilled hole (112) extending through at least a portion of the at least one electrically insulating layer structure (106) toward the end portion (116); and an etched neck (114) connecting the back-drilled hole (112) with the end portion (116) of the vertical through-connector (108), The vertical through-connector (108) includes an electrically conductive stud-shaped portion (120) located between the etched neck (114) and the electrically conductive trace (110), wherein the stud-shaped portion (120) protrudes beyond a vertical horizontal portion of the electrically conductive trace (110).

2. The component carrier (100) according to claim 1, wherein: The vertical length (b) of the pile-shaped portion (120) is no greater than 0.2 mm.

3. The component carrier (100) according to claim 1, wherein: The vertical length (b) of the pile-shaped portion (120) is no greater than 0.1 mm.

4. The component carrier (100) according to any one of claims 1 to 3, wherein: The component carrier (100) includes at least one component (126) surface mounted on the component carrier (100).

5. A method for manufacturing a component carrier (100), wherein: The method comprises: Providing a stack (102) comprising a plurality of electrically conductive layer structures (104) and at least one electrically insulating layer structure (106); forming an electrically conductive layer structure (104) having an electrically conductive vertical through-connector (108) and a horizontally extending electrically conductive trace (110), the electrically conductive trace (110) being electrically coupled at an end portion (116) of the vertical through-connector (108); Drilling a back-drilled hole (112) through at least a portion of the at least one electrically insulating layer structure (106) and into the vertical through-connector (108); and etching an etched neck (114) between the back-drilled hole (112) and the end portion (116) of the vertical through-connector (108), The vertical through-connector (108) includes an electrically conductive stub portion (120) located between the etched neck (114) and the electrically conductive trace (110), the stub portion (120) protruding beyond a vertical horizontal portion of the electrically conductive trace.

6. The method according to claim 5, wherein: The method includes etching the etch neck (114) by wet etching.

7. The method according to claim 6, wherein: The method includes etching the etched neck (114) by alkaline etching or by acid etching.

8. The method according to claim 5, wherein: The method includes etching the etch neck (114) by dry etching.

9. The method according to claim 6, wherein: The method includes etching the etch neck (114) by plasma etching.

10. The method according to any one of claims 6 to 9, wherein: The method includes cleaning the back-drilled hole (112) by flushing.

11. The method according to claim 10, wherein: The method includes cleaning the back-drilled hole (112) by high pressure flushing.

12. The method according to any one of claims 6 to 9, wherein: The method includes mechanically drilling the back-drilled hole (112).

13. The method according to any one of claims 6 to 9, wherein: The method comprises: applying an electrical test signal to one of at least one horizontally extending electrically conductive dummy trace (130) and the electrically conductive trace (110), the at least one horizontally extending electrically conductive dummy trace (130) being disposed at a vertical height of the back-drilled hole (112) and connected to the back-drilled hole (112), and / or the at least one horizontally extending electrically conductive dummy trace (130) being disposed at a vertical height of the etched neck (114) and connected to the etched neck (114); detecting a response signal at the other of the at least one horizontally extending electrically conductive imaginary trace (130) and the electrically conductive trace (110); and Information indicative of the functionality of the backdrilled via (112) and / or the etched neck (114) is determined based on the detected response signal.

14. A method of using a component carrier (100) according to any one of claims 1 to 4 for high-frequency applications.

15. The method according to claim 14, comprising at least one of the following features: in, The component carrier (100) is used for wireless communication; The component carrier (100) is used for high-frequency applications above 1 GHz.

16. The method according to claim 14, wherein the component carrier (100) is used for wireless communication according to 5G.

17. The method according to claim 14, wherein the component carrier (100) is used for high frequency applications above 100 GHz.

18. A component carrier (100), wherein: The component carrier (100) comprises: A stack (102) comprising a plurality of electrically conductive layer structures (104) and at least one electrically insulating layer structure (106); wherein the electrically conductive layer structure (104) comprises an electrically conductive vertical through-connector (108) and a horizontally extending electrically conductive trace (110), wherein the horizontally extending electrically conductive trace (110) is electrically connected at an end portion (116) of the vertical through-connector (108); a back-drilled hole (112) extending through at least a portion of the at least one electrically insulating layer structure (106) toward the end portion (116); and A test structure (150) comprising at least one horizontally extending electrically conductive dummy trace (130) located at the vertical height of the back-drilled via (112) and connected to the back-drilled via (112) and / or located at the vertical height of an optional etched neck (114) and connected to the etched neck (114) connecting the back-drilled via (112) with the end portion (116) of the vertical through-connector (108), wherein the vertical through-connector (108) comprises an electrically conductive stub (120) located between the etched neck (114) and the electrically conductive trace (110), the stub (120) protruding beyond the vertical level of the electrically conductive trace (110).

19. The component carrier (100) according to claim 18, wherein: The test structure (150) is configured such that an electrical test signal is applied to one of the at least one electrically conductive dummy trace (130) and the electrically conductive trace (110) and a response signal is detected at the other of the at least one electrically conductive dummy trace (130) and the electrically conductive trace (110) to indicate functionality of the backdrilled via (112) and / or the etched neck (114).

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