Code generation method and device, electronic device and storage medium

Abstract

The present disclosure relates to a code generation method and device, an electronic device and a storage medium, the method comprising: obtaining an initial code; parsing the initial code to obtain an initial abstract representation of the initial code; optimizing the initial abstract representation to obtain a target abstract representation; and obtaining a target code corresponding to the initial code according to the target abstract representation. Through the above process, the existing code can be utilized, and the target abstract representation can be obtained by converting it into the form of an initial abstract representation and improving the initial abstract representation. The target code generated according to the target abstract representation not only utilizes the characteristics of the existing initial code, but also has better performance. Therefore, the code generation method proposed in the embodiment of the present disclosure can automatically realize code optimization, thereby effectively saving human resources and time resources, and is conducive to improving the performance of the generated code.

Description

Technical Field

[0001] The present disclosure relates to the technical field of machine learning, and in particular to a code generation method and device, an electronic device, and a storage medium. Background Art

[0002] As the number of backend devices and deep learning operations increases rapidly, we need more and more manpower to write code on each backend device to implement deep learning operations. There are many common acceleration techniques for efficient code, but these acceleration techniques are difficult to migrate, so often repeated work must be done for each code to apply these acceleration techniques to specific scenarios, resulting in a waste of manpower and time resources. Summary of the invention

[0003] The present disclosure proposes a code generation technology solution.

[0004] According to one aspect of the present disclosure, there is provided a code generation method, comprising:

[0005] Acquire an initial code; parse the initial code to obtain an initial abstract representation of the initial code; optimize the initial abstract representation to obtain a target abstract representation; and obtain a target code corresponding to the initial code according to the target abstract representation.

[0006] In a possible implementation, the optimizing the initial abstract representation to obtain the target abstract representation includes optimizing at least one of a loop structure and a loop parameter in the initial abstract representation to obtain the target abstract representation.

[0007] In one possible implementation, the optimizing at least one of the loop structure and loop parameters in the initial abstract representation to obtain a target abstract representation includes: optimizing the initial abstract representation based on multiple candidate optimization combinations to obtain multiple candidate abstract representations, wherein each candidate optimization combination includes a candidate loop structure and candidate loop parameters; converting the multiple candidate abstract representations into multiple test codes; and determining a target abstract representation from the multiple candidate abstract representations based on the test performance of the multiple test codes.

[0008] In a possible implementation manner, the initial abstract representation includes an initial syntax tree, and the target abstract representation includes a target syntax tree.

[0009] In one possible implementation, the optimizing the initial abstract representation to obtain a target abstract representation includes: obtaining a first sub-syntax tree of the initial syntax tree, wherein the root node of the first sub-syntax tree is a first loop node in the initial syntax tree; optimizing at least one of the loop structure and loop parameters of the first sub-syntax tree to obtain a second sub-syntax tree; and obtaining a target syntax tree based on the second sub-syntax tree.

[0010] In one possible implementation, the optimizing at least one of the loop structure and loop parameters of the first sub-syntax tree to obtain the second sub-syntax tree includes: adjusting the loop structure of the first sub-syntax tree to obtain a candidate loop structure; obtaining candidate loop parameters of the first sub-syntax tree based on the current loop parameters of the first sub-syntax tree and the candidate loop structure; obtaining candidate sub-syntax trees of the first sub-syntax tree based on the candidate loop structure and the candidate loop parameters; and determining the second sub-syntax tree from the candidate sub-syntax trees and the first sub-syntax tree based on the test performance of the test codes corresponding to the candidate sub-syntax trees and the first sub-syntax tree.

[0011] In a possible implementation, obtaining a target syntax tree based on the second sub-syntax tree includes: selecting a third sub-syntax tree from an updated syntax tree including the second sub-syntax tree for a next round of iterative optimization until a cutoff condition for iterative optimization is met, thereby obtaining the target syntax tree.

[0012] According to one aspect of the present disclosure, there is provided a code generation device, comprising:

[0013] An acquisition module is used to acquire an initial code; a parsing module is used to parse the initial code to obtain an initial abstract representation of the initial code; an optimization module is used to optimize the initial abstract representation to obtain a target abstract representation; and a conversion module is used to obtain a target code corresponding to the initial code based on the target abstract representation.

[0014] In a possible implementation, the optimization module is used to optimize at least one of a loop structure and a loop parameter in the initial abstract representation to obtain a target abstract representation.

[0015] In one possible implementation, the optimization module is further used to: optimize the initial abstract representation based on multiple candidate optimization combinations to obtain multiple candidate abstract representations, wherein each candidate optimization combination includes a candidate loop structure and candidate loop parameters; convert the multiple candidate abstract representations into multiple test codes; and determine a target abstract representation from the multiple candidate abstract representations based on the test performance of the multiple test codes.

[0016] In a possible implementation manner, the initial abstract representation includes an initial syntax tree, and the target abstract representation includes a target syntax tree.

[0017] In one possible implementation, the optimization module is used to: obtain a first sub-grammar tree of the initial grammar tree, wherein the root node of the first sub-grammar tree is a first loop node in the initial grammar tree; optimize at least one of the loop structure and loop parameters of the first sub-grammar tree to obtain a second sub-grammar tree; and obtain a target grammar tree based on the second sub-grammar tree.

[0018] In one possible implementation, the optimization module is further used to: adjust the loop structure of the first sub-syntax tree to obtain a candidate loop structure; obtain candidate loop parameters of the first sub-syntax tree based on the current loop parameters of the first sub-syntax tree and the candidate loop structure; obtain candidate sub-syntax trees of the first sub-syntax tree based on the candidate loop structure and the candidate loop parameters; and determine the second sub-syntax tree from the candidate sub-syntax trees and the first sub-syntax tree based on the test performance of the test code corresponding to the candidate sub-syntax tree and the first sub-syntax tree.

[0019] In a possible implementation, the optimization module is further used to: select a third sub-syntax tree from the updated syntax tree including the second sub-syntax tree for the next round of iterative optimization until a cutoff condition of the iterative optimization is met to obtain the target syntax tree.

[0020] According to one aspect of the present disclosure, there is provided an electronic device, including:

[0021] processor;

[0022] a memory for storing processor-executable instructions;

[0023] Wherein, the processor is configured to: execute the above-mentioned code generation method.

[0024] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above-mentioned code generation method is implemented.

[0025] In the embodiment of the present disclosure, the initial code is obtained, and the corresponding initial abstract representation is generated according to the initial code, and the initial abstract representation is optimized to obtain the target abstract representation, and then the corresponding target code is obtained according to the target abstract representation. Through the above process, the existing code can be used to convert it into the form of the initial abstract representation, and the initial abstract representation is improved to obtain the target abstract representation. The target code generated according to the target abstract representation not only utilizes the characteristics of the existing initial code, but also has better performance. Therefore, the code generation method proposed in the embodiment of the present disclosure can automatically realize the optimization of the code, thereby effectively saving human resources and time resources, and is conducive to improving the performance of the generated code.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0028] Figure 1 A flowchart of a code generation method according to an embodiment of the present disclosure is shown.

[0029] Figure 2 A schematic diagram showing generating a corresponding first syntax tree according to an initial code according to an embodiment of the present disclosure is shown.

[0030] Figure 3 A schematic diagram showing an application example according to the present disclosure.

[0031] Figure 4 A schematic diagram showing an application example according to the present disclosure.

[0032] Figure 5 A block diagram of a code generating device according to an embodiment of the present disclosure is shown.

[0033] Figure 6 A block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0034] Figure 7 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0036] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0037] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0038] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0039] Figure 1 A flowchart of a code generation method according to an embodiment of the present disclosure is shown, and the method can be applied to a code generation device, and the code generation device can be a terminal device, a server or other processing device, etc. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc.

[0040] In some possible implementations, the code generation method can be implemented by a processor calling computer-readable instructions stored in a memory. In one example, the processor can be a general-purpose processor such as a central processing unit (CPU), a graphics processing unit (GPU), etc., or an artificial intelligence processor such as an artificial intelligence (AI) chip.

[0041] like Figure 1As shown, the code generation method may include:

[0042] Step S11, obtaining an initial code.

[0043] Step S12, parsing the initial code to obtain an initial abstract representation of the initial code.

[0044] Step S13, optimizing the initial abstract representation to obtain the target abstract representation.

[0045] Step S14, obtaining the target code corresponding to the initial code according to the target abstract representation.

[0046] In the above disclosed embodiments, the initial code may be an existing code that can be compiled in a processor to instruct the processor to work. The implementation of the initial code is not limited. In one possible implementation, the initial code may be a code written by a relevant person; in one possible implementation, the initial code may be a code generated by a device that automatically generates certain codes; in one possible implementation, the initial code may also be a code that can be used in other devices, copied to the current device, and so on.

[0047] The abstract representation of the code can be a machine-readable form of the code, and its specific implementation form can be flexibly determined according to the actual situation of the machine. For example, it can be a readable form of hardware devices such as a syntax tree, a computational graph, or an assembly language (such as the assembly code of the underlying virtual machine (LLVM, Low Level Virtual Machine)). In a possible implementation, when the abstract representation is in the form of a syntax tree, the initial abstract representation may include an initial syntax tree, and the target abstract representation may include a target syntax tree.

[0048] By expressing the initial abstract representation as an initial syntax tree and the target abstract representation as a target syntax tree, the hardware device can optimize the code according to the abstract representation of the code, thereby realizing an automatic optimization process of the code.

[0049] In the embodiment of the present disclosure, an initial code is obtained, a corresponding initial abstract representation is generated according to the initial code, and the initial abstract representation is optimized to obtain a target abstract representation, and then the corresponding target code is obtained according to the target abstract representation. Through the above process, the existing code can be utilized, and the initial abstract representation can be improved according to the actual functional requirements of the code by converting it into the form of an initial abstract representation to obtain a target abstract representation. The target code generated according to the target abstract representation not only utilizes the characteristics of the existing code, but also has better performance. Since the abstract representation is a machine-readable form of expression, the code generation method proposed in the embodiment of the present disclosure can be automatically implemented by a machine, thereby improving the automation degree and generation effect of code generation, and effectively saving human resources and time resources.

[0050] The above disclosed embodiments have proposed that the implementation of the initial code is not limited, so accordingly, the method of obtaining the initial code in step S11 is also not limited, and can be flexibly determined according to the implementation form of the initial code. In a possible implementation, when the initial code is a code written by a relevant person, the method of obtaining the initial code can be to read the written initial code; in a possible implementation, when the initial code is an automatically generated code, the method of obtaining the initial code can be to receive the automatically generated initial code; in a possible implementation, when the initial code is a code for other devices, the method of obtaining the initial code can be to copy and paste the initial code into the current code generation device.

[0051] After the initial code is obtained, the initial abstract representation of the initial code can be obtained according to the initial code through step S12. The implementation method of step S12 is not limited and can be flexibly determined according to the implementation form of the abstract representation. In a possible implementation method, when the abstract representation is in the form of a syntax tree, the structure of the initial code can be analyzed by identifying keywords in the initial code, such as function names, variable names, and expressions, so as to construct an abstract representation of the initial code, that is, generate an initial syntax tree corresponding to the complete structure of the initial code.

[0052] However, for a complete and executable code, converting its entire structure into a syntax tree may have strong expressive power, but it may store a lot of complex information. When optimizing the initial syntax tree, this complex information may reduce the adjustment efficiency. Therefore, in a possible implementation, only the content that can be further adjusted or optimized in the initial code can be identified to generate the corresponding initial syntax tree.

[0053] Specifically, for a piece of code, the running performance may depend on the implementation of the loop in the code, so the initial syntax tree may be generated by identifying the loop code in the initial code. Therefore, in a possible implementation, step S12 may include:

[0054] Step S121, identifying at least one loop code included in the initial code.

[0055] Step S122: According to the correspondence between the code and the syntax tree, each loop code segment is converted into a corresponding loop sub-syntax tree.

[0056] Step S123: Generate relevant nodes corresponding to the loop sub-syntax tree according to other codes except the loop code included in the initial code.

[0057] Step S124: Connect the loop sub-syntax tree and the related nodes according to the initial code to generate an initial syntax tree.

[0058] In the above disclosed embodiments, the loop code may be a loop statement in the code, such as a for statement, a while statement, or a do while statement, etc. For the initial code, it may include multiple loop codes. Therefore, when generating an initial syntax tree according to the initial code, the loop code included in the initial code can be identified through step S121. When the initial code only includes one loop code, this loop code can be identified through step S121. When the initial code includes multiple loop codes, each loop code can be identified separately through step S121. It is also possible to identify part of the multiple loop codes or a certain loop code that needs to be adjusted through step S121 according to actual needs. Which loop codes are specifically identified can be flexibly determined according to actual conditions, and are not limited in the disclosed embodiments.

[0059] After the loop code is identified, each loop code segment can be converted into a corresponding loop sub-syntax tree according to the correspondence between the code and the syntax tree through step S122, wherein the correspondence between the code and the syntax tree can be determined according to the generation rule of the syntax tree, which is not limited here.

[0060] Specifically, how to convert the loop code into the corresponding loop sub-syntax tree can be flexibly determined according to the actual situation of the loop code. In a possible implementation, converting the loop code into the corresponding loop sub-syntax tree may include:

[0061] Get the loop code including the loop condition and loop content.

[0062] Convert loop conditions to loop condition nodes and loop contents to loop contents nodes.

[0063] The loop condition node and the loop content node are connected in sequence to obtain the loop sub-syntax tree corresponding to the loop code.

[0064] It can be seen from the above disclosed embodiments that when the loop code is converted, the corresponding loop sub-syntax tree can be generated according to the loop condition and loop content included in the loop code. Wherein, the loop condition can be the condition for the loop code to enter the loop or jump out of the loop, and the loop content is the operation that needs to be performed indicated by the code under the loop condition. For example, when the loop code is a for statement, that is, for (i) {func (j)}, it can be represented in the case of for (i), the function func (j) is executed, and the loop condition of the loop code at this time is for (i), and the loop content is func (j). Therefore, in an example, for the above loop code, the loop condition for (i) can be converted into a loop condition node, the loop content func (j) can be converted into a loop content node, and the output of the loop condition node is pointed to the input of the loop content node, thereby indicating that the operation of func (j) is executed when the loop condition is for (i).

[0065] It should be noted that, for a loop code, the loop content executed under the loop condition may include multiple steps. For example, for func(j), it may include a combination of multiple steps such as assignment or calculation in sequence. In a possible implementation, these steps can be disassembled according to needs and converted into multiple loop content nodes. In a possible implementation, these steps can also be summarized by a function such as func(j), so that the loop content is converted into only one loop content node. When the loop content is converted into one loop content node, the simplicity and conversion efficiency of the first syntax tree can be improved, thereby improving the efficiency of code generation.

[0066] The loop condition and loop content included in the loop code are decomposed into loop condition nodes and loop content nodes respectively, and then connected to obtain the loop sub-syntax tree corresponding to the loop code. Through the above process, the loop content can be more conveniently converted into the corresponding loop sub-syntax tree, which improves the conversion efficiency and also expresses the tree structure of the loop code more clearly, thereby improving the convenience and efficiency of generating subsequent target codes.

[0067] After converting each loop code included in the initial code into a corresponding loop sub-syntax tree, step S123 can be used to convert other codes included in the initial code except the loop code into relevant nodes corresponding to the loop sub-syntax tree. For example, in addition to the loop statement, the initial code can also include some assignment statements or calculation statements that are not in the loop, or loop statements that do not need to be adjusted. There may be complex running orders and calculation relationships between these statements, but they do not affect the operation of the loop code that needs to be adjusted. Therefore, according to the execution order of these statements in the initial code, these statements can be simplified into input or output nodes of the loop sub-syntax tree, and through step S124, these input or output nodes are connected to the corresponding loop sub-syntax tree in the execution order. When there are multiple loop sub-syntax trees, since these related nodes can have a connection relationship with multiple loop sub-syntax trees, these loop sub-syntax trees can be naturally connected during connection to generate an initial syntax tree including multiple loop sub-syntax trees.

[0068] Figure 2 A schematic diagram of generating a corresponding initial syntax tree based on an initial code according to an embodiment of the present disclosure is shown. It can be seen from the figure that in an example, multiple loop codes included in the initial code can be converted into the form of loop condition nodes + loop content nodes, and connected in the nested order of the loops. For the non-loop code part in the initial code, it is converted into simpler related nodes, which are connected to the syntax tree according to the execution order between it and the loop code, thereby generating a final loop sub-syntax tree.

[0069] By identifying at least one loop code included in the initial code, each loop code is converted into a corresponding loop sub-syntax tree, and the relevant nodes corresponding to the loop sub-syntax tree are generated according to other codes included in the initial code except the loop code, and then the loop sub-syntax tree and the relevant nodes are connected to generate the initial syntax tree. Through the above process, the generated initial syntax tree can be related only to the loop code in the initial code, simplifying the structure of the initial syntax tree while focusing on the loop part, so as to facilitate the subsequent adjustment of the initial syntax tree to obtain the target syntax tree, thereby effectively improving the performance of the target code, and at the same time, the efficiency of the entire code generation process can also be improved.

[0070] After the initial abstract representation in the form of an initial syntax tree is generated, the initial abstract representation can be optimized in step S13 to obtain a target abstract representation. The specific optimization process can be flexibly determined according to actual conditions and is not limited to the following disclosed embodiments.

[0071] In a possible implementation, step S13 may include: optimizing at least one of a loop structure and a loop parameter in the initial abstract representation to obtain a target abstract representation.

[0072] Among them, the loop structure in the initial abstract representation can be the structure corresponding to the abstract representation converted from the loop code in the initial abstract representation. Taking the initial abstract representation as the initial syntax tree as an example, since the initial syntax tree can include multiple loop sub-syntax trees converted from different loop codes, these sub-syntax trees are used in the loop process. The loop-related structures involved, such as loop condition nodes or loop content nodes, can be regarded as loop structures.

[0073] The loop parameters in the initial abstract representation may be the corresponding parameters contained in the abstract representation converted from the loop code in the initial abstract representation. Also, taking the initial abstract representation as the initial syntax tree as an example, among the parameters involved in the loop sub-syntax tree included in the initial syntax tree, if there are some parameters whose parameter value changes do not affect the result of code execution but may affect the efficiency of code improvement, then these parameters may be regarded as loop parameters.

[0074] It has been proposed in the above disclosed embodiments that, in the process of converting the initial code, the loop code part thereof can be converted into multiple loop sub-syntax trees to obtain the initial abstract representation. Therefore, the initial abstract representation can be composed of the corresponding abstract expression form of the loop code. When optimizing the initial abstract representation, the loop structure or the loop parameters therein can be optimized, or both can be optimized at the same time, so that the obtained target abstract representation has a better structure and more appropriate parameters, and then the corresponding target code has a higher execution efficiency.

[0075] By optimizing at least one of the loop structure and loop parameters in the initial abstract representation to obtain the target abstract representation, a wider optimization space can be provided for code optimization, thereby further improving the execution efficiency of the obtained target code.

[0076] In a possible implementation, the process of optimizing the initial abstract representation to obtain the target abstract representation may include:

[0077] Based on multiple candidate optimization combinations, the initial abstract representation is optimized to obtain multiple candidate abstract representations, wherein each candidate optimization combination includes a candidate loop structure and a candidate loop parameter.

[0078] Convert multiple candidate abstract representations into multiple test codes.

[0079] Based on the test performance of the plurality of test codes, a target abstract representation is determined from a plurality of candidate abstract representations.

[0080] In the above disclosed embodiments, the candidate loop structure may be a structure obtained by adjusting the loop structure in the abstract representation. Since the loop structure may have multiple adjustment forms, the number of candidate loop structures may be one or more. The specific implementation method may refer to the subsequent disclosed embodiments, which will not be expanded here. The candidate loop parameter may be a parameter obtained by adjusting the parameter in the loop structure in the abstract representation. The adjustable numerical range may be flexibly determined according to the actual situation of the abstract representation, and is not limited here. By combining different candidate loop structures and candidate loop parameter forms, multiple candidate optimization combinations may be obtained. The abstract representation may be optimized according to different candidate optimization combinations to obtain multiple candidate abstract representations. Furthermore, in order to select the final optimization combination from these candidate optimization combinations to obtain the target abstract representation, these candidate abstract representations may be converted into multiple test codes, and based on the test performance of these test codes, the one with the highest test performance or the most appropriate one may be selected, and the candidate abstract representation corresponding to the test code may be used as the target abstract representation.

[0081] Through the above process, it is possible to optimize the initial abstract representation in various directions in terms of structure and parameters, and select the most appropriate optimization method from these multiple optimizations as the target abstract representation. This method can not only comprehensively optimize the initial abstract representation so that the obtained target abstract representation is as optimal as possible, but also facilitate automatic machine implementation, thereby improving the degree of automation of the entire code generation process.

[0082] Specifically, since the above disclosed embodiments have proposed that the initial abstract representation may include an initial syntax tree, and the target abstract representation may include a target syntax tree, the optimization process proposed in step S13 may be regarded as a process of optimizing the initial syntax tree to obtain the target syntax tree. In a possible implementation, when the abstract representation is in the form of a syntax tree, step S13 may include:

[0083] Step S131, obtaining a first sub-syntax tree of the initial syntax tree, wherein the root node of the first sub-syntax tree is the first loop node in the initial syntax tree.

[0084] Step S132: Optimize at least one of the loop structure and loop parameters of the first sub-grammar tree to obtain a second sub-grammar tree.

[0085] Step S133: Obtain a target syntax tree based on the second sub-syntax tree.

[0086] It has been proposed in the above-mentioned public embodiments that, when converting the initial code into the initial syntax tree, the multiple segments of cyclic code included in the initial code can be converted into multiple cyclic sub-syntax trees respectively, and then these cyclic sub-syntax trees are connected to obtain the initial syntax tree. Therefore, the initial syntax tree can be composed of multiple cyclic sub-syntax trees, and the first sub-syntax tree obtained from the initial syntax tree can be a cyclic sub-syntax tree in the initial syntax tree. In a possible implementation, the process of obtaining the first sub-syntax tree from the initial syntax tree can be a random process, that is, a cyclic sub-syntax tree is randomly selected from the initial syntax tree as the first sub-syntax tree. In a possible implementation, the first cyclic sub-syntax tree can also be selected as the first sub-syntax tree according to the order of the cyclic sub-syntax trees in the initial syntax tree.

[0087] After obtaining the first sub-syntax tree, at least one of the loop structure and loop parameters of the first sub-syntax tree can be optimized in step S132 to obtain a second sub-syntax tree, and a target syntax tree can be obtained based on the second sub-syntax tree. Through the above process, the optimization process of the initial syntax tree can be decomposed into the optimization process of multiple loop sub-syntax trees, further simplifying the optimization process, improving the optimization efficiency, and thus improving the efficiency of generating the target code.

[0088] Specifically, how to optimize the first sub-syntax tree into the second sub-syntax tree through step S132 can also be flexibly determined according to actual conditions and is not limited to the following disclosed embodiments. In a possible implementation, step S132 may include:

[0089] Step S1321: adjust the loop structure of the first sub-syntax tree to obtain a candidate loop structure.

[0090] Step S1322: Based on the current loop parameters and the candidate loop structures of the first sub-grammar tree, candidate loop parameters of the first sub-grammar tree are obtained.

[0091] Step S1323: Obtain a candidate sub-syntax tree of the first sub-syntax tree based on the candidate loop structure and the candidate loop parameter.

[0092] Step S1324: determine a second sub-syntax tree from the candidate sub-syntax trees and the first sub-syntax tree based on the test performance of the test code corresponding to the candidate sub-syntax tree and the first sub-syntax tree.

[0093] In the above disclosed embodiments, how to adjust the loop structure of the first sub-syntax tree needs to be flexibly selected according to the actual structure of the first sub-syntax tree. In the above disclosed embodiments, it has been proposed that the first sub-syntax tree can be a loop sub-syntax tree generated according to the loop code. Therefore, in a possible implementation, the loop structure of the first sub-syntax tree is adjusted to obtain a candidate loop structure, which may include:

[0094] Changing the nesting order of loops included in the first sub-syntax tree; and / or cutting the loops included in the first sub-syntax tree; and / or merging the loops included in the first sub-syntax tree; and / or expanding the loops included in the first sub-syntax tree.

[0095] In the above disclosed embodiment, the implementation form of changing the nesting order of the loops included in the first sub-syntax tree may be: the first sub-syntax tree may be composed of multiple nested loop structures, that is, the implementation form of the first sub-syntax tree may be as follows: Figure 2 As shown in the structure of the rightmost branch, it contains two loop conditions: for(i) and for(j). When the loop condition is i, it determines whether the loop condition is j. If it is j, func(i,j) is executed, otherwise func(i) is executed. At this time, it can be explained that the first sub-syntax tree is composed of two nested loop structures. At this time, we can consider adjusting the nesting order between the two loop conditions without changing the implementation form of the first sub-syntax tree to complete the structural change of the first sub-syntax tree.

[0096] In addition, it is also possible to consider cutting or merging the loop included in the first sub-grammar tree according to the loop condition of the first sub-grammar tree. For example, when the condition of a loop is that the value of its parameter a is between 0 and 10, it is possible to consider cutting it into two loop conditions, such as 0~x and x~10, where x is a number between 0 and 10, thereby completing the cutting of the loop included in the first sub-grammar tree; when the condition of a loop is that the value of parameter b is between 1 and 3, and the condition of another loop is that the value of parameter b is between 1 and 8, it is possible to consider merging the two loops into one loop with the loop condition that the value of parameter b is between 1 and 8, thereby completing the merging of the loop included in the first sub-grammar tree.

[0097] Furthermore, it is also possible to consider converting a first sub-syntax tree that is executed in a loop into a sequential code that is executed repeatedly for multiple times to complete the loop expansion included in the first sub-syntax tree.

[0098] In addition to the above-mentioned modification methods, other modification forms for the loop structure may also be selected, which are not listed here one by one. In practical applications, the specific modification methods may be flexibly selected according to the actual situation and are not limited here.

[0099] By using the above-mentioned multiple ways of changing the structure of the first sub-grammar tree, the flexibility and diversity of structural adjustment can be effectively improved, so that the final second sub-grammar tree has a better structural form, thereby improving the performance and execution efficiency of the target code.

[0100] After adjusting the loop structure of the first sub-grammar tree, the candidate loop parameters of the first sub-grammar tree can be obtained according to the current loop parameters and the candidate loop structure of the first sub-grammar tree, that is, according to the current structure of the first sub-grammar tree, the loop parameters that need to be adjusted in the first sub-grammar tree are adjusted to obtain the candidate loop parameters.

[0101] It should be noted that in the disclosed embodiment, when adjusting the parameters of the first sub-syntax tree, it is possible to first determine which parameters need to be adjusted. For a section of loop code, it may contain many parameters, but there may only be some parameters whose numerical changes will not affect the correctness of the code, but will affect the execution efficiency of the code. Therefore, when adjusting the parameters, only those parameters that will affect the efficiency of the code can be adjusted to obtain candidate loop parameters, thereby improving the optimization efficiency of the syntax tree, and then improving the generation efficiency of the target code. How to determine which loop parameters are adjusted to obtain candidate loop parameters can be obtained by screening the loop parameters according to preset rules. The specific preset rules can be determined according to the actual implementation form of the code, and are not limited here. Flexible selection and adjustment are sufficient.

[0102] Furthermore, how to adjust the loop parameter to obtain the candidate loop parameter can also be flexibly selected according to the actual parameter situation of the first sub-syntax tree. In a possible implementation, the process of adjusting the loop parameter may include: changing the value of the loop parameter within a preset range.

[0103] It has been mentioned in the above-mentioned public embodiments that when adjusting the loop parameters, it is possible to determine which loop parameters to adjust according to preset rules, that is, the loop parameters that need to be adjusted can be determined by matching the preset rules. Therefore, further, when adjusting the loop parameters to obtain candidate loop parameters, it is also possible to determine the preset range within which the loop parameters can be adjusted according to the preset rules. Changing the value of the loop parameter within this range may not affect the correctness of the first sub-syntax tree, and may also change the efficiency of the execution of the corresponding code of the first sub-syntax tree.

[0104] After obtaining the candidate loop parameters of the first sub-syntax tree, candidate sub-syntax trees of the first sub-syntax tree can be obtained based on the candidate loop structures and the candidate loop parameters. Since the first sub-syntax tree can have a variety of loop structures and loop parameter adjustment methods, the number of obtained candidate sub-syntax trees can be multiple. Through step S1324, the second sub-syntax tree can be further selected from these candidate sub-syntax trees and the first sub-syntax tree based on the test performance of the test codes corresponding to these candidate sub-syntax trees and the first sub-syntax tree.

[0105] In the above-mentioned disclosed embodiment, the loop structure and loop parameters of the first sub-syntax tree can be adjusted sequentially. In actual application, only the loop structure or loop parameters of the first sub-syntax tree can be adjusted according to the actual situation of the first sub-syntax tree, thereby further improving the adjustment speed of the first sub-syntax tree and then improving the generation efficiency of the target code.

[0106] Through the above process, the loop structure and loop parameters of the first sub-syntax tree can be adjusted in turn, thereby effectively expanding the adjustment and search space of the first syntax tree, so that the generated second syntax tree has more optimized performance, and then generates more efficient target code, thereby improving the quality and execution efficiency of the target code.

[0107] In a possible implementation, based on the test performance corresponding to the candidate sub-syntax tree and the first sub-syntax tree, the second sub-syntax tree is determined from the candidate sub-syntax tree and the first sub-syntax tree, and its implementation form can be flexibly determined according to actual conditions. In a possible implementation, step S1324 may include:

[0108] If the test performance of the test code corresponding to the candidate sub-syntax tree is better than the test performance of the test code corresponding to the first sub-syntax tree, the candidate sub-syntax tree is used as the second sub-syntax tree; and / or

[0109] If the test performance of the test code corresponding to the candidate sub-grammar tree is lower than the test performance of the test code corresponding to the first sub-grammar tree, the first sub-grammar tree is used as the second sub-grammar tree.

[0110] It can be seen from the above-mentioned disclosed embodiments that in a possible implementation method, the second sub-grammar tree can be determined from the candidate sub-grammar trees in an iterative manner, that is, when the test performance of the test code corresponding to the candidate sub-grammar tree is better than the test performance of the test code corresponding to the current first sub-grammar tree, the candidate sub-grammar tree can be used as the first sub-grammar tree, otherwise the current first sub-grammar tree is still used as the first sub-grammar tree, and then the next candidate sub-grammar tree is selected, and the performance of the test code corresponding to it is compared with the current first sub-grammar tree. Through multiple iterations, the sub-grammar tree with the best test performance of the test code can be determined from these multiple candidate sub-grammar trees and the first sub-grammar tree as the second sub-grammar tree.

[0111] In a possible implementation, a non-iterative approach may be used to compare the test code of each candidate sub-grammar tree with the test code of the first sub-grammar tree at the same time, and the sub-grammar tree with the best test code performance is selected as the second sub-grammar tree.

[0112] Through the above process, the sub-syntax tree with the best performance can be selected as the second sub-syntax tree by comparing the test performance of the test code of the candidate sub-syntax tree and the first sub-syntax tree, so that the target syntax tree obtained based on the second sub-syntax tree has the best performance and the quality of the code generation results is improved.

[0113] After the second sub-grammar tree is obtained, step S133 may be performed to obtain a target grammar tree based on the second sub-grammar tree. In a possible implementation, step S133 may include:

[0114] A third sub-syntax tree is selected from the updated syntax tree including the second sub-syntax tree for the next round of iterative optimization until a cutoff condition of the iterative optimization is met, thereby obtaining a target syntax tree.

[0115] Among them, the updated syntax tree is the syntax tree obtained after optimizing the first sub-syntax tree in the initial syntax tree into the second sub-syntax tree. The third syntax tree selected from the updated syntax tree can be a cyclic sub-syntax tree randomly selected from other cyclic sub-syntax trees except the second sub-syntax tree contained in the updated syntax tree; it can also be a cyclic sub-syntax tree selected in sequence after the second sub-syntax tree according to the logical order between the cyclic sub-syntax trees in the updated syntax tree. It can be flexibly selected according to the actual situation and is not limited here.

[0116] After the third sub-syntax tree is selected, the third sub-syntax tree can be optimized by optimizing the first sub-syntax tree into the second sub-syntax tree mentioned in the above disclosed embodiment, thereby obtaining the optimized third sub-syntax tree, thereby realizing the update of the update grammar tree again. According to the above process and so on, a loop sub-syntax tree can be selected from the update grammar tree each time for iterative optimization until the cutoff condition of the iterative optimization is met, at which time the optimized update grammar tree can be used as the target grammar tree.

[0117] The cutoff condition for iterative optimization can be flexibly selected according to actual needs. In one possible implementation, this cutoff condition may be that the number of iterative optimizations reaches a set threshold, and the specific threshold number is not limited here; in a possible implementation, this cutoff condition may also be that each cyclic sub-syntax tree included in the initial syntax tree is optimized once, and the specific cutoff condition is not limited here.

[0118] In one example, the complete process of iterative optimization mentioned in the above disclosed embodiment may be:

[0119] Set the initial value of the number of iterations to 0;

[0120] Randomly select an unoptimized cyclic sub-syntax tree from an initial syntax tree including multiple cyclic sub-syntax trees, try one or more optimization combinations through the methods proposed in the above disclosed embodiments, optimize the cyclic sub-syntax tree into a cyclic sub-syntax tree with higher corresponding code efficiency, replace the optimized cyclic sub-syntax tree with the initial syntax tree, and update the initial syntax tree;

[0121] Add one to the value of the number of iterations to determine whether the number of iterations exceeds the threshold. If the number of iterations is less than the threshold, return to the above optimization process until the iteration cutoff condition is reached. For example, the number of iterations reaches the threshold or the performance of the updated code reaches the expectation, or all the update iterations of the sub-syntax trees have been traversed, etc. At this time, the updated initial syntax tree can be used as the target syntax tree.

[0122] By selecting the third sub-syntax tree from the updated syntax tree containing the second sub-syntax tree for the next round of iterative optimization, until the cutoff condition of the iterative optimization is met, the target syntax tree is obtained. Through this process, each loop sub-syntax tree included in the initial syntax tree can be optimized once as much as possible, so that the performance of the final target syntax tree is better, that is, the corresponding target code can have better execution efficiency.

[0123] Application scenario examples

[0124] Figure 3-4A schematic diagram of an application example according to the present disclosure is shown. As shown in the figure, the embodiment of the present disclosure proposes a code generation method. The specific process of this generation method can be:

[0125] like Figure 3 As shown, the code generation method proposed in the embodiment of the present disclosure generates a target code by using the existing executable code as the initial code, parsing and converting it into an abstract representation, and then generating it through search and tuning.

[0126] Among them, the code parsing process can be: code parsing requires two parts of tasks, the first part is to extract the syntax tree of the initial code. The syntax tree is an abstraction of the code, and all codes, regardless of the back-end device, can be expressed as a syntax tree. Therefore, code parsing can convert the initial code of different back-end devices into the same structure, which is convenient for subsequent processing. However, compared with the general and cumbersome syntax tree, although it has strong expressive power, a lot of complex information will be saved, which is not helpful for helping to generate more efficient code. In the application example disclosed in the present invention, the program code is represented by a more concise abstract representation, that is, for the performance of the code, the main bottleneck is the loop, and the optimization of the code is mainly the optimization of the loop. Therefore, in the application example disclosed in the present invention, the syntax tree is further simplified, that is, the loop part in the initial code is extracted, and the initial code is simplified into a loop tree. Therefore, the analysis of the code structure only focuses on the loop structure. This can save a lot of complexity.

[0127] In addition to the loop structure, for a section of code, some parameters may be included, and the change of these parameters will not affect the correctness, but will affect the code execution efficiency. Therefore, in the disclosed application example, it is also necessary to extract these parameters, obtain a better solution in the search tuning, so as to generate efficient executable code. In a possible implementation, these parameters may be the loop parameters mentioned in the loop tree in the above-mentioned disclosed embodiment, in a possible implementation, these parameters may also be some parameters outside the loop tree, for example, in the process of converting the code into a syntax tree, only the loop part therein may be extracted, simplified to the loop tree, but when multiple loop subtrees are included in this loop tree, there may be certain connection relations between different loop subtrees, and some parameters may be included in these connection relations, these parameters also have the property of not affecting the correctness of the code but affecting the code execution efficiency when changing, so in an example, it is also possible to optimize these parameters in addition to optimizing the loop structure and loop parameters.

[0128] The process of search and tuning is as follows Figure 4As shown, it can be seen from the figure that after the extraction of the above-mentioned parsing process, a loop tree representing the relevant code and a set of parameters affecting the code performance can be obtained. In the disclosed application example, structure optimization and parameter optimization are performed for these two parts respectively. In an example, by trying a combination of multiple parameters and structures, for each combination, their corresponding executable codes are generated and executed, and the execution efficiency of the code is tested to determine the effect of the current optimization direction, that is, whether to retain this optimization, and then determine the direction of the next round of optimization. After several iterations as above, the target code finally generated has good performance and execution efficiency.

[0129] After obtaining the target code, since the target code can be automatically optimized and generated directly by the hardware device, the optimized code can be compiled and executed directly in the hardware device without the need to manually input the code into the corresponding hardware device, which greatly improves the efficiency of hardware work and saves labor and time costs.

[0130] Furthermore, the generated target code can also be directly and automatically uploaded to a cloud server or other target hardware device to achieve code sharing or direct control of multiple hardware devices.

[0131] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not go into details.

[0132] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0133] Figure 5 A block diagram of a code generating device according to an embodiment of the present disclosure is shown. The code generating device may be a terminal device, a server or other processing device, etc. The terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc.

[0134] In some possible implementations, the code generation device may be implemented by a processor calling computer-readable instructions stored in a memory.

[0135] like Figure 5 As shown, the code generating device 20 may include:

[0136] An acquisition module 21 is used to acquire an initial code;

[0137] A parsing module 22, used to parse the initial code to obtain an initial abstract representation of the initial code;

[0138] An optimization module 23, used to optimize the initial abstract representation to obtain a target abstract representation;

[0139] The conversion module 24 is used to obtain the target code corresponding to the initial code according to the target abstract representation.

[0140] In a possible implementation, the optimization module is used to optimize at least one of a loop structure and a loop parameter in the initial abstract representation to obtain a target abstract representation.

[0141] In one possible implementation, the optimization module is further used to: optimize the initial abstract representation based on multiple candidate optimization combinations to obtain multiple candidate abstract representations, wherein each candidate optimization combination includes a candidate loop structure and candidate loop parameters; convert the multiple candidate abstract representations into multiple test codes; and determine the target abstract representation from the multiple candidate abstract representations based on the test performance of the multiple test codes.

[0142] In a possible implementation, the initial abstract representation includes an initial syntax tree, and the target abstract representation includes a target syntax tree.

[0143] In one possible implementation, the optimization module is used to: obtain a first sub-grammar tree of an initial grammar tree, wherein the root node of the first sub-grammar tree is a first loop node in the initial grammar tree; optimize at least one of the loop structure and loop parameters of the first sub-grammar tree to obtain a second sub-grammar tree; and obtain a target grammar tree based on the second sub-grammar tree.

[0144] In one possible implementation, the optimization module is further used to: adjust the loop structure of the first sub-syntax tree to obtain a candidate loop structure; obtain candidate loop parameters of the first sub-syntax tree based on the current loop parameters of the first sub-syntax tree and the candidate loop structure; obtain candidate sub-syntax trees of the first sub-syntax tree based on the candidate loop structure and the candidate loop parameters; and determine the second sub-syntax tree from the candidate sub-syntax trees and the first sub-syntax tree based on the test performance of the test code corresponding to the candidate sub-syntax trees and the first sub-syntax tree.

[0145] In a possible implementation, the optimization module is further used to: select a third sub-syntax tree from the updated syntax tree including the second sub-syntax tree for the next round of iterative optimization until a cutoff condition of the iterative optimization is met to obtain a target syntax tree.

[0146] The embodiment of the present disclosure also provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented. The computer-readable storage medium may be a non-volatile computer-readable storage medium.

[0147] The embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured as the above method.

[0148] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0149] Figure 6 800 is a block diagram of an electronic device according to an embodiment of the present disclosure. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like.

[0150] Reference Figure 6 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0151] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0152] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0153] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0154] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0155] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0156] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0157] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of the components, such as the display and keypad of the electronic device 800, and the sensor assembly 814 can also detect the position change of the electronic device 800 or a component of the electronic device 800, the presence or absence of contact between the user and the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0158] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0159] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0160] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 804 including computer program instructions, which can be executed by a processor 820 of an electronic device 800 to perform the above method.

[0161] Figure 7 1 is a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server. Figure 7, the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0162] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

[0163] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0164] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0165] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0166] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0167] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0168] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0169] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0170] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0171] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0172] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A code generation method, characterized in that: include: Get the initial code; Parsing the initial code to obtain an initial abstract representation of the initial code; Optimizing the initial abstract representation to obtain a target abstract representation; Obtaining a target code corresponding to the initial code according to the target abstract representation; The initial abstract representation includes an initial syntax tree, and the target abstract representation includes a target syntax tree; The step of optimizing the initial abstract representation to obtain a target abstract representation includes: Obtain a first sub-grammar tree of the initial grammar tree, wherein the root node of the first sub-grammar tree is a first loop node in the initial grammar tree; Optimizing at least one of a loop structure and a loop parameter of the first sub-grammar tree to obtain a second sub-grammar tree; Based on the second sub-grammar tree, obtain a target grammar tree; The step of optimizing at least one of a loop structure and a loop parameter of the first sub-grammar tree to obtain a second sub-grammar tree includes: Adjusting the loop structure of the first sub-syntax tree to obtain a candidate loop structure; Based on the current loop parameter of the first sub-grammar tree and the candidate loop structure, obtaining candidate loop parameters of the first sub-grammar tree; Based on the candidate loop structure and the candidate loop parameter, obtain a candidate sub-grammar tree of the first sub-grammar tree; The second sub-syntax tree is determined from the candidate sub-syntax trees and the first sub-syntax tree based on test performances of test codes corresponding to the candidate sub-syntax trees and the first sub-syntax tree.

2. The method according to claim 1, characterized in that The step of optimizing the initial abstract representation to obtain a target abstract representation includes: At least one of a loop structure and a loop parameter in the initial abstract representation is optimized to obtain a target abstract representation.

3. The method according to claim 2, characterized in that The step of optimizing at least one of a loop structure and a loop parameter in the initial abstract representation to obtain a target abstract representation includes: Based on a plurality of candidate optimization combinations, the initial abstract representation is optimized to obtain a plurality of candidate abstract representations, wherein each candidate optimization combination includes a candidate loop structure and a candidate loop parameter; converting the plurality of candidate abstract representations into a plurality of test codes; Based on the test performance of the plurality of test codes, a target abstract representation is determined from the plurality of candidate abstract representations.

4. The method according to claim 1, characterized in that: The step of obtaining a target syntax tree based on the second sub-syntax tree comprises: A third sub-syntax tree is selected from the updated syntax tree including the second sub-syntax tree for the next round of iterative optimization until a cutoff condition of the iterative optimization is met, thereby obtaining the target syntax tree.

5. A code generating device, characterized in that: include: Acquisition module, used to obtain the initial code; A parsing module, used for parsing the initial code to obtain an initial abstract representation of the initial code; An optimization module, used for optimizing the initial abstract representation to obtain a target abstract representation; A conversion module, used for obtaining a target code corresponding to the initial code according to the target abstract representation; The initial abstract representation includes an initial syntax tree, and the target abstract representation includes a target syntax tree; The optimization module is used to: Obtain a first sub-grammar tree of the initial grammar tree, wherein the root node of the first sub-grammar tree is a first loop node in the initial grammar tree; Optimizing at least one of a loop structure and a loop parameter of the first sub-grammar tree to obtain a second sub-grammar tree; Based on the second sub-grammar tree, obtain a target grammar tree; The optimization module is further used for: Adjusting the loop structure of the first sub-syntax tree to obtain a candidate loop structure; Based on the current loop parameter of the first sub-grammar tree and the candidate loop structure, obtaining candidate loop parameters of the first sub-grammar tree; Based on the candidate loop structure and the candidate loop parameter, obtain a candidate sub-grammar tree of the first sub-grammar tree; The second sub-syntax tree is determined from the candidate sub-syntax trees and the first sub-syntax tree based on test performances of test codes corresponding to the candidate sub-syntax trees and the first sub-syntax tree.

6. The device according to claim 5, characterized in that The optimization module is used to: At least one of a loop structure and a loop parameter in the initial abstract representation is optimized to obtain a target abstract representation.

7. The device according to claim 6, characterized in that The optimization module is further used for: Based on a plurality of candidate optimization combinations, the initial abstract representation is optimized to obtain a plurality of candidate abstract representations, wherein each candidate optimization combination includes a candidate loop structure and a candidate loop parameter; converting the plurality of candidate abstract representations into a plurality of test codes; Based on the test performance of the plurality of test codes, a target abstract representation is determined from the plurality of candidate abstract representations.

8. The device according to claim 5, characterized in that The optimization module is further used for: A third sub-syntax tree is selected from the updated syntax tree including the second sub-syntax tree for the next round of iterative optimization until a cutoff condition of the iterative optimization is met, thereby obtaining the target syntax tree.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 4.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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