Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same, in which a gate space is formed by removing a sacrificial gate electrode, a gate dielectric layer is formed in the gate space, a conductive layer is formed on the gate dielectric layer to completely fill the gate space, the gate dielectric layer and the conductive layer are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. The recessed gate electrode does not contain tungsten, and the contact metal layer contains tungsten.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to semiconductor devices and methods for manufacturing the same, and more particularly, to gates and methods for manufacturing the same. Background Art

[0002] As the semiconductor industry has progressed to nanotechnology process nodes in pursuit of higher device density, higher performance and lower cost, challenges arising from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors (FETs), including fin field effect transistors (FinFETs) and gate-all-around (GAA) field effect transistors. In a fin field effect transistor, the gate electrode is adjacent to three side surfaces of the channel region, and there is an interposed gate dielectric layer between the channel regions. The gate electrode of the fin field effect transistor includes one or more layers of metallic materials formed by gate replacement technology. Summary of the invention

[0003] According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode, a gate dielectric layer is formed in the gate space, a conductive layer is formed on the gate dielectric layer to completely fill the gate space, the gate dielectric layer and the conductive layer are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. The recessed gate electrode does not include a tungsten layer, and the contact metal layer includes tungsten.

[0004] According to other aspects of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed on a substrate is formed, a sacrificial gate dielectric layer is formed on the fin structure, a sacrificial gate electrode layer is formed on the sacrificial gate dielectric layer, a gate sidewall spacer is formed, and one or more dielectric layers are formed; a gate space is formed by removing the sacrificial gate electrode layer and the sacrificial gate dielectric layer, and after forming the gate space, the gate sidewall spacer is recessed; a gate dielectric layer is formed in the gate space; a conductive layer is formed on the gate dielectric layer to completely fill the gate space, the gate dielectric layer and the conductive layer are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode.

[0005] According to another aspect of the present disclosure, a semiconductor device includes a fin structure protruding from an isolation insulating layer disposed on a substrate and having a channel region, a source / drain epitaxial layer, a gate dielectric layer on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode layer includes a lower portion and an upper portion, and the lower portion includes a conductive layer, at least one of the conductive layers has a U-shaped cross section, and at least one of the conductive layers does not have a U-shaped cross section. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of various features may be arbitrarily increased or reduced for the purpose of clarity of discussion.

[0007] Figure 1 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0008] Figure 2 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0009] Figure 3 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0010] Figure 4 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0011] Figure 5 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0012] Figure 6 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0013] Figure 7 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0014] Figure 8 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0015] Fig. 9 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0016] Fig.10 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0017] Fig.11 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0018] Fig.12showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0019] Fig.13 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0020] Fig.14 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0021] Fig.15 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0022] Fig.16 showing one of a plurality of stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0023] Fig.17A , Fig. 17B , Fig. 17C and Fig.17D The various stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown;

[0024] Fig.18A , Fig.18B , Fig.18C , Fig.18D , Fig.18E and Fig.18F The various stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown;

[0025] Fig.19A , Fig.19B , Fig.19C , Fig.19D , Fig.19E , Fig.19F and Figure 19G The various stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown;

[0026] Fig. 20A , Fig. 20B and Fig. 20C The various stages of a sequential process for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown;

[0027] Fig.21 showing one of the multiple stages of a sequential process for fabricating a field effect transistor device according to an embodiment of the present disclosure;

[0028] Fig.22A , Fig. 22B , Fig. 22C , Fig.22D, Fig.22E , Fig.22F and Figure 22G Various stages of a sequential process for fabricating a semiconductor device according to an embodiment of the present disclosure are shown.

[0029]

Explanation of symbols

[0030] 10:Substrate

[0031] 11: Lower part

[0032] 12: Dopant

[0033] 15: Mask layer

[0034] 15A: First mask layer

[0035] 15B: Second mask layer

[0036] 20: Fin structure

[0037] 22: cushion layer

[0038] 25: Fin structure

[0039] 30: Layer

[0040] 40: Sacrificial gate structure

[0041] 42: Sacrificial gate dielectric layer

[0042] 44: Sacrificial gate electrode layer

[0043] 45: Sidewall spacer / cladding layer

[0044] 46: Silicon nitride pad

[0045] 48: Mask layer

[0046] 49: Gate Space

[0047] 50: Source / drain epitaxial layer

[0048] 52: Porosity

[0049] 60: Insulation cushion layer

[0050] 65: Interlayer dielectric layer

[0051] 81: Interface layer

[0052] 82: Gate dielectric layer

[0053] 83: Barrier layer

[0054] 84: Work function adjustment material layer

[0055] 84-1: Work function adjustment material layer

[0056] 84-2: Work function adjustment material layer

[0057] 85: Work function adjustment material layer

[0058] 86: Blocking metal layer

[0059] 87: Contact metal layer

[0060] 88: Gate electrode

[0061] 88A: Lower gate electrode

[0062] 90: Top cover insulation layer

[0063] 110: Contact hole

[0064] 120: Silicide layer

[0065] 130: Conductive material

[0066] 135: Second interlayer dielectric layer

[0067] 140: third interlayer dielectric layer

[0068] 145: Gate contact

[0069] 181: Tungsten layer

[0070] 183: Tungsten layer

[0071] 185: Top cover insulation layer

[0072] 200: Pseudo-fin structure

[0073] 205: Lower level

[0074] 210: Middle layer

[0075] 215: Upper

[0076] 230: Separation embolism

[0077] X1-X1: Line

[0078] Y1-Y1: Line

[0079] X: Direction

[0080] Y: direction

[0081] Z: Direction

[0082] T1: Thickness

[0083] T2: Thickness

[0084] D1: Distance

[0085] D2: Distance DETAILED DESCRIPTION

[0086] It should be understood that the following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or desired properties of the device. In addition, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be sandwiched between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. For the purpose of simplicity and clarity, various features may be drawn at different scales.

[0087] In addition, for the purpose of brevity, spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature, as exemplified in the figures. Spatially relative terms are intended to encompass different orientations of the device when in use or in operation other than the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. Additionally, the term "made of" may mean "comprising" or "consisting of."

[0088] In the gate replacement technique, a sacrificial gate structure including a sacrificial gate electrode (made of, for example, polysilicon) is first formed over the channel region, and the sacrificial gate structure is subsequently replaced by a metal gate structure. In metal gate FinFETs, device performance is affected by the design of the metal gate profile (shape), and the metal gate profile is generally determined by the profile of the sacrificial gate electrode. In some FinFET devices, after the metal gate structure is formed by the gate replacement process, the upper portion of the metal gate structure is recessed, and a cap insulating layer is formed over the recessed gate structure to protect the isolation region between the metal gate electrode and the adjacent conductive contacts. In addition, in advanced FinFET devices, various field effect transistors (n-channel and p-channel field effect transistors) with different threshold voltages are fabricated on one device, and the field effect transistors may have different metal (e.g., work function adjustment metal) structures. The gate recess etch used to form the gate cap may be affected by the metal structure, and it is desirable to recess the metal gate structure to a desired height regardless of the metal structure. In the present disclosure, a method is provided for controlling the height of a recessed metal gate structure by adjusting the cross-section (shape) of a sacrificial gate electrode.

[0089] Figures 1 to 16The following is a sequential process for manufacturing a field effect transistor device according to an embodiment of the present disclosure. It should be understood that Figures 1 to 16 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the methods. The order of the operations / processes is interchangeable.

[0090] like Figure 1 As shown, impurity ions (dopants) 12 are implanted into a silicon substrate 10 to form a well region. The ion implantation is performed to prevent a punch-through effect.

[0091] In an embodiment, the substrate 10 includes a single crystal semiconductor layer on at least a portion of its surface. The substrate 10 may include a single crystal semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). In this embodiment, the substrate 10 is made of silicon.

[0092] The substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layer may be used to gradually change the lattice constant from the substrate to the source / drain region. The buffer layer may be formed of epitaxially grown single crystal semiconductor materials such as, but not limited to, silicon, germanium, germanium tin (GeSn), silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium arsenic antimonide, gallium nitride (GaN), gallium phosphide (GaP), and indium phosphide. In a specific embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the silicon substrate 10. The germanium concentration of the silicon germanium buffer layer may increase from 30% of the germanium atomic percentage in the bottom buffer layer to 70% in the top buffer layer.

[0093] The substrate 10 may include various regions that have been appropriately doped with impurities (eg, p-type or n-type conductivity). For example, the dopant 12 is boron (BF2) for n-type FinFETs and phosphorus for p-type FinFETs.

[0094] exist Figure 2In the process, a mask layer 15 is formed on the substrate 10. In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. In some embodiments, the first mask layer 15A is made of silicon nitride, and the second mask layer 15B is made of silicon oxide. In other embodiments, the first mask layer 15A is made of silicon oxide, and the second mask layer 15B is made of silicon nitride (SiN). The first and second mask layers 15A and 15B are formed by chemical vapor deposition (CVD), including low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other appropriate processes. The mask layer 15 is patterned into a mask pattern by using a patterning operation (including photolithography and etching).

[0095] Then, if Figure 3 As shown in FIG. 1 , by using the patterned mask layer 15 , the substrate 10 is patterned into a fin structure 25 extending in the X direction. Figure 3 In the embodiment, two fin structures 25 are arranged in the Y direction. However, the number of fin structures is not limited to two and can be as few as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 25 to improve pattern fidelity in the patterning operation.

[0096] The fin structure 25 may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography with a self-aligned process, thereby allowing the creation of patterns with, for example, a pitch that is smaller than would otherwise be possible using a single direct photolithography process. For example, in an embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure.

[0097] After forming the fin structure 25, an insulating material layer including one or more insulating materials is formed on the substrate 10 so that the fin structure is completely embedded in the insulating layer. The insulating material used for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), fluorine-doped silicate glass (FSG) or a low dielectric constant (k) dielectric material formed by low pressure chemical vapor deposition, plasma chemical vapor deposition or flowable chemical vapor deposition. An annealing operation may be performed after forming the insulating layer. Then, a planarization operation (such as a chemical mechanical polishing (CMP) method and / or an etch-back method) is performed so that the upper surface of the uppermost fin structure 25 is exposed from the insulating material layer 30, such as Figure 4 shown.

[0098] In some embodiments, before forming the insulating material layer 30, Figure 3 One or more liner layers 22 are formed on the structure, such as Figure 4 The liner layer 22 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride and silicon oxide.

[0099] Then, if Figure 5 As shown, the insulating material layer 30 is recessed to form an isolation insulating layer 30 to expose the upper portion of the fin structure 20. In this operation, the fin structures 25 are electrically isolated from each other by the isolation insulating layer 30, which is also called shallow trench isolation (STI). The lower portion 11 of the fin structure is embedded in the isolation insulating layer 30.

[0100] After forming the isolation insulating layer 30, a sacrificial gate dielectric layer 42 is formed. Figure 6 As shown. The sacrificial gate dielectric layer 42 includes one or more layers of insulating materials, such as a material mainly composed of silicon oxide. In an embodiment, silicon oxide formed by chemical vapor deposition is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 42 is in the range of about 1 nanometer to about 5 nanometers.

[0101] Figure 7The structure after forming a sacrificial gate structure 40 on the exposed fin structure 25 is illustrated. The sacrificial gate structure 40 includes a sacrificial gate electrode layer 44 and a sacrificial gate dielectric layer 42. The sacrificial gate structure 40 is formed on a portion of the fin structure 25, which will become the channel region. The sacrificial gate structure 40 is first formed by depositing a sacrificial gate dielectric layer 42 over the fin structure. Then, a sacrificial gate electrode layer 44 is deposited over the sacrificial gate dielectric layer 42 and over the fin structure 25, so that the fin structure 25 is completely embedded in the sacrificial gate electrode layer 44. The sacrificial gate electrode layer 44 includes silicon, such as polysilicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer 44 is subjected to a planarization operation. The sacrificial gate dielectric layer 42 and the sacrificial gate electrode layer 44 are deposited using chemical vapor deposition (including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition), physical vapor deposition, atomic layer deposition or other appropriate processes. Subsequently, a mask layer is formed over the sacrificial gate electrode layer 44. The mask layer includes a silicon nitride pad layer 46 and a silicon oxide mask layer 48 .

[0102] Next, a patterning operation is performed on the mask layer, and the sacrificial gate electrode layer 44 is patterned into a sacrificial gate structure 40, such as Figure 7 The patterning operation of the sacrificial gate structure 40 will be explained in more detail below.

[0103] In some embodiments, the sacrificial gate structure 40 includes a sacrificial gate dielectric layer 42, a sacrificial gate electrode layer 44 (e.g., polysilicon), a silicon nitride pad layer 46, and a silicon oxide mask layer 48. By patterning the sacrificial gate structure 40, an upper portion of the fin structure 20 is partially exposed on opposite sides of the sacrificial gate structure 40, thereby defining a source / drain (S / D) region, such as Figure 7 In the present disclosure, the source and drain can be used interchangeably, and their structures are substantially the same. Figure 7 In the embodiment of the present invention, a sacrificial gate structure is formed, but the number of sacrificial gate structures 40 is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the X direction. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure 40 to improve pattern fidelity.

[0104] After forming the sacrificial gate structure 40, a capping layer 45 of an insulating material for the sidewall spacers 45 is conformally formed by using chemical vapor deposition or other suitable methods, such as Figure 8As shown. The capping layer 45 is deposited in a conformal manner so that the capping layer 45 is formed to have substantially equal thickness on vertical surfaces (such as sidewalls), horizontal surfaces, and the top of the sacrificial gate structure 40. In some embodiments, the capping layer 45 is deposited to a thickness ranging from about 2 nanometers to about 10 nanometers. In an embodiment, the insulating material of the capping layer 45 is a silicon nitride-based material, such as silicon nitride, silicon oxynitride, silicon carbon nitride or silicon carbon nitride, and combinations thereof.

[0105] In addition, if Fig. 9 As shown, sidewall spacers 45 are formed on opposite sidewalls of the sacrificial gate structure 40, and then the fin structure of the source / drain region is recessed downward to below the upper surface of the isolation insulating layer 30. After forming the capping layer 45, an anisotropic etch is performed on the capping layer 45 using, for example, reactive ion etching (RIE). During the anisotropic etch process, most of the insulating material is removed from the horizontal surfaces, leaving a dielectric spacer layer on the vertical surfaces, such as the sidewalls of the sacrificial gate structure 40 and the sidewalls of the fin structure 25. The mask layer 48 may be exposed from the sidewall spacers 45. In some embodiments, an isotropic etch may be subsequently performed to remove the insulating material from the upper portion of the exposed source / drain region of the fin structure 25.

[0106] Then, by using dry etching and / or wet etching, the fin structure of the source / drain region is recessed downward to below the upper surface of the isolation insulating layer 30. Fig. 9 As shown, the sidewall spacers 45 formed on the source / drain regions of the exposed fin structure (fin sidewall) are partially left. However, in other embodiments, the sidewall spacers 45 formed on the source / drain regions of the exposed fin structure are completely removed. In the case of a full-surround gate field effect transistor, the inner spacers are formed after the source / drain regions are recessed.

[0107] Then, if Fig.10 As shown, a source / drain epitaxial layer 50 is formed. The source / drain epitaxial layer 50 includes one or more layers of silicon, silicon phosphide (SiP), silicon carbide (SiC) and silicon carbon phosphide (SiCP) for n-channel field effect transistors or silicon, silicon germanium, germanium, germanium tin (GeSn) and silicon germanium tin (SiGeSn) for p-channel field effect transistors. The source / drain epitaxial layer 50 is formed by an epitaxial growth method using chemical vapor deposition, atomic layer deposition or molecular beam epitaxy (MBE).

[0108] like Fig.10As shown, source / drain epitaxial layers 50 are grown separately from the recessed fin structure. In some embodiments, the grown epitaxial layers merge over the isolation insulating layer and form a pore 52.

[0109] Subsequently, an insulating liner layer 60 is formed as an etching stop layer, and then an interlayer dielectric (ILD) layer 65 is formed. Fig.11 As shown. The insulating liner layer 60 is made of a silicon nitride-based material (such as silicon nitride) and acts as a contact etch stop layer in a subsequent etching operation. The material used for the interlayer dielectric layer 65 includes a compound containing silicon, oxygen, carbon and / or light, such as silicon oxide, silicon carbide hydroxide (SiCOH) and silicon carbide oxide. Organic materials (such as polymers) can be used for the interlayer dielectric layer 65. After forming the interlayer dielectric layer 65, a planarization operation, such as chemical mechanical polishing, is performed to expose the top portion of the sacrificial gate electrode layer 44, as shown in FIG. Fig.11 shown.

[0110] Then, if Fig.12 As shown, the sacrificial gate electrode layer 44 and the sacrificial gate dielectric layer 42 are removed, thereby exposing the fin structure in the gate space 49. During the removal of the sacrificial gate structure, the interlayer dielectric layer 65 protects the source / drain epitaxial layer 50. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 44 is polysilicon and the interlayer dielectric layer 65 is silicon oxide, a wet etchant (such as tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 44. Thereafter, the sacrificial gate dielectric layer 42 is removed using plasma dry etching and / or wet etching.

[0111] After removing the sacrificial gate structure, a gate dielectric layer 82 is formed around the exposed fin structure 20, and a gate electrode 88 is formed on the gate dielectric layer 82, as shown in FIG. Fig.13 shown.

[0112] In some embodiments, the gate dielectric layer 82 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high dielectric constant dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 82 includes an interface layer formed between the channel layer and the dielectric material.

[0113] The gate dielectric layer 82 may be formed by chemical vapor deposition, atomic layer deposition, or any suitable method. In one embodiment, a highly conformal deposition process such as atomic layer deposition is used to form the gate dielectric layer 82 so as to ensure that the gate dielectric layer 82 formed on the channel region has a uniform thickness. In some embodiments, the thickness of the gate dielectric layer 82 is in a range from about 1 nanometer to about 6 nanometers.

[0114] A gate electrode 88 is formed on the gate dielectric layer 82. The gate electrode 88 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials and / or combinations thereof.

[0115] The gate electrode 88 may be formed by chemical vapor deposition, atomic layer deposition, electroplating or other suitable methods. The gate electrode 88 may also be deposited on the upper surface of the interlayer dielectric layer 65. Then, the gate dielectric layer 82 and the gate electrode 88 formed on the interlayer dielectric layer 65 are planarized by using, for example, chemical mechanical polishing until the top surface of the interlayer dielectric layer 65 is exposed.

[0116] After the planarization operation, the gate electrode 88 is recessed, and a cap insulating layer 90 is formed on the recessed gate electrode 88. Fig.13 In some embodiments, the cap insulating layer 90 includes one or more layers of silicon nitride-based materials, such as silicon nitride. The cap insulating layer 90 can be formed by depositing an insulating material and then performing a planarization operation.

[0117] In certain embodiments of the present disclosure, one or more work function adjustment layers (not shown) are inserted between the gate dielectric layer 82 and the gate electrode 88. The work function adjustment layer is made of a conductive material, such as a single layer of titanium nitride, tantalum nitride, tantalum aluminum carbide (TaAlC), titanium carbide (TiC), tantalum carbide (TaC), cobalt, aluminum, titanium aluminum, hafnium titanium (HfTi), titanium silicide (TiSi), tantalum silicide (TaSi), or titanium aluminum carbide (TiAlC), or multiple layers of two or more of these materials. For an n-channel field effect transistor, one or more of tantalum nitride, tantalum aluminum carbide, titanium nitride, titanium carbide, cobalt, titanium aluminum, hafnium titanium, titanium silicide, and tantalum silicide are used as the work function adjustment layer, and for a p-channel field effect transistor, one or more of tungsten nitride, tungsten carbonitride (WCN), tungsten, ruthenium, cobalt, titanium nitride, or titanium silicide nitride (TiSiN) are used as the work function adjustment layer. The work function adjustment layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation or other suitable processes. In addition, the work function adjustment layer may be formed separately for n-channel field effect transistors and p-channel field effect transistors that may use different metal layers.

[0118] Subsequently, a contact hole 110 is formed in the interlayer dielectric layer 65 by using dry etching, as shown in FIG. Fig.14 In some embodiments, the upper portion of the source / drain epitaxial layer 50 is etched.

[0119] A silicide layer 120 is formed on the source / drain epitaxial layer 50, such as Fig.15 As shown. The silicide layer 120 includes one or more of tungsten silicide (WSi), cobalt silicide (CoSi), nickel silicide (NiSi), titanium silicide (TiSi), molybdenum silicide (MoSi) and tantalum silicide (TaSi). Then, a conductive material 130 is formed in the contact hole 110, such as Fig.16 The conductive material 130 includes one or more of cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, and tantalum nitride.

[0120] It should be understood that the FinFET undergoes additional CMOS processes to form various features, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

[0121] FIG. 17A to FIG. 19G The following is a sequential process for gate replacement operation according to an embodiment of the present disclosure. It should be understood that FIG. 17A to FIG. 19G Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is interchangeable. The materials, processes, methods, dimensions, and / or configurations explained by the previous embodiments may be applied to the following embodiments, and their detailed descriptions may be omitted.

[0122] 17A to 17D Various diagrams are shown after removing the sacrificial gate structure (sacrificial gate electrode layer 44 and sacrificial gate dielectric layer 42), thereby forming a gate space 49, as shown in FIG. Fig.12 described. Fig.17A For along Fig.17D A cross-sectional view (plan view or projection view) of the line X1-X1, Fig. 17B For along Fig.17D A cross-sectional view of the line Y1-Y1, and Fig. 17C For along Fig.17D . In some embodiments, an insulating liner layer 60 serving as an etch stop layer is formed before forming the interlayer dielectric layer 65. In some embodiments, the insulating liner layer 60 includes silicon nitride. In some embodiments, an additional dielectric layer 66 is formed on the interlayer dielectric layer 65. In some embodiments, the additional dielectric layer 66 includes silicon nitride.

[0123] In some embodiments, the upper portion of the recessed gate sidewall spacer 45, such as Fig. 17B and Fig. 17C In some embodiments, the gate sidewall spacer 45 is recessed during the removal of the sacrificial gate dielectric layer, and in other embodiments, one or more dry and / or wet etching operations are performed to recess the gate sidewall spacer 45. In some embodiments, after recessing the gate sidewall spacer 45, the uppermost surface is made of only silicon nitride-based material (e.g., silicon nitride) (insulating liner layer 60 and dielectric layer 66).

[0124] FIG. 18A to FIG. 19G 17B or 17C is an enlarged view of the gate space 49 and the surrounding layer. Fig.18A As shown, an interface layer 81 is formed on the channel region of the fin structure 20, and a gate dielectric layer 82 is formed on the interface layer 81 and the inner wall of the gate sidewall spacer 45. In some embodiments, the gate dielectric layer 82 is formed on the upper surface of the insulating liner layer 60 and the additional dielectric layer 66. In some embodiments, the gate dielectric layer 82 is formed by an atomic layer deposition process to conformally form a layer on a high aspect ratio structure. In some embodiments, the aspect ratio (height / bottom diameter or area) of the gate space 49 is in the range of about 7 to about 25.

[0125] Then, if Fig.18BAs shown, a barrier layer 83 is formed on the gate dielectric layer 82. In some embodiments, the barrier layer 83 comprises one or more layers of tantalum, tantalum nitride, titanium, titanium nitride, or titanium nitride silicon. In some embodiments, the thickness of the barrier layer 83 is in the range of about 1 nanometer to about 3 nanometers. In some embodiments, the barrier layer 83 is not formed. In some embodiments, the thickness of the bottom of the barrier layer 83 is thicker than the thickness of the side. In some embodiments, the thickness of the bottom of the barrier layer 83 is about 0.5 times to 3 times the thickness of the side.

[0126] In addition, if Fig.18C As shown, one or more first work function adjustment material (WFM) layers 84 are formed on the barrier layer 83. In some embodiments, the first work function adjustment material layer 84 is a p-type work function adjustment material, such as tungsten nitride, tungsten carbonitride, tungsten, ruthenium, cobalt, titanium nitride, or titanium nitride silicon. In some embodiments, the thickness of the first work function adjustment material layer 84 is in the range of about 0.5 nanometers to about 10 nanometers, and in other embodiments, in the range of about 1 nanometer to about 2 nanometers. In some embodiments, the thickness of the bottom of the first work function adjustment material layer 84 is about 0.8 to 2 times the thickness of the side. When the first work function adjustment material layer is made of titanium nitride, the titanium nitride layer is formed from a source gas containing titanium tetrachloride (TiCl4) and ammonia (NH3). In some embodiments, the titanium nitride layer contains chlorine as an impurity. In some embodiments, the titanium concentration in the titanium nitride layer is in the range of about 10 atomic percent to about 80 atomic percent. When the titanium concentration is too small, the resistance of titanium nitride increases, and when the titanium concentration is too high, titanium diffusion may cause various problems (eg, punch-through).

[0127] Then, if Fig.18D As shown, the upper portion of the first work function adjustment material layer 84 is removed so that the uppermost portion of the first work function adjustment material layer 84 is lower than the uppermost portion of the insulating liner layer 60 and the additional dielectric layer 66. In some embodiments, the uppermost portion of the first work function adjustment material layer 84 is lower than the uppermost portion of the gate sidewall spacer 45, and in other embodiments, the uppermost portion of the first work function adjustment material layer 84 is equal to or higher than the uppermost portion of the gate sidewall spacer 45 and lower than the uppermost portion of the insulating liner layer 60 and the additional dielectric layer 66 (see Fig. 17B ).

[0128] In addition, if Fig.18EAs shown, one or more second work function adjustment material layers 85 are formed on the first work function adjustment material layer 84. In some embodiments, the second work function adjustment material layer 85 is an n-type work function adjustment material, such as titanium aluminum, titanium silicon aluminum (TiSiAl), titanium aluminum carbide, tantalum aluminum (TaAl), or tantalum aluminum carbide. In some embodiments, the thickness of the second work function adjustment material layer 85 is in the range of about 0.5 nanometers to about 6 nanometers, and in other embodiments, in the range of about 2 nanometers to about 5 nanometers. In some embodiments, the thickness of the bottom of the second work function adjustment material layer 85 is the same as the thickness of the side or up to 3 times the thickness of the side.

[0129] When the second work function adjustment material layer 85 is made of titanium aluminum carbide, the titanium aluminum carbide layer is formed from a source gas containing titanium tetrachloride and organic aluminum (e.g., triethylaluminum). In some embodiments, the titanium aluminum carbide layer contains chlorine as an impurity. In some embodiments, the aluminum concentration in the titanium aluminum carbide layer is in the range of about 5% to about 80% by weight. When the aluminum concentration is too low, the resistance of the titanium aluminum carbide layer increases, and when the aluminum concentration is too high, aluminum diffusion may cause various problems (e.g., threshold voltage (Vt) shift). In some embodiments, the p-type field effect transistor includes both the p-type work function adjustment material and the n-type work function adjustment material, such as Fig.18E As shown, the n-type field effect transistor does not include the first work function adjustment material layer (p-type work function adjustment material) 84 (see Fig.19F ). In some embodiments, similar to Fig.18D The explained operation removes the upper portion of the second work function adjusting material layer 85 .

[0130] After forming the work function adjustment material layers 84 and 85, a blocking metal layer 86 is formed on the work function adjustment material layers using one or more deposition and chemical mechanical polishing operations. The blocking metal layer 86 may also be referred to as a glue layer. Fig.18F As shown. In some embodiments, the blocking metal layer 86 includes one or more of tantalum, tantalum nitride, titanium, titanium nitride, or titanium nitride silicon. In some embodiments, titanium nitride is used. In other embodiments, tungsten carbonitride is used. In some embodiments, none of the barrier layer 83, the first work function adjustment material layer 84, the second work function adjustment material layer 85, and the blocking metal layer 86 includes a metal tungsten layer containing more than 90% tungsten atomic percentage. In some embodiments, the thickness of the blocking metal layer 86 is in the range of about 3 nanometers to about 20 nanometers. As shown Fig.18FAs shown, when the gate dielectric layer 82, the barrier layer 83, and the work function adjustment material layers 84, 85 comprise a U-shaped cross-section (with a bottom and two vertical portions) in the Y direction (source to drain direction), the blocking metal layer 86 completely fills the gate space 49. In some embodiments, since the gate sidewall spacer 45 is recessed, the insulating liner layer 60 and the additional dielectric layer 66, both made of silicon nitride, are used as chemical mechanical polishing stop layers to perform chemical mechanical polishing. Therefore, silicon oxide or silicon oxide-based materials are not polished in the chemical mechanical polishing operation.

[0131] Then, if Fig.19A As shown, the upper portion of the layer formed in the gate space is recessed by one or more etching operations. In some embodiments, during the etching operation, the upper portion of the sidewall spacer 45 and / or the upper portion of the gate dielectric layer 82 is also etched. Fig.19A As shown, in some embodiments, the top of the blocking metal layer 86 is lower than the top of the first work function adjustment material layer 84 and the second work function adjustment material layer 85, and the top of the work function adjustment material layer is lower than the top of the gate dielectric layer 82. In other embodiments, the top of the blocking metal layer 86 is higher than the top of either or both of the work function adjustment material layers.

[0132] Then, if Fig.19B As shown, a contact metal layer 87 is formed on the recessed layer. In some embodiments, the contact metal layer 87 includes tungsten, tantalum, tin, niobium, ruthenium, cobalt or molybdenum. In some embodiments, the contact metal layer 87 is formed by an atomic layer deposition process using a metal halide (chloride) gas (e.g., tantalum pentachloride (TaCl5), tin tetrachloride (SnCl4), niobium pentachloride (NbCl5) or molybdenum tetrachloride (MoCl4)). In some embodiments, the contact metal layer 87 includes a fluorine-free metal, for example, fluorine-free tungsten formed by using tungsten pentachloride (WCl5) as a source gas. In some embodiments, the atomic layer deposition process is a selective deposition process combined with an etching process, so that the contact metal layer 87 grows from a metallic lower layer (such as a barrier layer, a work function adjustment material layer and a blocking metal layer), and no metal layer grows from a dielectric layer. Since the aspect ratio of the gate space 49 is high (e.g., 3 to 20) when forming the contact metal layer 87, the atomic layer deposition process using the metal halide gas effectively forms the contact metal layer 87 without forming a void. In addition, as the metal gate pitch decreases, the width of the gate space is insufficient to form an additional (e.g., sacrificial) layer. By using selective deposition just above the work function adjustment material layer, it is possible to reduce damage to the metal gate structure.

[0133] In some embodiments, the thickness T1 of the contact metal layer 87 is in the range of about 1 nanometer to about 10 nanometers. When the thickness of the contact metal layer 87 is too small, a gate contact made of tungsten formed later may not be sufficiently formed because the contact metal layer 87 may serve as a seed layer for the tungsten layer. When the thickness of the contact metal layer 87 is too large, the contact metal layer may be formed over the gate sidewall spacer 45, which may cause leakage. In some embodiments, the lowest portion of the upper surface of the contact metal layer 87 is located directly above the blocking metal layer 86. In some embodiments, the top of the contact metal layer 87 is lower than the top of the gate sidewall spacer 45.

[0134] In some embodiments, the thickness T2 of the contact metal layer 87 on the gate dielectric layer 82 (e.g., at the center of the thickness of the vertical portion of the gate dielectric layer) is in the range of about 0.1 nanometers to about 1 nanometer. When the thickness is too small, damage on the sidewall of the contact metal layer 87 may be caused, and when the thickness is too large, a seam may be formed in the contact metal layer 87.

[0135] In some embodiments, the deposition of the contact metal layer 87 includes a cleaning operation inserted between two or more deposition processes. In some embodiments, the cleaning operation includes hot water cleaning (eg, 80 degrees Celsius or higher) and / or oxygen treatment.

[0136] In the aforementioned embodiments, the thickness of the layer formed in the gate space is measured along the Z direction (the normal direction of the substrate surface) at the center of the gate space, unless otherwise specified.

[0137] In addition, if Fig.19C As shown, a gate cap insulating layer 90 is formed on the contact metal layer 87. In some embodiments, the gate cap insulating layer 90 includes silicon nitride, silicon oxynitride and / or silicon oxycarbon nitride or any other suitable material. Fig.19D Display corresponds to Fig.17D A cross-sectional view along line X1-X1 of Fig.19E Display corresponds to Fig.17D 19D, the barrier layer is omitted. Fig.19D As shown, the first work function adjustment material layer 84, the second work function adjustment material layer 85, the blocking metal layer 86 and the contact metal layer 87 (and optionally, the barrier layer 83) may be collectively referred to as a metal gate electrode 88. In some embodiments, as Fig.19D As shown, the lowest point of the upper surface of the contact metal layer 87 is located between two adjacent fin structures 20 .

[0138] In some embodiments, in the n-type field effect transistor, the first work function adjustment material layer (p-type material layer) is not formed, as shown in FIGS. 19F and 19G . Figure 19G Display corresponds to Fig.17D A cross-sectional view of the line X1-X1 above the isolation insulating layer. Figure 19G In the figure, the barrier layer is omitted. Figure 19G As shown, the second work function adjustment material layer 85 , the blocking metal layer 86 and the contact metal layer 87 (and optionally, the barrier layer 83 ) may be collectively referred to as a metal gate electrode 88 .

[0139] Fig. 20A , Fig. 20B and Fig. 20C A cross-sectional view is shown after the gate contact 145 is formed. Fig. 20A Display corresponds to Fig.17D A cross-sectional view of the fin structure 20 taken along line Y1-Y1, and Fig. 20B Display corresponds to Fig.17D 4 is a cross-sectional view of the Y2-Y2 line on the isolation insulating layer 30. Fig. 20C Shows a cross section along the X direction.

[0140] In some embodiments, after forming the gate cap insulating layer 90, a second interlayer dielectric layer 135 and a third interlayer dielectric layer 140 are formed, and a contact hole is formed on the contact metal layer 87 using one or more lithography and etching operations. Then, the contact hole is filled with one or more conductive materials to form a gate contact 145. In some embodiments, the gate contact 145 includes tungsten formed using tungsten hexafluoride (WF6) or tungsten tetrafluoride (WF4) as a source gas. In some embodiments, the gate contact 145 includes more impurities (e.g., fluorine, nitrogen, and / or oxygen) than the contact metal layer 87. After depositing tungsten, a chemical mechanical polishing operation is performed to remove excess tungsten from the upper surface of the third interlayer dielectric layer 140. Fig. 20A and Fig. 20B As shown, the edge portion of the sidewall spacer 45 in contact with the upper surface of the contact metal layer 87 is higher than the center of the upper surface of the contact metal layer 87. In some embodiments, the highest point of the contact metal layer 87 is located between the gate sidewall spacer 45 and the vertical portion of one of the barrier layer 83 and the work function adjustment material layer 84, 85. Fig. 20C In the X-direction cross section of FIG. 8 , the barrier layer 83 , the second work function adjustment material layer 85 and the blocking metal layer 86 are collectively referred to as the lower gate electrode 88A. Fig. 20C As shown, the lower gate electrode 88A not including tungsten has a wall shape (not a U-shape), and a contact metal layer 87 made of tungsten is formed on the lower gate electrode 88A.

[0141] like Fig. 20CAs shown, in some embodiments, one or more dummy fin structures 200 are formed between active fin structures 20 used in functional circuits. In some embodiments, the dummy fin structure 200 includes a lower layer 205, an intermediate layer 210, and an upper layer 215, all of which are made of one or more dielectric materials. In some embodiments, the lower layer 205 and the upper layer 215 include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or any other suitable material. In some embodiments, the intermediate layer 210 is made of a material different from the lower and upper layers and includes a high-k dielectric material, such as hafnium oxide, aluminum oxide, or any other suitable material.

[0142] In addition, in some embodiments, a separation plug (or wall) 230 is provided to physically and electrically isolate one metal gate electrode from an adjacent one, such as Fig. 20C As shown. In some embodiments, the separation plug 230 is formed by patterning a sacrificial gate electrode to form an opening and filling the opening with an insulating material. In some embodiments, the separation plug 230 is formed in a manner of contacting the top of the dummy fin structure 200. In other embodiments, the separation plug 230 is in contact with the isolation insulating layer 30. In some embodiments, the gate contact 145 is located above the fin structure 20, and in other embodiments, the gate contact 145 is located above the dummy fin structure 200.

[0143] like Fig.21 As shown, in some embodiments, the angle formed by the horizontal line and the line connecting the lowest portion of the upper surface of the contact metal layer 87 (or the intersection of the center line of the gate space and the upper surface of the contact metal layer) and the highest portion of the upper surface of the contact metal layer 87 is in the range of about 30 degrees to about 60 degrees. When the angle is too small, damage on the sidewall of the contact metal layer 87 may be caused, and it may be difficult to make the angle greater than 60 degrees by a known deposition technique.

[0144] When the distance between the center line of the gate space and the inner sidewall of the gate sidewall spacer 45 is the distance D2, the highest portion of the contact metal layer 87 is located at a distance D1 from the center of the gate space, wherein, in some embodiments, 0.7≤D1 / D2≤1.0. In other embodiments, 0.8≤D1 / D2≤0.95. When the highest portion is located within such ranges, the contact metal layer effectively protects the aluminum-containing second work function adjustment material layer 85 from the subsequent chemical mechanical polishing operation used to form the gate contact.

[0145] FIG. 22A to FIG. 22G The following is a sequential process for gate replacement operation according to an embodiment of the present disclosure. It should be understood that FIG. 22A to FIG. 22GAdditional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is interchangeable. The materials, processes, methods, dimensions, and / or configurations explained by the previous embodiments may be applied to the following embodiments, and their detailed descriptions may be omitted.

[0146] exist FIG. 22A to FIG. 22G In the invention, metal gate structures for narrow channel field effect transistors with gate lengths equal to or less than about 14 nanometers (and greater than, for example, about 5 nanometers) and long channel field effect transistors with gate lengths equal to or greater than 20 nanometers (and less than, for example, about 1 micrometer) are fabricated. FIG. 22A to FIG. 22G , two p-type narrow channel field effect transistors PMOS1 and PMOS2 with different threshold voltages (and with different work function adjustment materials), an n-type narrow channel field effect transistor NMOS1, and an n-type long channel field effect transistor NMOS2 are shown. However, the semiconductor device may include two or more n-type narrow channel field effect transistors, three or more p-type narrow channel field effect transistors, one or more p-type long channel field effect transistors, and / or two or more n-type long channel field effect transistors.

[0147] like Fig.22A As shown, similar to Fig.18C For the first p-type field effect transistor PMOS1 and the second p-type field effect transistor PMOS2, a first p-type work function adjustment material layer 84-1 and a second p-type work function adjustment material layer 84-2 are formed on the gate dielectric layer 82, respectively. No p-type work function adjustment material layer is formed for the n-type field effect transistors NMOS1 and NMOS2. In some embodiments, a barrier layer is formed before forming the work function adjustment material layer, similar to Fig.18B In some embodiments, the first p-type work function adjustment material layer 84-1 and the second p-type work function adjustment material layer 84-2 are made of different materials and / or different thicknesses. In some embodiments, the first p-type work function adjustment material layer 84-1 includes a titanium-based material (titanium nitride, titanium silicide, etc.), and the second p-type work function adjustment material layer 84-2 includes a tungsten-based material (tungsten nitride, tungsten carbonitride, tungsten, etc.).

[0148] Then, something like Fig.18D , remove the upper portions of the p-type work function adjustment material layers 84-1 and 84-2, so that the uppermost portion of the p-type work function adjustment material layer is lower than the uppermost portion of the etching stop layer (insulating liner layer 60) and the additional dielectric layer 66, as shown in FIG. Fig. 22B shown.

[0149] In addition, similar to Fig.18E, an n-type work function adjustment material layer 85 is formed for the p-type field effect transistors PMOS1, PMOS2 and the n-type field effect transistors NOMS1, NMOS2, such as Fig. 22C Then, similar to Fig.18F , using one or more deposition and chemical mechanical polishing operations, a blocking metal layer 86 is formed on the work function adjustment material layers 84-1, 84-2 and 85. The blocking metal layer 86 may also be referred to as a glue layer, such as Fig.22D In some embodiments, when the blocking metal layer 86 is conformally formed in the gate space of the long channel field effect transistor NMOS2 showing a U-shaped cross section, the blocking metal layer 86 completely fills the gate spaces of the narrow channel field effect transistors PMOS1, PMOS2, and NMOS1.

[0150] Then, if Fig.22E As shown, one or more conductive layers are formed on the blocking metal layer (glue layer) 86 in the long channel n-type field effect transistor NMOS2. In some embodiments, the conductive layer includes a tungsten layer 181 formed by an atomic layer deposition process and a tungsten layer 183 formed by a chemical vapor deposition process. In addition, a cap insulating layer 185 is formed on the conductive layer. The conductive layer and / or the cap insulating layer 185 are formed by one or more deposition and chemical mechanical polishing operations. In some embodiments, the cap insulating layer 185 includes silicon nitride.

[0151] Then, similar to Fig.19A , by recessing the upper portion of the layer formed in the gate space through one or more etching operations, such as Fig.22F In some embodiments, during the etching operation, the cap insulating layer 185 is not etched, thus protecting the tungsten layers 181 and 183 at the bottom of the cap insulating layer 185 .

[0152] Then, something like Fig.19B , a contact metal layer 87 is formed on the recessed structure, such as Figure 22G As shown. Subsequently, a gate cap insulating layer 90 is formed. Figure 22G Following the structure shown, one or more dielectric layers (eg, interlayer dielectrics) are formed over the contact metal layer 87 .

[0153] Various embodiments or examples described herein provide several advantages over the prior art. In the disclosed embodiments, since the gate space is completely filled with the blocking metal layer (glue layer), no seam is formed in the tungsten layer in the metal gate electrode. In addition, the tungsten layer formed on the recessed work function adjustment material layer can protect the work function adjustment material layer from the chemicals used in the chemical mechanical polishing operation performed subsequently.

[0154] It should be understood that not all advantages are necessarily discussed herein, that all embodiments or examples do not require a particular advantage, and that other embodiments or examples may provide different advantages.

[0155] According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode, a gate dielectric layer is formed in the gate space, a conductive layer is formed on the gate dielectric layer to completely fill the gate space, the gate dielectric layer and the conductive layer are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. The recessed gate electrode does not include a tungsten layer, and the contact metal layer includes tungsten. In one or more of the foregoing and following embodiments, at least one of the conductive layers has a U-shaped cross-section, and at least one of the conductive layers does not have a U-shaped cross-section. In one or more of the foregoing and following embodiments, at least one of the conductive layers that does not have a U-shaped cross-section includes titanium nitride or tungsten carbonitride. In one or more of the foregoing and following embodiments, the contact metal layer covers the top of the gate dielectric layer. In one or more of the foregoing and following embodiments, the upper surface of the contact metal layer has a convex shape toward the recessed gate electrode. In one or more of the foregoing and following embodiments, the convex shape has a slope with an angle between 30 degrees and 60 degrees. In one or more of the foregoing and following embodiments, the contact metal layer is formed by atomic layer deposition using a fluorine-free tungsten source gas.

[0156] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed on a substrate is formed, a sacrificial gate dielectric layer is formed on the fin structure, a sacrificial gate electrode layer is formed on the sacrificial gate dielectric layer, a gate sidewall spacer is formed, and one or more dielectric layers are formed; a gate space is formed by removing the sacrificial gate electrode layer and the sacrificial gate dielectric layer, and after forming the gate space, the gate sidewall spacer is recessed; a gate dielectric layer is formed in the gate space; a conductive layer is formed on the gate dielectric layer to completely fill the gate space, the gate dielectric layer and the conductive layer are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. In one or more of the foregoing and following embodiments, the one or more dielectric layers include an etch stop layer formed conformally on the side of the gate sidewall spacer, and an interlayer dielectric layer formed on the etch stop layer. In one or more of the foregoing and following embodiments, the interlayer dielectric layer includes a silicon oxide layer and a silicon nitride layer, both of which contact the etch stop layer. In one or more of the foregoing and following embodiments, the etch stop layer comprises silicon nitride. In one or more of the foregoing and following embodiments, a gate dielectric layer is formed on top of the recessed gate sidewall spacer, and the gate dielectric layer contacts the etch stop layer. In one or more of the foregoing and following embodiments, the contact metal layer is one of tungsten, tantalum, tin, niobium or molybdenum formed by a deposition method using a metal chloride gas. In one or more of the foregoing and following embodiments, a gate cap insulating layer is formed on the contact metal layer, one or more dielectric layers are formed on the gate cap insulating layer, and a gate contact of the contact metal layer is formed. In one or more of the foregoing and following embodiments, the contact metal layer comprises fluorine at a content lower than that of the gate contact.

[0157] According to another aspect of the present disclosure, a semiconductor device includes a fin structure protruding from an isolation insulating layer disposed on a substrate and having a channel region, a source / drain epitaxial layer, a gate dielectric layer on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode layer includes a lower portion and an upper portion, and the lower portion includes a conductive layer, at least one of the conductive layers has a U-shaped cross-section, and at least one of the conductive layers does not have a U-shaped cross-section. In one or more of the foregoing and following embodiments, the upper portion is made of tungsten. In one or more of the foregoing and following embodiments, the cross-section of the gate dielectric layer has a U-shape, and the upper portion covers the top of the U-shaped vertical portion of the gate dielectric layer. In one or more of the foregoing and following embodiments, the upper surface of the upper portion has a convex shape toward the lower portion, and the convex shape has a slope with an angle between 30 degrees and 60 degrees. In one or more of the foregoing and following embodiments, the semiconductor device also includes a gate contact that contacts the upper portion and has a higher fluorine concentration than the upper portion.

[0158] The foregoing summarizes the features of several embodiments or examples so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, but can be variously changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: Forming a gate space by removing a sacrificial gate electrode, wherein the gate space exposes a sidewall of a gate sidewall spacer; forming a gate dielectric layer in the gate space; forming a plurality of conductive layers on the gate dielectric layer to completely fill the gate space; recessing the gate dielectric layer and the plurality of conductive layers to form a recessed gate electrode; forming a contact metal layer on the recessed gate electrode, wherein the recessed gate electrode does not include a tungsten layer, and The contact metal layer comprises tungsten; and A gate cap insulating layer is formed on the contact metal layer and the gate sidewall spacer, wherein the gate cap insulating layer contacts a top surface of the gate sidewall spacer.

2. The method according to claim 1, characterized in that At least one of the conductive layers has a U-shaped cross section, and at least one of the conductive layers does not have a U-shaped cross section.

3. The method according to claim 2, characterized in that The at least one of the conductive layers that does not have the U-shaped cross section includes titanium nitride or tungsten carbonitride.

4. The method according to claim 1, characterized in that The contact metal layer covers a top portion of the gate dielectric layer.

5. The method according to claim 1, characterized in that An upper surface of the contact metal layer has a convex shape toward the recessed gate electrode.

6. The method according to claim 5, characterized in that The protrusion has a slope ranging from 30 degrees to 60 degrees.

7. The method according to claim 1, characterized in that The contact metal layer is formed by atomic layer deposition using a fluorine-free tungsten source gas.

8. A method for manufacturing a semiconductor device, characterized in that: Include: Forming a fin structure protruding from an isolation insulating layer disposed on a substrate; forming a sacrificial gate dielectric layer on the fin structure; forming a sacrificial gate electrode layer on the sacrificial gate dielectric layer; forming a plurality of gate sidewall spacers; forming one or more dielectric layers; forming a gate space by removing the sacrificial gate electrode layer and the sacrificial gate dielectric layer; After forming the gate space, recessing the plurality of gate sidewall spacers; forming a gate dielectric layer in the gate space; forming a plurality of conductive layers on the gate dielectric layer to completely fill the gate space; recessing the gate dielectric layer and the plurality of conductive layers to form a recessed gate electrode; forming a contact metal layer on the recessed gate electrode; as well as A gate cap insulating layer is formed on the contact metal layer and the plurality of gate sidewall spacers, wherein the gate cap insulating layer contacts the plurality of top surfaces of the plurality of gate sidewall spacers.

9. The method according to claim 8, characterized in that The one or more dielectric layers include an etch stop layer conformally formed on the sides of the gate sidewall spacers, and an interlayer dielectric layer formed on the etch stop layer.

10. The method according to claim 9, characterized in that The interlayer dielectric layer includes a silicon oxide layer and a silicon nitride layer, and both the silicon oxide layer and the silicon nitride layer are in contact with the etching stop layer.

11. The method according to claim 10, characterized in that The etch stop layer includes silicon nitride.

12. The method according to claim 9, characterized in that The gate dielectric layer is formed on a top portion of the recessed gate sidewall spacer and contacts the etch stop layer.

13. The method according to claim 9, characterized in that The contact metal layer is one of tungsten, tantalum, tin, niobium or molybdenum formed by a deposition method using a metal chloride gas.

14. The method according to claim 9, characterized in that Also includes: forming one or more dielectric layers on the gate cap insulating layer; and A gate contact is formed to contact the contact metal layer.

15. The method according to claim 14, characterized in that The contact metal layer contains fluorine at a content lower than that of the gate contact.

16. A semiconductor device, characterized in that: Include: A fin structure protrudes from an isolation insulating layer disposed on a substrate and has a channel region; a source / drain epitaxial layer; a gate dielectric layer disposed on the channel region; A gate electrode layer is disposed on the gate dielectric layer, wherein: The gate electrode layer includes a lower portion and an upper portion, and The lower portion includes a plurality of conductive layers, at least one of the plurality of conductive layers having a U-shaped cross-section, and at least one of the plurality of conductive layers not having a U-shaped cross-section; a gate sidewall spacer disposed on a sidewall of the gate electrode layer; and A gate cap insulating layer is disposed on the gate electrode layer and the gate sidewall spacer, wherein the gate cap insulating layer contacts a top surface of the gate sidewall spacer.

17. The semiconductor device according to claim 16, wherein: The upper portion is made of tungsten.

18. The semiconductor device according to claim 17, wherein: in: The gate dielectric layer has a U-shape in a cross section, and The upper portion of the gate electrode layer covers a top portion of a vertical portion of the U-shape of the gate dielectric layer.

19. The semiconductor device according to claim 16, wherein: in: An upper surface of the upper portion of the gate electrode layer has a convex shape toward the lower portion, and The protrusion has a slope ranging from 30 degrees to 60 degrees.

20. The semiconductor device according to claim 16, wherein The semiconductor device also includes a gate contact in contact with the upper portion of the gate electrode layer, wherein the gate contact has a fluorine concentration higher than that of the upper portion of the gate electrode layer.

Images