Space efficient and low parasitic half-bridge

Abstract

A packaged half-bridge circuit includes: a carrier having a dielectric core and a first metallization layer formed on an upper surface of the carrier; a first semiconductor chip and a second semiconductor chip, each semiconductor chip including a first terminal, a second terminal and a control terminal; and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first metallization layer. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first semiconductor chip and the second semiconductor chip is embedded in the dielectric core of the carrier. The conductive connector is electrically connected to one of the first terminal and the second terminal from one or both of the first semiconductor chip and the second semiconductor chip.

Description

Technical Field

[0001] The present application relates to semiconductor devices, and in particular to packaged voltage converters. Background Art

[0002] Power applications (i.e., applications utilizing voltages exceeding 250V, 500V, 1000V, etc. or more and / or currents exceeding 1A, 5A, 10A, etc. or more) typically employ circuits having semiconductor transistors. An example is a so-called half-bridge circuit, which is used in power converters, such as AC to DC, DC to DC, etc. A half-bridge circuit includes two switching devices connected in series. These switching devices can be implemented with semiconductor transistors, such as MOSFETs (metal oxide semiconductor field effect transistors), HEMTs (high electron mobility field effect transistors), IGBTs (insulated gate bipolar transistors), etc.

[0003] A half-bridge circuit for a power converter can be implemented in a single device package. In such a device package, an important design goal is to reduce the parasitic effects of the electrical connections of the circuit, i.e., resistance, inductance, capacitance, etc. Since the half-bridge circuit operates at high frequencies and conducts large currents, minimizing the parasitic effects of the electrical connections between the switching devices and the input / output terminals of the device advantageously reduces power consumption. However, known packaging configurations for half-bridge circuits have poor space efficiency and high parasitic effects. Summary of the invention

[0004] A packaged half-bridge circuit is disclosed. According to one embodiment, the packaged half-bridge circuit includes a carrier, a first semiconductor chip and a second semiconductor chip, and a conductive connector, the carrier including a dielectric core and a first metallization layer formed on an upper surface of the carrier, the first semiconductor chip and the second semiconductor chip each including a first terminal, a second terminal and a control terminal, and the conductive connector is mounted on the upper surface of the carrier and electrically connected to the first metallization layer. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first semiconductor chip and the second semiconductor chip is embedded in the dielectric core of the carrier. The conductive connector is electrically connected to one of the first terminal and the second terminal from one or both of the first semiconductor chip and the second semiconductor chip.

[0005] Alone or in combination, the half-bridge circuit further includes a driver chip electrically connected to control terminals of the first semiconductor chip and the second semiconductor chip, and the driver chip is disposed on or within the carrier.

[0006] Alone or in combination, a driver chip is mounted on the upper surface of the carrier.

[0007] Alone or in combination, the driver chip is embedded within the dielectric core of the carrier.

[0008] Alone or in combination, the packaged half-bridge circuit further includes a passive electrical component electrically connected to one or both of the high-side switch and the low-side switch, wherein the passive electrical component is disposed on or within the carrier.

[0009] Alone or in combination, a second semiconductor chip is embedded in the dielectric core of the carrier, a first terminal of the second semiconductor chip is arranged on a rear surface of the second semiconductor chip facing the upper surface of the carrier, and the first terminal of the second semiconductor chip is electrically connected to a first bonding pad formed in the first metallization layer.

[0010] Either individually or in combination, a first semiconductor chip is mounted on an upper surface of a carrier directly above a second semiconductor chip and directly above a first bonding pad, a second terminal of the first semiconductor chip is arranged on a main surface of the first semiconductor chip facing the upper surface of the carrier, and the second terminal of the first semiconductor chip is electrically connected to the first bonding pad.

[0011] Either individually or in combination, the first terminal of the first semiconductor chip is arranged on a rear surface of the first semiconductor chip facing away from the upper surface of the carrier, the conductive connector is electrically connected to the first terminal of the first semiconductor chip and a second bonding pad formed in the first metallization layer, and the second bonding pad is electrically connected to a voltage source terminal of the packaged half-bridge circuit.

[0012] Alone or in combination, the conductive connector is a metal clip secured to the first semiconductor chip and the second bonding pad by a conductive adhesive material.

[0013] Either individually or in combination, the carrier also includes a sixth bonding pad and a seventh bonding pad, each of which is formed in a first metallization layer, and the metal clip includes a first wing extending across a first edge side of the first semiconductor chip and reaching the second bonding pad, a second wing extending across a second edge side of the first semiconductor chip and reaching the sixth bonding pad, and a third wing extending across a third edge side of the first semiconductor chip and reaching the seventh bonding pad.

[0014] Alternatively or in combination, the packaged half-bridge circuit further comprises an electrically insulating package body formed on the upper surface of the carrier, the package body encapsulating the first semiconductor chip, and the upper surface of the metal clip is exposed from the upper surface of the package body.

[0015] Either individually or in combination, the first semiconductor chip and the conductive connector are integrated components of a discrete semiconductor device mounted on an upper surface of a carrier, the conductive connector is a lead frame of the discrete semiconductor device, the discrete semiconductor device is arranged such that the first semiconductor chip is disposed between the lead frame and the carrier, and the lead frame extends to and is in electrical contact with a second bonding pad.

[0016] Alternatively or in combination, the packaged half-bridge circuit further includes an electrically insulating package body formed on the upper surface of the carrier, the package body encapsulating the packaged semiconductor device, and an upper surface of the lead frame is exposed from the upper surface of the package body.

[0017] Alone or in combination, the first semiconductor chip is embedded in a dielectric core of a carrier, the second terminal of the first semiconductor chip is arranged on a main surface of the first semiconductor chip facing the upper surface of the carrier, and the conductive connector forms at least a part of the electrical connection between the second terminal of the first semiconductor chip and the output terminal of the packaged half-bridge circuit.

[0018] Either alone or in combination, the conductive connector is arranged such that current must flow through the conductive connector when flowing between the second terminal of the first semiconductor chip device and the output terminal of the packaged half-bridge circuit.

[0019] A method for producing a packaged half-bridge circuit is disclosed. According to one embodiment, the method includes: providing a carrier including a dielectric core and a first metallization layer formed on an upper surface of the carrier; providing a first semiconductor chip and a second semiconductor chip, each semiconductor chip including a first terminal, a second terminal and a control terminal; and mounting a conductive connector on the upper surface of the carrier and electrically connecting the conductive connector to the first metallization layer. The first semiconductor chip is configured as a high-side switch of the packaged half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the packaged half-bridge circuit. At least one of the first semiconductor chip and the second semiconductor chip is embedded in the dielectric core of the carrier. The conductive connector is electrically connected to one of the first terminal and the second terminal from one or both of the discrete first semiconductor switch device and the second semiconductor switch device.

[0020] Either alone or in combination, the method further includes embedding a second semiconductor chip in a dielectric core of a carrier such that a rear surface of the second semiconductor chip including a first terminal of the second semiconductor chip faces an upper surface of the carrier; mounting the first semiconductor chip on the upper surface of the carrier such that a rear surface of the first semiconductor chip including a first terminal of the first semiconductor chip faces away from the upper surface of the carrier; and electrically connecting the first terminal of the first semiconductor chip to a second bonding pad formed in the first metallization layer using a conductive connector.

[0021] Either alone or in combination, electrically connecting the first terminal of the first semiconductor chip to the second bonding pad includes attaching a metal clip to the first terminal of the first semiconductor chip and the second bonding pad.

[0022] Either alone or in combination, the method further includes providing a discrete semiconductor device comprising a first semiconductor chip mounted on a conductive lead frame; and mounting the discrete semiconductor device on an upper surface of a carrier, wherein the first semiconductor chip is disposed between the lead frame and the carrier, and wherein the lead frame extends to and is in electrical contact with a second bonding pad.

[0023] Either alone or in combination, the method further comprises embedding a second semiconductor chip in a dielectric core of a carrier such that a rear surface of the second semiconductor chip including a first terminal of the second semiconductor chip faces an upper surface of the carrier; embedding a first semiconductor chip in a dielectric core of a carrier such that a main surface of the first semiconductor chip including a second terminal of the first semiconductor chip faces an upper surface of the carrier; and mounting a metal clip on the upper surface of the carrier such that the metal clip forms at least a part of an electrical connection between the second terminal of the first semiconductor chip and an output terminal of the packaged half-bridge circuit, wherein the metal clip is a conductive connector.

[0024] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The elements in the drawings are not necessarily drawn to scale with respect to each other. The same reference numerals represent corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and detailed in the subsequent description.

[0026] Figure 1 An electrical schematic diagram showing a half-bridge circuit according to one embodiment;

[0027] Figure 2 shows a cross-sectional view of a packaged half-bridge circuit according to one embodiment;

[0028] Figure 3 shows a cross-sectional view of a packaged half-bridge circuit according to one embodiment;

[0029] Figure 4 shows a cross-sectional view of a packaged half-bridge circuit according to one embodiment;

[0030] Figure 5 According to one embodiment, Figure 4 A plan view of a packaged half-bridge circuit;

[0031] Figure 6 shows a cross-sectional view of a packaged half-bridge circuit according to one embodiment;

[0032] Figure 7 shows a cross-sectional view of a packaged half-bridge circuit according to one embodiment;

[0033] Figure 8 shows a cross-sectional view of a packaged half-bridge circuit according to one embodiment;

[0034] Fig. 9 shows a cross-sectional view of a packaged half-bridge circuit according to one embodiment;

[0035] Fig.10 A cross-sectional view of a packaged half-bridge circuit is shown according to one embodiment. DETAILED DESCRIPTION

[0036] Embodiments of packaged half-bridge circuits with advantageous space efficiency and low parasitic electrical connections are described herein. The packaged half-bridge circuit may include a carrier structure having a PCB (printed circuit board) configuration, i.e., a board having an insulating core and patterned conductive traces formed on or within the insulating core. The switches of the half-bridge circuit may be implemented by discrete semiconductor chips housed by the carrier. At least one of these discrete semiconductor chips may be embedded in the dielectric core of the carrier. This allows a short connection path to the output terminal of the half-bridge circuit. Another of the output connections of the half-bridge circuit may be provided by a low-resistance electrical connector mounted on the upper surface of the carrier. The electrical connector extends across a short span to reach its connection point. Therefore, both output connections have low resistance and / or inductance. At the same time, a smaller device area may be achieved by embedding at least one of the semiconductor chips in the carrier. In addition, the carrier of the PCB configuration allows other components of the half-bridge circuit (e.g., driver chips and passive components) to be integrated in one device package.

[0037] refer to Figure 1 , schematically depicting a half-bridge circuit 100 according to one embodiment. The half-bridge circuit 100 includes a high-side switch 102 and a low-side switch 104. The high-side switch 102 and the low-side switch 104 are connected in series between a fixed voltage source (e.g., a voltage of 200V, 500V, 1000V, etc.) and a reference potential (e.g., GND). The high-side switch 102 and the low-side switch 104 can be implemented by transistor devices. For example, in the depicted embodiment, the high-side switch 102 and the low-side switch are each implemented by an enhancement mode MOSFET device. The MOSFET devices are connected in series so that the source terminal of the high-side switch 102 is connected to the drain terminal of the low-side switch 104. The source terminal of the high-side switch 102 and the drain terminal of the low-side switch 104 are connected to the output terminal 105 of the half-bridge circuit 100. More generally, the high-side switch 102 and the low-side switch 104 can be implemented using a variety of different switching devices, such as MOSFETs (both enhancement and depletion modes), IGBTs, HEMTs, etc.

[0038] The half-bridge circuit 100 can be configured as a power converter, such as AC to AC, AC to DC, DC to DC. Power conversion is achieved by cycling the high-side switch 102 and the low-side switch 104 between the ON (conduction) and OFF (shutdown) states. To this end, the driver circuit 106 is connected to the control terminals of the high-side switch 102 and the low-side switch 104, that is, the gate terminals in the depicted MOSFET example. The driver circuit 106 cycles the high-side switch 102 and the low-side switch 104 between the ON and OFF states according to a timing scheme that is optimized for efficient power conversion while preventing harmful short-circuit events. An example of such a timing scheme is a so-called pulse width modulation (PWM) control scheme.

[0039] The half-bridge circuit 100 may include one or more passive components, such as capacitors, inductors, resistors, etc. In general, these passive components may be electrically connected to any node of the half-bridge circuit 100 and may be used for many different functions, such as high frequency filtering and decoupling, level shift biasing, managing device drive strength, managing ringing frequency, etc. In the depicted embodiment, the half-bridge circuit 100 includes a capacitor 108 connected between a voltage source and a reference potential. The capacitor 108 may have a relatively large capacitance value (e.g., 100 pF or greater) that is used to provide high frequency bias filtering.

[0040] refer to Figure 2 , depicts a packaged device 200 according to one embodiment. The packaged device 200 is a reference Figure 1 The half-bridge circuit 100 described herein is a discrete package implementation. That is, the packaged device 200 is configured to mate with an external device such as a PCB and provide a reference at the I / O connection of the external device. Figure 1 The power conversion function of the half-bridge circuit 100 is described.

[0041] The package device 200 includes a carrier 202. The carrier 202 includes a dielectric core 204 and one or more metallization layers. In the depicted embodiment, the carrier 202 includes a first metallization layer 206 formed on an upper surface of the carrier 202 and a second metallization layer 208 formed on a lower surface of the carrier 202 opposite the upper surface. In other embodiments, the carrier 202 may include one or more metallization layers within the dielectric core 204.

[0042] The dielectric core 204 may include various electrically insulating materials, such as plastics, ceramics, laminates, glass, pre-impregnated composite fibers, etc. In one embodiment, the dielectric core 204 has a thickness between about 250 and 500 μm (micrometers). The metallization layer may include a variety of conductive metals, such as copper, aluminum, nickel, gold, etc. and alloys thereof. In one embodiment, the metallization layers 206, 208 have a thickness between about 5 μm and 250 μm.

[0043] The carrier 202 may further include a via structure 210 extending vertically through the dielectric core 204 and forming an electrical connection to a device and / or a metallization layer.

[0044] In one embodiment, the carrier 202 has a configuration similar or identical to a commercial PCB (printed circuit board). In this embodiment, the dielectric core 204 includes a PCB dielectric material, such as FR-2, FR-3, FR-4, CEM-1, CEM-2, CEM-3. In addition, the metallization layers 206, 208 form conductive traces that form electrical interconnections between the various components housed by the carrier 202.

[0045] The carrier 202 includes a plurality of bonding pads formed in first and second metallization layers 206, 208. Each of these bonding pads is a flat metallization area that is configured as a contact surface for mating with an external conductive element (e.g., a bonding wire, a clip, a ribbon, an external bonding pad, etc.). In the depicted embodiment, the carrier 202 includes first and second bonding pads 212, 214 formed in the first metallization layer 206, and third, fourth, and fifth bonding pads 216, 218, and 220 formed in the second metallization layer 208. The depicted carrier 202 is configured for surface mount mating with an external device (e.g., a PCB), wherein the third, fourth, and fifth bonding pads 216, 218, and 220 form external I / O terminals that mate with and are electrically connected to corresponding I / O terminals in the external device. The third bonding pad 216 is configured as a voltage source terminal of the half-bridge circuit 100, the fourth bonding pad 218 is configured as a reference potential terminal of the half-bridge circuit 100, and the fifth bonding pad 220 is configured as the output terminal 105 of the half-bridge circuit 100. In each case, a conductive adhesive material 222 can be provided on these bonding pads to assist in surface mounting connections. At the upper surface of the carrier 202, the first and second bonding pads 212, 214 provide connection points to the opposite side terminals. Specifically, the first bonding pad 212 is electrically connected to the fifth bonding pad 220 (i.e., the output terminal) through the through-hole structure 210, and the second bonding pad 214 is electrically connected to the third bonding pad 216 (i.e., the voltage source terminal) through the through-hole structure 210.

[0046] The packaged device 200 further includes a first semiconductor chip 224 and a second semiconductor chip 226. The first semiconductor chip 224 is configured as the high-side switch 102 of the half-bridge circuit 100, while the second semiconductor chip 226 may be configured as the low-side switch 104 of the half-bridge circuit 100. Each of the first semiconductor chip 224 and the second semiconductor chip 226 includes a first terminal 228, a second terminal 230, and a control terminal 232. In each case, these terminals may be implemented as conductive bonding pads disposed on a main surface or a rear surface of the respective semiconductor chip.

[0047] In general, the first semiconductor chip 224 and the second semiconductor chip 226 can be configured as any of various discrete switching devices, such as MOSFET (metal oxide semiconductor field effect transistor), IGBT (insulated gate bipolar transistor), JFET (junction field effect transistor), etc., wherein the first terminal 228 and the second terminal 230 correspond to the load terminal (e.g., source, drain, collector, emitter, etc.), and the control terminal 232 is a terminal (e.g., gate, base, etc.) that controls the conductive connection between the load terminals. The first semiconductor chip 224 and the second semiconductor chip 226 can include any of a variety of semiconductor materials, for example, IV semiconductors such as silicon, silicon germanium, silicon carbide, etc., and III-V semiconductors such as gallium nitride, gallium arsenide, etc. According to one embodiment, the first semiconductor chip 224 and the second semiconductor chip 226 have a vertical device configuration. This means that the first terminal 228 and the second terminal 230 of the load current of the conductive device are arranged on the main surface and the rear surface of the opposite surface of the semiconductor chip, and these devices control the vertical current flowing between the upper surface and the lower surface of the opposite surface. Alternatively, the first semiconductor chip 224 and the second semiconductor chip 226 may have a lateral configuration.

[0048] According to one embodiment, the first semiconductor chip 224 and the second semiconductor chip 226 are each configured as a discrete MOSFET device. Specifically, the first semiconductor chip 224 and the second semiconductor chip 226 can be configured as discrete power MOSFETs, which are configured to block a considerable voltage (e.g., a voltage in the range of 100V, 500V, 1000V or more) and / or control a considerable current (e.g., a current in the range of 1A, 2A, 5A or more) between the corresponding first terminal 228 and the second terminal 230 of these chips. In these embodiments, the first terminal 228 of the first semiconductor chip 224 corresponds to the source terminal of the high-side switch 102, the second terminal 230 of the first semiconductor chip 224 corresponds to the drain terminal of the high-side switch 102, and the control terminal 232 of the first semiconductor chip 224 corresponds to the gate terminal of the high-side switch 102. Similarly, the first terminal 228 of the second semiconductor chip 226 corresponds to the source terminal of the low side switch 104, the second terminal 230 of the second semiconductor chip 226 corresponds to the drain terminal of the low side switch 104, and the control terminal 232 of the second semiconductor chip 226 corresponds to the gate terminal of the low side switch 104.

[0049] At least one of the first semiconductor chip 224 and the second semiconductor chip 226 is embedded within the dielectric core 204 of the carrier 202. This means that the chips are contained within the upper and lower surfaces of the carrier 202 and are at least laterally surrounded by the area of ​​the dielectric core 204. In the depicted embodiment, the second semiconductor chip 226 is embedded within the dielectric core 204 of the carrier 202.

[0050] One of the first semiconductor chip 224 and the second semiconductor chip 226 may be mounted on the carrier 202. This means that the semiconductor chips are arranged outside the upper and lower surfaces of the carrier 202 and are attached to the carrier 202 in a separate process step, for example by an adhesive such as solder, sinter, conductive glue, etc. In the depicted embodiment, the first semiconductor chip 224 is mounted on the upper surface of the carrier 202.

[0051] The package device 200 further includes a conductive connector 234. The conductive connector 234 is mounted on the surface of the carrier 202. That is, the conductive connector 234 is disposed outside the upper and lower surfaces of the carrier 202 and is attached to the carrier 202 in a separate process step, for example, by an adhesive such as solder, sinter, conductive glue, etc.

[0052] The conductive connector 234 is electrically connected to one of the first terminal 228 and the second terminal 230 from one or both of the first semiconductor chip 224 and the second semiconductor chip 226. In other words, the conductive connector 234 is connected to at least one terminal from one chip. For example, the conductive connector 234 can connect the high-side switch 102 to a voltage source, or connect the low-side switch 104 to a reference potential, or connect one or both of the high-side switch 102 and the low-side switch 104 to an output terminal.

[0053] In general, the conductive connector 234 may include various conductive materials, for example, metals such as copper, aluminum, gold, etc. and their alloys. In addition, the properties (e.g., thickness, geometry, etc.) of the conductive connector 234 may be appropriately adapted to meet application requirements including resistance, inductance, etc.

[0054] In the depicted embodiment, the conductive connectors 234 are configured as metal clips. This means that the conductive connectors 234 are metal pieces of substantially uniform thickness having a planar contact surface that are suitable for directly interfacing with the semiconductor chip and the bonding pads of the carrier 202. These metal clips may be provided from planar sheet metal processed according to techniques such as bending, punching, stamping, etc. In one embodiment, the conductive connectors 234 are metal clips having a thickness between about 100 μm and 250 μm.

[0055] In the depicted embodiment, the second semiconductor chip 226 is arranged such that the first terminal 228 of the second semiconductor chip 226 is disposed on a rear surface of the second semiconductor chip 226 facing the upper surface of the carrier 202. The first terminal 228 of the second semiconductor chip 226 is electrically connected to the first bonding pad 212 via a through-hole structure 210 extending through the dielectric core 204. The second terminal 230 of the second semiconductor chip 226 is disposed on a rear surface of the second semiconductor chip 226 facing the lower surface of the carrier 202. The second terminal 230 of the second semiconductor chip 226 is electrically connected to the fourth bonding pad 218 via a through-hole structure 210 extending through the dielectric core 204.

[0056] In the depicted embodiment, the first semiconductor chip 224 is arranged such that the first terminals 228 of the first semiconductor chip 224 are disposed on a rear surface of the first semiconductor chip 224 facing away from the upper surface of the carrier 202. The second terminals 230 of the first semiconductor chip 224 are disposed on a main surface of the first semiconductor chip 224 facing the upper surface of the carrier 202. The second terminals 230 of the first semiconductor chip 224 are electrically connected to the first bonding pads 212 via a conductive adhesive material 222 (e.g., solder, sinter, conductive glue, etc.).

[0057] Figure 2The arrangement and electrical connection of the packaged device 200 have significant benefits. Specifically, the vertical overlapping arrangement of the first semiconductor chip 224 and the second semiconductor chip 226 means that the first bonding pad 212 can be directly arranged between the drain terminal and the source terminal of the high-side switch 102 and the low-side switch 104 of the half-bridge circuit 100, respectively. As a result, there is a very short vertical current path for the load connection of the high-side switch 102 and the low-side switch 104. In addition, compared with the side-by-side configuration, the vertical stacking of the semiconductor chips advantageously reduces the lateral area required for the packaged half-bridge. At the same time, the conductive connector 234 advantageously provides a short conductive path between the source terminal of the high-side switch 102 and the second bonding pad 214 (i.e., the voltage source contact point). Due to the short connection distance, the thickness of the conductive connector 234 can be advantageously kept low (e.g., below 250 μm) to minimize the inductance while maintaining low resistance losses. Therefore, the packaged device 200 provides a low parasitic connection for multiple nodes of the half-bridge circuit 100.

[0058] The packaged device 200 may optionally include a driver chip 235. The driver chip 235 is a discrete semiconductor chip configured to provide the functionality of the driver circuit 106 of the half-bridge circuit 100. That is, the driver chip 235 is configured to operate the control terminals of the low-side switch 104 and the high-side switch 102 according to a timing control scheme (e.g., PWM). In the depicted embodiment, the control terminal 232 of the first semiconductor chip 224 (i.e., the gate of the high-side switch 102) is disposed on the main surface of the first semiconductor chip 224, and the control terminal 232 of the second semiconductor chip 226 (i.e., the gate of the low-side switch 104) is disposed on the main surface of the second semiconductor chip 226. In each case, these control terminals 232 can be electrically connected to a bonding pad, which in turn is electrically connected to one of the output terminals of the driver chip 235 through a conductive trace (not shown) formed in the carrier 202. In general, the driver chip 235 can be a logic chip, such as a silicon-based ASIC (application-specific integrated circuit).

[0059] The driver chip 235 may be disposed on or within the carrier 202. That is, the driver chip 235 is embedded within the carrier 202, for example in a manner similar to the second semiconductor chip 226, or is mounted on a surface of the carrier 202, for example in a manner similar to the first semiconductor chip 224. In the depicted embodiment, the driver chip 235 is mounted on an upper surface of the carrier 202.

[0060] The packaged device 200 may optionally include one or more passive components. The passive components may be disposed on or within the carrier 202. The passive components may be configured as described previously with reference to FIG. Figure 1The described approach is incorporated into the half-bridge circuit 100. For example, these passive components can be configured for DC blocking, ESD protection, impedance matching, etc. in the half-bridge circuit 100.

[0061] In the depicted embodiment, the packaged device 200 includes a discrete capacitor 236 embedded in the dielectric core 204. The discrete capacitor 236 corresponds to a reference potential connected between the voltage source terminal and the reference potential terminal. Figure 1 To this end, a discrete capacitor 236 is connected between the second bonding pad 214 and the fourth bonding pad 218 through the via structure 210 .

[0062] More generally, the passive components of the packaged device 200 may be implemented in a variety of different ways. For example, discrete components (e.g., capacitors, resistors, etc.) may be mounted on bonding pads formed on the upper or lower surface of the carrier 202. Alternatively, the passive components may be integrally formed features of the carrier 202. For example, the metallization of the carrier 202 may be configured with a desired geometry to provide a defined reactance, such as patterned conductive traces, radial stubs, parallel plate capacitors, etc.

[0063] refer to Figure 3 , depicts a packaged device 200 according to another embodiment. In addition to the driver chip 235 being embedded in the dielectric core 204 of the carrier 202, Figure 3 The packaged device 200 and Figure 2 The electrical connection between the driver chip 235 and the control terminals 232 of the first semiconductor chip 224 and the second semiconductor chip 226 can be implemented by conductive traces formed in the metallization layer of the carrier 202 in a similar manner as previously described. One advantage of this configuration is that by removing the driver chip 235 from the upper surface of the carrier 202, the size of the bonding pads and / or the conductive connectors 234 can be increased.

[0064] refer to Figure 4 and 5 , depicts a packaged device 200 according to another embodiment. In this embodiment, the conductive connector 234 is a metal clip having a multi-directional configuration. Figure 5As shown, the conductive connector 234 includes a first wing 238, a second wing 240, and a third wing 242. Each of these wings is arranged to carry current in different directions away from the first semiconductor chip 224. The conductive connector 234 is installed so that the first wing 238 extends across the first edge side 244 of the first semiconductor chip 224 and reaches the second bonding pad 214, the second wing 240 extends across the second edge side 246 of the first semiconductor chip 224 and reaches the sixth bonding pad 248, and the third wing 240 extends across the third edge side 250 of the first semiconductor chip 224 and reaches the seventh bonding pad 252. Figure 5 The outline of the semiconductor chip 224 is shown, as well as the outlines of the second, sixth and seventh bonding pads 214, 248, 252. The sixth and seventh bonding pads 248, 252 are each formed in the first metallization layer 206 and are electrically connected to the third bonding pad 216 (i.e., a voltage supply terminal) in a similar manner as the second bonding pad 214. Figure 4 and Figure 5 The multi-directional clamp design advantageously reduces the resistance associated with the voltage source connection of the high-side switch 102 of the half-bridge circuit 100 .

[0065] refer to Figure 6 , depicts a packaged device 200 according to another embodiment. In this embodiment, the packaged device 200 further includes an electrically insulating package body 254 formed on the upper surface of the carrier 202. Generally speaking, the package body 254 may include any of a variety of molding compounds, such as epoxy resins, thermosetting plastics, etc. The package body 254 may be formed by transfer molding techniques such as injection molding, compression molding, etc.

[0066] The package body 254 encapsulates the first semiconductor chip 224. That is, the package body 254 surrounds the first semiconductor chip 224 and protects the first semiconductor chip 224 from the external environment. The upper surface 256 of the conductive connector 234 is exposed from the upper surface 258 of the package body 254. One benefit of this configuration is enhanced heat dissipation. In this case, the conductive connector 234 (a metal clip in this embodiment) draws heat away from the first semiconductor chip 224 and toward the surface exposed to the external environment. An external heat sink structure (not shown) can be installed on the top of the package device 200 for improved heat dissipation.

[0067] refer to Figure 7, depicts a packaged device 200 according to another embodiment. In this embodiment, the first semiconductor chip 224 and the conductive connector 234 are integrated components of a discrete semiconductor device 300. Although in the previous embodiments, the first semiconductor chip 224 and the conductive connector 234 were provided separately and mounted to the carrier 202 at different times, in this embodiment, the two elements are initially provided together as a discrete semiconductor device 300, and the discrete semiconductor device 300 is then mounted to the carrier 202. The discrete semiconductor device 300 is provided to start with a conductive lead frame 302. The lead frame 302 can be provided from a metal sheet and constructed by known techniques (e.g., etching, stamping, etc.). The first semiconductor chip 224 is mounted on the lead frame 302 and electrically connected to the lead frame 302, for example, using a conductive adhesive such as solder or sinter. The resulting device (i.e., the discrete packaged device 300) is then placed on the carrier 202 and mounted to the carrier 202.

[0068] In this embodiment, the lead frame 302 of the discrete semiconductor device 300 provides a conductive connector 234. The discrete packaged device 300 is mounted on the carrier 202 so that the first semiconductor chip 224 is disposed between the lead frame 302 and the carrier 202. The second terminal 230 and the control terminal 232 of the first semiconductor chip 224 face the upper surface of the carrier 202 and can be electrically connected to the carrier 202 in a similar manner as previously described. The lead frame 302 extends to the pads of the first semiconductor chip 224 and is in electrical contact with the second bonding pad 214 in a similar manner as previously described. As shown, the carrier 202 may also include an eighth bonding pad 260 in the first metallization layer 206, which provides a second connection point to the voltage supply terminal.

[0069] refer to Figure 8 , depicts a packaged device 200 according to another embodiment. In addition to the packaged device 200 also including a package body 254, the packaged device 200 and Figure 2 The sealing body 254 can be the same as the device. Figure 6 The seal 254 in the embodiment of the present invention is substantially similar or identical. The upper surface 304 of the lead frame 302 is exposed from the upper surface 258 of the seal 254. Therefore, the lead frame 302 is exposed to the upper surface 258 of the seal 254. Figure 6 The metal clip discussed above provides a heat dissipation structure in a similar manner.

[0070] refer to Fig. 9, depicts a package device 200 according to another embodiment. Unlike the previously described embodiments, a first semiconductor chip 224 is embedded in a dielectric core 204 of a carrier 202. Therefore, in this embodiment, both the first semiconductor chip 224 and the second semiconductor chip 226 are embedded in the dielectric core 204. The first semiconductor chip 224 is arranged so that the first terminal 228 of the first semiconductor chip 224 is arranged on the rear surface of the lower surface of the first semiconductor chip 224 facing the carrier 202. The first terminal 228 of the first semiconductor chip 224 is electrically connected to the third bonding pad 216 (i.e., the voltage source terminal) through the through-hole structure 210. In addition, the first semiconductor chip 224 is arranged so that the second terminal 230 and the control terminal 232 of the first semiconductor chip 224 are arranged on the main surface of the upper surface of the first semiconductor chip 224 facing the carrier. The second terminal 230 of the first semiconductor chip 224 and the first terminal 228 of the second semiconductor chip 226 are each connected to the first bonding pad 212 through the through-hole structure 210.

[0071] exist Fig. 9 In the embodiment of the present invention, in addition to the first bonding pad 212, the conductive connector 234 provides an alternative current path for the output terminal of the half-bridge circuit 100. The conductive connector 234, which is implemented as a metal clip in the present embodiment, is directly mounted on the first bonding pad 212. In this case, a large area of ​​a conductive adhesive 222 such as solder, sinter, etc. can be provided on the first bonding pad 212, and a large surface area portion of the conductive connector 234 can be attached by the conductive adhesive 212. As a result, the resistance between the second terminal 230 of the first semiconductor chip 224 and the fifth bonding pad 220, i.e., the output terminal of the half-bridge circuit 100, is reduced.

[0072] refer to Fig.10 , depicts a packaged device 200 according to another embodiment. Except that the conductive connector 234 is not mounted on a continuous bonding pad structure, Fig.10 Examples and Fig. 9The embodiment of the present invention is the same. Instead, the carrier 202 includes a ninth bonding pad 262 directly above the first semiconductor chip 224. The ninth bonding pad 262 is formed in the first metallization layer 206. A gap is provided between the ninth bonding pad 262 and the first bonding pad 212 so that the two bonding pads are electrically isolated without external electrical connection. A separation area of ​​the conductive adhesive 222 is provided on the first and ninth bonding pads 212, 262, and the conductive connector 234 is electrically connected to both the first and ninth bonding pads 212, 262 via the conductive adhesive 222. As a result, the conductive connector 234 is arranged so that the current must flow through the conductive connector 234 when flowing between the second terminal 230 of the first semiconductor chip and the third bonding pad 220 (i.e., the output terminal of the half-bridge circuit 100). Therefore, the output connection of the high-side switch 102 has a low-impedance connection path.

[0073] As used herein, the terms “electrically connected,” “directly electrically connected,” and the like describe a permanent low-impedance connection between electrically connected elements, such as direct contact between the relevant elements or a low-impedance connection via metal and / or highly doped semiconductor.

[0074] For ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. are used to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the device in addition to those different from those depicted in the figures. In addition, terms such as "first", "second", etc. are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the specification, the same terms refer to the same elements.

[0075] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0076] Each embodiment is provided in an illustrative manner and is not intended to limit the present invention. For example, a feature shown or described as part of one embodiment may also be used on other embodiments or used in combination with other embodiments to produce another embodiment. The present invention is intended to include such modifications and variations. These embodiments are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps are represented by the same reference numerals in different drawings unless otherwise specified.

[0077] With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor by the accompanying drawings. Instead, the present invention is limited only by the appended claims and their legal equivalents.

Claims

1. A half-bridge circuit, comprising: a carrier including a dielectric core and a first metallization layer formed on an upper surface of the carrier; a first semiconductor chip and a second semiconductor chip, each semiconductor chip including a first terminal, a second terminal and a control terminal; as well as a conductive connector mounted on the upper surface of the carrier and electrically connected to the first metallization layer; The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. wherein at least one of the first semiconductor chip and the second semiconductor chip is embedded in the dielectric core of the carrier, wherein the conductive connector is electrically connected to one of the first terminal and the second terminal from one or both of the discrete first semiconductor switching device and the second semiconductor switching device, wherein the second semiconductor chip is embedded in the dielectric core of the carrier, wherein the first terminal of the second semiconductor chip is arranged on a rear surface of the second semiconductor chip, the rear surface of the second semiconductor chip faces the upper surface of the carrier, and wherein the first terminal of the second semiconductor chip is electrically connected to a first bonding pad formed in the first metallization layer, and wherein the first terminal of the first semiconductor chip is arranged on the rear surface of the first semiconductor chip, the rear surface of the first semiconductor chip is opposite to the upper surface of the carrier, wherein the conductive connector is electrically connected to the first terminal of the first semiconductor chip and a second bonding pad formed in the first metallization layer, and wherein the second bonding pad is configured as a power terminal of the half-bridge circuit.

2. The half-bridge circuit according to claim 1, wherein: The half-bridge circuit further includes a driver chip electrically connected to control terminals of the first semiconductor chip and the second semiconductor chip, and wherein the driver chip is disposed on or within the carrier.

3. The half-bridge circuit according to claim 2, wherein: The driver chip is mounted on the upper surface of the carrier.

4. The half-bridge circuit according to claim 2, wherein: The driver chip is embedded within the dielectric core of the carrier.

5. The half-bridge circuit according to claim 1, wherein: The half-bridge circuit further comprises a passive electrical component electrically connected to one or both of the high-side switch and the low-side switch, and wherein the passive electrical component is disposed on or within the carrier.

6. The half-bridge circuit according to claim 1, wherein: The first semiconductor chip is mounted on the upper surface of the carrier, and the first semiconductor chip is directly above the second semiconductor chip and directly above the first bonding pad, wherein the second terminal of the first semiconductor chip is arranged on the main surface of the first semiconductor chip, the main surface of the first semiconductor chip faces the upper surface of the carrier, and wherein the second terminal of the first semiconductor chip is electrically connected to the first bonding pad.

7. The half-bridge circuit according to claim 1, wherein: The conductive connector is a metal clip fixed to the first semiconductor chip and the second bonding pad by a conductive adhesive material.

8. The half-bridge circuit according to claim 7, wherein: The carrier also includes a third bonding pad and a fourth bonding pad, and the third bonding pad and the fourth bonding pad are each formed in the first metallization layer, wherein the third bonding pad and the fourth bonding pad are each configured as a power terminal of the half-bridge circuit, wherein the metal clip includes a first wing, a second wing and a third wing, the first wing extends across the first edge side of the first semiconductor chip and reaches the second bonding pad, the second wing extends across the second edge side of the first semiconductor chip and reaches the third bonding pad, and the third wing extends across the third edge side of the first semiconductor chip and reaches the fourth bonding pad.

9. The half-bridge circuit according to claim 7, further comprising an electrically insulating package formed on an upper surface of the carrier, wherein: The package body encapsulates the first semiconductor chip, and wherein an upper surface of the metal clip is exposed from an upper surface of the package body.

10. The half-bridge circuit according to claim 9, wherein: The first semiconductor chip and the conductive connector are integrated components of a discrete packaged semiconductor device mounted on the upper surface of the carrier, wherein the conductive connector is a lead frame of the discrete packaged semiconductor device, wherein the discrete packaged semiconductor device is arranged such that the first semiconductor chip is disposed between the lead frame and the carrier, and wherein the lead frame extends to and is in electrical contact with the second bonding pad.

11. The half-bridge circuit according to claim 10, further comprising an electrically insulating package formed on an upper surface of the carrier, wherein The package body encapsulates the discrete package semiconductor device, and wherein an upper surface of the lead frame is exposed from an upper surface of the package body.

12. The half-bridge circuit according to claim 1, wherein: The first semiconductor chip is embedded in a dielectric core of the carrier, wherein a second terminal of the first semiconductor chip is arranged on a main surface of the second semiconductor chip, the main surface of the second semiconductor chip faces the upper surface of the carrier, and wherein the conductive connector electrically connects the second terminal of the first semiconductor chip to the first terminal of the second semiconductor chip.

13. The half-bridge circuit according to claim 7, wherein: The metal clip is part of an electrically conductive connection through which current must flow when flowing between the second terminal of the first semiconductor chip and the first terminal of the second semiconductor chip.

14. A method for generating a half-bridge circuit, the method comprising: providing a carrier comprising a dielectric core and a first metallization layer formed on an upper surface of the carrier; providing a first semiconductor chip and a second semiconductor chip, each semiconductor chip including a first terminal, a second terminal and a control terminal; mounting a conductive connector on the upper surface of the carrier and electrically connecting the conductive connector to the first metallization layer; embedding the second semiconductor chip within the dielectric core of the carrier such that a rear surface of the second semiconductor chip including a first terminal of the second semiconductor chip faces an upper surface of the carrier; mounting the first semiconductor chip on the upper surface of the carrier so that a rear surface of the first semiconductor chip including the first terminals of the first semiconductor chip faces away from the upper surface of the carrier; as well as electrically connecting a first terminal of the first semiconductor chip to a second bonding pad formed in the first metallization layer using the conductive connector, The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. wherein at least one of the first semiconductor chip and the second semiconductor chip is embedded in a dielectric core of the carrier, and The conductive connector is electrically connected to one of a first terminal and a second terminal from one or both of the discrete first semiconductor switching device and the discrete second semiconductor switching device.

15. The method according to claim 14, wherein: Electrically connecting the first terminal of the first semiconductor chip to the second bonding pad includes attaching a metal clip to the first terminal of the first semiconductor chip and the second bonding pad.

16. The method of claim 14, further comprising providing a discrete packaged semiconductor device comprising the first semiconductor chip mounted on a conductive lead frame, wherein: The mounting of the first semiconductor chip and the electrical connection of the first terminal include mounting the discrete packaged semiconductor device on an upper surface of the carrier, wherein the first semiconductor chip is disposed between the lead frame and the carrier, and wherein the lead frame extends to and is in electrical contact with the second bonding pad.

17. The method according to claim 14, further comprising: embedding the second semiconductor chip within the dielectric core of the carrier such that a rear surface of the second semiconductor chip including a first terminal of the second semiconductor chip faces an upper surface of the carrier; embedding the first semiconductor chip within a dielectric core of the carrier such that a main surface of the first semiconductor chip including a second terminal of the first semiconductor chip faces an upper surface of the carrier; as well as mounting a metal clip on the upper surface of the carrier such that the metal clip electrically connects the second terminal of the first semiconductor chip to the first terminal of the second semiconductor chip, Wherein, the metal clip is the conductive connector.

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