Method of forming a semiconductor device

Abstract

A method of forming a semiconductor device includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench, and forming a hardmask (HM) layer in a space surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After recessing the gate WF layer, the method further includes removing the HM layer in the gate trench. After removing the HM layer, the method further includes depositing a metal layer in the gate trench.

Description

[0001] This application is a divisional application of patent application No. 201710061615.9 with the title "Semiconductor Device and Method of Forming a Semiconductor Device" and filed on January 26, 2017. TECHNICAL FIELD

[0002] The present disclosure relates to a method of forming a semiconductor device, and more particularly to a method of forming a metal gate for a field-effect transistor (FET). BACKGROUND

[0003] The semiconductor integrated circuit (IC) industry has experienced rapid growth. ICs have been used in many applications, such as personal computers, mobile phones, and digital cameras. The demand for smaller ICs with greater performance has increased the need for smaller features, which in turn has increased the complexity of processing and manufacturing ICs.

[0004] One development in some IC designs is the replacement of traditional polysilicon gates with high-k / metal gates (HK / MG). A typical HK / MG includes a high-k gate dielectric layer, a work function (WF) metal layer, and a low-resistance metal fill layer. This structure should improve transistor density and switching speed, while reducing switching power and gate leakage. As technology nodes continue to shrink, some difficulties arise in the fabrication of HK / MG. One of the difficulties is that the metal fill layer can have a small footprint, so the gate contact can not land properly on the metal fill layer. SUMMARY

[0005] A method of forming a semiconductor device includes receiving a device having a substrate and a first dielectric layer on the substrate, the first dielectric layer surrounding a gate trench; depositing a gate dielectric layer in the gate trench; depositing a gate work function layer in the gate trench on the gate dielectric layer; forming a hard mask layer in a space in the gate trench surrounded by the gate work function layer; recessing the gate work function layer such that a top surface of the gate work function layer in the gate trench is below a top surface of the first dielectric layer; after recessing the gate work function layer, removing the hard mask layer in the gate trench; and after removing the hard mask layer, depositing a metal layer in the gate trench.

[0006] The present disclosure further relates to a method of forming a semiconductor device, comprising: receiving a device, the device having a substrate, a gate spacer, and a first dielectric layer, the gate spacer on the substrate and providing a gate trench, the first dielectric layer on the substrate and surrounding the gate spacer; depositing a gate dielectric layer on a bottom and sidewalls of the gate trench; depositing a gate work function layer in the gate trench and on the gate dielectric layer; forming a hard mask layer on the substrate and filling a gap surrounded by the gate work function layer; etching the hard mask layer such that a top surface of the hard mask layer in the gate trench is below a top surface of the first dielectric layer; etching the gate work function layer such that a top surface of the gate work function layer in the gate trench is below a top surface of the first dielectric layer; etching the gate dielectric layer such that a top surface of the gate dielectric layer in the gate trench is below a top surface of the first dielectric layer; removing the hard mask layer in the gate trench, thereby providing a first gap surrounded by the gate work function layer and a second gap between respective top surfaces of the gate work function layer and the gate dielectric layer and the top surface of the first dielectric layer; and filling a metal layer in the first gap and the second gap.

[0007] The present disclosure further relates to a semiconductor device, comprising: a substrate; a first dielectric layer on the substrate and surrounding a gate trench; a gate dielectric layer on a bottom and sidewalls of the gate trench; a gate work function layer on the gate dielectric layer and in the gate trench, wherein a top surface of the gate work function layer is lower than a top surface of the first dielectric layer; and a metal layer filling a first gap in the gate trench and a second gap, wherein the first gap is surrounded by the gate work function layer and the second gap is between the top surface of the gate work function layer and the top surface of the first dielectric layer.

[0008] The present disclosure is described in detail below with reference to the attached drawing figures and specific embodiments, but it is to be understood that the application is not limited to the specifics of this description, which is to be exemplificative only. BRIEF DESCRIPTION OF DRAWINGS

[0009] The present disclosure is best understood from the following detailed description when read in connection with the accompanying drawing figures and specific embodiments. It is emphasized that various features are not to scale and are given for descriptive purposes only. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0010] Figure 1 A semiconductor device with a metal gate structure constructed in accordance with an embodiment of the present disclosure is described;

[0011] Figure 2A and Figure 2B Block diagrams of methods of forming semiconductor devices in accordance with various aspects of the present disclosure are shown;

[0012] Figure 3A A semiconductor device in accordance with an embodiment of the present disclosure is described; Figure 2A andFigure 2B partial perspective view of a semiconductor device during a fabrication phase of a method according to some embodiments;

[0013] Figure 3B , Figure 3C , Figure 3D , Figure 3D-1 , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K and Figure 3L illustrate cross-sectional views of a target semiconductor device formed according to a method according to some embodiments; Figure 2A and Figure 2B illustrate cross-sectional views of a target semiconductor device formed according to a method according to some embodiments;

[0014] Figure 4 block diagrams showing methods of forming semiconductor devices according to various aspects of the present disclosure; and

[0015] Figure 5A , Figure 5B and Figure 5C illustrate cross-sectional views of a target semiconductor device formed according to a method according to some embodiments. Figure 4 wherein reference numerals

[0016] 1 line

[0017]

[0018] 100 semiconductor device

[0019] 102 substrate

[0020] 104 fin

[0021] 104a source / drain region

[0022] 104b channel region

[0023] 106 isolation structure

[0024] 108 gate spacer

[0025] 110 dielectric layer

[0026] 112 gate trench

[0027] 114 interface layer

[0028] 116 gate dielectric layer

[0029] 118 work function layer

[0030] 120 spacer

[0031] 120-1 spacer ​

[0032] 122 hard mask layer

[0033] 124 spacer

[0034] 128 metal fill layer

[0035] 128L lower portion

[0036] 128U upper portion

[0037] 130 metal gate

[0038] 132 dielectric layer

[0039] 134 gate contact

[0040] 200 method

[0041] 202 operation

[0042] 204 operation

[0043] 206 operation

[0044] 208 operation

[0045] 210 operation

[0046] 212 operation

[0047] 214 operation

[0048] 216 operation

[0049] 218 operation

[0050] 220 operation

[0051] 222 operation

[0052] 400 method

[0053] 408 operation

[0054] D1 depth

[0055] D2 dimension

[0056] D3 dimension

[0057] S110 top surface

[0058] S116 top surface

[0059] S118 top surface

[0060] S122 top surface

[0061] S128 top surface

[0062] W1 dimension

[0063] W2 dimension

[0064] W3 dimension DETAILED DESCRIPTION

[0065] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of a first feature over or on a second feature in the following description can include embodiments in which the first feature is formed directly on the second feature, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0066] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0067] The present disclosure is generally directed to semiconductor devices and fabrication. In particular, the present disclosure is directed to metal gates for field-effect transistors (FETs), such as high-k / metal gate (HK / MG), and methods of forming metal gates.

[0068] Figure 1 A semiconductor device 100 having a metal gate 130 (enclosed by dashed lines) according to an embodiment of the present disclosure is shown. Reference is made to FIG. 1 for a detailed description of the semiconductor device 100. Figure 1The device 100 includes a substrate 102, a gate spacer 108 disposed on the substrate 102, and a dielectric layer 110 surrounding the gate spacer 108. The device 100 further includes a gate dielectric layer 116, a work function (WF) layer 118, and a metal fill layer 128 deposited in a space defined by the gate spacer 108. A lower portion of the metal fill layer 128 is surrounded by the WF layer 118. The gate dielectric layer 116, the WF layer 118, and the metal fill layer 128 are layers of a metal gate 130. In an embodiment, although not shown, the device 100 can include other features, such as an interface layer under the gate dielectric layer 116. The gate dielectric layer 116 can include a high-k dielectric material, thus making the metal gate 130 an HK / MG. The device 100 further includes another dielectric layer 132 on the gate spacer 108, the dielectric layer 110, and the gate trench 128. The device 100 further includes a gate contact 134 that penetrates the dielectric layer 132 and lands on the metal gate 130, specifically on the metal fill layer 128.

[0069] Still referring to Figure 1 A top surface of the metal fill layer 128 is higher than respective top surfaces of the gate dielectric layer 116 and the WF layer 118. The metal fill layer 128 has a relatively large footprint (viewed from a top view) compared to the gate dielectric layer 116 and the WF layer 118. Thus, the gate contact 134 directly contacts the metal fill layer 128, but does not directly contact the gate dielectric layer 116 or the WF layer 118. In an embodiment, the metal fill layer 128 includes a low-resistance metal. Due to the large footprint of the metal fill layer 128, the device 100 provides a low gate contact resistance. Specifically, the device 100 provides a lower gate contact resistance compared to a case where the metal fill layer 128 has a smaller footprint and the gate contact 134 directly contacts the WF layer 118 or the gate dielectric layer 116. Moreover, the large footprint of the metal fill layer 128 advantageously enlarges a process window for fabricating the gate contact 134.

[0070] Referring to Figure 2A and Figure 2B A method 200 of forming a semiconductor device, such as the device 100, according to various aspects of the present disclosure is shown. The method 200 is an example and is not intended to limit the present disclosure to anything less than what is expressly and implicitly set forth in the claims that follow this description. Additional operations can be provided before, during, and after the method 200, and some operations described can be replaced, eliminated, or rearranged, to implement additional embodiments of the method. The method 200 is described below in connection with Figures 3A to 3L the device 100. Figure 3A A perspective view of a portion of the semiconductor device 100 is shown, while Figures 3B to 3L A cross-sectional view along lineFigure 3A A cross-sectional view of a portion of the semiconductor device 100 along the "1-1" line.

[0071] As will be shown, device 100 is a finned FET device. This does not necessarily limit the embodiment to any device type, any number of devices, any number of regions, or any structure or region configuration. For example, the provided object can be applied in the manufacture of flat FET devices and other types of multi-gate FET devices to reduce gate contact resistance during gate contact fabrication and to extend the process window. Furthermore, device 100 can be an intermediate device manufactured during the processing of an IC or a portion thereof, which may include static random access memory (SRAM) and / or other logic circuitry, passive components (such as resistors, capacitors, and inductors) and active components (such as p-type FETs (PFETs), n-type FETs (NFETs), finned FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors), other memory cells, and combinations thereof.

[0072] refer to Figure 2A At operation 202, method 200 provides or includes apparatus 100 in a processing state. (See common reference) Figure 3A and Figure 3B The device 100 includes a substrate 102, a fin 104 on the substrate 102, and an isolation structure 106 on the substrate 102. The fin 104 protrudes beyond the isolation structure 106. The fin 104 includes a channel region 104b and two source / drain regions 104a. In this embodiment, the device 100 further includes a gate spacer 108 disposed on the fin 104 and the isolation structure 106. In an alternative embodiment, the gate spacer 108 may be omitted. Further in this embodiment, the device 100 includes a dielectric layer 110 surrounding the gate spacer 108 (at least on its sidewalls). The inner sidewalls of the gate spacer 108 define a gate trench 112, which is substantially aligned with the channel region 104b along the "z" direction. Various elements of the device 100 are further described below.

[0073] In this embodiment, the substrate 102 is a silicon substrate. Alternatively, the substrate 102 can include another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In yet another alternative, the substrate 102 is a semiconductor-on-insulator (SOI) substrate. The substrate 102 can include epitaxial features, be strained to achieve performance enhancement, and / or have other suitable enhancement features.

[0074] The fins 104 include a semiconductor material and are suitable for forming finFET devices thereon, such as p-type finFETs or n-type finFETs. The fins 104 can be fabricated using suitable processes, including lithography and etching processes. The lithography processes can include forming a photoresist (photoresist) layer overlying the substrate 102, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask element including the photoresist. The mask element is then used to etch recesses into the substrate 102 while leaving the fins 104 remaining on the substrate 102. The etching processes can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process can implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases, and / or a plasma, and / or combinations thereof. For example, a wet etching process can include etching in a diluted hydrofluoric acid (DHF); a potassium hydroxide (KOH) solution; an ammonia solution; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH), or other suitable wet etchants. In some embodiments, the fins 104 can be formed by a double-patterning lithography (DPL) process. Numerous other embodiments of methods of forming the fins 104 on the substrate 102 can be suitable.

[0075] The isolation structure 106 can be formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. In one embodiment, the isolation structure 106 is formed by etching a trench in the substrate 102, e.g., as part of a process to form the fins 104. The trench can then be filled with an insulating material, followed by a chemical mechanical planarization (CMP) process. The isolation structure 106 can also include field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures. The isolation structure 106 can include a multi-layer structure, e.g., with one or more thermal oxide liner layers.

[0076] The gate spacers 108 can include silicon oxide, silicon nitride, silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon carbon oxynitride (SiCON), or other suitable dielectric materials. The gate spacers 108 can be formed by deposition and etching processes. The deposition process can be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition techniques. In one example, the etching process can be an anisotropic dry etching process. In an embodiment in which the method 200 includes a gate replacement process, the gate spacers 108 are first formed on the sidewalls of dummy gates, and the dummy gates are then removed, providing the gate trenches 112 between the opposing sidewalls of the gate spacers 108. The gate trenches 112 have a dimension Wl along the "x" direction, which is also the channel length direction. The value of the dimension Wl depends on the type of finFET device 100 (e.g., SRAM device or logic device) and the process node used to form the finFET device 100 (e.g., 22 nm, 10 nm, 7 nm, etc.).

[0077] The dielectric layer 110 can include one or more dielectric materials, such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The dielectric layer 110 can be deposited by plasma enhanced CVD (PECVD) process, flowable CVD (FCVD), or other suitable deposition techniques. In one embodiment, the device 100 further includes an etch stop layer (not shown) under the dielectric layer 110, and the etch stop layer can include silicon nitride, silicon oxide, silicon oxynitride, and / or other materials.

[0078] At operation 204, the method 200 Figure 2A deposits a gate dielectric layer 116 in the gate trench 112. Referring to Figure 3C , the gate dielectric layer 116 is deposited on the bottom and sidewall surfaces of the gate trench 112. In the present embodiment, the method 200 deposits an interface layer 114 in the gate trench 112 and on the channel region 104b prior to depositing the gate dielectric layer 116. The interface layer 114 can include a dielectric material, such as a silicon oxide layer (SiO2) or silicon oxynitride (SiON), and can be formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable techniques. In an alternative embodiment, the interface layer 114 is omitted.

[0079] Continuing with the present embodiment as shown in Figure 3C , the gate dielectric layer 116 is deposited on the interface layer 114. The gate dielectric layer 116 can include a high-k dielectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal oxides, or combinations thereof. The gate dielectric layer 116 can be formed by ALD and / or other suitable methods.

[0080] At operation 206, the method 200 Figure 2A deposits a gate WF layer 118 on the bottom and sidewalls of the gate trench 112. Referring to Figure 3DThe gate WF layer 118 is deposited on the gate dielectric layer 116 and partially fills the gate trench 112. Depending on the type of finFET 100, the gate WF layer 118 can be a p-type or n-type work function layer. A p-type work function layer includes a metal with a sufficiently large effective work function selected from, but not limited to, the group consisting of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. An n-type work function layer includes a metal with a sufficiently low effective work function selected from, but not limited to, the group consisting of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), or combinations thereof. The gate WF layer 118 can include multiple layers and can be deposited by CVD, PVD, and / or other suitable processes. In one embodiment, the method 200 performs a CMP process to remove excess material of the gate dielectric layer 116 and the gate WF layer 118 outside of the gate trench 112, thereby planarizing the top surface of the device 100.

[0081] Still referring to Figure 3D , the gate WF layer 118 provides a gap 120 having a dimension W2 along the "x" direction. As will be shown later, a metal fill layer, such as the metal fill layer 128 of Figure 1 , will be deposited into the gap 120. In the present embodiment, the width W2 is equal to or greater than a critical dimension for depositing the metal fill layer 128. As process nodes become smaller, the gap 120 can also become smaller. As Figure 3D-1 indicated, in one example, after depositing the gate WF layer 118, the gap 120-1 as surrounded by the gate WF layer 118 has a dimension W3 that is less than the critical dimension. Thus, the metal fill layer 128 can not be properly filled into the gap 120-1 because its profile is narrow. Continuing with this example, the method 200 expands the gap 120-1 via a patterning and etching process such that the gap 120-1 is enlarged, as shown in Figure 3D . The patterning process can include lithography, and the etching process can be selectively adapted to etch the gate WF layer 118.

[0082] At operation 208, the method 200 Figure 2A deposits a hard mask (HM) layer 122 on the layers 108, 110, 116, and 118 and fills the gap 120. Referring to Figure 3EThe HM layer 122 may include a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiCON), silicon oxynitride (SiON), other suitable dielectric materials, or combinations thereof. The HM layer 122 may be formed by ALD, thermal oxidation, chemical oxidation, CVD, PVD, or other deposition techniques. In one embodiment, the HM layer 122 is a photoresist and is formed by a process including spin coating. In various embodiments, the HM layer 122 has etch selectivity relative to the gate spacer 108, dielectric layer 110, gate dielectric layer 116, and work function layer 118. In one embodiment, the HM layer 122 is deposited on the entire surface of the device 100, which includes both PFETs and NFETs.

[0083] At operation 210, method 200 ( Figure 2A HM layer 122 was etched back. (Reference) Figure 3F Remove portions of the HM layer 122 covering the gate spacer 108, dielectric layer 110, gate dielectric layer 116, and work function layer 118. Furthermore, remove portions of the HM layer 122 within the spacer 120. Figure 3D The HM layer 122 is recessed such that the top surface S122 of the HM layer 122 is located below the top surface S110 of the dielectric layer 110 by an dimension D1 along the "z" direction. In an embodiment where the device 100 includes both a PFET and an NFET, the HM layer 122 may be etched back into the PFET (or NFET) region while being protected by a masking element in the NFET (or PFET) region. This allows for independent tuning of the performance of the PFET and NFET. Such independent PFET and NFET tuning can be similarly applied in subsequent operations including operations 212, 214, 216, and 218, which are discussed later. In embodiments, operation 210 may use wet etching, dry etching, atomic layer etching (ALE), reactive ion etching, or other etch-back techniques. Furthermore, in one embodiment, operation 210 uses selective etching, adapted to etch the HM layer 122 while keeping the layer gate spacer 108, dielectric layer 110, gate dielectric layer 116, and work function layer 118 substantially unchanged. Moreover, the etching of the HM layer 122 is self-aligned, meaning that the HM layer 122 is etched without using a photolithography patterning process other than the independent adaptations of the PFET and NFET as described above. In one example, operation 210 may use a timer mode to control the depth D1.

[0084] In operation 212, method 200 ( Figure 2A This causes the gate WF layer 118 to be recessed in the gate trench 112. (Reference) Figure 3G This causes the gate WF layer 118 to be recessed so that the top surface S of the gate WF layer 118 is... 118a top surface S of the dielectric layer 110 110 along the "z" direction. From a top view, the respective top surfaces of the gate WF layer 118 / hard mask layer 122 and the top surface S 110 are separated by a gap 124 having a footprint that is larger than the footprint of the gap 120 Figure 3D . In embodiments, along the "z" direction, the surface S 118 may be higher or lower than the surface S 122 . Alternatively, the surface S 118 may be at substantially the same level as the surface S 122 . Operation 212 can include dry etching, wet etching, ALE, or other etching techniques. Moreover, operation 212 includes an etching process that is selectively adapted to etch the gate WF layer 118 while leaving the gate spacers 108, the dielectric layer 110, the gate dielectric layer 116, and the hard mask layer 122 substantially unchanged. The HM layer 122 protects the bottom surface and portions of the sidewalls of the gate WF layer 118 from the etching process. In one example, operation 212 can use a timer mode to control the dimension D2. As will be shown, the dimension D2 is related to the thickness Figure 1 of the metal fill layer 128. Moreover, the etching of the gate WF layer 118 is self-aligned, i.e., the gate WF layer 118 is recessed within the gate trench 112 without using a lithography patterning process.

[0085] At operation 214, the method 200 Figure 2B recesses the gate dielectric layer 116 in the gate trench 112. With reference to Figure 3H , the gate dielectric layer 116 is recessed such that a top surface S 116 of the gate dielectric layer 116 is located along the "z" direction a dimension D3 below the top surface S 110 . Operation 214 further expands the gap 124 along the "x" direction. In embodiments, along the "z" direction, the surface S 116 may be higher or lower than the surface S 118 . Alternatively, the surface S 116 may be at substantially the same level as the surface S 118 . Operation 214 can include dry etching, wet etching, ALE, or other etching techniques. Moreover, operation 214 includes an etching process that is selectively adapted to etch the gate dielectric layer 116 while leaving the gate spacers 108, the dielectric layer 110, the work function layer 118, and the hard mask layer 122 substantially unchanged. In one example, operation 214 can use a timer mode to control the dimension D3. As will be shown, in some embodiments, the dimension D3 is related to the thickness Figure 1). In addition, the etching of the gate dielectric layer 116 is self-aligned, i.e., the gate dielectric layer 116 is recessed within the gate trench 112 without using a lithography patterning process.

[0086] In one embodiment of the method 200, operation 214 is not performed, and the method 200 continues from operation 212 to operation 216 without recessing the gate dielectric layer 116. In another embodiment of the method 200, operations 212 and 214 are performed in one fabrication step, i.e., the gate WF layer 118 and the gate dielectric layer 116 are etched simultaneously. Continuing this embodiment, the layers 116 and 118 are etched using the same recipe that includes an etchant for both layers. For example, the recipe can use a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6) to etch the gate WF layer 118, and a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3) to etch the gate dielectric layer 116, simultaneously.

[0087] At operation 216, the method 200 Figure 2B ) removes the HM layer 122 from the gate trench 112. Referring to Figure 3I , the device 100 after the HM layer 122 is removed is shown. Within the gate trench 112, the device 100 includes the recessed gate WF layer 118 and the recessed gate dielectric layer 116. Spacers are provided in the gate trench 112 and include the spacers 120 and 124. In various embodiments, many aspects of operation 216 are similar to those of operation 210. In particular, operation 216 uses a selective etch that is adapted to etch the HM layer 122 while leaving the gate spacers 108, the dielectric layer 110, the gate dielectric layer 116, and the layer 118 substantially unchanged. Operation 216 can perform a cleaning process that cleans various surfaces surrounding the spacers 120 and 124.

[0088] At operation 218, the method 200 Figure 2B ) deposits a metal fill layer (or metal layer) 128 in the gate trench 112. Referring to Figure 3J , the metal fill layer 128 fills the spacers 120 and 124. The metal fill layer 128 can include aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials. The metal fill layer 128 can be deposited by CVD, PVD, electroplating, and / or other suitable processes. In one embodiment, operation 218 further includes a CMP process that removes excess metal material outside the gate trench 112 and planarizes a top surface of the device 100. Thus, a top surface S 128 of the metal fill layer 128 is substantially coplanar with the surface S 110 . Still referring to Figure 3J, the metal fill layer 128 has two portions: a lower portion 128L surrounded by the gate WF layer 118, and an upper portion 128U on the lower portion 128L and on the respective top surfaces S 118 and S 116 From a top view, the upper portion 128U has a larger footprint (or area) than the lower portion 128L.

[0089] At operation 220, the method 200 Figure 2B forms gate contacts 134 on the metal fill layer 128. Referring to Figure 3K , the gate contacts 134 penetrate the dielectric layer 132 and are in electrical contact with the metal fill layer 128. In an embodiment, operation 220 involves a variety of processes, including deposition, CMP, lithography, and etching processes. For example, operation 220 deposits a dielectric layer 132 on the gate spacers 108, the dielectric layer 110, and the metal fill layer 128, and performs a CMP process on the dielectric layer 132. The dielectric layer 132 can include a dielectric material similar to that of the dielectric layer 110, and can be deposited by a PECVD process, an FCVD process, or other suitable deposition technique. In an embodiment, the dielectric layer 132 can include one or more material layers. Subsequently, operation 220 forms openings in the dielectric layer 132 via a lithography patterning and etching process. The openings expose the metal fill layer 128. Due to the increased footprint of the metal fill layer 128, operation 220 has a larger process window in the lithography patterning process. Subsequently, operation 220 forms gate contacts 134 in the openings. As shown in Figure 3K , the gate contacts 134 fall completely on the metal fill layer 128. Since the metal fill layer 128 is a low-resistance material, the total gate contact resistance is reduced.

[0090] In an embodiment, the gate contacts 134 include a barrier layer and a gate via on the barrier layer. The barrier layer can include tantalum (Ta), tantalum nitride (TaN), or another suitable metal diffusion barrier material; can be deposited using CVD, PVD, ALD, or other suitable processes. The gate via uses a conductive material, such as aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), combinations thereof, or other suitable materials; and can be deposited using suitable processes, such as CVD, PVD, electroplating, and / or other suitable processes.

[0091] Figure 3L Another embodiment of the display device 100 that does not undergo operation 214 as discussed above. Referring to Figure 3L , in this embodiment, the upper portion 128U of the metal fill layer 128 is surrounded by the gate dielectric layer 116; thus, it has a smaller footprint compared to in Figure 3K . However, its footprint is still larger than that of the lower portion 128L.

[0092] At operation 222, the method 200 Figure 2B continues to other steps to complete fabrication of the device 100. For example, the operation 222 can form metal interconnects that connect various elements of the device 100 (e.g., p-type finFETs, n-type finFETs, other types of FETs, resistors, capacitors, and inductors) to form a complete IC.

[0093] Figure 4 A flowchart illustrating a method 400, which can be considered an embodiment of the method 200, is shown. Many aspects of the method 400 are similar to aspects of the method 200. Accordingly, a brief discussion of these aspects is provided below in connection with Figures 5A to 5C .

[0094] Referring to Figure 4 , the method 400 continues from operation 206 to operation 408, which deposits a HM layer 122 Figure 5A in the spacers 120 that are surrounded by the WF layer 118. In one embodiment, the operation 408 includes the operations 208 and 210, as discussed above, where the operation 210 only slightly recesses the HM layer 122 within the gate trenches 112 (i.e., the depth Dl is minimal). In another embodiment, the operation 408 includes the operation 208, which is used to deposit the HM layer 122 over the various gate spacers 108, dielectric layer 110, gate dielectric layer 116, and work function layer 118 (see Figure 3E ). And further includes the operation 210, which uses a CMP process to etch back the HM layer 122, such that a portion of the HM layer 122 remains in the gate trenches 112, as shown in Figure 5A .

[0095] The method 400 Figure 4 continues from operation 408 to operation 212, which recesses the WF layer 118 in the gate trenches 112, as shown in Figure 5B . Accordingly, the top surface S 118 is below the top surface S 110 . In this embodiment, the recessing of the WF layer 118 is self-aligned, i.e., without using photolithography patterning processes. This is an example where the surface S 118 is at (or below) the surface S 122 . Further, the operation 212 uses a selective etching process, as discussed in connection with Figure 3G .

[0096] The method 400 Figure 4 continues from operation 212 to operation 214, which recesses the gate dielectric layer 116 in the gate trenches 112, as shown in Figure 5C . Accordingly, the top surface S 116 is below the top surface S 110below. In this embodiment, the recessing of the gate dielectric layer 116 is self-aligned, i.e., without using lithography patterning processes. Furthermore, operation 214 uses the same selective etch process as discussed above with respect to Figure 3H In an embodiment, the method 400 can skip operation 214, as discussed above. In an alternative embodiment, the method 400 can perform operations 212 and 214 in one manufacturing step, as discussed above.

[0097] The method 400 continues to operation 216, which removes the HM layer 122 from the gate trench 112. In one embodiment, this is the same as operation 216 of the method 200, as discussed above. Thus, the device 100 provides the first spacer 120 and the second spacer 124, as shown in FIG. 2B. Thereafter, the method 400 continues to operation 218 to deposit the metal fill layer 128, as discussed above with respect to Figure 4 Figure 2B Figure 3I Figure 4 Figure 2B Figure 3J

[0098] While not intended to be limiting, one or more embodiments of the present disclosure provide numerous benefits for semiconductor devices and formation thereof. For example, embodiments of the present disclosure recess the gate work function layer and the gate dielectric layer prior to depositing the metal fill layer. The resulting metal fill layer has an increased upper portion, which provides a larger footprint compared to a typical metal gate. This advantageously enlarges the process window for the gate contact patterning process. This also advantageously reduces the gate contact resistance. Furthermore, the recessing of the gate work function layer and the gate dielectric layer is self-aligned, i.e., without using lithography patterning processes. Embodiments of the present disclosure can be easily integrated into existing manufacturing flows for improving metal gate processes and improving device performance.

[0099] In one example aspect, the present disclosure is directed to a method of forming a semiconductor device, including receiving a device having a substrate and a first dielectric layer on the substrate, the first dielectric layer surrounding a gate trench; the method further includes depositing a gate dielectric layer in the gate trench; the method further includes depositing a gate work function layer in the gate trench and on the gate dielectric layer; the method further includes forming a hard mask layer in a spacer in the gate trench and surrounded by the gate work function layer; the method further includes recessing the gate work function layer such that a top surface of the gate work function layer in the gate trench is below a top surface of the first dielectric layer; the method further includes, after recessing the gate work function layer, removing the hard mask layer in the gate trench. The method further includes, after removing the hard mask layer, depositing a metal layer in the gate trench.

[0100] ​​​​​​In some examples, the method discussed above further includes, prior to depositing the metal layer, recessing the gate dielectric layer such that a top surface of the gate dielectric layer in the gate trench is below a top surface of the first dielectric layer. In some examples, the method discussed above further includes forming a gate contact on the metal layer and electrically connected to the metal layer. In some examples, the method discussed above further includes recessing the gate work function layer includes a selective etch process adapted to etch the gate work function layer while leaving the first dielectric layer and the hardmask layer substantially unaltered. In some examples, the method discussed above further includes recessing the gate work function layer further recesses the gate dielectric layer such that a top surface of the gate dielectric layer in the gate trench is below a top surface of the first dielectric layer. In some examples, the method discussed above further includes removing the hardmask layer includes a selective etch process adapted to etch the hardmask layer while leaving the first dielectric layer, the gate dielectric layer, and the gate work function layer substantially unaltered. In some examples, the method discussed above further includes, prior to forming the hardmask layer, etching the gate work function layer to provide the spacing. In some examples, the method discussed above further includes forming the hardmask layer includes depositing a hardmask material on the substrate and filling the spacing; and etching back the hardmask material. In some examples, the method discussed above further includes etching back the hardmask material includes a selective etch process adapted to etch the hardmask material while leaving the first dielectric material, the gate dielectric material, and the gate work function material substantially unaltered. In some examples, the method discussed above further includes etching back the hardmask material includes a chemical mechanical planarization (CMP) process. In some examples, the method discussed above further includes the device further includes a gate spacer as sidewalls of the gate trench.

[0101] In another example aspect, the disclosure relates to a method of forming a semiconductor device. The method includes receiving a device having a substrate, a gate spacer on the substrate and providing a gate trench, and a first dielectric layer on the substrate and surrounding the gate spacer. The method further includes depositing a gate dielectric layer on a bottom and sidewalls of the gate trench, and depositing a gate work function layer in the gate trench and on the gate dielectric layer. The method further includes forming a hard mask layer on the substrate and filling a gap surrounded by the gate work function layer, and etching the hard mask layer such that a top surface of the hard mask layer in the gate trench is below a top surface of the first dielectric layer. The method further includes etching the gate work function layer such that a top surface of the gate work function layer in the gate trench is below a top surface of the first dielectric layer. The method further includes etching the gate dielectric layer such that a top surface of the gate dielectric layer in the gate trench is below a top surface of the first dielectric layer. The method further includes removing the hard mask layer in the gate trench, thereby providing a first gap surrounded by the gate work function layer and a second gap between respective top surfaces of the gate work function layer and the gate dielectric layer and the top surface of the first dielectric layer. The method further includes filling a metal layer in the first gap and the second gap.

[0102] In some examples, each of the etching of the hard mask layer and the removing of the hard mask layer in the above-discussed methods includes a selective etch process adapted to etch the hard mask layer while leaving the gate spacer, the first dielectric layer, the gate dielectric layer, and the gate work function layer substantially unchanged. In some examples, the etching of the gate work function layer in the above-discussed methods includes a selective etch process adapted to etch the gate work function layer while leaving the gate spacer, the first dielectric layer, and the hard mask layer substantially unchanged. In some examples, the etching of the gate work function layer and the etching of the gate dielectric layer in the above-discussed methods are performed in one fabrication step.

[0103] In another exemplary aspect, the disclosure relates to a semiconductor device. The semiconductor device includes a substrate; a first dielectric layer on the substrate and surrounding a gate trench; a gate dielectric layer on a bottom and sidewalls of the gate trench; and a gate work function layer on the gate dielectric layer in the gate trench, wherein a top surface of the gate work function layer is lower than a top surface of the first dielectric layer. The semiconductor device further includes a metal layer filling a first space and a second space in the gate trench, wherein the first space is surrounded by the gate work function layer and the second space is between the top surface of the gate work function layer and the top surface of the first dielectric layer. In some examples, the above-discussed device further includes a gate spacer as the sidewalls of the gate trench. In some examples, in the above-discussed device, a top surface of the gate dielectric layer is lower than the top surface of the first dielectric layer, and the metal layer fills a third space between the top surface of the gate dielectric layer and the top surface of the first dielectric layer. In some examples, in the above-discussed device, the gate dielectric layer includes a high-k dielectric material, and the metal layer includes one of aluminum (Al), tungsten (W), copper (Cu), and cobalt (Co). In some examples, the above-discussed device further includes a gate contact in direct contact with the metal layer, the gate contact not being in direct contact with the gate work function layer.

[0104] The foregoing outlines features of several embodiments so that a general appreciation of the aspects of the disclosure can be gained. It will be appreciated by those of ordinary skill in the art that they can readily choose equivalents for the aspects described and claimed herein without departing from the spirit and scope of the disclosure. Those of ordinary skill in the art will readily understand that the aspects and variations of the disclosure as set forth herein can be applied to any number of other system configurations and scenarios not explicitly described herein without departing from the spirit and scope of the disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that, Include: A receiving device having a substrate and a first dielectric layer disposed on the substrate and surrounding a gate trench. A gate dielectric layer is deposited in the gate trench; A gate work function layer is deposited in the gate trench and on the gate dielectric layer, wherein the gate work function layer surrounds a spacer located in the gate trench; The gate work function layer is etched to reduce the width and height of the gap adjacent to the gate work function layer in order to extend the gap laterally and downward, wherein the etching of the gate work function layer to reduce the width and height of the gap adjacent to the gate work function layer in order to extend the gap laterally and downward is performed by performing a photolithography patterning process. After the gap is extended laterally and downward, a hard masking layer is formed in the gap; The gate work function layer and the gate dielectric layer are recessed such that a top surface of the hard mask layer is higher than a top surface of the recessed gate dielectric layer, wherein the gate work function layer and the gate dielectric layer are recessed by performing a self-aligned etching process. After recessing the gate work function layer and the gate dielectric layer, the hard masking layer in the gate trench is removed; After removing the hard mask layer, a metal layer is deposited in the gate trench; as well as A gate contact is formed to directly contact the metal layer, wherein the gate contact is electrically connected to the metal layer, and wherein a top surface of the metal layer is larger than a bottom surface of the gate contact.

2. The method according to claim 1, characterized in that, The gate contact includes a barrier layer and a gate via on the barrier layer.

3. The method according to claim 2, characterized in that, The barrier layer contains tantalum or tantalum nitride, and the gate via contains aluminum, tungsten, copper, or cobalt.

4. The method according to claim 1, characterized in that, The recessed gate work function layer and the gate dielectric layer are controlled by a timer mode, which is used to control the recessed size of the gate work function layer and the recessed size of the gate dielectric layer.

5. The method according to claim 1, characterized in that, The recessed gate work function layer and the gate dielectric layer further cause the top surface of the gate work function layer in the gate trench to be lower than the top surface of the first dielectric layer.

6. The method according to claim 1, characterized in that, The recessed gate work function layer and the gate dielectric layer further ensure that the top surface of the gate dielectric layer and the top surface of the gate work function layer are at the same level.

7. The method according to claim 1, characterized in that, The recessing of the gate work function layer and the gate dielectric layer includes performing a selective etching process adapted to etch the gate work function layer and the gate dielectric layer while keeping the first dielectric layer and the hard mask layer unchanged.

8. The method according to claim 1, characterized in that, The device also includes a gate spacer to serve as multiple sidewalls of the gate trench.

9. The method according to claim 1, characterized in that, Before recessing the gate work function layer and the gate dielectric layer, the hard masking layer is recessed such that the top surface of the hard masking layer is higher than the top surface of the gate dielectric layer.

10. A method for forming a semiconductor device, characterized in that, Include: A receiving device has a substrate, a gate spacer and a first dielectric layer, the gate spacer being on the substrate and providing a gate trench, and the first dielectric layer being on the substrate and surrounding the gate spacer. A gate dielectric layer is deposited on a bottom and multiple sidewalls of the gate trench; A gate work function layer is directly deposited in the gate trench and on the gate dielectric layer, wherein the gate work function layer surrounds a spacer; The gate work function layer is etched to reduce the width and height of the gap adjacent to the gate work function layer in order to extend the gap laterally and downward, wherein the etching of the gate work function layer to reduce the width and height of the gap adjacent to the gate work function layer in order to extend the gap laterally and downward is performed by performing a photolithography patterning process. After the gap is extended laterally and downward, a hard mask layer is formed on the substrate and fills the gap surrounded by the gate work function layer; After forming the hard mask layer, the gate work function layer is recessed to expose one sidewall of the gate dielectric layer and one sidewall of the gate work function layer, wherein the gate work function layer is recessed by performing a self-aligned etching process. After recessing the gate work function layer, the hard masking layer in the gate trench is removed; After removing the hard masking layer in the gate trench, a metal layer is filled into the gate trench; as well as A gate contact is formed to directly contact the metal layer, wherein the gate contact is electrically connected to the metal layer, and wherein a top surface of the metal layer is larger than a bottom surface of the gate contact.

11. The method according to claim 10, characterized in that, It also includes: Before recessing the gate work function layer, the hard mask layer is etched such that a top surface of the hard mask layer in the gate trench is lower than a top surface of the first dielectric layer.

12. The method according to claim 10, characterized in that, The gate work function layer is recessed such that a top surface of the gate dielectric layer is higher than a top surface of the gate work function layer, and the top surface of the gate work function layer is higher than a top surface of the hard mask layer, forming a step difference between the top surface of the gate dielectric layer, the top surface of the gate work function layer, and the top surface of the hard mask layer.

13. The method according to claim 10, characterized in that, The metal layer is deposited such that a top surface of the gate spacer, a top surface of the metal layer, and a top surface of the first dielectric layer are at the same level.

14. The method according to claim 10, characterized in that, The gate work function layer is recessed such that a top surface of the gate spacer is higher than a top surface of the gate work function layer.

15. A method for forming a semiconductor device, characterized in that, Include: A gate trench is formed in a first dielectric layer, wherein the first dielectric layer is located on a substrate; A gate dielectric layer is deposited on a bottom and multiple sidewalls of the gate trench; A gate work function layer is directly deposited in the gate trench and on the gate dielectric layer, wherein the gate work function layer surrounds a spacer; The gate work function layer is etched to reduce the width and height of the gap adjacent to the gate work function layer in order to extend the gap laterally and downward, wherein the etching of the gate work function layer to reduce the width and height of the gap adjacent to the gate work function layer in order to extend the gap laterally and downward is performed by performing a photolithography patterning process. After the gap is extended laterally and downward, a hard masking layer is formed in the gap; After forming the hard mask layer in the spacing, the gate work function layer is recessed, wherein the gate work function layer is recessed by performing a self-aligned etching process. Remove the hard mask layer in the gate trench; A metal layer is filled into the gate trench; as well as A gate contact is formed to directly contact the metal layer, wherein the gate contact is electrically connected to the metal layer, and wherein a top surface of the metal layer is larger than a bottom surface of the gate contact.

16. The method according to claim 15, characterized in that, Before recessing the gate work function layer, the hard mask layer is etched such that one top surface of the hard mask layer is lower than one top surface of the gate work function layer.

17. The method according to claim 15, characterized in that, The metal layer is filled in such that it directly contacts the gate work function layer.

18. The method according to claim 15, characterized in that, The gate work function layer is recessed such that a top surface of the gate work function layer is lower than a top surface of the gate dielectric layer.

19. The method according to claim 15, characterized in that, The gate work function layer is recessed such that one top surface of the gate work function layer is lower than one top surface of the first dielectric layer.

20. The method according to claim 15, characterized in that, The metal layer is filled in such that the top surface of the metal layer is at the same level as the top surface of the first dielectric layer.

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