A GIP compensation circuit and its control method

Abstract

The present invention relates to the technical field of GIP compensation circuits, and particularly relates to a GIP compensation circuit and its control method, including transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, capacitor C1, capacitor C2, and capacitor C3. The gate of transistor T5 is electrically connected to the drain of transistor T8, the gate of transistor T9, the drain of transistor T7, and one end of capacitor C3 respectively. The source of transistor T8 is electrically connected to the drain of transistor T9. The gate of transistor T7 is electrically connected to the source of transistor T7. The gate of transistor T8 is connected to the second gate trace. In this way, the Vth compensation part composed of transistor T7, transistor T8, transistor T9, and capacitor C3 in the GIP compensation circuit can be utilized, thereby solving the problem of circuit failure caused by the Vth offset of some TFTs in the GIP compensation circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of GIP compensation circuits, and particularly relates to a GIP compensation circuit and a control method therefor. Background Art

[0002] In recent decades, with the progress of the times and the development of information technology, people's demand for electronic consumer products has been increasing day by day, which has promoted the development of the liquid crystal display industry. And with the development of the times, electronic products are constantly developing towards being light, thin, and power-saving.

[0003] In the display industry, liquid crystal display occupies an important position. In a liquid crystal display screen, each pixel has a TFT (fully known as Thin Film Transistor in English, that is, a thin film field effect transistor), whose gate is connected to the horizontal scanning line, the drain is connected to the vertical data line, and the source is connected to the pixel electrode. If a sufficient positive voltage is applied to a certain scanning line in the horizontal direction, all the TFTs on this line will be turned on. At this time, the pixel electrodes on this line will be connected to the vertical data line, and the video signal voltage on the data line will be written into the pixels, controlling the light transmittance of different liquid crystals to achieve the effect of controlling colors.

[0004] When driving the gate circuit, there are currently two main methods: one is to externally bond an IC to the panel; the other is to complete it through GIP (i.e., Gate In Panel) technology. However, with the development of the times, people's requirements for a high screen-to-body ratio of the panel display are getting higher and higher, and GIP technology has become the main way to drive the gate circuit. The basic concept of GIP is to integrate the gate driver of the LCD Panel on the glass substrate to replace the technology of using an external silicon wafer, forming a scanning drive for the panel. Compared with the traditional COF (fully known as Chip On Film in English, often called flip-chip thin film, which is a chip-on-flex technology that fixes an integrated circuit (IC) on a flexible printed circuit board) and COG (fully known as Chip On Glass, that is, the chip is directly bonded to the glass) processes, this technology not only saves costs, but also can eliminate the process of bonding in the gate direction, which is extremely beneficial to improving production capacity and increasing the integration of the TFT-LCD panel. Therefore, GIP technology reduces the usage amount of the gate driver IC, reduces power consumption and costs, and at the same time can reduce the border of the display panel to achieve a narrow border design, which is a technology worthy of attention.

[0005] Since the GIP circuit is a combination of TFT devices integrated on an Array (i.e., array) substrate, the TFT devices are vulnerable to the influence of frequency, voltage, and temperature, resulting in the shift of the threshold voltage Vth of the TFT devices. In the GIP circuit, due to the long-term action of high-frequency signals on the GIP pull-down voltage stabilization circuit, the Vth of the TFT devices on its circuit is prone to shift, and this shift will cause abnormalities in the GIP circuit, thereby making the gate signal Gn output on the GIP circuit abnormal. To solve this problem, it is of great significance to design a GIP compensation circuit with Vth. Summary of the Invention

[0006] The technical problem to be solved by the present invention is: to provide a GIP compensation circuit to solve the problem of circuit failure caused by the Vth shift of some TFTs in the GIP compensation circuit.

[0007] To solve the above technical problem, the first technical solution adopted by the present invention is:

[0008] A GIP compensation circuit includes transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, capacitor C1, capacitor C2, and capacitor C3. The source of transistor T2 is electrically connected to the gate of transistor T2, the source of transistor T6, the drain of transistor T3, one end of capacitor C2, and the gate of transistor T4 respectively. The drain of transistor T2 is electrically connected to the gate of transistor T3 and one end of capacitor C1 respectively. The source of transistor T2 is electrically connected to the source of transistor T3, the source of transistor T9, and the source of transistor T5 respectively. The source of transistor T4 is electrically connected to the other end of capacitor C2 and the drain of transistor T5 respectively. The gate of transistor T5 is electrically connected to the drain of transistor T8, the gate of transistor T9, the drain of transistor T7, and one end of capacitor C3 respectively. The source of transistor T8 is electrically connected to the drain of transistor T9. The gate of transistor T7 is electrically connected to the source of transistor T7, and both the gate and the source of transistor T7 are connected to the first gate trace. The gate of transistor T8 is connected to the second gate trace. The gate of transistor T1 is connected to the third gate trace. The gate of transistor T6 is connected to the fourth gate trace.

[0009] The second technical solution adopted by the present invention is:

[0010] A control method for a GIP compensation circuit includes the following steps:

[0011] S1. In the first time period, a high level is input to both the gate and the source of transistor T7, and a low level is input to the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the drain of transistor T5, the other end of capacitor C2, the gate of transistor T6, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3;

[0012] S2. In the second time period, a high level is input to the gate of transistor T8, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3;

[0013] S3. In the third time period, a high level is input to the gate of transistor T1 and the other end of capacitor C3, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, the drain of transistor T4, and the other end of capacitor C1;

[0014] S4. In the fourth time period, a high level is input to the drain of transistor T4 and the other end of capacitor C1, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, and the other end of capacitor C3;

[0015] S5. In the fifth time period, a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3;

[0016] S6. In the sixth time period, a high level is input to the gate of transistor T6, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3;

[0017] S7. In the seventh time period, a high level is input to the other end of the capacitor C3, and low levels are input to the gate of the transistor T7, the source of the transistor T7, the gate of the transistor T8, the gate of the transistor T1, the source of the transistor T4, the other end of the capacitor C2, the drain of the transistor T5, the drain of the transistor T4, and the other end of the capacitor C1; the first time period, the second time period, the third time period, the fourth time period, the fifth time period, the sixth time period, and the seventh time period are all successively consecutive time periods.

[0018] The beneficial effects of the present invention are as follows:

[0019] By electrically connecting the source of the transistor T2 to the gate of the transistor T2, the source of the transistor T6, the drain of the transistor T3, one end of the capacitor C2, and the gate of the transistor T4 respectively, connecting the drain of the transistor T2 to the gate of the transistor T3 and one end of the capacitor C1 respectively, connecting the source of the transistor T2 to the source of the transistor T3, the source of the transistor T9, and the source of the transistor T5 respectively, connecting the source of the transistor T4 to the other end of the capacitor C2 and the drain of the transistor T5 respectively, connecting the gate of the transistor T5 to the drain of the transistor T8, the gate of the transistor T9, the drain of the transistor T7, and one end of the capacitor C3 respectively, connecting the source of the transistor T8 to the drain of the transistor T9, connecting the gate of the transistor T7 to the source of the transistor T7 and both the gate and the source of the transistor T7 are connected to the first gate trace, connecting the gate of the transistor T8 to the second gate trace, connecting the gate of the transistor T1 to the third gate trace, and connecting the gate of the transistor T6 to the fourth gate trace, it is possible to utilize the Vth compensation part composed of the transistors T7, T8, T9, and the capacitor C3 in the GIP compensation circuit, thereby solving the problem of circuit failure caused by the Vth offset of some TFTs in the GIP compensation circuit. Description of the Drawings

[0020] Figure 1 It is the circuit schematic diagram of a GIP compensation circuit according to the present invention;

[0021] Figure 2 It is the timing diagram of a GIP compensation circuit according to the present invention;

[0022] Figure 3 It is the circuit schematic diagram of a GIP compensation circuit according to the present invention;

[0023] Figure 4 It is the circuit schematic diagram of a GIP compensation circuit according to the present invention;

[0024] Figure 5 It is the circuit schematic diagram of a GIP compensation circuit according to the present invention;

[0025] Figure 6 The circuit schematic diagram of a GIP compensation circuit according to the present invention;

[0026] Figure 7 The circuit schematic diagram of a GIP compensation circuit according to the present invention;

[0027] Figure 8 The circuit schematic diagram of a GIP compensation circuit according to the present invention;

[0028] Figure 9 The circuit schematic diagram of a GIP compensation circuit according to the present invention;

[0029] Figure 10 The circuit schematic diagram of a GIP compensation circuit according to the present invention;

[0030] Figure 11 The step flow chart of a control method of a GIP compensation circuit according to the present invention. Specific embodiments

[0031] To illustrate the technical content, achieved objectives and effects of the present invention in detail, the following is described in conjunction with embodiments and accompanied by drawings.

[0032] Please refer to Figure 1 , a technical solution provided by the present invention:

[0033] A GIP compensation circuit includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1, a capacitor C2 and a capacitor C3. The source of the transistor T2 is electrically connected to the gate of the transistor T2, the source of the transistor T6, the drain of the transistor T3, one end of the capacitor C2 and the gate of the transistor T4 respectively. The drain of the transistor T2 is electrically connected to the gate of the transistor T3 and one end of the capacitor C1 respectively. The source of the transistor T2 is electrically connected to the source of the transistor T3, the source of the transistor T9 and the source of the transistor T5 respectively. The source of the transistor T4 is electrically connected to the other end of the capacitor C2 and the drain of the transistor T5 respectively. The gate of the transistor T5 is electrically connected to the drain of the transistor T8, the gate of the transistor T9, the drain of the transistor T7 and one end of the capacitor C3 respectively. The source of the transistor T8 is electrically connected to the drain of the transistor T9. The gate of the transistor T7 is electrically connected to the source of the transistor T7, and both the gate and the source of the transistor T7 are connected to a first gate trace. The gate of the transistor T8 is connected to a second gate trace. The gate of the transistor T1 is connected to a third gate trace. The gate of the transistor T6 is connected to a fourth gate trace.

[0034] As can be seen from the above description, the beneficial effects of the present invention are as follows:

[0035] By electrically connecting the source of transistor T2 to the gate of transistor T2, the source of transistor T6, the drain of transistor T3, one end of capacitor C2, and the gate of transistor T4 respectively, the drain of transistor T2 to the gate of transistor T3 and one end of capacitor C1 respectively, the source of transistor T2 to the source of transistor T3, the source of transistor T9, and the source of transistor T5 respectively, the source of transistor T4 to the other end of capacitor C2 and the drain of transistor T5 respectively, the gate of transistor T5 to the drain of transistor T8, the gate of transistor T9, the drain of transistor T7, and one end of capacitor C3 respectively, the source of transistor T8 to the drain of transistor T9, the gate of transistor T7 to the source of transistor T7 and both the gate and the source of transistor T7 are connected to the first gate trace, the gate of transistor T8 is connected to the second gate trace, the gate of transistor T1 is connected to the third gate trace, and the gate of transistor T6 is connected to the fourth gate trace, it is possible to utilize the Vth compensation part composed of transistor T7, transistor T8, transistor T9, and capacitor C3 in the GIP compensation circuit, thereby solving the problem of circuit failure caused by the Vth offset of some TFTs in the GIP compensation circuit.

[0036] Further, the other end of capacitor C1 and the drain of transistor T4 are both connected to the first clock signal, and the other end of capacitor C3 is connected to the second clock signal.

[0037] Further, the drain of transistor T1 is connected to the positive pole of the power supply.

[0038] Further, the drain of transistor T6, the source of transistor T2, the source of transistor T3, the source of transistor T9, and the source of transistor T5 are all connected to the negative pole of the power supply.

[0039] Further, transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9 are all N-channel MOS transistors.

[0040] As can be seen from the above description, by using N-channel MOS transistors, the output waveform of the GIP compensation circuit can be further stabilized, the cost of improving the GIP process is saved, and the display effect of the display screen is optimized.

[0041] Please refer to Figure 11 , another technical solution provided by the present invention:

[0042] A control method for a GIP compensation circuit, comprising the following steps:

[0043] S1. In the first time period, a high level is input to both the gate and the source of transistor T7, and a low level is input to the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the drain of transistor T5, the other end of capacitor C2, the gate of transistor T6, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3;

[0044] S2. In the second time period, a high level is input to the gate of transistor T8, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3;

[0045] S3. In the third time period, a high level is input to the gate of transistor T1 and the other end of capacitor C3, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, the drain of transistor T4, and the other end of capacitor C1;

[0046] S4. In the fourth time period, a high level is input to the drain of transistor T4 and the other end of capacitor C1, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, and the other end of capacitor C3;

[0047] S5. In the fifth time period, a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3;

[0048] S6. In the sixth time period, a high level is input to the gate of transistor T6, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3;

[0049] S7. In the seventh time period, the other end of the capacitor C3 is controlled to input a high level, and the gates of the transistors T7 and T8, the sources of the transistors T7 and T1, the source of the transistor T4, the other end of the capacitor C2, the drains of the transistors T5 and T4, and the other end of the capacitor C1 are all controlled to input low levels; the first time period, the second time period, the third time period, the fourth time period, the fifth time period, the sixth time period, and the seventh time period are all successively continuous time periods.

[0050] From the above description, it can be seen that the beneficial effects of the present invention are as follows:

[0051] Through the control method of the GIP compensation circuit designed by this solution, the Vth compensation part composed of the transistors T7, T8, T9 and the capacitor C3 in the GIP compensation circuit can be utilized, thereby solving the problem of circuit failure caused by the Vth shift of some TFTs in the GIP compensation circuit.

[0052] Furthermore, the following steps are also included:

[0053] In the eighth time period, the drains of the transistors T4 and the other end of the capacitor C1 are controlled to input high levels, and the gates of the transistors T7 and T8, the sources of the transistors T7 and T1, the source of the transistor T4, the other end of the capacitor C2, the drains of the transistors T5 and T6, and the other end of the capacitor C3 are all controlled to input low levels.

[0054] Please refer to Figures 1 to 10 , Embodiment 1 of the present invention is:

[0055] Please refer to Figure 1, A GIP compensation circuit includes transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, capacitor C1, capacitor C2, and capacitor C3. The source of transistor T2 is electrically connected to the gate of transistor T2, the source of transistor T6, the drain of transistor T3, one end of capacitor C2, and the gate of transistor T4 respectively. The drain of transistor T2 is electrically connected to the gate of transistor T3 and one end of capacitor C1 respectively. The source of transistor T2 is electrically connected to the source of transistor T3, the source of transistor T9, and the source of transistor T5 respectively. The source of transistor T4 is electrically connected to the other end of capacitor C2 and the drain of transistor T5 respectively. The gate of transistor T5 is electrically connected to the drain of transistor T8, the gate of transistor T9, the drain of transistor T7, and one end of capacitor C3 respectively. The source of transistor T8 is electrically connected to the drain of transistor T9. The gate of transistor T7 is electrically connected to the source of transistor T7, and both the gate and the source of transistor T7 are connected to the first gate trace. The gate of transistor T8 is connected to the second gate trace. The gate of transistor T1 is connected to the third gate trace. The gate of transistor T6 is connected to the fourth gate trace.

[0056] The other end of capacitor C1 and the drain of transistor T4 are both connected to the first clock signal. The other end of capacitor C3 is connected to the second clock signal.

[0057] The drain of transistor T1 is connected to the positive pole of the power supply.

[0058] The drain of transistor T6, the source of transistor T2, the source of transistor T3, the source of transistor T9, and the source of transistor T5 are all connected to the negative pole of the power supply.

[0059] Transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9 are all N-channel MOS transistors.

[0060] Please refer to Figure 1 , In the 9T3C GIP compensation circuit, there are a total of 9 TFTs and 3 capacitors. Among them, the Vth compensation part is composed of transistor T7, transistor T8, transistor T9, and capacitor C3. The output pre-charge part is composed of transistor T1 and capacitor C2. The output part is composed of transistor T4. The pull-down part is composed of transistor T2, transistor T3, transistor T5, transistor T6, and capacitor C1, which consists of four parts in total.

[0061] Figure 2It is the timing diagram of the GIP compensation circuit designed in this solution: In this timing diagram, it is divided into seven time periods, namely the compensation pre-charge stage t1, the compensation stage t2, the output pre-charge stage t3, the output stage t4, the pull-down output stage t5, the pull-down Q point stage t6, and the pull-down voltage regulation stage t7.

[0062] Figure 3 It is the schematic diagram of the compensation pre-charge stage of the GIP compensation circuit designed in this solution: In this stage (i.e., the compensation pre-charge stage t1), Gn-6 is at the high potential VH, and Gn-4, Gn-2, Gn, Gn+4, CK1, and CK7 are at the low potential VL; at this time, the transistor T7 is turned on, and the P1 of the capacitor C3 changes from the low potential to the high potential V1 through the transistor T7. Since P1 is at the high potential V1 at this time, the transistors T5 and T9 are turned on, and Gn is pulled down by VGL and maintained at the low potential VL; the other end of the capacitor C1 is at the potential VL because CK7 is at the low potential at this time.

[0063] Figure 4 It is the schematic diagram of the compensation stage of the GIP compensation circuit designed in this solution: In this stage (i.e., the compensation stage t2), Gn-4 and P1 are at the high potential VH, and Gn-6, Gn-2, Gn, Gn+4, CK1, and CK7 are at the low potential VL; at this time, Gn maintains the VL voltage through the transistor T5, and P1 is connected to VGL through the turned-on transistors T8 and T9, so that the potential of the P1 point is pulled down by VGL until the transistor T9 is turned off. At this time, the potential of the P1 point drops from V1 to VL+Vth. At this time, the transistors T5 and T9 are turned off, and the Vth of the transistor T9 is stored on the capacitor C3. At this time, the potential of P1 is VL+Vth, and the other end of the capacitor C3 is maintained at the VGL potential by CK7.

[0064] Figure 5 It is the schematic diagram of the output pre-charge stage of the GIP compensation circuit designed in this solution: In this stage (i.e., the output pre-charge stage t3), Gn-2 and CK7 are at the high potential VH, and Gn-6, Gn-4, Gn, Gn+4, and CK1 are at the low potential VL; at this time, the Q point is charged from VGH to the high potential VH through the transistor T1. Since the Q point is at the high potential at this time, the transistors T2 and T4 are turned on, Gn is maintained at VL through the transistor T4, and P2 is pulled down and maintained at VL through the turned-on transistor T2. Since one end of the capacitor C3 connected to CK7 rises to VH at this time, the potential of the other end P1 point of the capacitor C3 rises to VH+Vth through capacitive coupling. At this time, the transistors T9 and T5 are turned on, and Gn can also be pulled down and maintained at the low potential VL through the transistor T5.

[0065] Figure 6It is a schematic diagram of the output stage of the GIP compensation circuit designed in this solution: In this stage (i.e., output stage t4), Q and CK1 are at high potential VH, and Gn-6, Gn-4, Gn-2, Gn, Gn+4, and CK7 are at low potential VL; Since the Q point is at high potential at this time, transistor T4 is turned on, and the high potential output by CK1 of Gn through transistor T4 makes Gn output high potential VH, and through the coupling effect of capacitor C2, the voltage of the Q point rises, stabilizing the output of Gn. At the same time, since transistor T2 is also turned on at this time, P2 is pulled down and maintained at VL through the turned-on transistor T2. Since one end of capacitor C3 connected to CK7 rises to VL at this time, the other end P1 of capacitor C3 drops to VL+Vth through capacitive coupling potential, and at this time transistors T9 and T5 are turned off, stabilizing the output L of Gn.

[0066] Figure 7 It is a schematic diagram of the pull-down output stage of the GIP compensation circuit designed in this solution: In this stage (i.e., pull-down output stage t5), Q is at high potential VH, and Gn-6, Gn-4, Gn-2, Gn, Gn+4, CK1, and CK7 are at low potential VL; Since the Q point is at high potential at this time, transistor T4 is turned on, and the low potential output by CK1 of Gn through transistor T4 pulls Gn down from high potential VH to low potential VL. At the same time, since transistor T2 is also turned on at this time, P2 is pulled down and maintained at VL through the turned-on transistor T2. Since one end of capacitor C3 connected to CK7 is still at VL at this time, the other end P1 of capacitor C3 remains at VL+Vth.

[0067] Figure 8 It is a schematic diagram of the pull-down Q point stage of the GIP compensation circuit designed in this solution: In this stage (i.e., pull-down Q point stage t6), Gn+4 is at high potential VH, and Gn-6, Gn-4, Gn-2, Gn, CK1, and CK7 are at low potential VL; Since the Q point is at high potential at this time, transistor T2 is turned on, and Q is pulled down from high potential VH to low potential VL by the VGL signal through transistor T2. Since one end of capacitor C3 connected to CK7 is still at VL at this time, the other end P1 of capacitor C3 remains at VL+Vth.

[0068] The pull-down voltage stabilization stage t7 is divided into two stages. Figure 9It is a schematic diagram of the first stage of the pull-down voltage regulation of the GIP compensation circuit designed in this solution: In this stage, CK7 is at the high potential VH, and Gn-6, Gn-4, Gn-2, Gn, and CK1 are at the low potential VL; Since one end of the capacitor C3 connected to CK7 rises to VH at this time, the other end P1 of the capacitor C3 rises to VH + Vth. At this time, the transistor T5 is turned on to maintain the low potential of Gn, playing a voltage regulation role. And because the gate of the transistor T5 is driven by a high-frequency voltage, it is easy to cause Vth drift, affecting the stability of the GIP compensation circuit. And because the potential of the P1 point is VH + Vth, the Vgs of the transistor T5 in this stage is VH + Vth - VL. Since I (linear region) = μC (W / L) {(Vgs - Vth)Vds - (1 / 2)Vds 2}; I (saturation region) = 1 / 2μCox (W / L) (Vgs - Vth) 2 (where Vth is the threshold voltage, Vgs is the voltage difference between the gate and the source, Vds is the voltage difference between the drain and the source, W is the channel width of the thin-film transistor, L is the channel length of the thin-film transistor, μ is the electron mobility, Cox is the capacitance per unit area of the gate insulating layer, VH is the high potential, and VL is the low potential). The Vth in both regions can be eliminated, avoiding the Vth drift of the transistor T5 and thus affecting the stability of the GIP compensation circuit.

[0069] Figure 10 It is a schematic diagram of the second stage of the voltage regulation of the GIP compensation circuit designed in this solution: In this stage, CK1 is at the high potential VH, and Gn-6, Gn-4, Gn-2, Gn, Gn+4, and CK7 are at the low potential VL; Due to the capacitive coupling effect of C1 when CK1 is at the high potential at this time, it rises to the high potential VH, causing the transistor T3 to be turned on, maintaining the Q point being pulled down to the low potential VL, preventing the Q point from being capacitively coupled to the high potential of CK1 by the parasitic capacitance of the transistor T4.

[0070] Please refer to Figures 1 to 11 , the second embodiment of the present invention is:

[0071] Please refer to Figure 11 , a control method for a GIP compensation circuit, comprising the following steps:

[0072] S1. In the first time period, control the gate of the transistor T7 and the source of the transistor T7 to both input high levels, and control the gate of the transistor T8, the gate of the transistor T1, the source of the transistor T4, the drain of the transistor T5, the other end of the capacitor C2, the gate of the transistor T6, the drain of the transistor T4, the other end of the capacitor C1, and the other end of the capacitor C3 to all input low levels;

[0073] S2. In the second time period, control the gate of transistor T8 to input a high level, and control the gates of transistor T7, the source of transistor T7, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3 to all input low levels;

[0074] S3. In the third time period, control the gate of transistor T1 and the other end of capacitor C3 to both input high levels, and control the gates of transistor T7, the source of transistor T7, the gate of transistor T8, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, the drain of transistor T4, and the other end of capacitor C1 to all input low levels;

[0075] S4. In the fourth time period, control the drain of transistor T4 and the other end of capacitor C1 to both input high levels, and control the gates of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, and the other end of capacitor C3 to all input low levels;

[0076] S5. In the fifth time period, control the gates of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3 to all input low levels;

[0077] S6. In the sixth time period, control the gate of transistor T6 to input a high level, and control the gates of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3 to all input low levels;

[0078] S7. In the seventh time period, control the other end of capacitor C3 to input a high level, and control the gates of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, and the other end of capacitor C1 to all input low levels; The first time period, the second time period, the third time period, the fourth time period, the fifth time period, the sixth time period, and the seventh time period are all consecutive time periods in sequence.

[0079] It further includes the following steps:

[0080] In the eighth time period, a high level is input to both the drain of the control transistor T4 and the other end of the capacitor C1, and a low level is input to the gate of the control transistor T7, the source of the transistor T7, the gate of the transistor T8, the gate of the transistor T1, the source of the transistor T4, the other end of the capacitor C2, the drain of the transistor T5, the gate of the transistor T6, and the other end of the capacitor C3.

[0081] Please refer to Figure 1 , in the GIP compensation circuit of 9T3C, there are a total of 9 TFTs and 3 capacitors. Among them, the Vth compensation part consists of the transistor T7, the transistor T8, the transistor T9, and the capacitor C3, the output pre-charge part consists of the transistor T1 and the capacitor C2, the output part consists of the transistor T4, and the pull-down part consists of the transistor T2, the transistor T3, the transistor T5, the transistor T6, and the capacitor C1, which are composed of four parts in total.

[0082] Figure 2 is the timing diagram of the GIP compensation circuit designed in this scheme: In this timing diagram, it is divided into seven time periods, namely the compensation pre-charge stage t1, the compensation stage t2, the output pre-charge stage t3, the output stage t4, the pull-down output stage t5, the pull-down Q point stage t6, and the pull-down voltage stabilization stage t7.

[0083] Figure 3 is the schematic diagram of the compensation pre-charge stage (i.e., the first time period) of the GIP compensation circuit designed in this scheme: In this stage (i.e., the compensation pre-charge stage t1), Gn-6 is at the high potential VH, and Gn-4, Gn-2, Gn, Gn+4, CK1, and CK7 are at the low potential VL; at this time, the transistor T7 is turned on, and the P1 of the capacitor C3 changes from the low potential to the high potential V1 through the transistor T7. Since P1 is at the high potential V1 at this time, the transistors T5 and T9 are turned on, and Gn is pulled down by VGL and maintained at the low potential VL; the other end of the capacitor C1 is at the potential VL because CK7 is at the low potential at this time.

[0084] Figure 4 is the schematic diagram of the compensation stage (i.e., the second time period) of the GIP compensation circuit designed in this scheme: In this stage (i.e., the compensation stage t2), Gn-4 and P1 are at the high potential VH, and Gn-6, Gn-2, Gn, Gn+4, CK1, and CK7 are at the low potential VL; at this time, Gn maintains the VL voltage through the transistor T5, and P1 is connected to VGL through the turned-on transistors T8 and T9, so that the potential of the P1 point is pulled down by VGL until the transistor T9 is turned off. At this time, the potential of the P1 point drops from V1 to VL+Vth. At this time, the transistors T5 and T9 are turned off, and the Vth of the transistor T9 is stored on the capacitor C3. At this time, the potential of P1 is VL+Vth, and the other end of the capacitor C3 is maintained at the VGL potential by CK7.

[0085] Figure 5 It is a schematic diagram of the output pre-charge stage of the GIP compensation circuit designed in this solution (i.e., the third time period): In this stage (i.e., the output pre-charge stage t3), Gn-2 and CK7 are at the high potential VH, and Gn-6, Gn-4, Gn, Gn+4, and CK1 are at the low potential VL; at this time, point Q is charged from VGH to the high potential VH through the transistor T1. Since point Q is at the high potential at this time, the transistors T2 and T4 are turned on. Gn is maintained at VL through the transistor T4. P2 is pulled down and maintained at VL through the turned-on transistor T2. Since one end of the capacitor C3 connected to CK7 rises to VH at this time, the potential at the other end P1 of the capacitor C3 rises to VH+Vth through capacitive coupling. At this time, the transistors T9 and T5 are turned on, and Gn can also be pulled down and maintained at the low potential VL through the transistor T5.

[0086] Figure 6 It is a schematic diagram of the output stage of the GIP compensation circuit designed in this solution (i.e., the fourth time period): In this stage (i.e., the output stage t4), Q and CK1 are at the high potential VH, and Gn-6, Gn-4, Gn-2, Gn, Gn+4, and CK7 are at the low potential VL; since point Q is at the high potential at this time, the transistor T4 is turned on. The high potential output by CK1 makes Gn output the high potential VH through the transistor T4. And through the coupling effect of the capacitor C2, the voltage at point Q rises, stabilizing the output of Gn. At the same time, since the transistor T2 is also turned on at this time, P2 is pulled down and maintained at VL through the turned-on transistor T2. Since one end of the capacitor C3 connected to CK7 rises to VL at this time, the potential at the other end P1 of the capacitor C3 drops to VL+Vth through capacitive coupling. At this time, the transistors T9 and T5 are turned off, stabilizing the output L of Gn.

[0087] Figure 7 It is a schematic diagram of the pull-down output stage of the GIP compensation circuit designed in this solution (i.e., the fifth time period): In this stage (i.e., the pull-down output stage t5), Q is at the high potential VH, and Gn-6, Gn-4, Gn-2, Gn, Gn+4, CK1, and CK7 are at the low potential VL; since point Q is at the high potential at this time, the transistor T4 is turned on. The low potential output by CK1 makes Gn be pulled down from the high potential VH to the low potential VL through the transistor T4. At the same time, since the transistor T2 is also turned on at this time, P2 is pulled down and maintained at VL through the turned-on transistor T2. Since one end of the capacitor C3 connected to CK7 remains at VL at this time, the other end P1 of the capacitor C3 still remains at VL+Vth.

[0088] Figure 8It is a schematic diagram of the pull-down Q-point stage (i.e., the sixth time period) of the GIP compensation circuit designed in this solution: In this stage (i.e., the pull-down Q-point stage t6), Gn+4 is at the high potential VH, and Gn-6, Gn-4, Gn-2, Gn, CK1, and CK7 are at the low potential VL; since the Q-point is at the high potential at this time, the transistor T2 is turned on, and Q is pulled down from the high potential VH to the low potential VL by the VGL signal through the transistor T2. Since one end of the capacitor C3 connected to CK7 is still at VL at this time, the other end P1 of the capacitor C3 remains at VL+Vth.

[0089] The pull-down voltage regulation stage t7 is divided into two stages. Figure 9 It is a schematic diagram of the first stage of the pull-down voltage regulation stage (i.e., the seventh time period) of the GIP compensation circuit designed in this solution: In this stage, CK7 is at the high potential VH, and Gn-6, Gn-4, Gn-2, Gn, and CK1 are at the low potential VL; since one end of the capacitor C3 connected to CK7 rises to VH at this time, the other end P1 of the capacitor C3 rises to VH+Vth. At this time, the transistor T5 is turned on to maintain the low potential of Gn, playing a voltage regulation role. And because the gate of the transistor T5 is driven by a high-frequency voltage, it is easy to cause Vth drift, affecting the stability of the GIP compensation circuit. And because the potential of the P1 point is VH+Vth, the Vgs of the transistor T5 in this stage is VH+Vth-VL. Since I (linear region) = μC(W / L){(Vgs-Vth)Vds-(1 / 2)Vds 2}; I (saturation region) = 1 / 2μCox(W / L)(Vgs-Vth) 2 (where Vth is the threshold voltage, Vgs is the voltage difference between the gate and the source, Vds is the voltage difference between the drain and the source, W is the channel width of the thin-film transistor, L is the channel length of the thin-film transistor, μ is the electron mobility, Cox is the capacitance per unit area of the gate insulation layer, VH is the high potential, and VL is the low potential), the Vth in both regions can be eliminated, avoiding the Vth drift of the transistor T5 and thus affecting the stability of the GIP compensation circuit.

[0090] Figure 10 It is a schematic diagram of the second stage of the voltage regulation stage (i.e., the eighth time period) of the GIP compensation circuit designed in this solution: In this stage, CK1 is at the high potential VH, and Gn-6, Gn-4, Gn-2, Gn, Gn+4, and CK7 are at the low potential VL; due to the capacitive coupling effect of C1 when CK1 is at the high potential at this time, it rises to the high potential VH, causing the transistor T3 to be turned on, maintaining the Q-point pulled down to the low potential VL, preventing the Q-point from being affected by the high potential of the parasitic capacitance coupling CK1 of the transistor T4.

[0091] In summary, a GIP compensation circuit and its control method provided by the present invention electrically connect the source of transistor T2 to the gate of transistor T2, the source of transistor T6, the drain of transistor T3, one end of capacitor C2, and the gate of transistor T4 respectively. The drain of transistor T2 is electrically connected to the gate of transistor T3 and one end of capacitor C1 respectively. The source of transistor T2 is electrically connected to the source of transistor T3, the source of transistor T9, and the source of transistor T5 respectively. The source of transistor T4 is electrically connected to the other end of capacitor C2 and the drain of transistor T5 respectively. The gate of transistor T5 is electrically connected to the drain of transistor T8, the gate of transistor T9, the drain of transistor T7, and one end of capacitor C3 respectively. The source of transistor T8 is electrically connected to the drain of transistor T9. The gate of transistor T7 is electrically connected to the source of transistor T7, and both the gate and the source of transistor T7 are connected to the first gate trace. The gate of transistor T8 is connected to the second gate trace. The gate of transistor T1 is connected to the third gate trace. The gate of transistor T6 is connected to the fourth gate trace. In this way, the Vth compensation part composed of transistor T7, transistor T8, transistor T9, and capacitor C3 in the GIP compensation circuit can be utilized to solve the problem of circuit failure caused by the Vth offset of some TFTs in the GIP compensation circuit.

[0092] The above are only the embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in the relevant technical fields, shall be included in the patent protection scope of the present invention by the same token.

Claims

1. A GIP compensation circuit, characterized in that, it includes transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, capacitor C1, capacitor C2 and capacitor C3. The source of transistor T1 is electrically connected to the gate of transistor T2, the source of transistor T6, the drain of transistor T3, one end of capacitor C2 and the gate of transistor T4 respectively. The drain of transistor T2 is electrically connected to the gate of transistor T3 and one end of capacitor C1 respectively. The source of transistor T2 is electrically connected to the source of transistor T3, the source of transistor T9 and the source of transistor T5 respectively. The source of transistor T4 is electrically connected to the other end of capacitor C2 and the drain of transistor T5 respectively. The gate of transistor T5 is electrically connected to the drain of transistor T8, the gate of transistor T9, the drain of transistor T7 and one end of capacitor C3 respectively. The source of transistor T8 is electrically connected to the drain of transistor T9. The gate of transistor T7 is electrically connected to the source of transistor T7, and both the gate and the source of transistor T7 are connected to the first gate trace. The gate of transistor T8 is connected to the second gate trace. The gate of transistor T1 is connected to the third gate trace. The gate of transistor T6 is connected to the fourth gate trace; the other end of capacitor C1 and the drain of transistor T4 are both connected to the first clock signal. The other end of capacitor C3 is connected to the second clock signal; the drain of transistor T1 is connected to the positive pole of the power supply; the drain of transistor T6, the source of transistor T2, the source of transistor T3, the source of transistor T9 and the source of transistor T5 are all connected to the negative pole of the power supply; transistors T1, T2, T3, T4, T5, T6, T7, T8 and T9 are all N-channel MOS transistors.

2. A control method for the GIP compensation circuit according to claim 1, characterized in that, it includes the following steps: S1. In the first time period, control the gate and the source of transistor T7 to both input high levels, and control the gates of transistor T8, transistor T1, the source of transistor T4, the drain of transistor T5, the other end of capacitor C2, the gate of transistor T6, the drain of transistor T4, the other end of capacitor C1 and the other end of capacitor C3 to all input low levels; S2. In the second time period, control the gate of transistor T8 to input a high level, and control the gates of transistor T7, the source of transistor T7, transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, the drain of transistor T4, the other end of capacitor C1 and the other end of capacitor C3 to all input low levels; S3. In the third time period, a high level is input to both the gate of transistor T1 and the other end of capacitor C3, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, the drain of transistor T4, and the other end of capacitor C1; S4. In the fourth time period, a high level is input to both the drain of transistor T4 and the other end of capacitor C1, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, and the other end of capacitor C3; S5. In the fifth time period, a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3; S6. In the sixth time period, a high level is input to the gate of transistor T6, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, the other end of capacitor C1, and the other end of capacitor C3; S7. In the seventh time period, a high level is input to the other end of capacitor C3, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the drain of transistor T4, and the other end of capacitor C1; The first time period, the second time period, the third time period, the fourth time period, the fifth time period, the sixth time period, and the seventh time period are all consecutive time periods in sequence.

3. The control method of the GIP compensation circuit according to claim 2, wherein, it further includes the following steps: In the eighth time period, a high level is input to both the drain of transistor T4 and the other end of capacitor C1, and a low level is input to the gate of transistor T7, the source of transistor T7, the gate of transistor T8, the gate of transistor T1, the source of transistor T4, the other end of capacitor C2, the drain of transistor T5, the gate of transistor T6, and the other end of capacitor C3.

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