Display devices

Abstract

A display device comprises: a substrate including a display area and a peripheral area, a semiconductor element, a pixel structure, and a plurality of dummy patterns. The semiconductor element is arranged in the display area on the substrate, and the pixel structure is arranged on the semiconductor element. A dummy pattern having a stacked structure is arranged in the peripheral area on the substrate and contains the same material as the material constituting the semiconductor element. The dummy patterns are arranged in different layers in a grid shape, and each of the dummy patterns includes a central portion and an edge portion surrounding the central portion. The edge portions of the dummy patterns adjacent to each other in different layers in the dummy patterns overlap each other in a direction from the substrate to the pixel structure.

Description

Technical Field

[0001] The present disclosure relates generally to a display device, and more particularly, to a display device including a plurality of dummy patterns. Background Art

[0002] Due to its light and thin characteristics, flat panel display devices are used as display devices for replacing cathode ray tube display devices. As representative examples of such flat panel display devices, there are liquid crystal display devices and organic light emitting diode display devices.

[0003] The display device may include a display area and a peripheral area surrounding the display area. Semiconductor elements and pixel structures may be arranged in the display area, and wiring and pad electrodes, etc. may be arranged in the peripheral area. When etching the active layer and gate electrode (e.g., pattern) included in the semiconductor element in the process of manufacturing the display device, the size (e.g., width of the pattern) in the central part (e.g., the first area) of the display area and the display area (e.g., the second area) adjacent to the peripheral area may be different from each other. For example, since relatively more semiconductor elements are arranged in the first area, there may be relatively more etching target patterns in the first area, and since the second area is adjacent to the peripheral area, there may be relatively fewer etching target patterns in the second area. In other words, the density of the patterns in the first area and the second area may be different from each other, and the concentration of the etchant for etching the pattern may be relatively lower in the second area than in the first area. In this case, the size of the pattern formed in the second area may be relatively large, and the pattern may be short-circuited. Summary of the Invention

[0004] The present disclosure provides a display device including a plurality of dummy patterns.

[0005] According to some example embodiments, a display device includes a substrate, a semiconductor element, a pixel structure, and a plurality of dummy patterns. The substrate has a display area and a peripheral area. The semiconductor element is disposed in the display area on the substrate. The pixel structure is disposed on the semiconductor element. The dummy pattern is disposed in the peripheral area on the substrate and has the same material as the material constituting the semiconductor element. The dummy pattern has a stacked structure. The dummy patterns are arranged in different layers in a grid shape, and each of the dummy patterns includes a central portion and an edge portion surrounding the central portion. The edge portions of the dummy patterns adjacent to each other in different layers in the dummy pattern overlap each other in a direction from the substrate to the pixel structure.

[0006] In exemplary embodiments, central portions of dummy patterns adjacent to each other in different layers may not overlap with each other.

[0007] In example embodiments, the display device may further include an active pattern disposed between the dummy pattern and the substrate. The active pattern may be arranged in a lattice shape and may overlap at least a portion of the dummy pattern.

[0008] In example embodiments, the dummy patterns may include a reference dummy pattern, a lower dummy pattern, an intermediate dummy pattern, and an upper dummy pattern. The reference dummy patterns may be spaced apart from each other by a first spacing. The lower dummy patterns may be disposed on the reference dummy patterns and may be spaced apart from each other by a first spacing. The lower dummy patterns may overlap with the first corner, second corner, third corner, and fourth corner of each of the reference dummy patterns. The intermediate dummy patterns may be disposed on the lower dummy patterns and may be spaced apart from each other by a first spacing. The intermediate dummy patterns may overlap with the first and second sides of each of the reference dummy patterns and the first and second sides of each of the lower dummy patterns. The upper dummy patterns may be disposed on the intermediate dummy patterns and may be spaced apart from each other by a first spacing. The upper dummy patterns may overlap with the third and fourth sides of each of the reference dummy patterns, the third and fourth sides of each of the lower dummy patterns, and the first, second, third, and fourth corners of each of the intermediate dummy patterns. In each of the reference dummy pattern and the lower dummy pattern, the first side portion may face the second side portion, and the third side portion may face the fourth side portion.

[0009] In example embodiments, the reference dummy pattern, the lower dummy pattern, the middle dummy pattern, and the upper dummy pattern may have the same shape.

[0010] In an example embodiment, in each of the reference dummy patterns, both ends of the first side portion may include a first corner and a second corner, respectively, both ends of the second side portion may include a third corner and a fourth corner, respectively, both ends of the third side portion may include a first corner and a third corner, respectively, and both ends of the fourth side portion may include a second corner and a fourth corner, respectively.

[0011] In example embodiments, in each of the lower dummy patterns, both ends of the first side portion may include a first corner and a third corner, respectively, both ends of the second side portion may include a second corner and a fourth corner, respectively, both ends of the third side portion may include a first corner and a second corner, respectively, and both ends of the fourth side portion may include a third corner and a fourth corner, respectively.

[0012] In example embodiments, the display device may further include an active pattern disposed between the reference dummy pattern and the substrate. The active patterns may be arranged in a lattice shape while being spaced apart from each other by a first interval, and the active patterns may overlap the reference dummy pattern.

[0013] In example embodiments, a semiconductor element may include an active layer disposed on a substrate, a gate insulating layer disposed on the active layer and covering the active layer, a first gate electrode disposed on the gate insulating layer, a first insulating interlayer disposed on the first gate electrode and covering the first gate electrode, a second gate electrode disposed on the first insulating interlayer, a second insulating interlayer disposed on the second gate electrode and covering the second gate electrode, a third gate electrode disposed on the second insulating interlayer, a third insulating interlayer disposed on the third gate electrode and covering the third gate electrode, and a source electrode and a drain electrode both disposed on the third insulating interlayer.

[0014] In an example embodiment, the gate insulating layer may extend from the display region to the peripheral region on the substrate to cover the active pattern in the peripheral region on the substrate, and the first insulating interlayer may extend from the display region to the peripheral region on the gate insulating layer to cover the reference dummy pattern in the peripheral region on the gate insulating layer. The second insulating interlayer may extend from the display region to the peripheral region on the first insulating interlayer to cover the lower dummy pattern in the peripheral region on the first insulating interlayer, and the third insulating interlayer may extend from the display region to the peripheral region on the second insulating interlayer to cover the intermediate dummy pattern in the peripheral region on the second insulating interlayer.

[0015] In an exemplary embodiment, the active layer may be located on the same layer as the active pattern, and the first gate electrode may be located on the same layer as the reference dummy pattern. The second gate electrode may be located on the same layer as the lower dummy pattern. The third gate electrode may be located on the same layer as the middle dummy pattern. The source electrode and the drain electrode may be located on the same layer as the upper dummy pattern.

[0016] In example embodiments, the dummy patterns may include first to nth reference dummy patterns (where n is an integer of 1 or greater), first to mth lower dummy patterns (where m is an integer of 1 or greater) disposed on the first to nth reference dummy patterns, first to qth intermediate dummy patterns (where q is an integer of 1 or greater) disposed on the first to mth lower dummy patterns, and first to pth upper dummy patterns (where p is an integer of 1 or greater) disposed on the first to qth intermediate dummy patterns. The first corner, second corner, third corner and fourth corner of the kth reference dummy pattern (where k is an integer between 1 and n) among the first to nth reference dummy patterns may overlap with the jth, j+1th, j+2th and j+3th lower dummy patterns (where j is an integer between 1 and m) among the first to mth lower dummy patterns, the hth and h+1th intermediate dummy patterns (where h is an integer between 1 and q) among the first to qth intermediate dummy patterns, and the gth and g+1th upper dummy patterns (where g is an integer between 1 and p) among the first to pth upper dummy patterns.

[0017] In example embodiments, the gth upper dummy pattern may be located between the jth and j+2th lower dummy patterns, and the jth and j+2th lower dummy patterns and the gth upper dummy pattern may be located in the same row. The g+1th upper dummy pattern may be located between the j+1th and j+3th lower dummy patterns, and the j+1th and j+3th lower dummy patterns and the g+1th upper dummy pattern may be located in the same row. The kth reference dummy pattern may be located between the hth and h+1th intermediate dummy patterns, and the hth and h+1th intermediate dummy patterns and the kth reference dummy pattern may be located in the same row.

[0018] In example embodiments, the hth intermediate dummy pattern may be located between the jth and j+1th lower dummy patterns, and the jth and j+1th lower dummy patterns and the hth intermediate dummy pattern may be located in the same column. The kth reference dummy pattern may be located between the gth and g+1th upper dummy patterns, and the gth and g+1th upper dummy patterns and the kth reference dummy pattern may be located in the same column. The h+1th intermediate dummy pattern may be located between the j+2th and j+3th lower dummy patterns, and the j+2th and j+3th lower dummy patterns and the h+1th intermediate dummy pattern may be located in the same column.

[0019] In example embodiments, the jth, j+1th, j+2th, and j+3th lower dummy patterns, the hth and h+1th middle dummy patterns, and the gth and g+1th upper dummy patterns may surround the kth reference dummy pattern.

[0020] In an example embodiment, the first corner, the second corner, the third corner, and the fourth corner of the k+1th reference dummy pattern located in the same row as the kth reference dummy pattern may overlap with the j+2th and j+3th lower dummy patterns, the j+4th and j+5th lower dummy patterns, the h+1th middle dummy pattern, the h+2th middle dummy pattern, and the g+2th and g+3th upper dummy patterns.

[0021] In example embodiments, the g+2th upper dummy pattern may be located between the j+2th and j+4th lower dummy patterns, and the jth, j+2th, and j+4th lower dummy patterns and the g+2th and g+2th upper dummy patterns may be located in the same row. The g+3th upper dummy pattern may be located between the j+3th and j+5th lower dummy patterns, and the j+1th, j+3th, and j+5th lower dummy patterns and the g+1th and g+3th upper dummy patterns may be located in the same row. The k+1th reference dummy pattern may be located between the h+1th and h+2th intermediate dummy patterns, and the hth, h+1th, and h+2th intermediate dummy patterns and the kth and k+1th reference dummy patterns may be located in the same row.

[0022] In example embodiments, the h+1th intermediate dummy pattern may be located between the j+2nd and j+3th lower dummy patterns, and the j+2nd and j+3th lower dummy patterns and the h+1th intermediate dummy pattern may be located in the same column. The k+1th reference dummy pattern may be located between the g+2nd and g+3th upper dummy patterns, and the g+2nd and g+3th upper dummy patterns and the k+1th reference dummy pattern may be located in the same column. The h+2th intermediate dummy pattern may be located between the j+4th and j+5th lower dummy patterns, and the j+4th and j+5th lower dummy patterns and the h+2th intermediate dummy pattern may be located in the same column.

[0023] In example embodiments, the j+2nd, j+3rd, j+4th, and j+5th lower dummy patterns, the h+1st and h+2nd middle dummy patterns, and the g+2nd and g+3th upper dummy patterns may surround the k+1th reference dummy pattern.

[0024] In an example embodiment, the display device may further include a planarization layer covering the semiconductor element and the dummy pattern on the substrate. The pixel structure may include a lower electrode disposed in a display region on the planarization layer, a light-emitting layer disposed on the lower electrode, and an upper electrode disposed on the light-emitting layer. The lower electrode of the pixel structure is electrically connected to a drain electrode of the semiconductor element via a contact hole formed by removing a portion of the planarization layer.

[0025] A display device according to an exemplary embodiment of the present disclosure includes an active pattern and a dummy pattern structure disposed in a peripheral region adjacent to a display region, so that gaps between the gate insulating layer, the first insulating interlayer, the second insulating interlayer, and the third insulating interlayer may be less noticeable. Consequently, residues of a photoresist used in a process of etching each of the active pattern, the reference dummy pattern, the lower dummy pattern, the intermediate dummy pattern, and the upper dummy pattern may not remain, and the active layer, the first gate electrode, the second gate electrode, the third gate electrode, the source electrode, and the drain electrode disposed in the display region may not be short-circuited by the residues.

[0026] In a method for manufacturing a display device according to an exemplary embodiment of the present disclosure, the active pattern and dummy pattern structure formed in a peripheral region adjacent to the display region has a waffle shape with multiple grooves, so that the gaps between the gate insulating layer, the first insulating interlayer, the second insulating interlayer, and the third insulating interlayer can be less noticeable. As a result, residues of the photoresist used in the process of etching each of the active pattern, the reference dummy pattern, the lower dummy pattern, the intermediate dummy pattern, and the upper dummy pattern may not remain in the steps. As a result, when the active layer, the first gate electrode, the second gate electrode, the third gate electrode, the source electrode, and the drain electrode are formed in the display region, defects caused by the residues may not occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Example embodiments may be understood in more detail from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a top view illustrating a display device according to an example embodiment of the present disclosure;

[0029] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 It shows Figure 1 A partial enlarged top view of the "A" area;

[0030] Figure 8 It is used to describe the Figure 1 a top view of a reference dummy pattern in a display device;

[0031] Figure 9 It is used to describe the Figure 1 A top view of a lower dummy pattern in a display device;

[0032] Figure 10 It is along Figure 1 Line I-I' and Figure 7 A cross-sectional view taken along line II-II';

[0033] Figure 11 It is along Figure 7 A cross-sectional view taken along line III-III';

[0034] Figure 12 It is along Figure 7 A cross-sectional view taken along line IV-IV'; and

[0035] Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 、 Figure 25 、 Figure 26 、 Figure 27 、 Figure 28 and Figure 29 is a cross-sectional view illustrating a method of manufacturing a display device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Hereinafter, a display device and a method of manufacturing the display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals refer to the same or similar elements.

[0037] Figure 1 is a top plan view illustrating a display device according to an example embodiment of the present disclosure.

[0038] refer to Figure 1 , the display device 100 may have a display area 10 and a peripheral area 20. In this case, the peripheral area 20 may substantially surround the display area 10 (or at least partially surround the display area 10), and a pad electrode 470 electrically connected to an external device that generates a drive signal (e.g., a data signal, a gate signal, an emission control signal, a gate initialization signal, an initialization voltage, and a power supply voltage, etc.) may be provided on one side of the peripheral area 20. In addition, the display area 10 may include a plurality of pixel areas 30. For example, when viewed in a top view, the peripheral area 20 may have a hollow rectangular shape. In other words, when viewed in a top view, the peripheral area 20 may have a rectangular shape having an opening that exposes the display area 10.

[0039] The pixel region 30 may be arranged over the entire display region 10. For example, Figure 10 The pixel structure 200 and the semiconductor element 250 shown in FIG. 3 and the like may be provided in each of the pixel regions 30 . A driving signal may be supplied to the pixel structure 200 and the semiconductor element 250 , and an image may be displayed on the display region 10 through the pixel structure 200 and the semiconductor element 250 .

[0040] Although the display area 10 and the pixel area 30 according to the present disclosure have been described as having a rectangular shape when viewed from above, the configuration of the present disclosure is not limited. For example, when viewed from above, the display area 10 and the pixel area 30 may each have a triangular, diamond, polygonal, circular, racetrack, or elliptical shape.

[0041] In addition, a plurality of wirings may be provided in the peripheral region 20. For example, the wirings may include data signal wirings, gate signal wirings, emission control signal wirings, gate initialization signal wirings, initialization voltage wirings, and power supply voltage wirings. The wirings may be connected to the pad electrodes 470 in the peripheral region 20 and may extend from the peripheral region 20 to the display region 10 so as to be electrically connected to the pixel structure 200 and the semiconductor element 250. In other words, the drive signal may be transmitted to the pixel structure 200 and the semiconductor element 250 through the pad electrodes 470 and the wirings. In addition, a gate driver, a data driver, and the like may be provided in the peripheral region 20.

[0042] In an example embodiment, Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 The active pattern 530 and the dummy patterns 570, 575, 585 and 610 (eg, Figure 10 The dummy pattern structure 500 may be provided in the peripheral region 20.

[0043] For example, when etching the active layer and gate electrode (e.g., pattern) included in the semiconductor element in the process of manufacturing a conventional display device, the size of the pattern (e.g., the width of the pattern) in the central portion of the display area (e.g., the first area) and the display area adjacent to the peripheral area (e.g., the second area) may be different from each other. For example, since more semiconductor elements are arranged in the first area, there may be more etching target patterns in the first area, and since the second area is adjacent to the peripheral area, there may be fewer etching target patterns in the second area. In other words, the density of the pattern in the first area and the second area may be different from each other, and the concentration of the etchant used to etch the pattern may be relatively lower in the second area than in the first area. For example, after the initial metal layer is formed over the entire display area and the peripheral area, the pattern can be formed by partially etching the initial metal layer, wherein the pattern is not formed in the peripheral area, so that the concentration of the etchant can become relatively low in order to etch all the initial metal layers located in the peripheral area. In this case, the size of the pattern formed in the second area adjacent to the peripheral area may be relatively large, and the pattern may be short-circuited.

[0044] The display device 100 according to an exemplary embodiment of the present disclosure may include an active pattern 530 and dummy patterns 570, 575, 585, and 610 disposed in the peripheral region 20 adjacent to the display region 10. In this case, in the process of forming the semiconductor element 250 adjacent to the peripheral region 20, the active pattern 530 and the dummy patterns 570, 575, 585, and 610 disposed in the peripheral region 20 are simultaneously formed, so that the concentration of the etchant in the central portion of the display region 10 and in the display region 10 adjacent to the peripheral region 20 can be substantially the same. In other words, the distance between the semiconductor element 250 adjacent to the peripheral region 20 and the active pattern 530 and the dummy patterns 570, 575, 585, and 610 located in the peripheral region 20 can be determined in consideration of the distance between the semiconductor elements 250 disposed in the central portion of the display region 10. Therefore, the semiconductor element 250 formed in the central portion of the display area 10 and the semiconductor element 250 formed in the display area 10 adjacent to the peripheral area 20 can have substantially the same size, and the semiconductor element 250 formed in the display area 10 adjacent to the peripheral area 20 can have no defects.

[0045] Although the active pattern 530 and the dummy patterns 570, 575, 585, and 610 according to the present disclosure have been shown as being provided only at the peripheral "A" region, the configuration of the present disclosure is not limited. For example, the active pattern 530 and the dummy patterns 570, 575, 585, and 610 may be formed over the entire peripheral region 20 to substantially surround the display region 10, or may be formed only in a portion of the peripheral region 20 adjacent to a portion where an etchant concentration difference occurs.

[0046] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 It shows Figure 1 A partial enlarged top view of the "A" area, Figure 8 It is used to describe the Figure 1 a top view of a reference dummy pattern in a display device, and Figure 9 It is used to describe the Figure 1 For example, the display device 100 may include an active pattern 530 and dummy patterns 570, 575, 585, and 610 having a stacked structure, and the dummy patterns 570, 575, 585, and 610 may be classified as a reference dummy pattern 570, a lower dummy pattern 575, an intermediate dummy pattern 585, and an upper dummy pattern 610. In addition, Figure 2 is a top view showing the active pattern 530 arranged in the "A" area, Figure 3 is a top view showing a reference dummy pattern 570 arranged in the “A” region, Figure 4 is a top view showing the lower dummy pattern 575 arranged in the "A" area, Figure 5 is a top view showing the intermediate dummy pattern 585 arranged in the "A" area, Figure 6 is a top view showing the upper dummy pattern 610 arranged in the "A" area, and Figure 7 is a top view illustrating the active pattern 530 , the reference dummy pattern 570 , the lower dummy pattern 575 , the middle dummy pattern 585 , and the upper dummy pattern 610 together.

[0047] refer to Figure 2 , the display device 100 may further include Figure 10 , the active patterns 530 may be arranged in a lattice shape on the substrate 110 in the peripheral region 20. In other words, each of the active patterns 530 may be spaced apart from one another at a first interval in a first direction D1 parallel to the top surface of the substrate 110 and a second direction D2 perpendicular to the first direction D1 on the substrate 110 in the peripheral region 20.

[0048] refer to Figure 3 、 Figure 7 and Figure 8 , the reference dummy patterns 570 may be disposed on the active patterns 530. The reference dummy patterns 570 may be arranged in a grid shape on the active patterns 530. In other words, each of the reference dummy patterns 570 may be spaced apart from each other at a first interval in the first direction D1 and the second direction D2. In example embodiments, each of the reference dummy patterns 570 may overlap with each of the active patterns 530, respectively, and the active patterns 530 and the reference dummy patterns 570 may have substantially the same shape.

[0049] like Figure 8As shown in , each of the reference dummy patterns 570 may have a first side portion 570_1, a second side portion 570_2, a third side portion 570_3, and a fourth side portion 570_4. For example, in one of the reference dummy patterns 570, the first side portion 570_1 may be located on the left side, the second side portion 570_2 may be located on the right side, the third side portion 570_3 may be located on the upper side, and the fourth side portion 570_4 may be located on the lower side. In other words, the first side portion 570_1 and the second side portion 570_2 may face each other along the first direction D1, and the third side portion 570_3 and the fourth side portion 570_4 may face each other along the second direction D2. In addition, the two ends of the first side portion 570_1 may respectively include a first corner portion 570_6 and a second corner portion 570_7, the two ends of the second side portion 570_2 may respectively include a third corner portion 570_8 and a fourth corner portion 570_9, the two ends of the third side portion 570_3 may respectively include a first corner portion 570_6 and a third corner portion 570_8, and the two ends of the fourth side portion 570_4 may respectively include a second corner portion 570_7 and a fourth corner portion 570_9. In other words, the portion where the first side portion 570_1 and the third side portion 570_3 overlap with each other can be defined as a first corner portion 570_6, the portion where the first side portion 570_1 and the fourth side portion 570_4 overlap with each other can be defined as a second corner portion 570_7, the portion where the second side portion 570_2 and the third side portion 570_3 overlap with each other can be defined as a third corner portion 570_8, and the portion where the second side portion 570_2 and the fourth side portion 570_4 overlap with each other can be defined as a fourth corner portion 570_9.

[0050] refer to Figure 4 、 Figure 7 and Figure 9 , the lower dummy pattern 575 may be disposed on the reference dummy pattern 570. The lower dummy pattern 575 may be arranged in a grid shape on the reference dummy pattern 570. In other words, the lower dummy patterns 575 may be spaced apart at a first pitch in the first direction D1 and the second direction D2. In example embodiments, the lower dummy pattern 575 may overlap with the first corner 570_6, the second corner 570_7, the third corner 570_8, and the fourth corner 570_9 of each of the reference dummy patterns 570. The active pattern 530, the reference dummy pattern 570, and the lower dummy pattern 575 may have substantially the same shape.

[0051] like Figure 9As shown in , each of the lower dummy patterns 575 may have a first side portion 575_1, a second side portion 575_2, a third side portion 575_3, and a fourth side portion 575_4. For example, in one of the lower dummy patterns 575, the first side portion 575_1 may be located at the lower side, the second side portion 575_2 may be located at the upper side, the third side portion 575_3 may be located at the right side, and the fourth side portion 575_4 may be located at the left side. In other words, the first side portion 575_1 and the second side portion 575_2 may face each other along the second direction D2, and the third side portion 575_3 and the fourth side portion 575_4 may face each other along the first direction D1. In addition, the two ends of the first side portion 575_1 may respectively include a first corner portion 575_6 and a third corner portion 575_8, the two ends of the second side portion 575_2 may respectively include a second corner portion 575_7 and a fourth corner portion 575_9, the two ends of the third side portion 575_3 may respectively include a first corner portion 575_6 and a second corner portion 575_7, and the two ends of the fourth side portion 575_4 may respectively include a third corner portion 575_8 and a fourth corner portion 575_9. In other words, the portion where the first side portion 575_1 and the third side portion 575_3 overlap with each other can be defined as a first corner portion 575_6, the portion where the first side portion 575_1 and the fourth side portion 575_4 overlap with each other can be defined as a third corner portion 575_8, the portion where the second side portion 575_2 and the third side portion 575_3 overlap with each other can be defined as a second corner portion 575_7, and the portion where the second side portion 575_2 and the fourth side portion 575_4 overlap with each other can be defined as a fourth corner portion 575_9.

[0052] In example embodiments, one reference dummy pattern 570 may be adjacent to four lower dummy patterns 575. In addition, when the adjacent four lower dummy patterns 575 are defined as first to fourth lower dummy patterns 575, a first corner 575_6 of the first lower dummy pattern 575 and a first corner 570_6 of the one reference dummy pattern 570 may overlap with each other, a second corner 575_7 of the second lower dummy pattern 575 and a second corner 570_7 of the one reference dummy pattern 570 may overlap with each other, a third corner 575_8 of the third lower dummy pattern 575 and a third corner 570_8 of the one reference dummy pattern 570 may overlap with each other, and a fourth corner 575_9 of the fourth lower dummy pattern 575 and a fourth corner 570_9 of the one reference dummy pattern 570 may overlap with each other.

[0053] refer to Figure 5 and Figure 7, the intermediate dummy pattern 585 may be disposed on the lower dummy pattern 575. The intermediate dummy pattern 585 may be arranged in a grid shape on the lower dummy pattern 575. In other words, the intermediate dummy patterns 585 may be spaced apart at a first pitch in the first direction D1 and the second direction D2. In example embodiments, the intermediate dummy pattern 585 may overlap the first side portion 570_1 and the second side portion 570_2 of each of the reference dummy patterns 570 and the first side portion 575_1 and the second side portion 575_2 of each of the lower dummy patterns 575. The active pattern 530, the reference dummy pattern 570, the lower dummy pattern 575, and the intermediate dummy pattern 585 may have substantially the same shape.

[0054] In example embodiments, one reference dummy pattern 570 may be adjacent to two intermediate dummy patterns 585. In addition, when the adjacent two intermediate dummy patterns 585 are defined as first and second intermediate dummy patterns 585, the first intermediate dummy pattern 585 may simultaneously overlap the first side 575_1 of the first lower dummy pattern 575, the first side 570_1 of the one reference dummy pattern 570, and the second side 575_2 of the second lower dummy pattern 575, and the second intermediate dummy pattern 585 may simultaneously overlap the first side 575_1 of the third lower dummy pattern 575, the second side 570_2 of the one reference dummy pattern 570, and the second side 575_2 of the fourth lower dummy pattern 575.

[0055] In this case, the portion of the first intermediate dummy pattern 585 overlapping with the first corner 570_6 of the one reference dummy pattern 570 and the first corner 575_6 of the first lower dummy pattern 575 can be defined as the first corner of the first intermediate dummy pattern 585, the portion of the first intermediate dummy pattern 585 overlapping with the second corner 570_7 of the one reference dummy pattern 570 and the second corner 575_7 of the second lower dummy pattern 575 can be defined as the second corner of the first intermediate dummy pattern 585, the portion of the second intermediate dummy pattern 585 overlapping with the third corner 570_8 of the one reference dummy pattern 570 and the third corner 575_8 of the third lower dummy pattern 575 can be defined as the third corner of the second intermediate dummy pattern 585, and the portion of the second intermediate dummy pattern 585 overlapping with the fourth corner 570_9 of the one reference dummy pattern 570 and the fourth corner 575_9 of the fourth lower dummy pattern 575 can be defined as the fourth corner of the second intermediate dummy pattern 585.

[0056] refer to Figure 6 and Figure 7, the upper dummy pattern 610 may be disposed on the intermediate dummy pattern 585. The upper dummy pattern 610 may be arranged in a grid shape on the intermediate dummy pattern 585. In other words, the upper dummy patterns 610 may be spaced apart at a first pitch in the first direction D1 and the second direction D2. In example embodiments, the upper dummy pattern 610 may overlap the third side 570_3 and the fourth side 570_4 of each of the reference dummy patterns 570, the third side 575_3 and the fourth side 575_4 of each of the lower dummy patterns 575, and the first to fourth corners of each of the intermediate dummy patterns 585. The active pattern 530, the reference dummy pattern 570, the lower dummy pattern 575, the intermediate dummy pattern 585, and the upper dummy pattern 610 may have substantially the same shape.

[0057] In example embodiments, one reference dummy pattern 570 may be adjacent to two upper dummy patterns 610. Additionally, when the adjacent two upper dummy patterns 610 are defined as first and second upper dummy patterns 610, the first upper dummy pattern 610 may simultaneously overlap with the third side 575_3 of the first lower dummy pattern 575, the third side 570_3 of the one reference dummy pattern 570, the fourth side 575_4 of the third lower dummy pattern 575, the first corner of the first intermediate dummy pattern 585, and the third corner of the second intermediate dummy pattern 585, and the second upper dummy pattern 610 may simultaneously overlap with the third side 575_3 of the second lower dummy pattern 575, the fourth side 570_4 of the one reference dummy pattern 570, the fourth side 575_4 of the fourth lower dummy pattern 575, the second corner of the first intermediate dummy pattern 585, and the fourth corner of the second intermediate dummy pattern 585.

[0058] In other words, the dummy patterns 570, 575, 585 and 610 may include first to nth reference dummy patterns 570 (where n is an integer of 1 or greater), first to mth lower dummy patterns 575 (where m is an integer of 1 or greater) disposed on the first to nth reference dummy patterns 570, first to qth intermediate dummy patterns 585 (where q is an integer of 1 or greater) disposed on the first to mth lower dummy patterns 575, and first to pth upper dummy patterns 610 (where p is an integer of 1 or greater) disposed on the first to qth intermediate dummy patterns 585.

[0059] The first to fourth corners of the kth reference dummy pattern 570 (where k is an integer between 1 and n) among the first to nth reference dummy patterns 570 may overlap with the jth, j+1th, j+2th, and j+3th lower dummy patterns 575 (where j is an integer between 1 and m) among the first to mth lower dummy patterns 575, the hth and h+1th intermediate dummy patterns 585 (where h is an integer between 1 and q) among the first to qth intermediate dummy patterns 585, and the gth and g+1th upper dummy patterns 610 (where g is an integer between 1 and p) among the first to pth upper dummy patterns 610.

[0060] The gth upper dummy pattern 610 may be located between the jth and j+2th lower dummy patterns 575, and the jth and j+2th lower dummy patterns 575 and the gth upper dummy pattern 610 may be located in the same row; the g+1th upper dummy pattern 610 may be located between the j+1th and j+3th lower dummy patterns 575, and the j+1th and j+3th lower dummy patterns 575 and the g+1th upper dummy pattern 610 may be located in the same row; and the kth reference dummy pattern 570 may be located between the hth and h+1th intermediate dummy patterns 585, and the hth and h+1th intermediate dummy patterns 585 and the kth reference dummy pattern 510 may be located in the same row.

[0061] The hth intermediate dummy pattern 585 can be located between the jth and j+1th lower dummy patterns 575, and the jth and j+1th lower dummy patterns 575 and the hth intermediate dummy pattern 585 can be located in the same column; the kth reference dummy pattern 570 can be located between the gth and g+1th upper dummy patterns 610, and the gth and g+1th upper dummy patterns 610 and the kth reference dummy pattern 570 can be located in the same column; and the h+1th intermediate dummy pattern 585 can be located between the j+2th and j+3th lower dummy patterns 575, and the j+2th and j+3th lower dummy patterns 575 and the h+1th intermediate dummy pattern 585 can be located in the same column.

[0062] The jth, j+1th, j+2th, and j+3th lower dummy patterns 575 , the hth and h+1th middle dummy patterns 585 , and the gth and g+1th upper dummy patterns 610 may surround the kth reference dummy pattern 570 .

[0063] The first to fourth corners of the k+1th reference dummy pattern 570 located in the same row as the kth reference dummy pattern 570 may overlap with the j+2th and j+3th lower dummy patterns 575, the j+4th and j+5th lower dummy patterns 575, the h+1th middle dummy pattern 585, the h+2th middle dummy pattern 585, and the g+2th and g+3th upper dummy patterns 610.

[0064] The g+2th upper dummy pattern 610 may be located between the j+2th and j+4th lower dummy patterns 575, and the j, j+2th, and j+4th lower dummy patterns 575 and the g and g+2th upper dummy patterns 610 may be located in the same row, the g+3th upper dummy pattern 610 may be located between the j+3th and j+5th lower dummy patterns 575, and the j+1th, j+3th, and j+5th lower dummy patterns 575 and the g+1th and g+3th upper dummy patterns 610 may be located in the same row, and the k+1th reference dummy pattern 570 may be located between the h+1th and h+2th intermediate dummy patterns 585. The h, h+1th, and h+2th intermediate dummy patterns 585 and the k and k+1th reference dummy patterns 570 may be located in the same row.

[0065] The h+1th intermediate dummy pattern 585 may be located between the j+2th and j+3th lower dummy patterns 575, and the j+2th and j+3th lower dummy patterns 575 and the h+1th intermediate dummy pattern 585 may be located in the same column, the k+1th reference dummy pattern 570 may be located between the g+2th and g+3th upper dummy patterns 610, and the g+2th and g+3th upper dummy patterns 610 and the k+1th reference dummy pattern 570 may be located in the same column, and the h+2th intermediate dummy pattern 585 may be located between the j+4th and j+5th lower dummy patterns 575. The j+4th and j+5th lower dummy patterns 575 and the h+2th intermediate dummy pattern 585 may be located in the same column.

[0066] The j+2nd, j+3rd, j+4th, and j+5th lower dummy patterns 575 , the h+1st and h+2nd middle dummy patterns 585 , and the g+2nd and g+3rd upper dummy patterns 610 may surround the k+1th reference dummy pattern 570 .

[0067] As described above, the dummy patterns 570, 575, 585, and 610 may be arranged in different layers in a lattice shape, and each of the dummy patterns 570, 575, 585, and 610 may include a central portion CP and an edge portion EP surrounding the central portion CP (see FIG. Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 and Figure 6). Edge portions EP of the dummy patterns 570, 575, 585, and 610 that are adjacent to each other in different layers may overlap with each other along a third direction D3 perpendicular to the first direction D1 and the second direction D2. In other words, central portions CP of the dummy patterns 570, 575, 585, and 610 that are adjacent to each other in different layers may not overlap with each other. That is, the active pattern 530 and the dummy patterns 570, 575, 585, and 610 may have a waffle shape having a plurality of grooves. For example, the first side 570_1, the second side 570_2, the third side 570_3, and the fourth side 570_4 of the reference dummy pattern 570 may be defined as an edge portion EP of the reference dummy pattern 570, and the remaining portion of the reference dummy pattern 570 other than the first side 570_1, the second side 570_2, the third side 570_3, and the fourth side 570_4 may be defined as a central portion CP of the reference dummy pattern 570. In addition, the first side 575_1, the second side 575_2, the third side 575_3, and the fourth side 575_4 of the lower dummy pattern 575 may be defined as an edge portion EP of the lower dummy pattern 575, and the remaining portion of the lower dummy pattern 575 other than the first side 575_1, the second side 575_2, the third side 575_3, and the fourth side 575_4 may be defined as a central portion CP of the lower dummy pattern 575. Similarly, each of the active pattern 530 , the middle dummy pattern 585 , and the upper dummy pattern 610 may also have an edge portion EP and a central portion CP defined as described above.

[0068] The display device 100 according to an example embodiment of the present disclosure may include an active pattern 530 and dummy patterns 570, 575, 585, and 610 provided in a peripheral region 20 adjacent to the display region 10. In this case, the semiconductor element 250 formed in the central portion of the display region 10 and the semiconductor element 250 formed in the display region 10 adjacent to the peripheral region 20 may have substantially the same size, and the semiconductor element 250 formed in the display region 10 adjacent to the peripheral region 20 may not have defects. In addition, edge portions EP of the dummy patterns 570, 575, 585, and 610 adjacent to each other in different layers overlap with each other in the third direction D3, so that the insulating layer (e.g., Figure 10 The gap between the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195 and the third insulating interlayer 205 may not be obvious. Therefore, the residue of the photoresist used in the process of etching the dummy patterns 570, 575, 585 and 610 may not remain, and the electrodes (e.g., Figure 10The active layer 130, the first gate electrode 170, the second gate electrode 175, the third gate electrode 185, the source electrode 210, and the drain electrode 230 may not be short-circuited by the residue.

[0069] Although the dummy patterns 570, 575, 585, and 610 according to the present disclosure have been described as four patterns, the configuration of the present disclosure is not limited thereto. For example, the number of the dummy patterns 570, 575, 585, and 610 may be determined so that the edge portions EP of the dummy patterns 570, 575, 585, and 610 adjacent to each other in different layers overlap each other along the third direction D3.

[0070] Figure 10 It is along Figure 1 Line I-I' and Figure 7 A cross-sectional view taken along line II-II', Figure 11 It is along Figure 7 A cross-sectional view taken along line III-III', and Figure 12 It is along Figure 7 A cross-sectional view taken along line IV-IV'.

[0071] refer to Figure 10 、 Figure 11 and Figure 12 , the display device 100 may include a substrate 110, a semiconductor element 250, a pixel structure 200, a planarization layer 270, a pixel defining layer 310, a dummy pattern structure 500, and an active pattern 530. In this case, the semiconductor element 250 may include an active layer 130, a gate insulating layer 150, a first gate electrode 170, a first insulating interlayer 190, a second gate electrode 175, a second insulating interlayer 195, a third gate electrode 185, a third insulating interlayer 205, a source electrode 210, and a drain electrode 230, and the pixel structure 200 may include a lower electrode 290, an organic light emitting layer 330, and an upper electrode 340. In addition, the dummy pattern structure 500 may include a reference dummy pattern 570, a lower dummy pattern 575, an intermediate dummy pattern 585, and an upper dummy pattern 610.

[0072] A substrate 110 including a transparent or opaque material may be provided. The substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (F-doped quartz substrate), a soda-lime glass substrate, and an alkali-free glass substrate.

[0073] In some embodiments, the substrate 110 can be a transparent resin substrate with flexibility. One of the examples of the transparent resin substrate that can be used as the substrate 110 includes a polyimide substrate. In this case, the polyimide substrate can include a first polyimide layer, a barrier film layer, and a second polyimide layer. For example, the polyimide substrate can have a configuration in which the first polyimide layer, the barrier film layer, and the second polyimide layer are sequentially stacked on a rigid glass substrate. In the method for manufacturing the display device 100, after the insulating layer (e.g., a buffer layer) is provided on the second polyimide layer of the polyimide substrate, the upper structure (e.g., semiconductor element 250 and pixel structure 200, etc.) can be provided on the insulating layer. After forming the upper structure, the rigid glass substrate can be removed. In other words, since the polyimide substrate is thin and flexible, it may be difficult to form the upper structure directly on the polyimide substrate. Taking these aspects into account, the upper structure can be formed by using a rigid glass substrate, and then the glass substrate can be removed so that the polyimide substrate can be used as the substrate 110.

[0074] Since the display device 100 includes a display region 10 including a pixel region 30 and a peripheral region 20 , the substrate 110 may also be divided into the display region 10 (or the pixel region 30 ) and the peripheral region 20 .

[0075] A buffer layer (not shown) may be provided on the substrate 110. The buffer layer may be provided over the entire display area 10 and the peripheral area 20 on the substrate 110. The buffer layer may prevent metal atoms or impurities from diffusing from the substrate 110 to the semiconductor element 250, and may control the heat transfer rate during the crystallization process for forming the active layer 130 and the active pattern 530 to obtain a substantially uniform active layer 130 and a substantially uniform active pattern 530. In addition, when the surface of the substrate 110 is uneven, the buffer layer may be used to improve the flatness of the surface of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers may be provided on the substrate 110, or no buffer layer may be provided. The buffer layer may include an organic insulating material or an inorganic insulating material.

[0076] The active layer 130 may be provided in the display region 10 on the substrate 110. The active layer 130 may include a metal oxide semiconductor, an inorganic semiconductor (e.g., an amorphous silicon or polycrystalline silicon semiconductor), or an organic semiconductor, etc. The active layer 130 may have a source region, a drain region, and a channel region located between the source region and the drain region.

[0077] The active pattern 530 may be provided in the peripheral region 20 on the substrate 110. The active pattern 530 may be arranged in a lattice shape. In example embodiments, the active pattern 530 may include the same material as the active layer 130 and may be located on the same layer as the active layer 130.

[0078] The gate insulating layer 150 may be disposed on the substrate 110, the active layer 130, and the active pattern 530. The gate insulating layer 150 may extend from the display area 10 to the peripheral area 20 to cover the active layer 130 in the display area 10 on the substrate 110, and may cover the active pattern 530 in the peripheral area 20. For example, the gate insulating layer 150 may be disposed with a uniform thickness along the contours of the active layer 130 and the active pattern 530 to cover the active layer 130 and the active pattern 530 on the substrate 110. In some embodiments, the gate insulating layer 150 may fully cover the active layer 130 in the display area 10 and the active pattern 530 in the peripheral area 20 on the substrate 110, and may have a substantially flat top surface without forming steps around the active layer 130 and the active pattern 530. The gate insulating layer 150 may include a silicon compound and a metal oxide. For example, the gate insulating layer 150 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), silicon carbonitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ) and titanium oxide (TiO x In other example embodiments, the gate insulating layer 150 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0079] The first gate electrode 170 may be disposed in the display region 10 on the gate insulating layer 150. The first gate electrode 170 may be disposed on a portion of the gate insulating layer 150 under which the active layer 130 is located (e.g., to overlap with the channel region of the active layer 130). The first gate electrode 170 may include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. For example, the first gate electrode 170 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an aluminum alloy, aluminum nitride (AlN), or the like. x ), silver alloy, tungsten nitride (WN x ), copper-containing alloys, molybdenum-containing alloys, titanium nitride (TiNx ), chromium nitride (CrN x ), tantalum nitride (TaN x ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (ZnO x ), indium tin oxide (ITO), tin oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ) and indium zinc oxide (IZO). These may be used alone or in combination with each other. In other example embodiments, the first gate electrode 170 may have a multilayer structure including a plurality of metal layers. For example, these metal layers may have different thicknesses or may include different materials.

[0080] The reference dummy pattern 570 may be disposed in the peripheral region 20 on the gate insulating layer 150. The reference dummy pattern 570 may be arranged in a grid shape. In other words, the reference dummy pattern 570 may be disposed on portions of the gate insulating layer 150 under which the active patterns 530 are respectively located. Figure 8 As shown in FIG, each of the reference dummy patterns 570 may include a first side 570_1, a second side 570_2, a third side 570_3, and a fourth side 570_4. The first side 570_1 may include a first corner 570_6 and a second corner 570_7 at both ends, the second side 570_2 may include a third corner 570_8 and a fourth corner 570_9 at both ends, the third side 570_3 may include a first corner 570_6 and a third corner 570_8 at both ends, and the fourth side 570_4 may include a second corner 570_7 and a fourth corner 570_9 at both ends. In example embodiments, the reference dummy pattern 570 may include the same material as the first gate electrode 170 and may be located on the same layer as the first gate electrode 170.

[0081] A first insulating interlayer 190 may be disposed on the gate insulating layer 150, the first gate electrode 170, and the reference dummy pattern 570. The first insulating interlayer 190 may extend from the display region 10 to the peripheral region 20 to cover the first gate electrode 170 in the display region 10 on the gate insulating layer 150, and may cover the reference dummy pattern 570 in the peripheral region 20. For example, the first insulating interlayer 190 may be disposed with a uniform thickness along the contours of the first gate electrode 170 and the reference dummy pattern 570 to cover the first gate electrode 170 and the reference dummy pattern 570 on the gate insulating layer 150. In some embodiments, the first insulating interlayer 190 may fully cover the first gate electrode 170 and the reference dummy pattern 570 on the gate insulating layer 150 and may have a substantially flat top surface without forming steps around the first gate electrode 170 and the reference dummy pattern 570. The first insulating interlayer 190 may include a silicon compound, a metal oxide, or the like. In other example embodiments, the first insulating interlayer 190 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0082] The second gate electrode 175 may be disposed in the display region 10 on the first insulating interlayer 190. The second gate electrode 175 may be disposed on the portion of the first insulating interlayer 190 below which the first gate electrode 170 is located. The second gate electrode 175 may include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These may be used alone or in combination with one another. In other example embodiments, the second gate electrode 175 may have a multilayer structure including multiple metal layers. For example, these metal layers may have different thicknesses or may include different materials.

[0083] The lower dummy patterns 575 may be provided in the peripheral region 20 on the first insulating interlayer 190. The lower dummy patterns 575 may be arranged in a grid shape. In other words, each of the lower dummy patterns 575 may partially overlap with the reference dummy pattern 570 at a portion of the first insulating interlayer 190 under which the reference dummy pattern 570 is located. In addition, the lower dummy pattern 575 may overlap with the first corner 570_6, the second corner 570_7, the third corner 570_8, and the fourth corner 570_9 of each of the reference dummy patterns 570. Figure 9As shown in , each of the lower dummy patterns 575 may have a first side portion 575_1, a second side portion 575_2, a third side portion 575_3, and a fourth side portion 575_4. The first side portion 575_1 may have first and third corner portions 575_6 and 575_8 at both ends, the second side portion 575_2 may have second and fourth corner portions 575_7 and 575_9 at both ends, the third side portion 575_3 may have first and second corner portions 575_6 and 575_7 at both ends, and the fourth side portion 575_4 may have third and fourth corner portions 575_8 and 575_9 at both ends. In example embodiments, the lower dummy pattern 575 may include the same material as the second gate electrode 175 and may be located on the same layer as the second gate electrode 175.

[0084] A second insulating interlayer 195 in the display region 10 and the peripheral region 20 may be disposed over the first insulating interlayer 190, the second gate electrode 175, and the lower dummy pattern 575. The second insulating interlayer 195 may extend from the display region 10 to the peripheral region 20 to cover the second gate electrode 175 in the display region 10 on the first insulating interlayer 190 and may cover the lower dummy pattern 575 in the peripheral region 20. For example, the second insulating interlayer 195 may be disposed with a uniform thickness along the contours of the second gate electrode 175 and the lower dummy pattern 575 to cover the second gate electrode 175 and the lower dummy pattern 575 on the first insulating interlayer 190. In some embodiments, the second insulating interlayer 195 may fully cover the second gate electrode 175 and the lower dummy pattern 575 on the first insulating interlayer 190 and may have a substantially flat top surface without forming steps around the second gate electrode 175 and the lower dummy pattern 575. The second insulating interlayer 195 may include a silicon compound and a metal oxide. In other example embodiments, the second insulating interlayer 195 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0085] The third gate electrode 185 may be disposed in the display region 10 on the second insulating interlayer 195. The third gate electrode 185 may be disposed on the portion of the second insulating interlayer 195 below which the second gate electrode 175 is located. The third gate electrode 185 may include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These may be used alone or in combination. In other exemplary embodiments, the third gate electrode 185 may have a multilayer structure including multiple metal layers. For example, these metal layers may have different thicknesses or may include different materials.

[0086] Intermediate dummy patterns 585 may be disposed in the peripheral region 20 on the second insulating interlayer 195. The intermediate dummy patterns 585 may be arranged in a grid pattern. In other words, each of the intermediate dummy patterns 585 may partially overlap the reference dummy pattern 570 and the lower dummy pattern 575 at the portion of the second insulating interlayer 195 where the reference dummy pattern 570 and the lower dummy pattern 575 are located. Furthermore, the intermediate dummy patterns 585 may overlap the first side 570_1 and the second side 570_2 of each of the reference dummy patterns 570, as well as the first side 575_1 and the second side 575_2 of each of the lower dummy patterns 575. In example embodiments, the intermediate dummy patterns 585 may include the same material as the third gate electrode 185 and may be located on the same layer as the third gate electrode 185.

[0087] A third insulating interlayer 205 in the display region 10 and the peripheral region 20 may be disposed on the second insulating interlayer 195, the third gate electrode 185, and the intermediate dummy pattern 585. The third insulating interlayer 205 may extend from the display region 10 to the peripheral region 20 to cover the third gate electrode 185 in the display region 10 on the second insulating interlayer 195 and may also cover the intermediate dummy pattern 585 in the peripheral region 20. For example, the third insulating interlayer 205 may be disposed with a uniform thickness along the contours of the third gate electrode 185 and the intermediate dummy pattern 585 to cover the third gate electrode 185 and the intermediate dummy pattern 585 on the second insulating interlayer 195. In some embodiments, the third insulating interlayer 205 may fully cover the third gate electrode 185 and the intermediate dummy pattern 585 on the second insulating interlayer 195 and may have a substantially flat top surface without forming steps around the third gate electrode 185 and the intermediate dummy pattern 585. The third insulating interlayer 205 may include a silicon compound and a metal oxide. In other example embodiments, the third insulating interlayer 205 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0088] The source electrode 210 and the drain electrode 230 may be disposed in the display region 10 on the third insulating interlayer 205. The source electrode 210 may be connected to the source region of the active layer 130 via a contact hole formed by removing the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195, and the first portion of the third insulating interlayer 205. The drain electrode 230 may be connected to the drain region of the active layer 130 via a contact hole formed by removing the second portion of the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195, and the third insulating interlayer 205. Each of the source electrode 210 and the drain electrode 230 may include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These may be used alone or in combination with one another. In other example embodiments, each of the source electrode 210 and the drain electrode 230 may have a multilayer structure including multiple metal layers. For example, these metal layers may have different thicknesses or may include different materials.

[0089] Thus, a semiconductor element 250 including an active layer 130 , a gate insulating layer 150 , a first gate electrode 170 , a first insulating interlayer 190 , a second gate electrode 175 , a second insulating interlayer 195 , a third gate electrode 185 , a third insulating interlayer 205 , a source electrode 210 , and a drain electrode 230 may be provided.

[0090] Although the semiconductor element 250 has been described as having a top gate structure, the configuration of the present disclosure is not limited thereto. For example, the semiconductor element 250 may have a bottom gate structure.

[0091] In addition, although the display device 100 has been described as including one semiconductor element, the configuration of the present disclosure is not limited thereto. For example, the display device 100 may include at least one semiconductor element and at least one storage capacitor.

[0092] Furthermore, although the semiconductor element 250 has been described as having three gate electrodes, the configuration of the present disclosure is not limited thereto. For example, the semiconductor element 250 may have at least one gate electrode. In this case, the active pattern 530 may overlap with one of the first corner 570_6, the second corner 570_7, the third corner 570_8, and the fourth corner 570_9 of each of the reference dummy patterns 570, while partially overlapping with the reference dummy pattern 570.

[0093] The upper dummy patterns 610 may be disposed in the peripheral region 20 on the third insulating interlayer 205. The upper dummy patterns 610 may be arranged in a grid pattern. In other words, each of the upper dummy patterns 610 may partially overlap the reference dummy pattern 570, the lower dummy pattern 575, and the intermediate dummy pattern 585 at portions of the third insulating interlayer 205 where the reference dummy pattern 570, the lower dummy pattern 575, and the intermediate dummy pattern 585 are located. Furthermore, the upper dummy patterns 610 may overlap the third side 570_3 and the fourth side 570_4 of each of the reference dummy patterns 570, the third side 575_3 and the fourth side 575_4 of each of the lower dummy patterns 575, and the first corner, second corner, third corner, and fourth corner of each of the intermediate dummy patterns 585. In example embodiments, the upper dummy pattern 610 may include the same material as the source electrode 210 and the drain electrode 230 , and may be located on the same layer as the source electrode 210 and the drain electrode 230 .

[0094] Thus, the dummy pattern structure 500 including the reference dummy pattern 570 , the lower dummy pattern 575 , the middle dummy pattern 585 , and the upper dummy pattern 610 may be provided.

[0095] The planarization layer 270 in the display area 10 and the peripheral area 20 may be disposed on the third insulating interlayer 205, the upper dummy pattern 610, the source electrode 210, and the drain electrode 230. The planarization layer 270 may extend to the peripheral area 20 to cover the source electrode 210 and the drain electrode 230 in the display area 10 on the third insulating interlayer 205, and may cover the upper dummy pattern 610 in the peripheral area 20. The planarization layer 270 may be disposed in the display area 10 and the peripheral area 20 with a relatively thick thickness. In this case, the planarization layer 270 may have a substantially flat top surface. To achieve such a flat top surface of the planarization layer 270, a planarization process may be additionally performed on the planarization layer 270. In some embodiments, the planarization layer 270 may be disposed in the display area 10 and the peripheral area 20 on the third insulating interlayer 205 with a uniform thickness along the contours of the upper dummy pattern 610, the source electrode 210, and the drain electrode 230. The planarization layer 270 may be formed of an organic insulating material or an inorganic insulating material. In example embodiments, the planarization layer 270 may include an organic insulating material. For example, the planarization layer 270 may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, and an epoxy resin.

[0096] The lower electrode 290 may be disposed in the display region 10 on the planarization layer 270. The lower electrode 290 may be connected to the drain electrode 230 via a contact hole formed by removing a portion of the planarization layer 270 to electrically connect to the semiconductor element 250. The lower electrode 290 may include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These may be used alone or in combination with one another. In other example embodiments, the lower electrode 290 may have a multilayer structure including a plurality of metal layers. For example, these metal layers may have different thicknesses or may include different materials.

[0097] The pixel defining layer 310 may extend from the display region 10 to the peripheral region 20 to expose a portion of the lower electrode 290 in the display region 10 on the planarization layer 270. In some embodiments, the pixel defining layer 310 may be provided only in the display region 10 and not in the peripheral region 20. The pixel defining layer 310 may be formed of an organic material or an inorganic material. In example embodiments, the pixel defining layer 310 may include an organic material.

[0098] The organic light emitting layer 330 in the display area 10 may be disposed on the lower electrode 290 partially exposed by the pixel defining layer 310. The organic light emitting layer 330 may be formed according to the pixel by using at least one of the light emitting materials for emitting light of different colors (i.e., red light, green light, blue light, etc.). Alternatively, the organic light emitting layer 330 may be formed by stacking a plurality of light emitting materials for generating light of different colors such as red light, green light, and blue light to emit white light as a whole. In this case, a color filter may be disposed on the organic light emitting layer 330. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. In some embodiments, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin or a color photoresist.

[0099] The upper electrode 340 may be disposed in the display region 10 above the pixel defining layer 310 and the organic light emitting layer 330. The upper electrode 340 may include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These may be used alone or in combination with one another. In other exemplary embodiments, the upper electrode 340 may have a multilayer structure including multiple metal layers. For example, these metal layers may have different thicknesses or may include different materials.

[0100] Thus, the pixel structure 200 including the lower electrode 290 , the organic light emitting layer 330 , and the upper electrode 340 may be provided.

[0101] An encapsulation substrate (not shown) may be disposed on the upper electrode 340 in the display area 10. The encapsulation substrate may face the substrate 110. The encapsulation substrate may include substantially the same material as the substrate 110. For example, the encapsulation substrate may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a F-doped quartz substrate, a soda-lime glass substrate, and an alkali-free glass substrate. In other example embodiments, the encapsulation substrate may be replaced by a thin film encapsulation structure in which at least one inorganic layer and at least one organic layer are alternately stacked to improve the flexibility of the display device 100. In this case, the thin film encapsulation structure may include a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer. For example, a first inorganic insulating layer having flexibility may be disposed along the contour of the upper electrode 340, an organic insulating layer having flexibility may be disposed on the first inorganic insulating layer, and a second inorganic insulating layer having flexibility may be disposed on the organic insulating layer.

[0102] The display device 100 according to an exemplary embodiment of the present disclosure includes an active pattern 530 and a dummy pattern structure 500 disposed in the peripheral region 20 adjacent to the display region 10, so that gaps between the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195, and the third insulating interlayer 205 may not be noticeable. Therefore, residues of a photoresist used in a process of etching each of the active pattern 530, the reference dummy pattern 570, the lower dummy pattern 575, the intermediate dummy pattern 585, and the upper dummy pattern 610 may not remain, and the active layer 130, the first gate electrode 170, the second gate electrode 175, the third gate electrode 185, the source electrode 210, and the drain electrode 230 disposed in the display region 10 may not be short-circuited by the residues.

[0103] Although the display device 100 according to the present disclosure has been described as an organic light emitting diode display device, the configuration of the present disclosure is not limited thereto. In other example embodiments, the display device 100 may include a liquid crystal display device (LCD), a field emission display device (FED), a plasma display device (PDP), or an electrophoretic image display device (EPD).

[0104] Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 、 Figure 25 、 Figure 26 、 Figure 27 、 Figure 28 and Figure 29is a cross-sectional view illustrating a method of manufacturing a display device according to an example embodiment of the present disclosure.

[0105] refer to Figure 2 、 Figure 13 、 Figure 14 and Figure 15 A substrate 110 including a transparent or opaque material may be provided. The substrate 110 may be formed using a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, an F-doped quartz substrate, a soda-lime glass substrate, and an alkali-free glass substrate. The substrate 110 may be divided into a display area 10 and a peripheral area 20.

[0106] The active layer 130 may be formed on the substrate 110 in the display region 10. The active layer 130 may be formed using a metal oxide semiconductor, an inorganic semiconductor, or an organic semiconductor. The active layer 130 may have a source region, a drain region, and a channel region between the source region and the drain region.

[0107] The active pattern 530 may be formed in the peripheral region 20 on the substrate 110. The active pattern 530 may be arranged in a lattice shape. In example embodiments, the active pattern 530 may be formed simultaneously with the active layer 130 using the same material as the active layer 130. For example, after the initial active layer is formed over the entire region of the substrate 110, the initial active layer may be partially etched to simultaneously form the active layer 130 and the active pattern 530.

[0108] The gate insulating layer 150 may be formed over the entire area of ​​the substrate 110, the active layer 130, and the active pattern 530. For example, the gate insulating layer 150 may be formed with a uniform thickness along the contours of the active layer 130 and the active pattern 530 to cover the active layer 130 and the active pattern 530 on the substrate 110. The gate insulating layer 150 may be formed by using silicon compounds, metal oxides, and the like. For example, the gate insulating layer 150 may include SiO x 、SiN x 、SiO x N y 、SiO x C y 、SiC x N y 、AlO x 、AlN x 、TaO x , HfO x 、ZrO x and TiO x .

[0109] refer to Figure 3 、 Figure 16 、 Figure 17 and Figure 18, the first gate electrode 170 may be formed in the display region 10 on the gate insulating layer 150. The first gate electrode 170 may be formed on a portion of the gate insulating layer 150 where the active layer 130 is located. The first gate electrode 170 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. For example, the first gate electrode 170 may include Au, Ag, Al, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, W, Cu, Mo, Sc, Nd, Ir, an aluminum alloy, AlN x , silver alloy, WN x , copper-containing alloys, molybdenum-containing alloys, TiN x 、CrN x 、TaN x 、SrRu x O y 、ZnO x 、ITO、SnO x 、InO x 、GaO x and IZO. These may be used alone or in combination with each other.

[0110] Reference dummy patterns 570 may be formed in the peripheral region 20 on the gate insulating layer 150. The reference dummy patterns 570 may be arranged in a lattice shape. Each of the reference dummy patterns 570 may overlap with each of the active patterns 530, respectively. In example embodiments, the reference dummy patterns 570 may be formed simultaneously with the first gate electrode 170 using the same material as the first gate electrode 170. For example, after a first preliminary electrode layer is formed over the entire region of the gate insulating layer 150, the first preliminary electrode layer may be partially etched to simultaneously form the first gate electrode 170 and the reference dummy patterns 570.

[0111] The first insulating interlayer 190 may be formed over the entire region of the gate insulating layer 150, the first gate electrode 170, and the reference dummy pattern 570. For example, the first insulating interlayer 190 may be formed with a uniform thickness along the contours of the first gate electrode 170 and the reference dummy pattern 570 to cover the first gate electrode 170 and the reference dummy pattern 570 on the gate insulating layer 150. The first insulating interlayer 190 may be formed by using a silicon compound and a metal oxide.

[0112] refer to Figure 19 、 Figure 20 、 Figure 21 and Figure 22, the second gate electrode 175 may be formed in the display region 10 on the first insulating interlayer 190. The second gate electrode 175 may be formed on a portion of the first insulating interlayer 190 where the first gate electrode 170 is located. The second gate electrode 175 may be formed using metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These may be used alone or in combination with one another.

[0113] Lower dummy patterns 575 may be formed in the peripheral region 20 on the first insulating interlayer 190. The lower dummy patterns 575 may be arranged in a lattice shape. Each of the lower dummy patterns 575 may partially overlap the reference dummy pattern 570. In example embodiments, the lower dummy patterns 575 may be formed simultaneously with the second gate electrode 175 using the same material as the second gate electrode 175. For example, after the second preliminary electrode layer is formed over the entire area of ​​the first insulating interlayer 190, the second preliminary electrode layer may be partially etched to simultaneously form the second gate electrode 175 and the lower dummy patterns 575.

[0114] The second insulating interlayer 195 may be formed over the entire area of ​​the first insulating interlayer 190, the second gate electrode 175, and the lower dummy pattern 575. For example, the second insulating interlayer 195 may be formed with a uniform thickness along the contours of the second gate electrode 175 and the lower dummy pattern 575 to cover the second gate electrode 175 and the lower dummy pattern 575 on the first insulating interlayer 190. The second insulating interlayer 195 may be formed by using a silicon compound and a metal oxide.

[0115] refer to Figure 23 、 Figure 24 、 Figure 25 and Figure 26 , a third gate electrode 185 may be formed in the display region 10 on the second insulating interlayer 195. The third gate electrode 185 may be formed on a portion of the second insulating interlayer 195 below which the second gate electrode 175 is located. The third gate electrode 185 may be formed using metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These may be used alone or in combination with one another.

[0116] Intermediate dummy patterns 585 may be formed in the peripheral region 20 on the second insulating interlayer 195. The intermediate dummy patterns 585 may be arranged in a grid shape. Each of the intermediate dummy patterns 585 may partially overlap the reference dummy pattern 570 and the lower dummy pattern 575. In example embodiments, the intermediate dummy patterns 585 may be formed simultaneously with the third gate electrode 185 using the same material as the third gate electrode 185. For example, after the third preliminary electrode layer is formed over the entire area of ​​the second insulating interlayer 195, the third preliminary electrode layer may be partially etched to simultaneously form the third gate electrode 185 and the intermediate dummy patterns 585.

[0117] The third insulating interlayer 205 may be formed over the entire area of ​​the second insulating interlayer 195, the third gate electrode 185, and the intermediate dummy pattern 585. For example, the third insulating interlayer 205 may be formed with a uniform thickness along the contours of the third gate electrode 185 and the intermediate dummy pattern 585 to cover the third gate electrode 185 and the intermediate dummy pattern 585 on the second insulating interlayer 195. The third insulating interlayer 205 may be formed using a silicon compound and a metal oxide.

[0118] refer to Figure 7 、 Figure 27 、 Figure 28 and Figure 29 , the source electrode 210 and the drain electrode 230 may be formed in the display region 10 on the third insulating interlayer 205. The source electrode 210 may be connected to the source region of the active layer 130 via a contact hole formed by removing the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195, and the first portion of the third insulating interlayer 205; and the drain electrode 230 may be connected to the drain region of the active layer 130 via a contact hole formed by removing the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195, and the second portion of the third insulating interlayer 205. Each of the source electrode 210 and the drain electrode 230 may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These may be used alone or in combination with each other.

[0119] Thus, a semiconductor element 250 including an active layer 130, a gate insulating layer 150, a first gate electrode 170, a first insulating interlayer 190, a second gate electrode 175, a second insulating interlayer 195, a third gate electrode 185, a third insulating interlayer 205, a source electrode 210, and a drain electrode 230 may be formed.

[0120] Upper dummy patterns 610 may be formed in the peripheral region 20 on the third insulating interlayer 205. The upper dummy patterns 610 may be arranged in a grid shape. Each of the upper dummy patterns 610 may partially overlap with the reference dummy pattern 570, the lower dummy pattern 575, and the intermediate dummy pattern 585. In example embodiments, the upper dummy patterns 610 may be formed simultaneously with the source electrode 210 and the drain electrode 230 using the same material as the source electrode 210 and the drain electrode 230. For example, after the fourth preliminary electrode layer is formed over the entire area of ​​the third insulating interlayer 205, the fourth preliminary electrode layer may be partially etched to simultaneously form the source electrode 210, the drain electrode 230, and the upper dummy patterns 610.

[0121] Thus, a dummy pattern structure 500 including the reference dummy pattern 570 , the lower dummy pattern 575 , the middle dummy pattern 585 , and the upper dummy pattern 610 may be formed.

[0122] The planarization layer 270 may be formed over the entire area of ​​the third insulating interlayer 205, the upper dummy pattern 610, the source electrode 210, and the drain electrode 230. The planarization layer 270 may be formed with a relatively thick thickness in the display area 10 and the peripheral area 20. In this case, the planarization layer 270 may have a substantially flat top surface. To achieve such a flat top surface of the planarization layer 270, a planarization process may be additionally performed on the planarization layer 270. The planarization layer 270 may be formed using an organic insulating material. For example, the planarization layer 270 may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, and an epoxy resin.

[0123] refer to Figure 10 , the lower electrode 290 may be formed on the planarization layer 270 in the display region 10. The lower electrode 290 may be formed by using metal, alloy, metal nitride, conductive metal oxide, and transparent conductive material. These may be used alone or in combination with each other.

[0124] The pixel defining layer 310 may extend from the display region 10 to the peripheral region 20 to expose a portion of the lower electrode 290 in the display region 10 on the planarization layer 270. The pixel defining layer 310 may be formed by using an organic insulating material.

[0125] The organic light emitting layer 330 may be formed on the lower electrode 290 partially exposed by the pixel defining layer 310. The organic light emitting layer 330 may be formed by using at least one of light emitting materials for emitting light of different colors (i.e., red light, green light, blue light, etc.) according to the pixel. Alternatively, the organic light emitting layer 330 may be formed by stacking a plurality of light emitting materials for generating light of different colors such as red light, green light, and blue light to emit white light as a whole.

[0126] The upper electrode 340 may be formed in the display region 10 on the pixel defining layer 310 and the organic light emitting layer 330. The upper electrode 340 may be formed using metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These may be used alone or in combination.

[0127] Thus, the pixel structure 200 including the lower electrode 290 , the organic light emitting layer 330 , and the upper electrode 340 may be formed.

[0128] An encapsulation substrate (not shown) may be formed on the upper electrode 340. The encapsulation substrate may face the substrate 110. The encapsulation substrate may be formed by using substantially the same material as the substrate 110.

[0129] As mentioned above, it is possible to produce Figure 1、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 and Figure 10 The display device 100 shown in FIG.

[0130] In the method of manufacturing the display device 100 according to an exemplary embodiment of the present disclosure, the active pattern 530 and the dummy pattern structure 500 formed in the peripheral region 20 adjacent to the display region 10 have a waffle shape with multiple grooves, so that the gaps between the gate insulating layer 150, the first insulating interlayer 190, the second insulating interlayer 195, and the third insulating interlayer 205 can be less noticeable. Therefore, residues of the photoresist used in the process of etching each of the active pattern 530, the reference dummy pattern 570, the lower dummy pattern 575, the intermediate dummy pattern 585, and the upper dummy pattern 610 may not remain in the steps. Therefore, when the active layer 130, the first gate electrode 170, the second gate electrode 175, the third gate electrode 185, the source electrode 210, and the drain electrode 230 are formed in the display region 10, defects caused by the residues may not occur.

[0131] For example, when photoresist residue remains in the gap, the residue may move to the display area 10 during the manufacturing process to hinder the formation of the active layer 130, the first gate electrode 170, the second gate electrode 175, the third gate electrode 185, the source electrode 210, and the drain electrode 230. In this case, the active layer 130, the first gate electrode 170, the second gate electrode 175, the third gate electrode 185, the source electrode 210, and the drain electrode 230 may be short-circuited by the residue.

[0132] The present disclosure may be applied to various electronic devices including display devices. For example, the present disclosure may be applied to vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, and / or medical display devices.

[0133] The foregoing illustrates example embodiments and should not be construed as limiting the example embodiments. Although several example embodiments have been described, those skilled in the art will readily appreciate that various modifications may be made to the example embodiments without materially departing from the novel teachings and advantages of the present disclosure. Therefore, it is intended that all such modifications be included within the scope of the inventive concept as defined in the claims. Therefore, it should be understood that the foregoing is illustrative of various example embodiments and should not be construed as limiting the specific example embodiments disclosed, and that modifications of the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, comprising: a substrate having a display area and a peripheral area; A semiconductor element is provided in the display area on the substrate; A pixel structure is provided on the semiconductor element; as well as a plurality of dummy patterns disposed in the peripheral region on the substrate, the dummy patterns having the same material as that constituting the semiconductor element and having a stacked structure; The dummy patterns are arranged in different layers in a grid shape. Each of the dummy patterns includes a central portion and an edge portion surrounding the central portion, The edge portions of the dummy patterns adjacent to each other in the different layers among the dummy patterns overlap with each other in a direction from the substrate to the pixel structure, and The central portions of the dummy patterns adjacent to each other in the different layers do not overlap with each other.

2. The display device according to claim 1, further comprising: An active pattern is provided between the dummy pattern and the substrate, the active pattern being arranged in a lattice shape, and the active pattern overlapping at least a portion of the dummy pattern.

3. The display device according to claim 1 , wherein the dummy pattern comprises: reference dummy patterns spaced apart from each other by a first interval; lower dummy patterns disposed on the reference dummy patterns, the lower dummy patterns being spaced apart from each other by the first interval, the lower dummy patterns overlapping first, second, third, and fourth corners of each of the reference dummy patterns; an intermediate dummy pattern disposed on the lower dummy pattern, the intermediate dummy patterns being spaced apart from each other by the first interval, the intermediate dummy pattern overlapping the first and second side portions of each of the reference dummy patterns and the first and second side portions of each of the lower dummy patterns; as well as an upper dummy pattern disposed on the middle dummy pattern, the upper dummy patterns being spaced apart from each other by the first pitch, the upper dummy pattern overlapping the third and fourth sides of each of the reference dummy patterns, the third and fourth sides of each of the lower dummy patterns, and the first, second, third, and fourth corners of each of the middle dummy patterns, and wherein, in each of the reference dummy pattern and the lower dummy pattern, the first side portion faces the second side portion, and the third side portion faces the fourth side portion.

4. The display device according to claim 3, wherein The reference dummy pattern, the lower dummy pattern, the middle dummy pattern, and the upper dummy pattern have the same shape.

5. The display device according to claim 3, wherein In each of the reference dummy patterns, Both ends of the first side portion include the first corner portion and the second corner portion respectively, Both ends of the second side portion include the third corner portion and the fourth corner portion, respectively. Both ends of the third side portion include the first corner portion and the third corner portion, respectively, and Both ends of the fourth side portion include the second corner portion and the fourth corner portion, respectively. The display device according to claim 3 , wherein: In each of the lower dummy patterns, Both ends of the first side portion include a first corner portion and a third corner portion, respectively. Both ends of the second side portion include a second corner portion and a fourth corner portion, respectively. Both ends of the third side portion include the first corner portion and the second corner portion, respectively, and Both ends of the fourth side portion include the third corner portion and the fourth corner portion, respectively. 7 . The display device of claim 3 , further comprising active patterns disposed between the reference dummy pattern and the substrate, the active patterns being arranged in a lattice shape while being spaced apart from each other by the first interval, the active patterns overlapping the reference dummy pattern.

8. The display device according to claim 7, wherein the semiconductor element comprises: an active layer disposed on the substrate; a gate insulating layer, disposed on the active layer, the gate insulating layer covering the active layer; a first gate electrode, disposed on the gate insulating layer; a first insulating interlayer, disposed on the first gate electrode, the first insulating interlayer covering the first gate electrode; a second gate electrode, disposed on the first insulating interlayer; a second insulating interlayer, disposed on the second gate electrode, the second insulating interlayer covering the second gate electrode; a third gate electrode, disposed on the second insulating interlayer; a third insulating interlayer, disposed on the third gate electrode, the third insulating interlayer covering the third gate electrode; as well as The source electrode and the drain electrode are both arranged on the third insulating interlayer.

9. The display device according to claim 8, wherein the gate insulating layer extends from the display area to the peripheral area on the substrate to cover the active pattern in the peripheral area on the substrate, The first insulating interlayer extends from the display area to the peripheral area on the gate insulating layer to cover the reference dummy pattern in the peripheral area on the gate insulating layer, The second insulating interlayer extends from the display area to the peripheral area on the first insulating interlayer to cover the lower dummy pattern in the peripheral area on the first insulating interlayer, and The third insulating interlayer extends from the display area to the peripheral area on the second insulating interlayer to cover the middle dummy pattern in the peripheral area on the second insulating interlayer.

10. The display device according to claim 8, wherein the active layer and the active pattern are located on the same layer, The first gate electrode and the reference dummy pattern are located on the same layer, The second gate electrode and the lower dummy pattern are located on the same layer, The third gate electrode and the intermediate dummy pattern are located on the same layer, and The source electrode and the drain electrode are located on the same layer as the upper dummy pattern.

11. The display device according to claim 1 , wherein the dummy pattern comprises: first to nth reference dummy patterns, where n is an integer of 1 or greater; first to mth lower dummy patterns disposed on the first to nth reference dummy patterns, wherein m is an integer of 1 or greater; first to qth intermediate dummy patterns disposed on the first to mth lower dummy patterns, where q is an integer of 1 or greater; and first to pth upper dummy patterns are provided on the first to qth intermediate dummy patterns, where p is an integer of 1 or greater, and wherein the first corner, second corner, third corner and fourth corner of the kth reference dummy pattern among the first to nth reference dummy patterns overlap with the jth lower dummy pattern, j+1th lower dummy pattern, j+2th lower dummy pattern and j+3th lower dummy pattern among the first to mth lower dummy patterns, the hth intermediate dummy pattern and the h+1th intermediate dummy pattern among the first to qth intermediate dummy patterns, and the gth upper dummy pattern and the g+1th upper dummy pattern among the first to pth upper dummy patterns, wherein k is an integer between 1 and n, j is an integer between 1 and m, h is an integer between 1 and q, and g is an integer between 1 and p.

12. The display device according to claim 11, wherein the gth upper dummy pattern is located between the jth lower dummy pattern and the j+2th lower dummy pattern, and the jth lower dummy pattern, the j+2th lower dummy pattern, and the gth upper dummy pattern are located in the same row, The g+1th upper dummy pattern is located between the j+1th lower dummy pattern and the j+3th lower dummy pattern, and the j+1th lower dummy pattern, the j+3th lower dummy pattern and the g+1th upper dummy pattern are located in the same row, and The kth reference dummy pattern is located between the hth intermediate dummy pattern and the h+1th intermediate dummy pattern, and the hth intermediate dummy pattern, the h+1th intermediate dummy pattern, and the kth reference dummy pattern are located in the same row.

13. The display device according to claim 11 , wherein the hth intermediate dummy pattern is located between the jth lower dummy pattern and the j+1th lower dummy pattern, and the jth lower dummy pattern, the j+1th lower dummy pattern, and the hth intermediate dummy pattern are located in the same column, The kth reference dummy pattern is located between the gth upper dummy pattern and the g+1th upper dummy pattern, and the gth upper dummy pattern, the g+1th upper dummy pattern, and the kth reference dummy pattern are located in the same column, and The h+1th middle dummy pattern is located between the j+2th lower dummy pattern and the j+3th lower dummy pattern, and the j+2th lower dummy pattern, the j+3th lower dummy pattern, and the h+1th middle dummy pattern are located in the same column.

14. The display device according to claim 11, wherein The jth lower dummy pattern, the j+1th lower dummy pattern, the j+2th lower dummy pattern, the j+3th lower dummy pattern, the hth intermediate dummy pattern, the h+1th intermediate dummy pattern, and the gth upper dummy pattern and the g+1th upper dummy pattern surround the kth reference dummy pattern.

15. The display device of claim 11 , wherein the first corner, the second corner, the third corner, and the fourth corner of the k+1th reference dummy pattern located in the same row as the kth reference dummy pattern overlap with the j+2th lower dummy pattern and the j+3th lower dummy pattern, the j+4th lower dummy pattern and the j+5th lower dummy pattern, the h+1th middle dummy pattern, the h+2th middle dummy pattern, and the g+2th upper dummy pattern and the g+3th upper dummy pattern.

16. The display device according to claim 15 , wherein the g+2th upper dummy pattern is located between the j+2th lower dummy pattern and the j+4th lower dummy pattern, and the jth lower dummy pattern, the j+2th lower dummy pattern, the j+4th lower dummy pattern, and the gth upper dummy pattern and the g+2th upper dummy pattern are located in the same row, The g+3th upper dummy pattern is located between the j+3th lower dummy pattern and the j+5th lower dummy pattern, and the j+1th lower dummy pattern, the j+3th lower dummy pattern, the j+5th lower dummy pattern, and the g+1th upper dummy pattern and the g+3th upper dummy pattern are located in the same row, and The k+1th reference dummy pattern is located between the h+1th intermediate dummy pattern and the h+2th intermediate dummy pattern, and the hth intermediate dummy pattern, the h+1th intermediate dummy pattern, the h+2th intermediate dummy pattern, and the kth reference dummy pattern and the k+1th reference dummy pattern are located in the same row.

17. The display device according to claim 15, wherein the h+1th intermediate dummy pattern is located between the j+2th lower dummy pattern and the j+3th lower dummy pattern, and the j+2th lower dummy pattern, the j+3th lower dummy pattern, and the h+1th intermediate dummy pattern are located in the same column, The k+1th reference dummy pattern is located between the g+2th upper dummy pattern and the g+3th upper dummy pattern, and the g+2th upper dummy pattern, the g+3th upper dummy pattern, and the k+1th reference dummy pattern are located in the same column, and The h+2th middle dummy pattern is located between the j+4th lower dummy pattern and the j+5th lower dummy pattern, and the j+4th lower dummy pattern, the j+5th lower dummy pattern, and the h+2th middle dummy pattern are located in the same column.

18. The display device according to claim 15, wherein the j+2th lower dummy pattern, the j+3th lower dummy pattern, the j+4th lower dummy pattern, the j+5th lower dummy pattern, the h+1th middle dummy pattern, the h+2th middle dummy pattern, and the g+2th upper dummy pattern and the g+3th upper dummy pattern surround the k+1th reference dummy pattern.

19. The display device according to claim 1, further comprising a planarization layer covering the semiconductor element and the dummy pattern on the substrate; The pixel structure includes: A lower electrode is provided in the display area on the planarization layer; a light-emitting layer disposed on the lower electrode; and The upper electrode is arranged on the light-emitting layer.

Images