Method and apparatus for gate fusion for measurement in quantum computing simulation

Abstract

A technique for simulating a quantum circuit based on the fusion of at least a portion of a measurement gate is provided. Data representing a quantum circuit including a quantum gate and a measurement gate is received. The measurement gate in the quantum circuit is divided into one or more virtual gates, and at least one of the one or more virtual gates is fused with a quantum gate. The gate fusion combines the fused gates and cache-blocking operations to more efficiently simulate the quantum circuit. In one embodiment, the simulation of the quantum circuit is performed locally on a computing device. Alternatively, the simulation of the quantum circuit is performed remotely via an application program interface ("API") over a network, and the results of the simulation are reported via the API.

Description

Background Art

[0001] The simulation of quantum circuits and quantum computations is an important part of studying quantum computing algorithms, architectures, and devices. However, simulating quantum circuits of any significant width (i.e., qubit count) requires a large amount of memory and central processing unit (CPU) resources. The memory requirements and time required to simulate basic circuit operations grow exponentially with the number of qubits. For example, the simulation of a 26-qubit quantum circuit using double-precision arithmetic requires 1 gigabyte (GB) of memory. In fact, the memory requirements follow an exponential curve, doubling for each additional qubit. A large amount of CPU resources are also required to perform the required calculations and manipulate the large data structures involved in simulating quantum circuits. Therefore, due to the size of quantum computing systems, the simulation of quantum circuits and computations may be difficult to simulate even with powerful computers or computing systems.

[0002] Smelyanskiy1 et al. discuss “the implementation of a quantum simulator on a classical computer that can simulate general single-qubit gates and two-qubit controlled gates.” See Smelyanskiy1 et al., “qHiPSTER: A Quantum High-Performance Software Testing Environment,” 2016, ArXiv:1601.07195v2 [quant-ph], Abstract. In addition, Smelyanskiy1 et al. discuss “multiple single-node and multi-node optimizations,” including vectorization, multithreading, cache blocking, and overlapping computation with communication “for execution.” See ibid.

[0003] However, these simulations are still inefficient in terms of memory utilization (eg, cache hits and misses) and execution time (eg, the time required to perform the simulation calculations). Summary of the invention

[0004] An overview is given below to provide a basic understanding of one or more embodiments of the present invention. This overview is not intended to identify key or important elements, or to delineate any scope of a particular embodiment of the present invention or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a preface to a more detailed description presented later. In one or more embodiments of the present invention described herein, a system, computer-implemented method, apparatus, and / or computer program product are provided to facilitate simulation based on gate fusion with a measure gate.

[0005] According to an embodiment of the present invention, a system may include a memory storing a computer executable component and a processor executing the computer executable component stored in the memory. The computer executable component may include a development component that receives data for a quantum circuit. The quantum circuit includes a quantum gate that manipulates the state of a quantum bit in the quantum circuit and a measurement gate that measures the state of a quantum bit in the quantum circuit. The development component generates a representation of the quantum circuit based on dividing the measurement gate into one or more virtual gates and fusing at least one of the one or more virtual gates with the quantum gate. An interface component submits a simulation based on the representation of the quantum circuit and receives a simulation result based on the simulation request. The advantage of dividing the measurement gate into virtual gates and fusing one or more virtual gates with the quantum gate in the quantum circuit is that it improves the temporal and spatial locality of the simulation data in the memory to alleviate and / or reduce fragmented access to the memory in the system.

[0006] According to another embodiment of the present invention, the interface component may include a simulator component for simulating the quantum circuit. This has the advantage that the quantum circuit can be locally simulated.

[0007] According to another embodiment of the present invention, the interface component may include a network interface to connect to a network and submit the simulation request to a location on the network. This has the advantage that it enables the system to utilize remote computing resources to perform simulations on its behalf, for example, for simulations of large qubit quantum circuits. In addition, this enables the system to collaborate with multiple simulators and / or hardware resources on the network.

[0008] According to another embodiment of the present invention, the development component divides the measurement gate into a first virtual gate for sum operation, a second virtual gate for determination operation and a third virtual gate for normalization operation. The first virtual gate can be fused with a quantum gate adjacent to the measurement gate and before the measurement gate, and the third virtual gate can be fused with a quantum gate adjacent to the measurement gate and after the measurement gate. This has the advantage that the virtual gate for the measurement gate can be fused with different quantum gates, for example, quantum gates adjacent before and after the measurement gate in a quantum circuit.

[0009] According to an embodiment of the present invention, a system may include a memory storing a computer executable component and a processor executing the computer executable component stored in the memory. The computer executable component may include an interface component that receives a simulation request including a representation of a quantum circuit from a network. The quantum circuit includes a quantum gate and a measurement gate, the measurement gate is divided into one or more virtual gates, and at least one of the one or more virtual gates is fused with the quantum gate. The simulation component simulates the quantum circuit based on the simulation request and sends the result to, for example, a user computer, a workstation, etc.

[0010] According to another embodiment of the present invention, the representation of the quantum circuit is divided into a first virtual gate for sum operation, a second virtual gate for determination operation and a third virtual gate for normalization operation based on the measurement gate. The first virtual gate can be fused with a quantum gate adjacent to and before the measurement gate, and the third virtual gate can be fused with a quantum gate adjacent to and after the measurement gate.

[0011] According to an embodiment of the present invention, a computer-implemented method may include receiving quantum circuit data representing a quantum circuit. The quantum circuit includes a quantum gate and a measurement gate. The measurement gate is divided into one or more virtual gates. The quantum circuit is simulated based on the fusion of at least one virtual gate with the quantum gate to generate a simulation result.

[0012] According to another embodiment of the present invention, the method may further include dividing the measurement gate into a first virtual gate for summing operation, a second virtual gate for determining operation, and a third virtual gate for normalizing operation. In another embodiment, the method may further include fusing the first virtual gate with a quantum gate adjacent to the measurement gate and before the measurement gate, and fusing the third virtual gate with a quantum gate adjacent to the measurement gate and after the measurement gate.

[0013] According to another embodiment of the present invention, a method may include receiving quantum circuit data for including quantum gates and measurement gates. A representation of the quantum circuit is generated based on dividing the measurement gate into one or more virtual gates and fusing at least one of the virtual gates with the quantum gate. Then, a simulation request based on the representation of the quantum circuit is sent to, for example, a backend computing system, a server, etc. The advantage of this method is that it enables the method to be performed using remote computing resources, for example, for the simulation of large qubit quantum circuits. In addition, this enables the method to be used on multiple simulators and / or hardware resources on a network, for example, to perform multiple simulations or large simulations.

[0014] According to another embodiment of the present invention, the method includes generating a representation of the quantum circuit to further include dividing the measurement gate into a first virtual gate for a summation operation, a second virtual gate for a determination operation, and a third virtual gate for a normalization operation. In another embodiment, the method may also include fusing the first virtual gate with a quantum gate adjacent to the measurement gate and before the measurement gate, and fusing the third virtual gate with a quantum gate adjacent to the measurement gate and after the measurement gate.

[0015] According to another embodiment of the present invention, a computer program product is provided to facilitate quantum computing simulation of a quantum circuit. The quantum circuit includes a quantum gate and a measurement gate. The computer program product includes a computer-readable storage medium having program instructions contained thereon. The program instructions are executable by a processor to cause the processor to receive quantum circuit data representing the quantum circuit, divide the measurement gate into one or more virtual gates, and request simulation of the quantum circuit based on fusion of at least one of the one or more virtual gates with the quantum gate.

[0016] According to another embodiment of the present invention, a computer program product may include program instructions executable by a processor to cause the processor to divide a measurement gate into a first virtual gate for a sum operation, a second virtual gate for a determination operation, and a third virtual gate for a normalization operation, and to fuse the first virtual gate with a quantum gate adjacent to and before the measurement gate, and to fuse the third virtual gate with a quantum gate adjacent to and after the measurement gate.

[0017] According to another embodiment of the present invention, the computer program product further comprises program instructions to enable the processor to connect to the network and request the simulation of the quantum circuit based on sending the simulation request to the location on the network. The advantage of this method is that it enables the processor to utilize remote computing resources when executing the program instructions, such as for the simulation of large qubit quantum circuits. In addition, this embodiment enables the processor to utilize multiple simulators and / or hardware resources on the network, for example, to perform multiple simulations or large simulations. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic representation of store and load operations in a memory for simulating a quantum circuit according to one embodiment of the present invention.

[0019] Figure 2 It shows dividing the measurement gate into virtual gates according to one embodiment of the present invention.

[0020] Figure 3 is a block diagram of a system that facilitates quantum computing simulation according to an embodiment of the present invention.

[0021] Figure 4 is a flowchart for simulating a quantum circuit according to an embodiment of the present invention.

[0022] Figure 5 is a flowchart for simulating a quantum circuit according to an embodiment of the present invention.

[0023] Figure 6 is a block diagram of an operating environment in which one or more embodiments described herein are facilitated. DETAILED DESCRIPTION

[0024] The following detailed description is illustrative only and is not intended to limit the invention and / or its application or uses. In addition, it is not intended to be bound by any express or implied information presented in the previous background or summary or detailed description.

[0025] Embodiments of the present invention are now described with reference to the accompanying drawings, wherein the same reference numerals are used to represent the same elements throughout. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, in various cases, it is apparent that one or more embodiments of the present invention can be practiced without these specific details.

[0026] To facilitate the use and study of quantum systems, embodiments of the present invention for simulating quantum circuits are described herein. In one embodiment of the present invention, software can be installed on a computing device, which allows a user to run a quantum circuit-based experimental program on a locally running quantum circuit simulator or on one or more simulators that can be remotely accessed through a network. Embodiments of the present invention allow users to create and input quantum circuits in text form, such as via a text editor, in graphical form, etc. Then a quantum circuit representation is generated by the software, such as an open quantum assembly language (QASM or OpenQASM) file. As will be further described herein, the quantum circuit representation is optimized to minimize the computing resources required to simulate the quantum circuit. (Locally or from a remote system) request the simulation of the quantum circuit, and the result is output to the user. The result can be any graphical text form that is convenient for the user or another computing device to analyze.

[0027] The problem with the prior art is that due to the complexity of the operations performed by the simulated measurement gate, the fusion of the measurement gate with another quantum gate for simulating a quantum circuit is neither taught nor suggested. In an embodiment of the present invention, dividing the measurement gate into a virtual gate provides a solution. Although gate fusion for quantum simulation is known, an embodiment of the present invention first identifies a gate fusion with at least a portion of the measurement gate based on dividing the measurement gate into a virtual gate.

[0028] An advantage of embodiments of the present invention is that the relatively high computational demands on a system running such a simulation are mitigated. For example, the fusion of a measurement gate with one or more other quantum gates enables load and store operations performed for the simulation to be performed more efficiently, for example based on cache blocking for the computations used by the simulation. Thus, some embodiments of the present invention provide improved temporal locality, allow more efficient memory usage, and reduce the execution time of the simulation.

[0029] In addition, in some embodiments of the present invention, the measurement gate can be divided into virtual gates for summation operations, determination operations, and renormalization (or renormalization) operations. Then, the virtual gate for the summation operation can be fused to the previous quantum gate adjacent to the measurement gate. The virtual gate for the renormalization operation can be fused with the quantum gate adjacent to the measurement gate. In embodiments of the present invention, in which the measurement gate is divided into a first virtual gate for the summation operation, a second virtual gate for the determination operation, and a third virtual gate for the normalization operation, these embodiments of the present invention are useful for enabling the virtual gate of the measurement gate to be fused with different quantum gates (e.g., quantum gates adjacent to before and after the measurement gate in a quantum circuit).

[0030] Embodiments of the invention in which simulation requests are submitted to a location on a network are also useful for enabling systems and methods to utilize remote computing resources to perform simulations, e.g., for simulation of large qubit quantum circuits. Furthermore, these embodiments of the invention are useful for allowing collaboration with multiple simulators and / or hardware resources over a network.

[0031] refer to Figure 1 , quantum circuit 100 may include a first quantum gate, a U3 gate 102 operating on qubit q1, a measurement gate 104 operating on qubit q0, and additional quantum gates, such as a second U3 gate 106 operating on qubit q1.

[0032] However, the measurement gate 104 may be divided into virtual gates 108, 110, and 112. The first virtual gate 108 may correspond to a sum operation that calculates the probability of a qubit being in state 0 or 1 based on iterations over all states. The second virtual gate 110 may correspond to a determination operation to determine whether a qubit is in state 0 or 1 based on a random number. The third virtual gate 112 may correspond to a normalization or renorm operation that normalizes the state of the qubit.

[0033] Then, one or more of virtual gates 108, 110, and 112 can be fused with quantum gates such as quantum gates 102 and 106. For example, as shown, to facilitate the simulation of quantum circuit 100, virtual gate 108 can be fused (and / or combined) with U3 gate 102, and virtual gate 112 can be fused (and / or combined) with U3 gate 106. As shown, this fusion allows storage and load operations to be performed based on block cache. For example, as shown in operations 114 and 116, the two halves of U3 gate 102 and virtual gate 108 are combined and executed within the same memory access. Similarly, as shown in operations 118 and 120, the two halves of U3 gate 106 and virtual gate 112 are combined and executed within the same memory access. Therefore, this method allows simulation to be performed with fewer operations.

[0034] Additionally, operations for virtual gates 108 and 112 may be scheduled and executed based on the commutativity of the operations for the quantum gates being fused (i.e., the degree to which a change in the order of operations does not change the outcome of the overall operation when fusion of virtual gates 108 and 112 with a quantum gate). For example, based on the degree of commutativity of the operations implemented by virtual gates 108 and 112 and the corresponding quantum gates into which they are fused, the summation operation implemented by virtual gate 108 may be executed and aggregated earlier, and virtual gate 112 may be executed and aggregated later. As another example, a single qubit measurement followed by fusion of two quantum gates may be efficiently simulated. Additionally, for example, a quantum circuit consisting of an exponentiated Pauli operator may be efficiently simulated when followed by a single qubit measurement.

[0035] refer to Figure 2 , the measurement gate 104 is divided into virtual gates 200, 202 and 204 for summing, determining and reordering operations, respectively. The virtual gates 200, 202 and 204 may be implemented or compiled into program codes to perform simulations.

[0036] For example, pseudo code portion 206 may perform a sum operation for virtual gate 200 in measurement gate 104. Pseudo code 208 may perform a determine operation for virtual gate 202 in measurement gate 104. And, pseudo code 210 may perform a reorder operation for virtual gate 212 in measurement gate 204.

[0037] Thus, when performing simulations, these code portions 206, 208, and 210 can be used together with code for other quantum gates, such as quantum gates 102 and 106 ( Figure 2 Store and load operations (not shown) are fused and optimized to alleviate memory access requests and improve their locality in memory.

[0038] refer to Figure 3 , a system that facilitates quantum computing simulation can be implemented based on the front-end system 300 and the back-end system 302.

[0039] Systems 300 and 302 may include a processor, a memory, a network interface, and / or a storage device. The memory may store computer-executable components and instructions.

[0040] Aspects of the systems (e.g., systems 300, 302, etc.), apparatuses, or processes explained herein may constitute machine-executable components (one or more) embodied within a machine (one or more), for example, embodied in one or more computer-readable media (or media) associated with one or more machines. When executed by one or more machines (e.g., computers, computing devices, virtual machines, etc.), such components may cause the machines to perform the operations described. For example, Figure 6 A computing environment 600 that may be implemented in systems 300 and 302 is described.

[0041] Systems 300 and 302 may be any type of component, machine, device, facility, apparatus, and / or instrument that includes a processor and / or is capable of effective and / or operable communication with a wired and / or wireless network. Components, machines, devices, equipment, facilities, and / or tools that may comprise the front-end system 300 may include tablet computing devices, handheld devices, server-class computing machines and / or databases, laptop computers, notebook computers, desktop computers, cellular phones, smart phones, consumer appliances and / or instruments, industrial and / or commercial equipment, handheld devices, digital assistants, multimedia Internet-enabled phones, multimedia players, and the like.

[0042] The components, machines, devices, equipment, facilities and / or tools that may comprise the backend system 302 may include server-class computing machines and / or databases, laptop computers, notebook computers, desktop computers, etc. The system 302 and / or components of the system 302 may be used to solve new problems caused by advances in the above-mentioned technologies, computer architectures, etc. The system 302 may provide technical improvements to quantum computing systems, quantum circuit systems, quantum processor systems, artificial intelligence systems, and / or other systems. The system 302 may also provide technical improvements to quantum processors (e.g., superconducting quantum processors) by improving the processing performance, processing efficiency, processing characteristics, timing characteristics, and / or power efficiency of the quantum processor.

[0043] Thus, systems 300 and 302 may employ hardware and / or software to solve problems that are highly technical, non-abstract, and not executable as a set of mental actions by a human being. Additionally, in certain embodiments, some of the processes performed may be performed by one or more special-purpose computers (e.g., one or more special-purpose processing units, special-purpose computers with quantum computing components, etc.) to perform defined tasks associated with machine learning.

[0044] Front-end system 300 may include development component 304 and interface component 306. These components will now be described further.

[0045] Development component 304 provides a development platform that allows users to create / input quantum circuits, compile quantum circuits into representations that can be simulated (such as QASM files), and simulate quantum circuits. Development component 304 is a software development kit that can be installed on front-end system 300. Development component 304 may include various application programming interfaces (APIs) and libraries that interface with programming languages ​​such as Python or C++. In addition, development component 304 may include various tools to help create and edit quantum circuit data, such as quantum circuit data 316, and compile quantum circuit data 316 into quantum circuit representations, such as QASM files. Development component 304 may also include various tools to analyze and format simulation result data 318 into graphics, text, or other desired formats.

[0046] As shown, development component 304 may include compiler 308. Compiler 308 may be a compiler or translator that transforms and converts quantum circuit data 316 into a suitable representation such as a QASM file. Compiler 308 may provide a method that allows quantum circuit data 316 to be simulated based on different hardware configurations, quantum ranges and widths, etc. Compiler 308 may receive quantum circuit data 316 as input, expand quantum circuit data 316 by extending data structures and definitions, perform various exchanges to optimize quantum circuits, and perform one or more gate eliminations.

[0047] Compiler 308 may divide a measurement gate, such as measurement gate 204, into virtual gates 108, 110, and 112. As described above, virtual gate 108 may correspond to a sum operation that calculates the probability of a qubit being in state 0 or 1 based on iterating between all states. Virtual gate 202 may correspond to a determination operation to determine whether a qubit is in state 0 or 1 based on a random number. Virtual gate 204 may correspond to a normalization or reshaping operation that normalizes the state of a qubit.

[0048] Compiler 308 may then fuse one or more of virtual gates 108, 110, and 112, which may then be fused with the quantum gates indicated in quantum circuit data 316, e.g., as described in reference Figure 2 and Figure 3 as described.

[0049] The local simulator 310 may be a simulator executed locally on the front-end system 300. The local simulator 310 may provide a local simulation environment to develop and deploy simulation experiments on the front-end system 300.

[0050] Interface component 306 provides an interface for front-end system 300 to communicate with other components running on system 300, such as compiler 308 and native emulator 310, and other computing devices, such as back-end system 302. Interface component 306 is software that provides various routines, protocols, and tools for front-end system 300.

[0051] The backend system 302 provides remote additional resources to perform quantum computing simulations. For example, the backend system 302 can be accessible via a network and provide an array of simulators and quantum computing hardware. Multiple front-end systems 300 can interface with the backend system 302, for example, to submit simulation requests. As shown, the backend system 302 can include an interface component 312 and a simulation controller 314.

[0052] The interface component 312 is the corresponding API of the interface component 306 running on the front-end system 300. The interface component 312 can assign a unique token to each simulation request received from the front-end system 300.

[0053] Simulation controller 314 schedules, executes, and outputs results of simulation requests received, for example, from front-end system 300. Simulation controller 314 provides simulation result data 318 via interface component 312. Simulation controller 314 may provide simulation result data 318 in various forms, such as graphical data, text / numeric data, streaming data, etc.

[0054] Figure 4 is a flow chart of method 500 , which may illustrate a process for simulating a quantum circuit locally on a computing device, such as front-end system 300 , and fusing at least a portion of measurement gates with quantum gates to improve the simulation.

[0055] At 402, quantum circuit data 316 is received by the front end system 300 (via the development component 304) for the quantum circuit. For example, a user at the front end system 300 may use the development component 304 to receive quantum circuit data 316 for the quantum circuit. The quantum circuit data 316 may be provided from a quantum algorithm, a text editor such as a QASM editor, or other form of data input. In response, the development component 304 and the compiler 308 may then generate a representation of the quantum circuit, such as in the form of a QASM file or other data format.

[0056] At 404, measurement gate 204 is divided into one or more virtual gates (e.g., via compiler 308 in development component 304). For example, compiler 308 in development component 304 can compile, analyze, and parse quantum circuit data 316 and perform various transformations or edits on the quantum circuit. As described above, compiler 308 can divide a measurement gate such as measurement gate 204 into one or more virtual gates 108, 110, and 112.

[0057] At 406, one or more of virtual gates 108, 110, and 112 are fused (e.g., by compiler 308 in development component 304) with a quantum gate, such as measurement gate 204, in a quantum circuit represented by quantum circuit data 316. For example, compiler 308 compiles virtual gates 108, 110, and 112 into code portions 206, 208, and 210, and combines these code portions with operations having quantum gates, such as a quantum gate adjacent to measurement gate 204. Development component 304 can then generate a new, modified representation of the quantum circuit and modify quantum circuit data 316 into, for example, a modified QASM file.

[0058] At 408, the quantum circuit is simulated (e.g., via local simulator 310). For example, development component 304 can submit a simulation request to interface component 306, which has an address locator corresponding to local simulator 310. Alternatively, development component 304 can use interface component 306 and submit a simulation request to backend system 302. For example, development component 304 can determine the location of the simulator, e.g., based on a network location specified in a QASM file for one or more simulators hosted by backend system 304.

[0059] Figure 5 is a flow chart of a method 500 for submitting a simulation request to a remote device, such as backend system 302. The simulation request is based on fusing at least a portion of measurement gates with quantum gates to improve memory and processing performance of the simulation.

[0060] At 502, quantum circuit data 316 for a quantum circuit is received (e.g., by development component 304). For example, a user at front-end system 300 may use development component 304 to receive quantum circuit data 316 for a quantum circuit. Quantum circuit data 316 may be provided from a quantum algorithm, a text editor such as a QASM editor, or other form of data input. In response, development component 304 and compiler 308 may then generate a representation of the quantum circuit, such as in the form of a QASM file or other data format.

[0061] At 504, the measurement gate 204 is divided (by the compiler 308 in the development component 304) into one or more virtual gates 108, 110, and 112. For example, the compiler 308 in the development component 304 can compile, analyze, and parse the quantum circuit data 316 and perform various transformations or edits on the quantum circuit. As described above, in one embodiment, the compiler 308 can divide a measurement gate such as the measurement gate 204 into one or more virtual gates 108, 110, and 112.

[0062] At 506, one or more of the virtual gates 108 and 112 are fused with a quantum gate in the quantum circuit, such as the measurement gate 204. For example, the compiler 308 compiles the virtual gates 108, 110, and 112 into code portions 206, 208, and 210, and combines these code portions with the operation of the quantum gate (e.g., the quantum gate adjacent to the measurement gate 204). For example, in one embodiment, the compiler 308 generates a quantum gate by creating 2 n ×2 n A unitary matrix is ​​used to represent each fused virtual gate and all unitary matrices are multiplied to calculate the new 2 n ×2 n The matrix is ​​used to represent the gate fusion, thereby fusing the virtual gates.

[0063] At 508, a representation of the quantum circuit is generated (by development component 304) based on the fusion of virtual gates and quantum gates in the quantum circuit. For example, development component 304 can generate a new, revised representation of the quantum circuit and modify quantum circuit data 316 into, for example, a modified QASM file.

[0064] At 510, the development component 304 may then create a simulation request based on the quantum circuit data 316 and send the simulation request to the backend system 302 (e.g., via the interface component 306). For example, the development component 304 may submit a simulation request to the interface component 306 with an address locator corresponding to the location of the backend system 302 on the network. In response, the interface component 306 may forward the simulation request to the interface component 312 at the backend system 302. The simulation controller 314 may then schedule and run the simulation. In some embodiments, the simulation controller 314 may provide multiple simulation platforms corresponding to quantum computing devices with different qubit widths, for example, 5 qubits or more. The simulation controller 314 will then generate simulation result data 318, for example, based on compiling and executing the program code (e.g., QASM data) in the simulation request. The simulation result data may be in any suitable form, such as text, digital data, graphical data, streaming data, etc.

[0065] At 512, simulation results are received. For example, front-end system 300 may receive simulation result data 318 from back-end system 302 via interface components 306 and 312. In one embodiment, a user may output, analyze, and / or visualize simulation result data 318 using one or more tools provided by development component 304.

[0066] In an example implementation, the program instructions may cause, for example, a processor on the front-end system 300 to receive quantum circuit data representing a quantum circuit. The quantum circuit includes a quantum gate and a measurement gate. The program instructions may also cause the processor to divide the measurement gate into one or more virtual gates, and simulate the quantum circuit based on the fusion of at least one virtual gate of the one or more virtual gates with the quantum gate to generate a simulation result.

[0067] According to another example embodiment, the program instructions may cause, for example, a processor on the front-end system 300 to receive quantum circuit data for a quantum circuit, generate a representation of the quantum circuit based on dividing a measurement gate into one or more virtual gates and fusing at least one of the one or more virtual gates with the quantum gate; and send a simulation request based on the representation of the quantum circuit, for example, to the back-end system 302 over a network.

[0068] For the sake of simplicity of explanation, the computer-implemented method is depicted and described as a series of actions. It is to be understood and appreciated that the present invention is not limited by the actions and / or order of actions shown, for example, the actions can occur in various orders and / or concurrently, and can occur together with other actions not presented and described herein. In addition, not all the actions shown are necessary for realizing the computer-implemented method according to the present invention. In addition, it will be understood and appreciated by those skilled in the art that the computer-implemented method can be represented as a series of interrelated states via state diagrams or events alternatively. In addition, it should also be understood that the computer-implemented method disclosed hereinafter and throughout this specification can be stored on a product, so that these computer-implemented methods are transmitted and transferred to a computer. The term product as used herein is intended to cover a computer program accessible from any computer-readable device or storage medium.

[0069] To provide context for various aspects of the invention, Figure 6 The following discussion is intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented.

[0070] Figure 6 is a block diagram of an operating environment 600 in which one or more embodiments of the present invention may be facilitated. Figure 6, the operating environment 600 may include a computer 612. The computer 612 may also include a processing unit 614, a system memory 616, and a system bus 618. The system bus 618 couples system components including, but not limited to, the system memory 616 to the processing unit 614. The processing unit 614 may be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 614. The system bus 618 may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), Video Electronics Standards Association (VESA), Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI). The system memory 616 may also include volatile memory 620 and non-volatile memory 622. The basic input / output system (BIOS), which contains basic routines for transferring information between elements within the computer 612, such as during startup, is stored in the nonvolatile memory 622. By way of illustration and not limitation, the nonvolatile memory 622 may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), flash memory, or a nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). The volatile memory 620 may also include RAM, which acts as an external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

[0071] The computer 612 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 6Disk storage 624 is shown. Disk storage 624 may also include, but is not limited to, devices such as a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 624 may also include storage media alone or in combination with other storage media, including, but not limited to, optical disk drives such as a compact disk ROM device (CD-ROM), a CD recordable drive (CD-R drive), a CD rewritable drive (CD-RW drive), or a digital versatile disk ROM drive (DVD-ROM). To facilitate connecting disk storage 624 to system bus 618, a removable or non-removable interface, such as interface 626, is typically used. Figure 6 Also depicted is software that acts as an intermediary between a user and the basic computer resources described in the appropriate operating environment 600. Such software may also include, for example, an operating system 628. The operating system 628, which may be stored on disk storage 624, is used to control and allocate the resources of the computer 612. System applications 630 utilize the management of resources by the operating system 628 through program modules 632 and program data 634 (e.g., program data stored in system memory 616 or disk storage 624). It should be understood that the present disclosure may be implemented with various operating systems or combinations of operating systems. A user inputs commands or information to the computer 612 through an input device 636. The input device 636 includes, but is not limited to, pointing devices such as a mouse, a trackball, a stylus, a touch pad, a keyboard, a microphone, a joystick, a game pad, a satellite dish, a scanner, a TV tuner card, a digital camera, a digital video camera, a web camera, and the like. These and other input devices are connected to the processing unit 614 through the system bus 618 via an interface port 638. The interface port 638 includes, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s) 640 use some of the same types of ports as input device(s) 636. Thus, for example, a USB port may be used to provide input to computer 612 and output information from computer 612 to output device 640. Output adapter 642 is provided to illustrate that in addition to other output devices 640, there are some output devices 640 that require special adapters, such as monitors, speakers, and printers. By way of illustration and not limitation, output adapter 642 includes graphics cards and sound cards that provide a method of connection between output device 640 and system bus 618. It should be noted that other devices and / or systems of devices provide input and output capabilities, such as remote computer 644.

[0072] The computer 612 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 644. The remote computer 644 can be a computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device, or other common network node, etc., and can also generally include many or all of the elements described with respect to the computer 612. For simplicity, only a memory storage device 646 is shown with the remote computer 644. The remote computer 644 is logically connected to the computer 612 through a network interface 648 and then physically connected through a communication connection 650. The network interface 648 includes a wired and / or wireless communication network, such as a local area network (LAN), a wide area network (WAN), a cellular network, etc. LAN technologies include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet, token ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like integrated services digital networks (ISDN) and their variants, packet switching networks, and digital subscriber lines (DSL). The communication connection 650 refers to the hardware / software used to connect the network interface 648 to the system bus 618. Although the communication connection 650 is shown as being internal to the computer 612 for clarity of illustration, it may also be external to the computer 612. For exemplary purposes only, the hardware / software used to connect to the network interface 648 may also include internal and external technologies such as modems including conventional telephone grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0073] The present invention may be a system, method and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or multiple media) on which are loaded computer-readable program instructions for causing a processor to implement various aspects of the present invention. A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, - but not limited to - an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of computer-readable storage media includes: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the above. The computer-readable storage medium used herein is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses through a fiber optic cable), or an electrical signal transmitted through wires.

[0074] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device through a network, such as the Internet, a local area network, a wide area network and / or a wireless network. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network, and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device. The computer program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcodes, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, and the programming languages ​​include object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized using the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present invention.

[0075] Here, various aspects of the present invention are described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present invention. It should be understood that each square frame of the flowchart and / or block diagram and the combination of each square frame in the flowchart and / or block diagram can be realized by computer-readable program instructions. These computer-readable program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so as to produce a machine, so that these instructions, when executed by the processor of the computer or other programmable data processing device, produce a device for realizing the function / action specified in one or more square frames in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions make the computer, programmable data processing device and / or other equipment work in a specific manner, so that the computer-readable medium storing the instructions includes a product of manufacture, which includes instructions for realizing various aspects of the function / action specified in one or more square frames in the flowchart and / or block diagram. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0076] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present invention. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0077] Although the present subject matter is described above in the general context of computer executable instructions of a computer program product running on one and / or multiple computers, it will be appreciated by those skilled in the art that the present disclosure may also be implemented in conjunction with other program modules. Typically, program modules include routines, programs, components, data structures, etc. that perform tasks and / or implement specific abstract data types. In addition, it will be appreciated by those skilled in the art that the computer-implemented method of the present invention may be implemented with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, large computers, and computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, etc. The various aspects shown may also be practiced in a distributed computing environment in which tasks are performed by a remote processing device linked by a communication network. However, some aspects of the present disclosure, if not all aspects, may be practiced on a stand-alone computer. In a distributed computing environment, program modules may be in local and remote memory storage devices.

[0078] As used in this application, the terms "component", "system", "platform", "interface", etc. may refer to and / or may include computer-related entities or entities related to operating machines having one or more specific functions. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program, and / or a computer running on a processor. As an illustration, both an application program and a server running on a server may be a component. One or more components may reside in a process and / or a thread of execution, and a component may be located on a computer and / or distributed between two or more computers. In another example, a corresponding component may be executed from various computer-readable media having various data structures stored thereon. These components may communicate via local and / or remote processes, for example, according to a signal having one or more data packets (e.g., data from a component, which interacts with another component in a local system, a distributed system, and / or interacts with other systems via a network such as the Internet). As another example, a component may be a device having a specific functionality provided by a mechanical component operated by an electrical or electronic circuit that is operated by a software or firmware application executed by a processor. In this case, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application. In another example, a component may be a device that provides a specific functionality through an electronic component rather than a mechanical component, where the electronic component may include a processor or other method to execute software or firmware that at least partially imparts the functionality to the electronic component. In one aspect, the component may emulate the electronic component via a virtual machine, such as within a cloud computing system.

[0079] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive arrangement. That is, if X uses A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing instances. In addition, unless otherwise specified or clear from the context to refer to the singular form, the articles "a" and "an" as used in this specification and the drawings should generally be interpreted as meaning "one or more". As used herein, the terms "example" and / or "exemplary" are used to indicate use as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to these examples. In addition, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as being preferred or advantageous over other aspects or designs, nor is it meant to exclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0080] As used in this specification, the term "processor" may refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreaded execution capability; a multi-core processor; a multi-core processor with software multithreaded execution capability; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. In addition, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In addition, the processor may employ a nanoscale architecture, such as, but not limited to, transistors, switches, and gates based on molecules and quantum dots, in order to optimize space usage or enhance the performance of user devices. The processor may also be implemented as a combination of computing processing units. In the present disclosure, terms such as "storage", "database", and substantially any other information storage component related to the operation and function of the component are used to refer to a "memory component", an entity embodied in a "memory", or a component including a memory. It should be understood that the memory and / or memory components described herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. As an illustration and not limitation, non-volatile memory may include ROM, PROM, EPROM, EEPROM, flash memory, or non-volatile RAM (e.g., FeRAM, and volatile memory may include RAM, which may act as external cache memory, for example. In addition, the memory components of the systems or computer-implemented methods disclosed herein are intended to include, but are not limited to, including these and any other suitable types of memory.

[0081] The above description includes only examples of systems and computer-implemented methods. Of course, it is not possible to describe every conceivable combination of components or computer-implemented methods for the purpose of describing the present disclosure, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. In addition, with respect to the use of the terms "including", "has", "possesses", etc. in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a manner similar to that in which the term "comprising" is interpreted when used as a transitional word in the claims. Descriptions of various embodiments have been presented for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to one of ordinary skill in the art without departing from the scope of the present invention. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing on the market, or to enable other persons of ordinary skill in the art to understand the embodiments of the present invention disclosed herein.

Claims

1. A computer system comprising: a memory storing computer executable components; as well as a processor that executes the computer executable components stored in the memory, wherein the computer executable components include: a development component that receives data for a quantum circuit, wherein the quantum circuit includes quantum gates that manipulate states of qubits in the quantum circuit and measurement gates that measure the states of the qubits in the quantum circuit, and wherein the development component generates a representation of the quantum circuit based on partitioning the measurement gates into virtual gates and fusing at least one of the virtual gates with the quantum gates; as well as an interface component that submits a simulation request based on the representation of the quantum circuit and receives a simulation result based on the simulation request, wherein by fusing at least one of the virtual gates with the quantum gate, load and store operations performed for the simulation are enabled to be performed based on cache blocking for the computations used by the simulation, and wherein the development component generates the representation of the quantum circuit based on dividing the measurement gate into a first virtual gate for a summation operation of the quantum state of the qubit measured by the measurement gate, a second virtual gate for a determination operation for determining the state of 0 or 1 of the measured qubit, and a third virtual gate for a normalization operation for normalizing the state of the measured qubit.

2. The computer system of claim 1, wherein the interface component further comprises a simulator that simulates the quantum circuit based on the simulation request.

3. The computer system of claim 1, wherein the interface component further comprises a network interface for connecting to a network and submitting the simulation request to a location on the network.

4. The computer system of claim 1, wherein the development component generates the representation of the quantum circuit based on fusing the first virtual gate with the quantum gate.

5. The computer system of claim 4, wherein the quantum circuit includes additional quantum gates, and the development component generates the representation of the quantum circuit based on fusing the third virtual gate with the additional quantum gate.

6. A computer system comprising: a memory storing computer executable components; as well as a processor that executes the computer executable components stored in the memory, wherein the computer executable components include: an interface component that receives a simulation request including a representation of a quantum circuit, wherein the quantum circuit includes quantum gates and measurement gates, the measurement gates having been partitioned into virtual gates, and at least one of the virtual gates having been fused with the quantum gate; and a simulation component that simulates the quantum circuit based on the simulation request and sends a result, wherein by fusing at least one of the virtual gates with the quantum gate, load and store operations performed for the simulation are enabled to be performed based on cache blocking for the computations used for the simulation, and, wherein the representation of the quantum circuit is divided into a first virtual gate for a summation operation of the quantum state of the qubit measured by the measurement gate, a second virtual gate for a determination operation of determining whether the quantum state of the measured qubit is 0 or 1, and a third virtual gate for a normalization operation of normalizing the quantum state of the measured qubit based on the measurement gate.

7. The computer system of claim 6, wherein the simulation component simulates the quantum circuit based on fusing the first virtual gate with the quantum gate.

8. The computer system of claim 6, wherein the quantum circuit includes additional quantum gates, and wherein the simulation component simulates the quantum circuit based on fusing the third virtual gate with the additional quantum gate.

9. A computer-implemented method comprising: receiving quantum circuit data representing a quantum circuit, wherein the quantum circuit includes quantum gates that manipulate states of qubits in the quantum circuit and measurement gates that measure the states of the qubits in the quantum circuit, wherein the measurement gates are partitioned into virtual gates; simulating the quantum circuit based on the fusion of at least one of the virtual gates and the quantum gate to generate a simulation result, wherein the simulation result is sent by a simulation component included in the computer system according to claim 6, wherein by fusing at least one of the virtual gates with the quantum gate, load and store operations performed for the simulation are enabled to be performed based on cache blocking for the computations used for the simulation, and, The measurement gate is divided into a first virtual gate for a summation operation of the quantum state of the qubit measured by the measurement gate, a second virtual gate for a determination operation of determining whether the quantum state of the measured qubit is 0 or 1, and a third virtual gate for a normalization operation of normalizing the quantum state of the measured qubit.

10. The computer-implemented method of claim 9, wherein simulating the quantum circuit is based on a fusion of the first virtual gate and the quantum gate.

11. The computer-implemented method of claim 10, wherein the quantum circuit includes an additional quantum gate, and simulating the quantum circuit is based on a fusion of the third virtual gate with the additional quantum gate.

12. A computer-implemented method comprising: receiving quantum circuit data of a quantum circuit, wherein the quantum circuit includes quantum gates that manipulate states of qubits in the quantum circuit and measurement gates that measure the states of the qubits in the quantum circuit; generating a representation of the quantum circuit based on partitioning the measurement gate into virtual gates and fusing at least one of the virtual gates with the quantum gate; and sending a simulation request over a network based on the representation of the quantum circuit, the simulation request being submitted by the interface component of the computer system according to claim 1, and receiving a simulation result based on the simulation request, wherein load and store operations performed for the simulation are enabled to be performed based on cache blocking for computations used for the simulation by fusing at least one of the virtual gates with the quantum gate, and wherein generating the representation of the quantum circuit is based on dividing the measurement gate into a first virtual gate for a summation operation of the quantum state of the qubit measured by the measurement gate, a second virtual gate for a determination operation for determining whether the quantum state of the qubit being measured is 0 or 1, and a third virtual gate for a normalization operation for normalizing the quantum state of the qubit being measured.

13. The computer-implemented method of claim 12, wherein generating the representation of the quantum circuit is based on fusing the first virtual gate with the quantum gate.

14. The computer-implemented method of claim 13, wherein generating the representation of the quantum circuit is based on fusing the third virtual gate with an additional quantum gate in the quantum circuit.

15. The computer implemented method of claim 12, transmitting the simulation request is based on converting the representation of the quantum circuit into executable program code.

16. A computer program product comprising a computer-readable storage medium having program instructions contained therein, the program instructions being executable by a processor to cause the processor to perform the steps of the method according to any one of claims 9 to 15.

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