Hall integrated circuit and corresponding method of manufacturing a hall integrated circuit using wafer stacking

Abstract

A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer stacked in a vertical direction, the second wafer including a CMOS substrate and a stack of dielectric layers arranged on the CMOS substrate, the CMOS substrate integrated with CMOS processing circuitry coupled to the vertical Hall element, and the first wafer including a Hall sensor layer having a first surface and a second surface opposing along the vertical direction and extending in a horizontal plane perpendicular to the vertical direction, the first wafer and the second wafer bonded by interposing a dielectric layer arranged above the first surface of the Hall sensor layer. The vertical Hall element has at least one first Hall terminal being a first doped region arranged on the first surface of the Hall sensor layer, at least one second Hall terminal being a second doped region arranged on the second surface of the Hall sensor layer, the second doped region aligned with the first doped region along the vertical direction and separated from the first doped region by a thickness of the Hall sensor layer, a deep trench isolation ring extending from the first surface through the Hall sensor layer to the second surface and enclosing and isolating a Hall sensor region of the Hall sensor layer in which the first Hall terminal and the second Hall terminal are arranged, and first and second conductive structures coupled to the first and second Hall terminals, respectively, and electrically connected to respective contact pads embedded in the second wafer stack.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to European Patent Application No. 18207662.0, filed November 21, 2018, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present invention relates to a Hall integrated circuit (IC) and a corresponding method of manufacturing a Hall integrated circuit using wafer stacking. BACKGROUND

[0004] The working principle and basic technology of Hall devices are described in the book entitled "Hall Effect Devices" by R. S. Popovic, published in 2004 by the Institute of Physics Publishing, Bristol and Philadelphia.

[0005] US 2014 / 0347045 specifies an isotropic three-dimensional Hall sensor with at least three electrode pairs, wherein each electrode pair comprises a terminal on the front side of the wafer and a terminal on the back side of the wafer. The three electrode pairs can be arranged such that their directions through the wafer represent an orthogonal coordinate system. Furthermore, the Hall sensor area can be laterally defined by deep trenches etched into the substrate from both sides. The electrical connection can be made by flip-chip or wire bonding.

[0006] US 2006 / 0170406 specifies a vertical Hall element with three electrodes formed continuously on a main surface of a substrate and one buried electrode established by an epitaxial process. The three electrodes on the main surface are surrounded by a dielectric layer of predetermined depth through which a current flow area is defined. The buried electrode is electrically connected by a doped connection structure.

[0007] WO 2010 / 101815 specifies a vertical Hall sensor with three electrodes formed in a well along a first axis. A fourth buried electrode coupled to the well is formed by a deep diffusion region located below the well. The buried electrodes are electrically connected by a doped connection structure.

[0008] WO 2011 / 000601 specifies a vertical Hall sensor with a main surface of a substrate, a Hall sensor area in contact with the main surface, and a buried conductive region in contact with the Hall sensor area. A vertical Hall sensor with four electrodes on the main surface and four buried electrodes is disclosed. The buried electrodes are electrically connected by a doped connection structure.

[0009] US 2009 / 0256559 discloses a vertical Hall device formed on a substrate of a first conductivity type, which has an epitaxial layer of a second conductivity type and a buried conductive layer of the second conductivity type interposed therebetween. The vertical Hall device has four terminals. One terminal is connected to the conductive buried layer by a connection structure. There is an isolation structure between the connection structure and the other terminals.

[0010] Magnetic sensor ICs typically use silicon-based Hall elements monolithically integrated with the circuitry required for signal conditioning and amplification. Typical commercial products with monolithically integrated Hall elements are Hall switch ICs, Hall ICs for linear position measurement, right angle sensor Hall ICs, Hall ICs for current sensing, and 3D Hall sensor ICs. Depending on the product type, the Hall ICs can include horizontal Hall elements, vertical Hall elements, or both. Vertical Hall elements sense magnetic field strength in the plane direction of the silicon surface, especially in right angle sensor Hall ICs and 3D Hall sensor ICs.

[0011] A conventional vertical Hall element is formed as follows: a well with n-type conductivity is formed in a low-doped silicon substrate with p-type conductivity. The n-type well constitutes the Hall plate of the sensor, which is isolated from the substrate by a p-n junction. Then, three, four, five, or more Hall terminals are formed on the silicon surface within the n-type well region, typically in a row or in a circle (RSPopovic, 2004, Hall Effect Devices, 2nd Edition, Institute of Physics Publishing, Bristol and Philadelphia).

[0012] In these conventional vertical Hall elements, the sensitivity is limited by the finite depth of the n-type well in which the Hall terminals are placed. This is because only the vertical component of the operating current contributes to the measured Hall voltage between two sense terminals. Therefore, high-voltage CMOS processes with deep wells are typically used to fabricate Hall ICs with vertical Hall elements. Even in these processes, the well depth is typically only in the order of a few micrometers.

[0013] In addition to low sensitivity, conventional vertical Hall elements typically also have a high level of residual offset. The offset of a Hall element, i.e., the Hall voltage measured at zero magnetic field strength, can be reduced by known techniques such as current rotation, orthogonal coupling of several Hall elements, or a combination thereof. Effective offset reduction depends on the commutation of the Hall terminals and the fourfold symmetry of the Hall device. The terminals of a single conventional vertical Hall element are all placed on the same silicon surface, which necessarily deviates from the ideal fourfold symmetry.

[0014] Therefore, there is a need for a vertical Hall element with improved sensitivity and a lower level of residual offset, which can be integrated in a Hall IC together with the circuitry required for signal conditioning and amplification.

[0015] Moreover, there is a need for a new method that integrates a Hall element with improved characteristics with the circuit on the Hall IC to perform signal conditioning and amplification.

[0016] Finally, there is a need for a right-angle sensor Hall IC and a 3D Hall sensor IC with higher accuracy. SUMMARY

[0017] The object of the present application is to meet the aforementioned needs.

[0018] According to the present application, a Hall integrated circuit (IC) and a corresponding manufacturing method are thus provided as defined in the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0019] For a better understanding of the present application, the preferred embodiments are described hereinafter, purely by way of non-limiting example, with reference to the accompanying drawings in which:

[0020] - Figure 1 is a schematic top plan view of a portion of a Hall integrated circuit according to an embodiment of the present solution;

[0021] - Figure 2 and Figure 3 are schematic cross-sectional views of the Hall integrated circuit of Figure 1 taken along lines A-A’ and B-B’ of Figure 1 ;

[0022] - Figure 4 shows an equivalent electrical representation of the Hall element of the Hall integrated circuit of Figure 1 ;

[0023] - Figure 5 and Figure 6 are schematic cross-sectional views equivalent to Figure 2 , in which the geometrical and electrical characteristics are highlighted;

[0024] - Figure 7 is a schematic cross-sectional view of a Hall integrated circuit according to another aspect of the present solution;

[0025] - Figure 8 is a schematic top plan view of the Hall integrated circuit of Figure 7 ; and

[0026] - Figures 9 to 30 are schematic cross-sectional views of the Hall integrated circuit of Figure 7 in successive steps of a corresponding manufacturing method. DETAILED DESCRIPTION

[0027] As will be discussed in detail, according to embodiments of the present solution, a first wafer is provided having a thickness in the range of, for example, 10 to 30 microns and having an epitaxial semiconductor layer of low doped n-type conductivity. A first plurality of Hall terminals is formed on a first surface of the epitaxial semiconductor layer together with corresponding wiring. A second wafer is provided which is a silicon wafer having typical dopant concentrations and conductivity types used in CMOS fabrication. An integrated circuit for signal conditioning and amplification of the Hall element is formed on a first surface of the second wafer using standard CMOS fabrication techniques. The first wafer is flipped and its first surface is attached on the first surface of the second wafer, thereby achieving a permanent wafer-to-wafer bonding. The stacked wafers are thinned from a second surface of the first wafer until only the low doped semiconductor epitaxial layer of n-type conductivity remains. A second plurality of Hall terminals with corresponding wiring is formed on the thinned second surface of the first wafer using the same design rules and process conditions as the first set of Hall terminals. The first plurality of Hall terminals and the second set of Hall terminals are arranged on each surface such that the finished Hall element has four-fold symmetry. A deep trench isolation ring is formed extending through the entire epitaxial silicon layer and encircling the first plurality of Hall terminals as well as the second plurality of Hall terminals. Electrical connections are provided such that each of the first plurality of Hall terminals and each of the second plurality of Hall terminals are connected to the wiring on the second wafer, respectively.

[0028] Figure 1 , Figure 2 and Figure 3 A vertical Hall element 100 of an integrated Hall IC product is shown. Figure 1 A vertical Hall element 100 in the x-y plane is shown along the cutting direction C-C’ as indicated. Figure 2 and Figure 3 Two further cutting directions are shown in Figure 1 , a cutting direction A-A’ along the x-axis and a cutting direction B-B’ along the y-direction. Figure 2 is a cross-sectional view showing the vertical Hall element 100 in the X-Z plane along the cutting direction A-A’. Figure 3 The same Hall element is shown in the y-z plane along the cutting direction B-B’ as indicated in Figure 1 . The vertical Hall element 100 is formed on a first wafer 10 attached to a second wafer 20 comprising an integrated circuit for signal conditioning and amplification. The substrate 201 of the second wafer can be a low doped silicon substrate of p-type conductivity; but is not limited thereto. In general, any substrate suitable for the fabrication of CMOS devices and circuits can be chosen. In Figure 2 , Figure 3 ​​​​​​The CMOS devices and circuits formed on the substrate 201 of the second wafer 20 are not shown. 204 represents the dielectric layer stack formed on the substrate 201, in which the metal wiring of the circuit is embedded (according to standard CMOS processing technology). The vertical Hall element of the Hall IC is formed on the substrate 102 of the first wafer 10. The substrate 102 may be a lightly doped epitaxial silicon layer with n-type conductivity. The resistivity of the epitaxial silicon layer 102 is selected such that the vertical Hall element 100 has optimal characteristics, such as high magnetic field sensitivity. The substrate 102 may also be a germanium substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium antimonide (InSb) substrate, or a substrate of a different material that has optimal characteristics for the Hall element, such as high mobility. For clarity, it is assumed below that the substrate 102 is a lightly doped epitaxial silicon layer with n-type conductivity (the reason for choosing n-type doping for silicon is the higher mobility, which translates to a higher sensitivity value for the Hall sensor). Two shallow, heavily doped regions 1 and 2 are formed, exhibiting n-type conductivity and extending to the first surface 10b of the epitaxial silicon layer 102. For example... Figure 1 As shown, the two highly doped regions 1 and 2 have a rectangular shape in the xy plane; however, other shapes can also be considered. The two highly doped regions 1 and 2 have the same width w and the same length l. The distance between the two highly doped regions 1 and 2 is denoted by s. An oxide layer 104 is disposed on a first surface 10b having two openings, one located within the region of highly doped region 1 and the other within the region of highly doped region 2. Figure 2 and Figure 3 In the diagram, 111 represents a metal structure comprising a metal filler with an opening contacting the highly doped region 1 and metal lines disposed on an oxide layer 104 in contact with the metal filler. Similarly, 112 represents a metal structure comprising a metal filler with an opening contacting the highly doped region 2 and metal lines disposed on an oxide layer 104 in contact with the metal filler. Figure 3 As can be seen, the wiring portion of metal structure 111 extends to the left in the y-direction. The same applies to metal structure 112. An oxide layer 105 is formed on metal structures 111 and 112 and on oxide layer 104, such that the wiring portions of metal structures 111 and 112 are perpendicularly embedded in the oxide. Oxide layer 105 is planarized. Through the planarized oxide surface, wafer 10 is attached and permanently bonded to the planarized oxide surface of layer 204 of wafer 20. Using wafer 20 as a carrier, wafer 10 has been thinned from the back side, leaving only the epitaxial silicon layer 102. The thickness of the remaining epitaxial silicon after thinning is denoted by T3 (see [reference]). Figure 5 And it may be in the range of 10 to 30 micrometers; however, smaller or larger thickness values ​​can also be considered. Figure 2 and Figure 3In the middle, the second surface of the thinned epitaxial layer is denoted by 10d. 10b and 10d are two opposite surfaces of the epitaxial silicon layer 102 in the x-y plane that are parallel to each other. Two shallow and highly doped regions 3 and 4 are formed with n-type conductivity and extending to the second surface 10d of the epitaxial silicon layer 102. The two highly doped regions 3 and 4 have the same width w and the same length l as their counterparts 1 and 2. In addition, the two highly doped regions 3 and 4 are separated by the same distance s, whereby the highly doped regions 1 and 2 are separated from each other. Furthermore, the highly doped region 3 is located directly above the highly doped region 2 in the sense that a straight line connecting the center of region 3 and the center of region 2 will be perpendicular to the epitaxial silicon surfaces 10b and 10d. Likewise, the highly doped region 4 is located directly above the highly doped region 1 in the sense that a straight line connecting the center of region 4 and the center of region 1 will be perpendicular to the epitaxial silicon surfaces 10b and 10d. An oxide layer 106 is provided on the second surface 10d of the epitaxial silicon layer and a silicon nitride layer 108 is provided thereon. A deep trench isolation ring 107 is formed extending from the second surface 10d to the first surface 10b. The inner surface of the deep trench isolation is perpendicular to the two surfaces 10b and 10d of the epitaxial silicon layer. As seen in Figure 1 the middle, the deep trench isolation ring 107 surrounds the highly doped regions 1 and 2 extending to the first surface 10b. In the x-direction, the distance between the deep trench isolation ring 107 and the highly doped region 2 is denoted by d. The distance in the x-direction between the deep trench isolation ring 107 and the highly doped region 1 has the same value d. The epitaxial silicon volume enclosed by the deep trench isolation ring 107, separated and isolated from the rest of the epitaxial silicon layer 102 outside of it, constitutes the Hall sensor area or Hall plate of the finished vertical Hall element 100 and is denoted by 103. The combined stack of layers 106 and 108 has two openings, one located within the highly doped region 3 and the other located within the highly doped region 4. As on the first surface 10b, two metal structures 113 and 114 are formed. The metal structure 113 comprises a metal fill of the opening in contact with region 3 and a metal wiring provided on the silicon nitride layer 108 that is connected to said metal fill. Likewise, the metal structure 114 comprises a metal fill of the opening in contact with region 4 and a metal wiring provided on the silicon nitride layer 108 that is in contact with said metal fill. As shown in Figure 3 the middle, the wiring part of the metal structure 114 extends laterally to the right (in the y-direction). The same is true for the metal structure 113. An oxide layer 110 is provided on the metal structures 113 and 114 and on the silicon nitride layer 108. Thus, the wiring parts of the metal structures 113 and 114 are embedded perpendicularly in dielectric material. For passivation of the finished Hall IC, a silicon nitride layer 132 is provided on the oxide layer 110.

[0029] Figure 1 、 Figure 2 andFigure 3 The vertical Hall element depicted has four Hall terminals. Each Hall terminal is associated with one of four highly doped regions 1, 2, 3, and 4 formed in the epitaxial silicon layer 102. In the following text, the Hall terminals are denoted by the same numbers as their associated highly doped regions. A Hall element with four terminals can be represented by an equivalent circuit, such as... Figure 4 As shown in the diagram, terminals 1, 2, 3, and 4 are connected via four resistors R1, R2, R3, and R4 (in a Wheatstone bridge). As is known in the art, effective offset cancellation can be achieved if the four resistors R1, R2, R3, and R4 have the same or nearly the same values. It will be apparent to those skilled in the art that for... Figure 5 The vertical Hall element shown can be configured with an epitaxial silicon thickness T3, a Hall terminal width w, a lateral spacing s between them, and a distance d to the deep trench isolation, such that the four resistors R1, R2, R3, and R4 are equal or nearly equal. In other words, the vertical Hall element has four-fold or near-four-fold symmetry with respect to the four terminals (and therefore can have corresponding geometric and electrical characteristics). In this context, it should be noted that the doping concentration of the Hall sensor region 103 can be assumed to be uniform, since the doping is defined by the epitaxial growth of layer 102. Furthermore, the inner surface of the deep trench isolation is perpendicular to the first and second surfaces of the epitaxial silicon layer.

[0030] exist Figure 6 In the cross-sectional view, four different operating stages are shown by indicating the direction of the current. In the first stage, indicated by P1, the operating current flows between Hall terminals 3 and 1, and the Hall voltage is measured between Hall terminals 4 and 2. In the second stage, indicated by P2, the operating current flows between Hall terminals 4 and 2, and the Hall voltage is measured between Hall terminals 1 and 3. In the third stage, indicated by P3, the operating current flows between Hall terminals 2 and 4, and the Hall voltage is measured between Hall terminals 3 and 1. Finally, in the fourth stage, indicated by P4, the operating current flows between Hall terminals 2 and 4, and the Hall voltage is measured between Hall terminals 3 and 1. In each stage, the vertical Hall element is sensitive to a magnetic field oriented in the y-direction. In each stage, the current direction is perpendicular or nearly perpendicular to the straight line connecting the two Hall terminals, and the Hall voltage is measured between them. This geometry allows for high sensitivity values. In the vertical Hall element 100, short-circuit effects that typically reduce sensitivity in conventional vertical Hall elements are minimized. Because a larger thickness T3 can be selected, specifically, a depth much greater than that of the Hall plate of a conventional vertical Hall element, greater sensitivity can be obtained for the vertical Hall element 100.

[0031] exist Figure 1 , Figure 2 andFigure 3 The image shows only the vertical Hall element 100, without indicating how the four Hall terminals of the Hall element are connected to the integrated circuit formed on the second wafer 20. Figure 7 This is another cross-sectional view of the vertical Hall element 100 along the cutting direction B-B' in the y-direction, except... Figure 3 In addition, the connection between Hall terminals 1 and 4 and the integrated circuit of the Hall IC is also shown. For example... Figure 7 As shown, the metal structure 111, which contacts the Hall terminal 1, extends laterally to the left beyond the deep trench isolation 107. At the left end, a metal line is formed as a metal pad. A through-silicon via 121, seated on the metal pad, provides an electrical connection between the metal structure 111 and a metal bridge 115 formed above the second surface 10d of the epitaxial silicon layer. Specifically, the through-silicon via 121 extends through the combined stack of dielectric layers 106 and 108, through the epitaxial silicon layer 102, and through the oxide layer 104. The through-silicon via 121 is filled with a conductive material, which is dielectrically isolated from the surrounding substrate 102 by an oxide liner 109. The metal bridge 115 completely covers the through-silicon via 121 and is in electrical contact with it. The metal bridge 115 extends further laterally to the left and here covers a second through-silicon via indicated by 141. Through-silicon via (TSV) 141 provides an electrical connection between a metal bridge 115 and a bonding pad 221 embedded in an intermetallic oxide layer 204 disposed on a substrate 201 of the wafer 20. Specifically, TSV 141 extends through a combined stack of dielectric layers 106 and 108, through an epitaxial silicon layer 102, through oxide layers 104 and 105, and through a portion of the oxide layer 204 disposed on the silicon substrate 201 of the wafer 20. Similar to TSV 121, the TSV is filled with a conductive material, which is isolated from the epitaxial silicon substrate 201 by an oxide liner 109. The bonding pad 221 connects to wiring of an integrated circuit disposed on the substrate 20. Thus, an electrical connection is established between the Hall terminal 1 formed on the Hall device wafer 10 and the circuitry formed on the IC wafer 20. Figure 8 As further shown, the metal structure 114 extends to the right beyond the deep trench isolation. It covers another through-silicon via 164, thereby establishing an electrical contact with the conductive filler of the through-silicon via. The through-silicon via 164 extends through the combined stack of layers 106 and 108, through the entire epitaxial silicon layer 102, through oxide layers 104 and 105, and through a portion of the intermetallic oxide layer indicated by 204. The through-silicon via 164 is attached to a corresponding metal pad 224. In this way, an electrical connection is established between the Hall terminal 4 formed on the second surface 10d of the epitaxial silicon layer 102 and the wiring led out on the IC wafer 20.

[0032] Figure 8is a bird's eye view showing the wiring of the vertical Hall element 100 and the vertical interconnects required to reach each of the four Hall terminals from the circuitry formed on the wafer 20, respectively. Four metal pads denoted by 221, 222, 223 and 224 are embedded on the intermetal dielectric layer 204 of the wafer 20 to provide access points to the four Hall terminals 1, 2, 3 and 4, respectively. The through-silicon vias 141, 121 and 164 required to reach the two Hall terminals 1 and 4, respectively, are arranged along a straight line parallel to the y-direction, which passes through the centers of the Hall terminals 1 and 4. The distances of the through-silicon vias to the Hall element are denoted by D4, D2 and D6, respectively. Similarly, the through-silicon vias 142, 122 and 163 required to reach the Hall terminals 2 and 3, respectively, are arranged along a straight line parallel to the y-direction, which passes through the centers of the Hall terminals 2 and 3. The distances of the through-silicon vias 142, 122 and 163 to the Hall element are D4, D2 and D6, respectively, which are identical to the distances of the through-silicon vias 141, 121 and 164. Furthermore, the wiring of the Hall terminals and the metal bridges are both oriented in the y-direction.

[0033] In Figure 8 , the direction of the current flowing through the wiring and the vertical interconnects in the first operating phase PI is indicated, in which the current is fed from the Hall terminal 3 through the vertical Hall element to the Hall terminal 1. Obviously, the vertical current flowing through the through-silicon via 163 generates an induced magnetic field, which is sensed by the vertical Hall element. Similarly, the vertical current flowing through the through-silicon via 121 generates an induced magnetic field, which is sensed by the vertical Hall element. And similarly, the vertical current flowing through the through-silicon via 141 generates an induced magnetic field, which is sensed by the vertical Hall element. Since the current directions in the through-silicon vias 121 and 163 are identical, their induced magnetic fields tend to cancel out at the location of the vertical Hall element 100. Typically, the strength of the induced magnetic field at the vertical Hall element 100 depends on their distances D4, D2 and D6, respectively. Given the current directions indicated in the through-silicon vias 141, 121 and 163, the distances D4, D2 and D6 can be set such that the parasitic magnetic fields caused by the vertical current flowing through the through-silicon vias can be minimized at the location of the vertical Hall element. The same applies to the other three operating phases of the vertical Hall element 100.

[0034] In Figures 9 to 30 , the manufacturing of the stacked Hall sensor 100 is shown.

[0035] As Figure 9As shown, a wafer 10 comprising a silicon substrate 101 and an epitaxial layer 102 is provided. The substrate 101 is preferably a highly doped silicon substrate with n-type conductivity. The thickness T1 of the silicon substrate depends on the wafer size and can range from 600 micrometers to 800 micrometers. The epitaxial layer 102 is preferably also a lightly doped silicon epitaxial layer with n-type conductivity. The thickness T2 of the epitaxial layer can range from 10 micrometers to 30 micrometers; however, lower or higher values ​​of T2 are also considered. The resistivity of the silicon epitaxial layer is selected to obtain optimal Hall sensor characteristics for the finished device. As those skilled in the art will understand, the optimal resistivity of the silicon epitaxial layer 102 depends on the thickness and size of the Hall plate. Typical resistivities can range from 0.1 ohm-cm to 10 ohm-cm. Other semiconductor materials can also be considered for the epitaxial layer 102. The starting material can also be silicon on insulator (SOI). In this case, the epitaxial layer 102 is separated from the carrier substrate 101 by a buried oxide layer (BOX). For ease of discussion, the first surface of wafer 10, defined by the lightly doped epitaxial layer, is designated as 10b. The back surface of wafer 10 is designated as 10a.

[0036] In the first manufacturing step, alignment marks are created on surface 10b. As those skilled in the art know, this is achieved by photomask etching of the silicon. The alignment marks printed on the silicon are used to align subsequent photolithography layers performed on surface 10b of the wafer 10. Figure 9 Alignment markers are not shown.

[0037] Go to Figure 10 Shallow, highly doped regions 1 are generated by photomask implantation, followed by resist removal and laser thermal annealing. These highly doped regions 1 exhibit n-type conductivity and extend to the surface 10b. The doping concentration can be up to 10⁻⁶ per cubic centimeter. 20 10 per cubic centimeter 22 Within the range of individual atoms. In laser thermal annealing, the wafer is subjected to very short thermal pulses, so the heat is only dependent on the pulse duration, energy dose, and wavelength to penetrate to a limited depth in silicon. The depth of the highly doped region can range from 50 nanometers to 200 nanometers, which is much smaller than the thickness T2 of the silicon epitaxial layer 102.

[0038] like Figure 11As depicted, an oxide layer 104 is deposited on surface 10b. The oxide layer may be tetraethyl orthosilicate (TEOS) deposited by plasma-enhanced chemical vapor deposition (PECVD). Contact trenches or holes 151 are etched through the oxide layer 104 using a photomask etching process, thereby exposing the highly doped region 1. More precisely, the trenches or holes 151 expose the silicon epitaxial layer only within the highly doped region 1. As is known in the art, the silicon consumption of such photomask oxide etching can be very low, depending on the selectivity of the oxide for silicon in the etching chemistry and conditions. Thus, etching can be stopped within the shallow highly doped region 1, thereby ensuring a doping concentration of 10c per cubic centimeter at the silicon surface inside the trenches or holes 151. 20 From 10 atoms per cubic centimeter 22 Within the range of atoms.

[0039] The fabrication of the Hall sensor continues with the deposition of a metal layer, which is formed by photomask etching steps, such as... Figure 12 As shown in the diagram. The metal layer is preferably an aluminum-based metal stack, which typically includes a titanium adhesion layer, a titanium nitride barrier layer, an aluminum layer, and a titanium nitride capping layer. The thickness of the titanium nitride barrier layer can be increased compared to a typical thickness. In any case, the inventors consider a thickness in the range of 500 angstroms to be suitable. The metal structure 111 fills the contact trench or hole 151 such that the metal contacts the exposed highly doped silicon inside the trench or hole. Furthermore, the metal structure 111 extends to Figure 12 On the right side, wires or pads are formed on top of oxide layer 104.

[0040] An additional metallic structure is formed on top of the oxide layer 104, which serves as an alignment mark for processing wafer 10 on a second surface after wafer 10 thinning, and will become clearer below. (Not in...) Figure 12 The provided metal alignment structure is shown in the figure.

[0041] Go to Figure 13 An oxide layer 105 is deposited on top of the metal structure 111 and the exposed oxide layer 104. The oxide layer 105 is planarized by chemical mechanical polishing (CMP). 10c represents the top surface of the oxide layer 105 after planarization. To achieve good flatness of the oxide surface 10c, the steps of depositing the oxide layer and performing CMP can be repeated several times.

[0042] The description of the manufacture of Hall sensor product 100 continues as the CMOS wafer components are manufactured. For example... Figure 14As shown, a wafer 20 composed of a silicon substrate 201 is provided. 20b represents the top or front side of the wafer 20, and 20a represents the back side. The substrate 201 has p-type conductivity, which is a typical conductivity type used for forming CMOS devices and circuits. Additionally, the resistivity of the substrate 201 can be selected to suit the formation and isolation of CMOS devices. The wafer thickness T4 can be in the range of 600 micrometers to 800 micrometers.

[0043] The necessary devices and circuitry for the adjustment, readout, and signal amplification of the Hall sensor are typically formed on substrate 201. For simplicity, these are not shown in the diagram. Figure 15 These devices and circuits are shown in the diagram. The circuit wiring is embedded in an oxide layer, which... Figure 15 The overall shape is denoted by 204. Two embedded metal pads 221 and 224, preferably formed by the uppermost metal layer of the wiring, are provided for establishing contact with the finished Hall sensor device formed on the wafer 10. The uppermost metal layer may be an aluminum-based metal stack, typically comprising a titanium adhesion layer, a titanium nitride barrier layer, an aluminum layer, and a titanium nitride capping layer. The thickness of the titanium nitride capping layer can be increased compared to a typical thickness. In any case, the inventors consider a thickness in the range of 500 angstroms to be suitable. The top surface of the oxide layer 204 is denoted by 20c. To obtain a high flatness of surface 20c, chemical mechanical polishing (CMP) is performed after the final oxide deposition step. Alternatively, a series of oxide deposition and CMP steps can be performed to further improve the flatness of the oxide surface 20c. No bonding pads for external connectivity are provided on the wafer 20.

[0044] Go to Figure 16Wafer 10 is flipped and attached to surface 20c of wafer 20 with its surface 10c. A permanent bond is achieved between wafer 10 and wafer 20. The resulting stacked wafer is hereinafter referred to as 30. Wafer 30 has a surface 10a as a top or front surface and a surface 20a as a back surface. Several methods for permanent wafer bonding are known in the art. An example of the bonding process is described below. The planarized oxide surface 10c of wafer 10 is activated by a plasma with an inert gas. In the same manner, the planarized surface 20c of wafer 20 is activated by a plasma with an inert gas. Wafer 10 is then flipped and attached to surface 20c of wafer 20 with its surface 10c. The bonding alignment accuracy—that is, the alignment accuracy of wafer 10 attached to wafer 20—is typically on the order of several micrometers using standard methods known in the art. A low-temperature baking process is performed to enhance the bonding. The baking process can be in the range below 450°C, preferably below 400°C. Theoretically, bonding is believed to depend on van der Waals forces between the two oxide surfaces. Alternatively, for example, adhesive bonding using polymeric adhesives such as benzocyclobutene (BCB) or others can be used to achieve a reliable bond between wafer 10 and wafer 20.

[0045] A CMOS chip 20 is used as a carrier chip, and the Hall sensor chip 10 is processed from its back side 10a. For example... Figure 17 As shown, wafer 10 is thinned from the back side to remove most of the silicon material. Specifically, the initial substrate 101 of wafer 10 is completely removed, and the thickness of the epitaxial layer 102 is also slightly reduced. The resulting thickness T3 of the epitaxial layer 102 is slightly less than the initial thickness T2. The resulting epitaxial surface is denoted by 10d. The thinning process can include removal processes such as back grinding, chemical mechanical polishing (CMP), and wet or dry etching. A preferred method is described below. Most of the substrate 101 is removed by back grinding. Back grinding is stopped before the epitaxial layer 102 is exposed. Then, a wet etching process selectively targeting the doping concentration of the silicon material is performed. Since the substrate 101 is preferably selected to have a high doping concentration, wet etching can be selectively stopped on the lightly doped silicon epitaxial layer due to the large difference in doping concentration. A CMP process can then be performed to further planarize and smooth the resulting silicon surface. Using this method, good inter-wafer thickness T3 control and good intra-wafer uniformity of T3 can be achieved.

[0046] In the preceding text, 10b represents the first silicon surface of the Hall sensor device. It has been shown how Hall terminals and additional wiring can be formed on the first silicon surface using standard semiconductor processing methods, with the sole exception of laser thermal annealing for activating dopants. Below, the fabrication of the Hall sensor continues by performing a semiconductor fabrication process on the second surface 10d. To achieve a high degree of symmetry in the Hall sensor device, the same design rules and process conditions are carefully employed to form Hall terminals on both the first and second surfaces. As understood, another important aspect of achieving the desired symmetry is the precise alignment of the Hall terminals formed on the second surface 10d with those formed on the first surface 10b. As explained, alignment patterns have been created on the first surface by structuring the deposited metal layers accordingly. To make these alignment patterns visible on the second surface, silicon is removed in the areas where those alignment patterns are projected using a photomask etching process. Due to the large silicon openings required to capture the alignment patterns, these metal alignment patterns can be set only at the edges of the wafer. The inventors have realized that alignment precision in the range of 100 nm to 500 nm can be achieved by applying the described method. Furthermore, alignment can be achieved by using an open metal alignment pattern at the wafer edge, creating a new set of sequentially aligned alignment patterns on the second surface through photomask etching into the epitaxial silicon. This improves the mutual alignment of the optical layers applied to the second surface 10d.

[0047] continue Figure 18 A shallow, highly doped region 4 with n-type conductivity is formed on the second surface 10d in the same manner as the highly doped region 1 on the first surface. Specifically, the same implantation type, implantation dose, and energy are used to generate the doped region 1 as those used on the first surface. More specifically, after removing the resist, the same laser thermal annealing conditions applied to the first surface for activating the doped region 1 are applied. As those skilled in the art will understand, unlike other activation methods such as furnace annealing or rapid thermal processing, laser thermal annealing for dopant activation on the second surface prevents the aluminum-based metallization on the first surface of the Hall sensor wafer 10 from being destroyed by thermal processing. Furthermore, laser thermal annealing does not increase the thermal budget of the device formed on the CMOS wafer 20. The doped region 4 has the same lateral dimensions as the doped region 1. Figure 18 As shown, doped region 4 is located directly above doped region 1. The two doped regions 1 and 4 face each other and are separated by silicon epitaxial layer 102.

[0048] Go to Figure 19On the second surface 10d, an oxide layer 106 is deposited. More specifically, the layer 106 can be tetraethyl orthosilicate (TEOS) deposited by plasma-enhanced chemical vapor deposition (PECVD). PECVD allows TEOS deposition at temperatures of 400 °C or below. Through a photomask etching process, a ring-shaped opening 161 is etched through the oxide layer 106 exposing the silicon epitaxial layer 102. The ring-shaped opening is formed around the Hall sensor device. In Figure 19 a cross-sectional view, the ring-shaped opening of the oxide layer 106 appears as two openings located at the left and right side of the high doped region 4.

[0049] After removal of the photomask, a deep silicon etch is performed using the oxide layer 106 as a hard mask, as shown in Figure 20 The deep silicon etch is selectively stopped on the oxide layer 104 deposited on the first surface 10b of the Hall sensor wafer 10. By etching the entire depth of the epitaxial layer 102, a ring-shaped trench is formed around the silicon region in which the Hall terminals are formed. The enclosed silicon region will form the Hall plate of the finished Hall element and is denoted by 103. Deep silicon etch processes for etching trenches or vias with a depth of tens of micrometers or more are known in the art. For a given thickness T3 in the range of 10 to 30 micrometers, a plasma etch process with a gas chemistry consisting of SF6, HBr and O2 can be used. Alternatively, a so-called Bosch process can be applied, which is typically characterized by a better selectivity to the oxide hard mask. For both etch processes, a nearly vertical sidewall is obtained as known to the skilled person.

[0050] As shown in connection with Figure 21 The ring-shaped trench 161 is filled with a dielectric material which is removed by chemical mechanical polishing on top of the oxide layer 106. The dielectric material can be tetraethyl orthosilicate (TEOS) or a spin-on dielectric such as spin-on glass (SOG), polyimide (PI) or benzocyclobutene (BCB). In any case, the dielectric material can be chosen among dielectric materials which can be processed at temperatures not exceeding 400 °C. Subsequent removal of the dielectric material provided on top of the oxide layer 106 by chemical mechanical polishing is not an option for this oxide. The only critical point is to stop the CMP process before the silicon is exposed. After all, the Hall sensor region is confined by a deep trench isolation ring dielectric denoted by 107 in Figure 21

[0051] As Figure 22 ​As shown in the middle, a silicon nitride layer 108 is deposited on top of the oxide layer 106 by PECVD. The deposition temperature is not higher than 400°C. Using a photomask etching process, openings 171, 172 and 173 are etched through the stack of dielectric layers including the oxide layer 106 and the silicon nitride layer 108. At the bottom of the openings 171, 172 and 173, the underlying silicon epitaxial layer is exposed. The photoresist is stripped off. In Figure 22 In cross-section, the opening 171 is located above the metal pad 221. From the top, the opening 171 is laterally surrounded by the metal pad 221 and the opening 171 is laterally surrounded by the metal pad 221 with a certain overlap margin, which is defined by the wafer bonding alignment accuracy, among others. Likewise, the opening 173 is located above the metal pad 224 and is laterally surrounded by the metal pad with the same overlap margin. The opening 172 is located above the metal structure 111. In this position, the metal structure is formed as a metal pad, which laterally provides a surrounding for the opening 172. The overlap margin of the metal pad surrounding with respect to the opening 172 is defined by the alignment accuracy achieved between the two active silicon surfaces 10d, 10b of the Hall sensor wafer 10, among others.

[0052] Referring to Figure 23 A deep silicon etching process is performed using the silicon nitride layer 108 as a hard mask. For this purpose, the same dry etching process as for the definition of the deep trench isolation 107 can be employed. The deep silicon etching is selectively stopped on the oxide layer 104.

[0053] Turning now to Figure 24 A thin oxide layer 109 is deposited. More specifically, the layer 109 can be tetraethyl orthosilicate (TEOS) deposited by plasma enhanced chemical vapor deposition (PECVD) at a temperature not higher than 400°C. The oxide layer 109 serves as a dielectric liner on the silicon sidewalls exposed by the previous deep silicon etching. By way of example, the thickness of the oxide layer 109 can be 3000 Angstroms, but is not limited to this value.

[0054] As combined with Figure 25A further anisotropic dry etch process is performed using process conditions suitable for etching silicon nitride with high selectivity and titanium nitride with high selectivity, as shown. Thin oxide 109 is etched at the bottom of deep silicon vias 171, 172 and 173 and at the top over silicon nitride layer 108. Due to the high anisotropy of this etch process, oxide layer 109 is almost entirely preserved on the silicon sidewalls of vias 171, 172 and 173. Oxide layer 104 deposited on the first surface of wafer 10 is also etched away as the etch proceeds. In via opening 172, the dry etch selectively stops in the titanium nitride barrier layer of metal structure 111. Using typical polymer-rich fluorocarbon etch chemistry in combination with oxygen and argon, an oxide to titanium nitride selectivity of 20:1 to more than 40:1 can be achieved, as known in the art. Due to the increased thickness of the titanium nitride barrier layer of metal structure 111 and due to the high selectivity of the etch process, the etch can stop within the titanium nitride layer and aluminum is not exposed. This etch process also typically shows high selectivity to silicon nitride, so in the present case silicon nitride layer 108 is largely preserved. In vias 171 and 173, depending on the applied etch time, the etch can stop somewhere in oxide layer 105, as shown in Figure 25

[0055] Subsequently, a photoresist step is performed so that at least via 172 is filled and covered with photoresist and vias 171 and 173 are not filled and covered with photoresist. In Figure 26 the photoresist cover 195 is limited to via 172 with some overlap around the via. A further dry oxide etch process is performed with high oxide to titanium nitride selectivity. In vias 171 and 173, oxide layer 105 is etched through and, as the etch continues, metal pads 221 and 224, respectively, are reached. Due to the selectivity of the oxide etch process and the increased thickness of the titanium nitride cover layer of metal pads 221 and 224, the etch can stop within the titanium nitride layer without exposing the underlying aluminum. Since via 172 is filled and covered with photoresist, no etching occurs at the bottom of this via. In the areas not covered with photoresist, silicon nitride layer 108 acts as a hard mask. After the oxide etch process is completed, photoresist 195 is stripped.

[0056] Reference is made to Figure 27 ​The fabrication process is continued. A tantalum adhesion layer, an optional tantalum nitride barrier layer and a copper seed layer are deposited. Thereafter, the vias 171, 172 and 173 are filled with copper by electroplating. Due to the addition of the electroless plating layer and by careful adjustment of the electroplating rate, copper can be filled in the vias 171, 172 and 173 without leaving voids or seams. Methods are known in the art to fill high aspect ratio through silicon vias with electroplated copper without voids or seams. After electroplating, a copper CMP process is applied to remove the copper that was plated on top of the silicon nitride layer 108. By the copper CMP process, also the tantalum and the tantalum nitride that were deposited on top of the nitride layer 108 are completely removed. By filling the vias 171, 172 and 173 with an electrically conductive material, through silicon vias are formed that are denoted by 141, 121 and 124, respectively. The through silicon vias are electrically isolated from the surrounding epitaxial silicon 102 by the oxide liner 109. By landing on the metal pad 221, the through silicon via 141 establishes an electrical connection to the wiring of the CMOS die 20. Similarly, the through silicon via 124 establishes an electrical connection to the wiring of the CMOS die 20 by landing on the metal pad 224. In case the through silicon via 121 lands on the metal structure 111, an electrical connection to the highly doped region 1 formed on the first surface of the Hall sensor die 10 is achieved.

[0057] Turning to Figure 28 , a contact trench or hole 181 is formed through the silicon nitride layer 108 and the oxide layer 106 by a photo mask etching process so that the highly doped region 4 is exposed. More precisely, the trench or hole 181 exposes the silicon epitaxial layer only within the highly doped region 4. Due to the set of individually aligned patterns created on the second surface 10d, both the photo etching process for defining the doped region 4 and the photo etching process for defining the opening 181 can be aligned with the same set of alignment patterns, thereby ensuring a high degree of mutual overlay precision. Due to the high selectivity to silicon, the etching can be stopped within the shallow highly doped region 4, thereby ensuring that the doping concentration at the silicon surface inside the trench or hole 181 is in the range of 10 20 atoms per cubic centimeter to 10 22 atoms per cubic centimeter. After completion of the photo mask etching process, the photo mask is peeled off.

[0058] A metal layer is deposited to fill the contact trench or hole 181. The metal layer can be an aluminum based metal stack that includes a tantalum adhesion layer, a tantalum nitride barrier layer, an aluminum layer and a titanium nitride capping layer. After deposition, the metal layer is structured by a photo mask etching process, as Figure 29The metal structure 115 completely covers the top surface of the copper filling the through silicon via 141 and the top surface of the through silicon via 121, as shown, to achieve electrical connection between the two through silicon vias. The metal structure 114 includes filling of the contact trench or hole 181. The metal structure 114 extends to the right, through the deep trench isolation 107, and completely covers the top surface of the copper filling the through silicon via 124. Thus, the metal structure 114 provides electrical connection between the highly doped region 4 formed in the epitaxial silicon and the through silicon via 124.

[0059] The structure of the deposited aluminum-based metal stack is also used to form the bond or stud pads to enable external communication for the finished wafer stacked Hall IC product. Figure 29 The bond or stud pads, not shown in FIG. 6, are electrically connected to the wiring on the CMOS wafer 20 through a through silicon via (e.g., 141 or 124) that lands on a corresponding metal pad (e.g., 221 or 224) provided on the wafer 20.

[0060] Turning to FIG. 7, the metal structure 115 and 114 are formed by depositing a layer of aluminum 120 on the top of the epitaxial silicon 103 and the remaining silicon nitride layer 108. The aluminum layer 120 is then etched back to form the metal structure 115 and 114, as shown. The metal structure 115 and 114 are formed to completely cover the top surface of the copper filling the through silicon via 141 and the top surface of the through silicon via 121, as shown, to achieve electrical connection between the two through silicon vias. The metal structure 114 includes filling of the contact trench or hole 181. The metal structure 114 extends to the right, through the deep trench isolation 107, and completely covers the top surface of the copper filling the through silicon via 124. Thus, the metal structure 114 provides electrical connection between the highly doped region 4 formed in the epitaxial silicon and the through silicon via 124. Figure 30 Figure 29 The oxide / nitride stack is opened over the bond or stud pads by a photomask etch process, not shown in FIG. 6.

[0061] The advantages of the present solution are apparent from the foregoing discussion.

[0062] ​The proposed solution solves the problem of low sensitivity of the conventional vertical Hall element integrated in the Hall IC. For the vertical Hall element built on the first wafer, due to the Hall terminals on the first surface and on the second surface of the epitaxial semiconductor can be arranged so that in each phase of the device operation, the operating current flows vertically through the line connecting the two Hall terminals, the Hall voltage is measured between the Hall terminals, thus high sensitivity can be achieved. In this way, the shorting effect is minimized, which generally reduces the sensitivity in conventional vertical Hall elements. High sensitivity of the vertical Hall element can also be achieved by the proposed solution, as the thickness of the epitaxial semiconductor layer can be optimized towards high sensitivity. In principle, the proposed technical solution allows the use of epitaxial semiconductor materials other than silicon as the Hall plate. As known in the art, the Hall sensitivity is proportional to the mobility of the majority carriers. Therefore, the sensitivity can be further improved by selecting an optimized semiconductor material with high mobility. For example, low-doped germanium with n-type conductivity can be selected as an alternative material. In general, the vertical Hall element formed on the first wafer can be optimized for sensitivity without changing the semiconductor manufacturing processes, materials or design rules for manufacturing the wafers containing the Hall IC.

[0063] Furthermore, as the vertical Hall element built on the first wafer can be designed and manufactured with fourfold symmetry, the proposed solution solves the problem of high residual offset of the conventional vertical Hall element integrated in the Hall IC. As the technical solution allows the Hall terminals to be placed on both sides of the epitaxial semiconductor layer constituting the Hall plate, fourfold symmetry can be achieved in the design of the vertical Hall element. In this way, the four Hall terminals of the vertical Hall element can be arranged so that they exhibit fourfold symmetry like in the horizontal Hall element. As the epitaxial layer is used to build the Hall plate, a uniform dopant concentration can be assumed throughout the Hall sensor area. Furthermore, the proposed technical solution allows the same process conditions and design rules to be applied to the formation of the Hall terminals on the first and second surfaces of the epitaxial semiconductor. Furthermore, as will be explained in the detailed disclosure, there are available technologies that allow good overlay accuracy of the Hall terminals on the second surface with respect to the Hall terminals formed on the first surface of the epitaxial semiconductor layer to be achieved. In addition, the deep trench isolation rings limiting the Hall plate can be arranged to maintain fourfold symmetry.

[0064] Finally, it is clear that modifications and variations can be made to what is described and illustrated herein, without departing from the scope of the present application as defined in the appended claims.

[0065] In particular, according to a further embodiment of the present solution, some CMOS circuits are also formed on the first wafer 10 (with standard CMOS processing steps). With regard to the processing of the first wafer 10, in this embodiment, it is necessary to impose conditions on the same first wafer 10 compatible with CMOS components (apart from this consideration, the manufacturing process does not deviate substantially from that described above). This further embodiment can allow optimization of the use of silicon and implementation of lower manufacturing costs.

Claims

1. A Hall integrated circuit comprising a vertical Hall element (100), comprising a first wafer (10) and a second wafer (20) stacked in a vertical direction (z), the second wafer (20) comprising a CMOS substrate (201) and a stack of dielectric layers (204) arranged on the CMOS substrate (201), the CMOS substrate integrating a CMOS processing circuit configured to be coupled with the vertical Hall element (100), and the first wafer (10) comprising a Hall sensor layer (102) having a first surface (10b) and a second surface (10d), the first surface (10b) and the second surface (10d) being opposite along the vertical direction (z) and extending in a horizontal plane (xy) orthogonal to the vertical direction (z), the first wafer (10) and the second wafer (20) being bonded by interposing a dielectric layer (105) arranged above the first surface (10b) of the Hall sensor layer (102), wherein the vertical Hall element (100) comprising: at least a first Hall terminal (1) being a first doped region arranged at the first surface (10b) of the Hall sensor layer (102); at least a second Hall terminal (4) being a second doped region arranged at the second surface (10d) of the Hall sensor layer (102), the second doped region being aligned with the first doped region along the vertical direction (z) and separated from the first doped region by a thickness of the Hall sensor layer (102); a deep trench isolation ring (107) extending through the Hall sensor layer (102) from the first surface (10b) to the second surface (10d) and enclosing and isolating a Hall sensor region of the Hall sensor layer (102) in which the first Hall terminal (1) and the second Hall terminal (4) are arranged; and a first conductive structure (111) and a second conductive structure (114) coupled to the first Hall terminal (1), the second Hall terminal (4), respectively, and configured to be electrically connected to respective contact pads (221, 224) embedded in the stack (204) of the second wafer (20), wherein the vertical Hall element (100) further comprises a through-silicon via (121, 141, 164) extending through the Hall sensor layer (102), the through-silicon via being configured to electrically connect the first conductive structure (111) and the second conductive structure (114) to the contact pads (221, 224) embedded in the stack (204) of the second wafer (20).

2. The circuit of claim 1, wherein, The Hall sensor layer (102) is an epitaxial silicon layer and the first Hall terminal (1) and the second Hall terminal (4) are doped regions in the Hall sensor layer (102) having the same conductivity type as the Hall sensor layer.

3. The circuit of claim 1, wherein, The vertical Hall element (100) further comprises: at least one third Hall terminal (2) is a third doped region arranged at a first surface (10b) of the Hall sensor layer (102); at least one fourth Hall terminal (3) is a fourth doped region arranged at a second surface (10d) of the Hall sensor layer (102), the fourth doped region being aligned with the third doped region along the vertical direction (z) and separated from the third doped region by a thickness of the Hall sensor layer (102); a third conductive structure (112) and a fourth conductive structure (113) are coupled to the third Hall terminal (2) and to the fourth Hall terminal (3), respectively, and are configured to electrically connect the third Hall terminal (2) and the fourth Hall terminal (3), respectively, to a respective contact pad embedded in the stack (204) of the second wafer (20).

4. The circuit of claim 3, wherein, The first Hall terminal (1) and the second Hall terminal (4) and the third Hall terminal (2) and the fourth Hall terminal (3) are arranged at a same lateral distance (d) from the deep trench isolation ring (107).

5. The circuit of claim 1, further comprising a first dielectric layer (104) on the first surface (10b) and a second dielectric layer (106, 108) on the second surface (10d); wherein: The first conductive structure (111) comprises: a metal fill filling an opening through the first dielectric layer (104) in contact with the first doped region of the first Hall terminal (1); and a first metal line arranged on the first oxide layer (104) in contact with the metal fill and having a lateral extension outside the deep trench isolation ring (107); a first through-silicon via (121) electrically connecting the first metal line of the first conductive structure (111) with a conductive bridge (115) formed on the second dielectric layer (106, 108) above the second surface (10d); and a second through-silicon via (141) electrically connecting the conductive bridge (115) to a first contact pad (221) among the contact pads (221, 224) embedded in the stack (204) of the second wafer (20); and The second conductive structure (114) comprises: a respective metal fill filling an opening through the second dielectric layer (106, 108) in contact with the second doped region of the second Hall terminal (4); and a second metal line arranged on the second oxide layer (106, 108) in contact with the metal fill and having a lateral extension outside the deep trench isolation ring (107); a third through-silicon via (164) electrically connecting the second metal line of the second conductive structure (114) to a second contact pad (224) among the contact pads (221, 224) embedded in the stack (204) of the second wafer (20).

6. The circuit of claim 1, wherein, A part of the processing circuitry is integrated in a part of the Hall sensor layer (102) of the first wafer (10).

7. A method of manufacturing a Hall integrated circuit comprising a vertical Hall element (100), the method comprising forming a stack of: a first wafer (10) comprising a Hall sensor layer (102) having a first surface (10b) and a second surface (10d) opposite along a vertical direction (z) and extending in a horizontal plane (xy) orthogonal to the vertical direction (z); and a second wafer (20) comprising a CMOS substrate (201) integrated with CMOS processing circuitry configured to be coupled with the vertical Hall element (100), and a stack of dielectric layers (204) arranged on the CMOS substrate (201), wherein, the first wafer (10) and the second wafer (20) being bonded with a dielectric layer (105) arranged over the first surface (10b) of the Hall sensor layer (102) interposed therebetween, and wherein the vertical Hall element (100) comprises: at least a first Hall terminal (1) being a first doped region arranged at the first surface (10b) of the Hall sensor layer (102); at least a second Hall terminal (4) being a second doped region arranged at the second surface (10d) of the Hall sensor layer (102), the second doped region being aligned with the first doped region along the vertical direction (z) and separated therefrom by a thickness of the Hall sensor layer (102); a deep trench isolation ring (107) extending through the Hall sensor layer (102) from the first surface (10b) to the second surface (10d) and enclosing and isolating a Hall sensor region of the Hall sensor layer (102) in which the first Hall terminal (1) and the second Hall terminal (4) are arranged; and first and second conductive structures (111, 114) coupled to the first and second Hall terminals (1, 4), respectively, and configured to be electrically connected to respective contact pads (221, 224) embedded in the stack (204) of the second wafer (20); and the method further comprising forming a through-silicon via (121, 141, 164) of the Hall element (100) extending through the Hall sensor layer (102), the through-silicon via being configured to electrically connect the first and second conductive structures (111, 114) to the contact pads (221, 224) embedded in the stack (204) of the second wafer (20).

8. The method of claim 7, wherein, forming the stack comprises: providing the first wafer (10) comprising a substrate (101) and an epitaxial layer formed on the substrate (101), the epitaxial layer defining the first surface (10b), and the substrate (101) having a back surface (10a) opposite the first surface (10b) along the vertical direction (z); forming a first doped region of the first Hall terminal (1) at the first surface (10b); forming the first conductive structure (111) coupled to the first Hall terminal (1) and the dielectric layer (105) over the first conductive structure (111), the dielectric layer having a top surface; flipping the first wafer (10) and bonding the top surface of the dielectric layer (105) to a respective top surface of the stack (204) of the second wafer (20); thinning the first wafer (10) from the back surface (10a) so as to remove the substrate (101) and define the Hall sensor layer (102) and the second surface (10d) thereof from the epitaxial layer; forming a second doped region of the second Hall terminal (4) at the second surface (10d); forming a deep trench isolation ring (107) extending from the second surface (10d) through the Hall sensor layer (102) to the first surface (10b), the deep trench isolation ring (107) enclosing and isolating a Hall sensor region of the Hall sensor layer (102) in which the first Hall terminal (1) and the second Hall terminal (4) are arranged; and forming the second conductive structure (114) coupled to the second Hall terminal (4).

9. The method of claim 7, wherein, forming the first conductive structure (111) comprises forming first metal lines arranged on a first dielectric layer (104) on the first surface (10b), the first metal lines being in contact with the first Hall terminal (1) via a metal fill in an opening through the first dielectric layer (104) and having a lateral extension outside the deep trench isolation ring (107); and wherein forming a through silicon via (121, 141, 164) is performed before forming the second conductive structure (114), and forming a through silicon via (121, 141, 164) comprises: forming a first through silicon via (121) and a second through silicon via (141), the first through silicon via being electrically connected to a first metal line of the first conductive structure (111), the second through silicon via being electrically connected to a first contact pad (221) among the contact pads (221, 224) embedded in the stack (204) of the second wafer (20); and forming a third through silicon via (164) electrically connected to a second contact pad (224) among the contact pads (221, 224) embedded in the stack (204) of the second wafer (20); and wherein forming the second conductive structure (114) comprises forming second metal lines arranged on a second dielectric layer (106, 108) on the second surface (10d), the second metal lines being in contact with the second Hall terminal (4) via a metal fill in an opening through the second dielectric layer (106, 108) and having a lateral extension outside the deep trench isolation ring (107) all the way to the third through silicon via (164), forming a conductive bridge (115) in electrical contact with the first through-silica via (121) and the second through-silica via (141).

10. The method of claim 7, wherein, The Hall sensor layer (102) is an epitaxial silicon layer and the first Hall terminal (1) and the second Hall terminal (4) are doped regions in the Hall sensor layer (102) having the same conductivity type as the Hall sensor layer.

11. The method of claim 7, wherein, The vertical Hall element (100) further comprises: forming at least one third Hall terminal (2) being a third doped region arranged at the first surface (10b) of the Hall sensor layer (102); forming at least one fourth Hall terminal (3) being a fourth doped region arranged at the second surface (10d) of the Hall sensor layer (102), the fourth doped region being aligned with the third doped region along the vertical direction (z) and separated from the third doped region by a thickness of the Hall sensor layer (102); forming a third conductive structure (112) and a fourth conductive structure (113), the third conductive structure (112) and the fourth conductive structure (113) being coupled with the third Hall terminal (2) and the fourth Hall terminal (3), respectively, and configured to electrically connect the third Hall terminal (2) and the fourth Hall terminal (3), respectively, to a respective contact pad embedded in the stack (204) of the second wafer (20).

12. The method of claim 11, wherein, The first Hall terminal (1) and the second Hall terminal (4) and the third Hall terminal (2) and the fourth Hall terminal (3) are formed with corresponding manufacturing steps and arranged at the same lateral distance (d) from the deep trench isolation ring (107).

13. The method of claim 7, further comprising integrating a portion of the processing circuitry in a portion of the Hall sensor layer (102) of the first wafer (10).

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