Camera

Abstract

An imaging device according to one aspect of the present invention includes: a photoelectric conversion unit comprising a first electrode, a second electrode, a photoelectric conversion layer for converting incident light into signal charges, and a blocking layer; and a charge accumulation region connected to the second electrode for accumulating the signal charges. The energy barrier of the blocking layer for the movement of charges of opposite polarity to the signal charges from the second electrode to the photoelectric conversion layer is 1.8 eV or greater, and the energy barrier of the blocking layer for the movement of charges from the photoelectric conversion layer to the second electrode is 1.6 eV or less.

Description

Technical Field

[0001] The present invention relates to an imaging device that converts incident light into signal charges. Background Art

[0002] In recent years, with the widespread use of mobile phones and smartphones equipped with cameras, demand has grown for compact and lightweight solid-state imaging devices, in addition to image quality. Consequently, there is a demand for smaller image sensor chips and smaller pixel sizes per pixel, meaning more miniaturized pixels.

[0003] Here, focusing on the pixel structure of a typical CMOS image sensor, a silicon photodiode, serving as the photoelectric conversion unit, and a transistor, serving as the signal readout unit, are incorporated into a semiconductor substrate within a single pixel. Miniaturizing the transistors beyond a certain size as pixels become smaller can compromise driving capabilities. On the other hand, miniaturizing the pixels while maintaining the transistor size reduces the area occupied by the photodiode within a pixel, i.e., the aperture ratio. This can lead to reduced image quality due to decreased pixel sensitivity and reduced color reproducibility caused by color mixing.

[0004] Based on the above-mentioned problems, for example, in Patent Documents 1, 2, and 3, a functionally separated CMOS image sensor is proposed in which only a signal readout portion is formed in a semiconductor substrate and a photoelectric conversion portion composed of inorganic or organic materials is stacked on top.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2012 / 147302

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 2011-187544

[0009] Patent Document 3: Japanese Patent Application Laid-Open No. 2018-093297 Summary of the Invention

[0010] Problems to be solved by the invention

[0011] There is a demand for further miniaturization of pixels and suppression of dark current.

[0012] An object of the present invention is to provide an imaging device that has low dark current and can achieve miniaturization of pixels.

[0013] Means for solving problems

[0014] According to non-limiting exemplary embodiments of the present invention, the following technical solutions are provided.

[0015] An imaging device according to one embodiment of the present invention includes: a photoelectric conversion portion comprising a first electrode, a second electrode opposing the first electrode, a photoelectric conversion layer located between the first and second electrodes and configured to convert incident light into signal charges, and a blocking layer located between the photoelectric conversion layer and the second electrode; and a charge accumulation region connected to the second electrode and configured to accumulate the signal charges. The energy barrier to the movement of charges of opposite polarity to the signal charges from the second electrode to the photoelectric conversion layer due to the blocking layer is 1.8 eV or greater. The energy barrier to the movement of charges from the photoelectric conversion layer to the second electrode due to the blocking layer is 1.6 eV or less.

[0016] Inclusive or specific forms can also be achieved through components, devices, modules, systems or methods. In addition, inclusive or specific forms can also be achieved through any combination of components, devices, modules, systems and methods.

[0017] Additional effects and advantages of the disclosed embodiments will become apparent from the specification and drawings. Effects and / or advantages are provided by each of the various embodiments or features disclosed in the specification and drawings, and it is not necessary to obtain all of them in order to obtain one or more of them.

[0018] Effects of the Invention

[0019] According to the present invention, it is possible to provide an imaging device that has low dark current and can achieve miniaturization of pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a block diagram showing the overall configuration of an imaging device according to Embodiment 1 of the present invention.

[0021] Figure 2 This is a diagram showing an example of the circuit configuration of pixels and a voltage supply circuit of the imaging device according to the first embodiment of the present invention.

[0022] Figure 3 This is a diagram showing an example of a cross-sectional view of three pixels of the imaging device according to the first embodiment of the present invention.

[0023] Figure 4 This is a diagram schematically showing an example of a detailed configuration of a photoelectric conversion section of an imaging device according to Embodiment 1 of the present invention.

[0024] Figure 5 This is a diagram showing an example of typical current-voltage characteristics of the photoelectric conversion layer of the imaging device according to the first embodiment of the present invention.

[0025] Figure 6This is a diagram showing an example of an energy band diagram of the photoelectric conversion portion of the imaging device according to the first embodiment of the present invention.

[0026] Figure 7 This is a timing chart of control signals for pixels of the imaging device according to the first embodiment of the present invention.

[0027] Figure 8A This is a plan view of a first electrode in a pixel array section of the imaging device according to Embodiment 1 of the present invention.

[0028] Figure 8B This is a plan view of a first electrode in a pixel array section of an imaging device according to Modification 1 of the present invention.

[0029] Figure 8C This is a plan view of a first electrode in a pixel array section of an imaging device according to Modification 2 of the present invention.

[0030] Figure 9 This is a timing chart of control signals for pixels of the imaging device according to the second embodiment of the present invention.

[0031] Figure 10 This is a diagram schematically showing an example of the structure of a photoelectric conversion portion of an imaging device having pixels that use electrons as signal charges, according to another embodiment of the present invention.

[0032] Figure 11 This is a diagram showing an example of an energy band diagram of a photoelectric conversion layer of an imaging device having pixels that use electrons as signal charges according to another embodiment of the present invention.

[0033] Figure 12 This is a block diagram showing a configuration example of a camera system including an imaging device according to the present invention. DETAILED DESCRIPTION

[0034] (Understanding that forms the basis of the present invention)

[0035] The present inventors have discovered that the following problems occur with respect to the techniques disclosed in Patent Documents 1, 2, and 3.

[0036] In the technology disclosed in Patent Document 1, a pixel consists of three transistors. To cope with further miniaturization, the number of transistors must be reduced. Therefore, miniaturization of the pixels in the sensor described in Patent Document 1 is difficult to achieve. That is, even if the photoelectric conversion unit is formed outside the semiconductor substrate, miniaturization is limited in a structure with three transistors in the pixel. For example, it is difficult to miniaturize the pixel to the same level as the wavelength of the absorbed light, with a cut of 1μm, and some transistors must be excluded.

[0037] Furthermore, Patent Document 2 proposes a technique for removing the reset transistor used to reset the charge accumulated in the charge storage region from the pixel to achieve pixel miniaturization. However, in the technique of Patent Document 2, the photoelectric conversion unit has a structure in which the photoelectric conversion layer is directly sandwiched between two electrodes. Therefore, during charge accumulation, a small amount of charge with a positive and negative sign opposite to the signal charge may migrate from the charge storage region to the photoelectric conversion layer. This can cause dark current in the pixel.

[0038] Furthermore, Patent Document 3 proposes a technology that removes the reset transistor from the pixel to facilitate pixel miniaturization. Furthermore, the photoelectric conversion unit includes a photoelectric conversion layer that includes a blocking layer capable of blocking the movement of small amounts of charge. However, further measures are required to suppress dark current generated in the pixel. Furthermore, when resetting the charge storage area, a design is required that prevents the blocking layer from blocking the movement of small amounts of charge from the photoelectric conversion layer to the charge storage area.

[0039] (Summary of the Invention)

[0040] An imaging device according to one embodiment of the present invention includes: a photoelectric conversion portion comprising a first electrode, a second electrode opposing the first electrode, a photoelectric conversion layer located between the first and second electrodes and configured to convert incident light into signal charges, and a blocking layer located between the photoelectric conversion layer and the second electrode; and a charge accumulation region connected to the second electrode and configured to accumulate the signal charges. The energy barrier to the movement of charges of opposite polarity to the signal charges from the second electrode to the photoelectric conversion layer due to the blocking layer is 1.8 eV or greater. The energy barrier to the movement of charges from the photoelectric conversion layer to the second electrode due to the blocking layer is 1.6 eV or less.

[0041] Thus, the photoelectric conversion unit includes a blocking layer. Furthermore, the energy barrier due to the blocking layer for the movement of charges of opposite polarity to the signal charge from the second electrode to the photoelectric conversion layer is greater than 1.8 eV, and the energy barrier due to the blocking layer for the movement of a small amount of charge from the photoelectric conversion layer to the second electrode is less than 1.6 eV. Therefore, during charge accumulation, the movement of a small amount of charge from the charge accumulation region to the photoelectric conversion layer can be blocked with a high probability. This can suppress the occurrence of dark current. Furthermore, during the reset operation of the charge accumulation region, the movement of a small amount of charge from the photoelectric conversion layer to the charge accumulation region is not easily hindered. This allows for a smooth reset operation.

[0042] An imaging device according to one aspect of the present invention may further include a voltage supply circuit; wherein during a first period in which the signal charge is accumulated from the photoelectric conversion portion to the charge accumulation region, the voltage supply circuit supplies a first voltage to the first electrode; and during a second period in which the signal charge accumulated in the charge accumulation region is reset, the voltage supply circuit supplies a second voltage, different from the first voltage, to the first electrode. This eliminates the need for a reset transistor for resetting the charge accumulation region.

[0043] In addition, it may also be that the above-mentioned signal charges are holes; the electron affinity of the above-mentioned blocking layer is smaller than the work function of the above-mentioned second electrode, and the difference between the electron affinity of the above-mentioned blocking layer and the work function of the above-mentioned second electrode is greater than 1.8 eV; the electron affinity of the above-mentioned blocking layer is smaller than the electron affinity of the above-mentioned photoelectric conversion layer, and the difference between the electron affinity of the above-mentioned blocking layer and the electron affinity of the above-mentioned photoelectric conversion layer is less than 1.6 eV.

[0044] Furthermore, the ionization potential of the blocking layer may be higher than the ionization potential of the photoelectric conversion layer.

[0045] Thus, when the signal charges are holes, the movement of a small amount of charge from the charge storage region to the photoelectric conversion layer is highly likely blocked during the first period. Furthermore, the movement of a small amount of charge from the photoelectric conversion layer to the charge storage region can be smoothly performed during the second period.

[0046] In addition, the imaging device according to a technical solution of the present invention may also be provided with a voltage supply circuit; during the first period in which the signal charge is accumulated from the photoelectric conversion portion to the charge accumulation region, the voltage supply circuit supplies the first voltage to the first electrode; during the second period in which the signal charge accumulated in the charge accumulation region is reset, the voltage supply circuit supplies the first electrode with a second voltage that is smaller than the first voltage.

[0047] Thus, during the first period, a voltage greater than that of the second electrode is supplied to the first electrode. This enables a charge accumulation operation in which holes generated in the photoelectric conversion layer are concentrated at the second electrode. Furthermore, during the second period, which serves as a reset operation, a voltage less than that of the second electrode is supplied to the first electrode. This concentrates electrons at the second electrode, resetting the charge accumulation region and the second electrode.

[0048] Furthermore, an imaging device according to one aspect of the present invention may further include a semiconductor substrate having the charge accumulation region provided thereon; a third voltage may be supplied to the semiconductor substrate during the first period; and a fourth voltage different from the third voltage may be supplied to the semiconductor substrate during the second period. In this case, the third voltage may be lower than the first voltage, and the fourth voltage may be higher than the second voltage.

[0049] Thus, different voltages are supplied to the semiconductor substrate during the first period and the second period. Consequently, compared to a case where a constant voltage is constantly supplied to the semiconductor substrate, the second voltage supplied to the first electrode during the second period can be made closer to the first voltage. Consequently, compared to a case where a constant voltage is constantly supplied to the semiconductor substrate, the voltage range supplied by the voltage supply circuit can be narrowed.

[0050] In addition, it may also be that the above-mentioned signal charge is an electron; the ionization potential of the above-mentioned blocking layer is greater than the work function of the above-mentioned second electrode, and the difference between the ionization potential of the above-mentioned blocking layer and the work function of the above-mentioned second electrode is greater than 1.8eV; the ionization potential of the above-mentioned blocking layer is greater than the ionization potential of the above-mentioned photoelectric conversion layer, and the difference between the ionization potential of the above-mentioned blocking layer and the ionization potential of the above-mentioned photoelectric conversion layer is less than 1.6ev.

[0051] Furthermore, the electron affinity of the blocking layer may be lower than the electron affinity of the photoelectric conversion layer.

[0052] Thus, when the signal charges are electrons, the movement of a small amount of charge from the charge storage region to the photoelectric conversion layer is highly likely blocked during the first period. Furthermore, the movement of a small amount of charge from the photoelectric conversion layer to the charge storage region can be smoothly performed during the second period.

[0053] In addition, the imaging device according to a technical solution of the present invention may also be provided with a voltage supply circuit; during the first period in which the signal charge is accumulated from the photoelectric conversion portion to the charge accumulation region, the voltage supply circuit supplies the first voltage to the first electrode; during the second period in which the signal charge accumulated in the charge accumulation region is reset, the voltage supply circuit supplies the first electrode with a second voltage that is greater than the first voltage.

[0054] Thus, during the first period, a voltage lower than that of the second electrode is supplied to the first electrode. This enables a charge accumulation operation in which electrons generated by the photoelectric conversion layer are concentrated at the second electrode. Furthermore, during the second period, which serves as a reset operation, a voltage greater than that of the second electrode is supplied to the first electrode. This concentrates holes at the second electrode, resetting the charge accumulation region and the second electrode.

[0055] Furthermore, the imaging device according to one aspect of the present invention may further include a semiconductor substrate having the charge accumulation region provided thereon; a fifth voltage may be supplied to the semiconductor substrate during the first period; and a sixth voltage different from the fifth voltage may be supplied to the semiconductor substrate during the second period. In this case, the fifth voltage may be greater than the first voltage, and the sixth voltage may be less than the second voltage.

[0056] Thus, different voltages are supplied to the semiconductor substrate during the first period and the second period. Consequently, compared to a case where a constant voltage is constantly supplied to the semiconductor substrate, the second voltage supplied to the first electrode during the second period can be made closer to the first voltage. Consequently, compared to a case where a constant voltage is constantly supplied to the semiconductor substrate, the voltage range supplied by the voltage supply circuit can be narrowed.

[0057] In addition, it may also be that the above-mentioned photoelectric conversion layer has a diode characteristic; the above-mentioned photoelectric conversion part has a current-voltage characteristic with the following voltage ranges: a first voltage range, as the bias voltage applied to the above-mentioned photoelectric conversion layer increases in the opposite direction of the above-mentioned diode characteristic, the absolute value of the output current density of the above-mentioned photoelectric conversion part increases; a second voltage range, as the above-mentioned bias voltage increases in the positive direction of the above-mentioned diode characteristic, the above-mentioned output current density increases; and a third voltage range, which is between the above-mentioned first voltage range and the above-mentioned second voltage range, and the absolute value of the rate of change of the above-mentioned output current density with respect to the above-mentioned bias voltage is smaller than the above-mentioned first voltage range and the above-mentioned second voltage range; by supplying the above-mentioned first voltage to the above-mentioned first electrode, the above-mentioned bias voltage applied to the above-mentioned photoelectric conversion layer is within the above-mentioned first voltage range; by supplying the above-mentioned second voltage to the above-mentioned first electrode, the above-mentioned bias voltage applied to the above-mentioned photoelectric conversion layer is within the above-mentioned second voltage range.

[0058] Thus, voltages matching the current-voltage characteristics of the photoelectric conversion layer having diode characteristics are applied to the photoelectric conversion layer during the first and second periods. Therefore, charge accumulation is reliably performed during the first period, and reset is reliably performed during the second period.

[0059] Furthermore, the imaging device according to one aspect of the present invention may further include a plurality of pixels arranged in a matrix, and the first electrode may be arranged continuously with respect to all of the plurality of pixels.

[0060] Thus, the first electrode is formed commonly for all pixels. Therefore, the voltage supplied to the first electrode can be controlled simultaneously in all pixels. For example, a simultaneous reset operation of all pixels, i.e., a global reset operation, can be performed.

[0061] Furthermore, the imaging device according to one aspect of the present invention may further include a plurality of pixels arranged in a matrix, and the first electrode may be arranged continuously with respect to pixels located in the same row among the plurality of pixels.

[0062] Thus, the first electrode is formed in common for pixels located in the same row. Therefore, the voltage supplied to the first electrode can be controlled for each row, and the sensitivity of the pixels can be adjusted for each row.

[0063] Furthermore, the imaging device according to one aspect of the present invention may further include a plurality of pixels arranged in a matrix, and the first electrode may be arranged separately from each of the plurality of pixels.

[0064] Thus, the first electrode is independently formed for each pixel. Therefore, the voltage supplied to the first electrode can be controlled for each pixel, and the sensitivity can be adjusted for each pixel.

[0065] Furthermore, the imaging device according to one aspect of the present invention may further include an amplifying transistor including a gate connected to the second electrode; the charge accumulation region may include the gate; and the gate may not be connected to the semiconductor substrate.

[0066] This eliminates the need for a semiconductor region in which impurities are diffused as a charge accumulation region, thereby enabling further miniaturization of pixels.

[0067] Hereinafter, embodiments of the imaging device of the present invention will be described in detail with reference to the accompanying drawings. In addition, the embodiments described below all represent specific examples. Therefore, the numerical values, shapes, materials, components, configurations of components, and connection forms, etc. shown in the following embodiments are examples, and the present invention is not intended to be limited to these. Therefore, among the components of the following embodiments, the components that are not described in the independent claims representing the highest concepts are described as arbitrary components. In addition, each figure is a schematic diagram and is not necessarily a strict illustration. In addition, the same reference numerals are given to the same components in each figure.

[0068] Furthermore, the various elements shown in the drawings are merely schematic representations to facilitate understanding of the present invention, and their dimensional ratios and appearance may differ from those of the actual objects. In other words, the figures are schematic and do not necessarily represent exact representations. Therefore, for example, scales and other factors may not necessarily be consistent across the figures. Furthermore, in this specification, numerical ranges are not intended to represent strictly equivalent values, but rather to indicate substantially equivalent ranges, including differences of, for example, a few percentage points.

[0069] In addition, in the description of the structure in this specification, the terms "upper" and "lower" do not refer to the upper side (vertically above) and the lower side (vertically below) in absolute spatial recognition, but are used as terms defined by relative positional relationships based on the stacking order in the stacked structure. Specifically, the light-receiving side of the camera device is set as "upper" and the side opposite to the light-receiving side is set as "lower". In addition, the terms "upper" and "lower" are not only used when two components are spaced apart from each other and there are other components between the two components, but also apply to the case where two components are arranged in close contact with each other and the two components are in contact.

[0070] (Implementation Method 1)

[0071] First, use Figures 1 to 3 The overall configuration of the imaging device according to the first embodiment of the present invention will be described.

[0072] Figure 1 This is a block diagram showing the overall configuration of an imaging device according to Embodiment 1. The imaging device 100 shown in this figure includes a pixel array section 101, a vertical scanning section 102, a signal holding section 103, a horizontal scanning section 104, and an output-stage amplifier circuit section 105. In the pixel array section 101 and its surrounding area, vertical signal lines are arranged for each pixel column, and scanning lines are arranged for each pixel row.

[0073] The pixel array unit 101 is an imaging unit in which a plurality of pixels 200 are arranged in a matrix of, for example, m rows and n columns (m and n are both natural numbers).

[0074] The vertical scanning unit 102 has a function of controlling the reset operation, charge accumulation operation, and readout operation of the pixels 200 in units of rows.

[0075] The signal holding section 103 holds a differential signal between a pixel signal output from a pixel 200 and a reset signal corresponding to the pixel 200 , and outputs the differential signal in accordance with an instruction from a horizontal scanning section 104 described later.

[0076] The horizontal scanning section 104 has a function of sequentially selecting the differential signals corresponding to one row held in the signal holding section 103 and reading them out to the output stage amplifier circuit section 105 arranged on the output side of the signal holding section 103 .

[0077] Figure 2 This diagram shows an example of the circuit configuration of the pixel 200 and the voltage supply circuit 201 of the imaging device 100 according to Embodiment 1. This diagram shows a specific example of the circuit configuration of the pixel 200, the voltage supply circuit 201, power supply lines, and signal lines.

[0078] The pixel 200 includes a photoelectric conversion portion 204, a charge storage portion (floating diffusion) 205, an amplifier transistor 206, and a selection transistor 207. That is, the reset transistor that was conventionally required is eliminated.

[0079] The photoelectric conversion unit 204 generates a signal charge corresponding to the amount of incident light by performing photoelectric conversion on the incident light. Specifically, the photoelectric conversion unit 204 is composed of a first electrode 202, a second electrode 203, a photoelectric conversion layer 204b as an active layer sandwiched between the two electrodes, a hole blocking layer 204h sandwiched between the first electrode 202 and the photoelectric conversion layer 204b, and an electron blocking layer 204e sandwiched between the photoelectric conversion layer 204b and the second electrode 203. The photoelectric conversion layer 204b, for example, contains organic molecules with high light absorption ability. The thickness of the photoelectric conversion layer 204b is, for example, about 500 nm. In addition, the photoelectric conversion layer 204b is formed, for example, by vacuum evaporation. The above-mentioned organic molecules have high light absorption performance over the entire range of visible light with a wavelength of about 400 nm to about 700 nm. The details of the photoelectric conversion unit 204 are described using Figure 4 Described later.

[0080] The photoelectric conversion portion 204 of the pixel 200 of this embodiment is not limited to being composed of the aforementioned organic photoelectric conversion film and may, for example, be a photodiode composed of an inorganic material. Furthermore, the wavelength at which light can be absorbed is not limited to the visible light region and may also be in the infrared region, the ultraviolet region, or a combination thereof.

[0081] The charge storage section 205 is connected to the second electrode 203 of the photoelectric conversion section 204 and forms a charge storage region for storing signal charges generated by photoelectric conversion. Furthermore, the charge storage region is composed not only of the charge storage section 205 but also of the wiring connected to the second electrode 203 and the stray capacitance of the gate of the amplifier transistor 206. Therefore, as will be described later, the charge storage section 205 formed of an impurity semiconductor need not be used as a charge storage region. In other words, the charge storage region may be a region not connected to the semiconductor substrate, such as the gate of the amplifier transistor 206.

[0082] Amplifier transistor 206 and select transistor 207 are typically field-effect transistors (FETs). Unless otherwise specified, the following examples use N-channel MOSFETs (Metal Oxide Semiconductor FETs) as the transistors. The polarity of the FET and the potential at that point in time determine which of its two diffusion regions corresponds to the source and drain. Therefore, the source and drain correspond to different regions depending on the FET's operating state.

[0083] The gate of the amplifier transistor 206 is connected to the charge accumulation section 205 , and the power supply voltage Vdd is supplied to the drain terminal. The amplifier transistor 206 outputs a pixel signal corresponding to the amount of signal charges accumulated in the charge accumulation region.

[0084] The drain terminal of the selection transistor 207 is connected to the source terminal of the amplifier transistor 206 , and the source terminal is connected to the vertical signal line 208 , and determines the timing of outputting the pixel signal from the amplifier transistor 206 .

[0085] The voltage supply circuit 201 has two reference potentials, and one of the reference potentials can be selected by a switch and input to the first electrode 202. The two reference potentials are voltage VH and voltage VL. Figure 4 This will be described later. Voltage VH and voltage VL are examples of a first voltage and a second voltage different from the first voltage, respectively, applied to the first electrode 202. In this embodiment, voltage VH is greater than voltage VL. For example, voltage VH is 8V and voltage VL is -2V. In addition, in this specification, "large" and "small" voltages refer to "higher" and "lower" potentials, respectively. For example, voltage "1V" is greater than voltage "-2V".

[0086] Figure 3 1 is a diagram showing an example of a cross-sectional view of a three-pixel region of the imaging device 100. Note that, in actuality, 10 million pixels are arrayed in the pixel array unit 101, for example.

[0087] like Figure 3 As shown, the imaging device 100 includes a color filter 301, a protective film 302, a photoelectric conversion portion 204, an inter-electrode insulating film 305, an inter-wiring insulating film 307, a wiring layer 308, a substrate 309, a well 310, and an interlayer insulating film 311. The photoelectric conversion portion 204 includes a first electrode 202, a hole blocking layer 204h, a photoelectric conversion layer 204b, an electron blocking layer 204e, and a second electrode 203.

[0088] The substrate 309 is a semiconductor substrate, such as a silicon substrate.

[0089] The first electrode 202 is a conductive transparent electrode, and in this embodiment, is formed over the entire surface of the pixel array under the protective film 302. The first electrode 202 transmits visible light and is made of, for example, ITO (Indium Tin Oxide).

[0090] A plurality of second electrodes 203 are arranged in a matrix above the substrate 309. Furthermore, the plurality of second electrodes 203 are electrically isolated. Specifically, the second electrodes 203 are formed between the inter-electrode insulating film 305 and collect holes, which serve as signal charges generated by the photoelectric conversion layer 204b. The second electrodes 203 are made of, for example, TiN. Furthermore, the second electrodes 203 are formed on, for example, a planarized inter-wiring insulating film 307 having a thickness of 100 nm.

[0091] The second electrodes 203 are separated by a distance of, for example, 0.2 μm, and an inter-electrode insulating film 305 is embedded in the separation region.

[0092] The wiring layer 308 is connected to the gate terminals of the charge storage unit 205 and the amplifier transistor 206. Although not shown, the selection transistor 207 and the charge storage unit 205 formed in the same pixel are all formed in the same P-type well 310. In addition, the well 310 is formed in the substrate 309. That is, Figure 2 The signal readout circuit shown, which is composed of an amplifier transistor 206 and a selection transistor 207, is formed on a substrate 309. It generates a readout signal corresponding to the signal charge by detecting changes in current or voltage occurring in each of the plurality of second electrodes 203. Furthermore, the amplifier transistor 206 generates a readout signal by amplifying changes in current or voltage occurring in the second electrodes 203.

[0093] As described above, according to the imaging device 100 of this embodiment, by irradiating the photoelectric conversion layer 204b with light and applying a bias voltage between the first electrode 202 and the second electrode 203, the second electrode 203 can collect signal charges (either positive or negative) generated by photoelectric conversion and store the collected signal charges in the charge storage region. The inventors discovered that by using a photoelectric conversion layer 204b exhibiting the current-voltage characteristics described below and by setting the potential difference between the first electrode 202 and the second electrode 203 opposite to that during charge storage, the signal charges accumulated in the charge storage region can be extracted to the first electrode 202 via the photoelectric conversion layer 204b. Specifically, by controlling the magnitude of the bias voltage applied to the photoelectric conversion layer 204b, it was discovered that a signal charge reset function can be achieved without providing separate elements such as reset transistors in each of the multiple pixels. A typical example of the operation of the imaging device 100 will be described below.

[0094] Hereinafter, an example of the structure of the photoelectric conversion layer 204b and the current-voltage characteristics of the photoelectric conversion layer 204b will be described.

[0095] The photoelectric conversion layer 204b typically contains a semiconductor material. Here, an organic semiconductor material is used as the semiconductor material. For example, the photoelectric conversion layer 204b contains naphthalocyanine tin (hereinafter simply referred to as "naphthalocyanine tin") represented by the following general formula (1).

[0096] [Chemical Formula 1]

[0097]

[0098] In the general formula (1), R 1 ~R 24and independently represent a hydrogen atom or a substituent. The substituent is not limited to a specific substituent. The substituent may be a heavy hydrogen atom, a halogen atom, an alkyl group (including a cycloalkyl group, a bicycloalkyl group, a tricycloalkyl group), an alkenyl group (including a cycloalkenyl group, a bicycloalkenyl group), an alkynyl group, an aryl group, a heterocyclic group, a cyano group, a hydroxyl group, a nitro group, a carboxyl group, an alkoxy group, an aryloxy group, a silyloxy group, a heterocyclic group, an acyloxy group, a carbamoyloxy group, an alkoxycarbonyloxy group, an aryloxycarbonyloxy group, an amino group (including an anilino group), an ammonium group, an acylamino group, an aminocarbonylamino group, an alkoxycarbonylamino group, an aryloxycarbonylamino group, a sulfamoylamino group, an alkylsulfonylamino group, an arylsulfonylamino group Acylamino, thiol, alkylthio, arylthio, heterocyclic thio, sulfamoyl, sulfo, alkylsulfinyl, arylsulfinyl, alkylsulfonyl, arylsulfonyl, acyl, aryloxycarbonyl, alkoxycarbonyl, carbamoyl, arylazo, heterocyclic azo, imide, phosphino, phosphinyl, phosphinyloxy, phosphinylamino, phosphono, silyl, hydrazine, urea, boronic acid (-B(OH)2), phosphate (-OPO(OH)2), sulfate (-OSO3H), or other well-known substituents.

[0099] As the naphthalocyanine tin represented by the general formula (1), a commercially available product can be used. Alternatively, the naphthalocyanine tin represented by the general formula (1) can be synthesized using a naphthalene derivative represented by the following general formula (2) as a starting material, as described in Japanese Patent Application Laid-Open No. 2010-232410. R in the general formula (2) 25 to R 30 It can be the same as R in the general formula (1) 1 to R 24 Same substituents.

[0100] [Chemical Formula 2]

[0101]

[0102] In the tin naphthalocyanine represented by the above general formula (1), from the viewpoint of easily suppressing the aggregation state of the molecules, R 1 to R 24 More than 8 of them are hydrogen atoms or heavy hydrogen atoms, or R 1 to R 24 Sixteen or more of them may be hydrogen atoms or deuterium atoms, and all of them may be hydrogen atoms or deuterium atoms. Furthermore, tin naphthalocyanine represented by the following formula (3) is advantageous from the viewpoint of easy synthesis.

[0103] [Chemical Formula 3]

[0104]

[0105] Naphthalocyanine tin represented by the above-mentioned general formula (1) has absorption properties in the wavelength range of approximately 200 nm to 1100 nm. For example, naphthalocyanine tin represented by the above-mentioned formula (3) has an absorption peak at a wavelength of approximately 870 nm. In other words, by selecting a material containing naphthalocyanine tin as the material constituting the photoelectric conversion layer 204b, a photosensor capable of detecting near-infrared rays can be realized, for example.

[0106] Figure 4 An example of a detailed structure of the photoelectric conversion unit 204 is schematically shown. Figure 4 In the illustrated structure, the photoelectric conversion unit 204 includes a first electrode 202, a hole-blocking layer 204h, a photoelectric conversion layer 204b formed of an organic semiconductor material containing tin naphthalocyanine represented by the above-mentioned general formula (1) and converting incident light into signal charges, an electron-blocking layer 204e, and a second electrode 203. The hole-blocking layer 204h is disposed between the photoelectric conversion layer 204b and the first electrode 202. The electron-blocking layer 204e is disposed between the photoelectric conversion layer 204b and the second electrode 203.

[0107] Figure 4 The photoelectric conversion layer 204b shown includes at least one of a p-type semiconductor and an n-type semiconductor. Figure 4 In the illustrated structure, the photoelectric conversion layer 204b includes a p-type semiconductor layer 204p, an n-type semiconductor layer 204n, and a mixed layer 204m sandwiched between the p-type semiconductor layer 204p and the n-type semiconductor layer 204n. In other words, the photoelectric conversion layer 204b exhibits diode characteristics. The p-type semiconductor layer 204p is positioned between the electron-blocking layer 204e and the mixed layer 204m and performs photoelectric conversion and / or hole transport functions. The n-type semiconductor layer 204n is positioned between the hole-blocking layer 204h and the mixed layer 204m and performs photoelectric conversion and / or electron transport functions. As described later, the mixed layer 204m may also include at least one of a p-type semiconductor and an n-type semiconductor. The p-type semiconductor layer 204p includes an organic p-type semiconductor, and the n-type semiconductor layer 204n includes an organic n-type semiconductor. That is, the photoelectric conversion layer 204b includes: an organic photoelectric conversion material including tin naphthalocyanine represented by the above-mentioned general formula (1); and at least one of an organic p-type semiconductor and an organic n-type semiconductor.

[0108] Organic p-type semiconductor compounds are donor organic semiconductor compounds, mainly represented by hole transporting organic compounds, and refer to organic compounds with the property of easily donating electrons. In more detail, organic p-type semiconductor compounds refer to organic compounds with a smaller ionization potential when two organic materials are brought into contact. Therefore, as donor organic compounds, any organic compound can be used as long as it is an organic compound with electron donating properties. For example, metal complexes having triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, cyanine compounds, merocyanine compounds, oxonol compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, polyarylene compounds, condensed aromatic carbocyclic compounds (naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, fluoranthene derivatives), nitrogen-containing heterocyclic compounds as ligands can be used. Furthermore, donor organic semiconductors are not limited to these, and any organic compound having a lower ionization potential than an organic compound used as an n-type (acceptor) compound as described above can be used as a donor organic semiconductor. The above-mentioned tin naphthalocyanine is an example of an organic p-type semiconductor material.

[0109] Organic n-type semiconductor compounds are acceptor organic semiconductor compounds, and mainly refer to organic compounds with the property of easily accepting electrons, represented by electron-transporting organic compounds. In more detail, organic n-type semiconductor compounds refer to organic compounds with a larger electron affinity when two organic compounds are brought into contact and used. Therefore, as acceptor organic compounds, any organic compound can be used as long as it is an organic compound with electron-accepting properties. For example, there can be listed fullerenes, fullerene derivatives, condensed aromatic carbocyclic compounds (naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, fluoranthene derivatives), five-membered heterocyclic compounds containing nitrogen atoms, oxygen atoms, and sulfur atoms to seven-membered heterocyclic compounds (such as pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole ring, pyrazole, imidazole, thiazole , oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine, tribenzazepine, etc.), polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silyl compounds, metal complexes containing nitrogen-containing heterocyclic compounds as ligands, etc. Furthermore, without limitation thereto, any organic compound having a higher electron affinity than that of a p-type organic compound, in other words, an organic compound used as a donor organic compound, as described above, can be used as an acceptor organic semiconductor.

[0110] The mixed layer 204m can be, for example, a bulk heterojunction structure layer including a p-type semiconductor and an n-type semiconductor. In the case where the mixed layer 204m is formed as a layer having a bulk heterojunction structure, naphthalocyanine tin represented by the above-mentioned general formula (1) can be used as the p-type semiconductor material. As the n-type semiconductor material, for example, fullerene and / or fullerene derivatives can be used. The material constituting the p-type semiconductor layer 204p can also be the same as the p-type semiconductor material contained in the mixed layer 204m. Similarly, the material constituting the n-type semiconductor layer 204n can also be the same as the n-type semiconductor material contained in the mixed layer 204m. The bulk heterojunction structure is described in detail in Japanese Patent Gazette No. 5553727. For reference, the entire disclosure of Japanese Patent Gazette No. 5553727 is cited in this specification.

[0111] By using appropriate materials based on the desired wavelength band, an imaging device with sensitivity in the desired wavelength band can be realized. Photoelectric conversion layer 204b may also include inorganic semiconductor materials such as amorphous silicon. Photoelectric conversion layer 204b may also include layers composed of organic materials and layers composed of inorganic materials. The following describes an example in which a bulk heterojunction structure, obtained by co-evaporating tin naphthalocyanine and C60, is applied to photoelectric conversion layer 204b.

[0112] In this embodiment, the electron affinity of the electron blocking layer 204e is at least 1.8 eV less than the work function of the second electrode 203 and within 1.6 eV less than the electron affinity of the photoelectric conversion layer 204b. Furthermore, the ionization potential of the electron blocking layer 204e is greater than that of the photoelectric conversion layer 204b. Examples of material combinations that meet these conditions for the second electrode 203, the electron blocking layer 204e, and the photoelectric conversion layer 204b include TiN, α-NPD (4,4'-bis[N-(naphthyl)-N-phenyl-amino]biphenyl), and fullerene C60. The work function of TiN is 4.7 eV, the electron affinity of α-NPD is 2.4 eV, and the electron affinity of fullerene C60 is 4.0 eV.

[0113] (Current-voltage characteristics of the photoelectric conversion layer)

[0114] Figure 5 This is a diagram showing an example of a typical current-voltage characteristic of the photoelectric conversion layer 204b. The horizontal axis represents the applied voltage (V) to the photoelectric conversion layer 204b, and the vertical axis represents the density of the current flowing through the photoelectric conversion layer 204b, that is, the output current density (μA / cm 2 ).exist Figure 5 In the graph of FIG. 1 , the thick solid line represents an exemplary current-voltage characteristic (IV characteristic) of the photoelectric conversion layer 204 b when irradiated with light. Figure 5 In FIG, an example of IV characteristics in a state where no light is irradiated is also shown by a thick dotted line. Figure 5It represents the change in current density between the two main surfaces of the photoelectric conversion layer 204b when the bias applied between the two main surfaces is changed under a certain illumination. In this specification, the forward and reverse directions of the bias are defined as follows. As mentioned above, the photoelectric conversion layer 204b has diode characteristics. In the case where the photoelectric conversion layer 204b has a junction structure of a layered p-type semiconductor and a layered n-type semiconductor, the bias that makes the potential of the p-type semiconductor layer higher than that of the n-type semiconductor layer is defined as the forward bias of the diode characteristics. On the other hand, the bias that makes the potential of the p-type semiconductor layer lower than that of the n-type semiconductor layer is defined as the reverse bias of the diode characteristics. In the case of using an organic semiconductor material, the forward and reverse directions can also be defined in the same way as in the case of using an inorganic semiconductor material. In the case where the photoelectric conversion layer 204b has a bulk heterojunction structure, as in the above-mentioned Japanese Patent Gazette No. 5553727 Figure 1 As schematically shown in FIG, on one of the two principal surfaces of the bulk heterojunction structure facing the electrode, p-type semiconductor is present more than n-type semiconductor, while on the other surface, n-type semiconductor is present more than p-type semiconductor. Therefore, a bias voltage that makes the potential of the principal surface on which p-type semiconductor is present more than n-type semiconductor higher than the potential of the principal surface on which n-type semiconductor is present more than p-type semiconductor is defined as a forward bias voltage.

[0115] like Figure 5 As shown, the current-voltage characteristics of the photoelectric conversion layer 204b are generally characterized by three voltage ranges, namely the first voltage range to the third voltage range. The first voltage range is the reverse bias voltage range, in which the absolute value of the output current density increases as the reverse bias voltage increases. The first voltage range can also be said to be a voltage range in which the current increases as the bias voltage applied between the main surfaces of the photoelectric conversion layer 204b increases. The second voltage range is the forward bias voltage range, in which the output current density increases as the forward bias voltage increases. In other words, the second voltage range is a voltage range in which the forward current increases as the bias voltage applied between the main surfaces of the photoelectric conversion layer 204b increases. The third voltage range is a voltage range between the first and second voltage ranges.

[0116] The first voltage range to the third voltage range can be distinguished by the slope of the current-voltage characteristic curve when the vertical axis and horizontal axis are linear. Figure 5 In FIG, the average slopes of the curves for the first voltage range and the second voltage range are represented by dashed lines L1 and L2, respectively. The applied voltage at the intersection of dashed line L1 and the horizontal axis where the output current density is zero is the boundary between the first voltage range and the third voltage range, and the applied voltage at the intersection of dashed line L2 and the horizontal axis where the output current density is zero is the boundary between the third voltage range and the second voltage range. Figure 5As shown in the example, the rates of change of the output current density with respect to an increase in bias voltage are different in the first voltage range, the second voltage range, and the third voltage range. The third voltage range is defined as a voltage range in which the rate of change of the output current density with respect to bias voltage is smaller than the rates of change in the first voltage range and the second voltage range.

[0117] In addition, the third voltage range can also be determined based on the rising or falling position of the curve representing the IV characteristic. The third voltage range is typically greater than -1V and less than +1V. In the third voltage range, even if the bias voltage is changed, the current density between the main surfaces of the photoelectric conversion layer 204b hardly changes. Figure 5 As shown in the example, in the third voltage range, the absolute value of the current density is typically 100 μA / cm 2 the following.

[0118] (Charge accumulation and reset method)

[0119] Figure 6 This diagram shows an example of an energy band diagram for the photoelectric conversion unit 204. Specifically, it shows an example of an energy band diagram for the photoelectric conversion unit 204 in the first voltage range or the second voltage range described above. On the vertical axis, energy levels increase as they are viewed from the upper side, while electrode potentials decrease as they are viewed from the upper side. Furthermore, as described above, the electron affinity of the electron blocking layer 204e is at least 1.8 eV lower than the work function of the second electrode 203 and within 1.6 eV lower than the electron affinity of the photoelectric conversion layer 204b. That is, the LUMO energy level of the electron blocking layer 204e is at least 1.8 eV higher than the work function of the second electrode 203 and within 1.6 eV higher than the LUMO energy level of the photoelectric conversion layer 204b. Furthermore, the ionization potential of the electron blocking layer 204e is greater than that of the photoelectric conversion layer 204b. That is, the HOMO level of the electron blocking layer 204 e is lower than the HOMO level of the photoelectric conversion layer 204 b .

[0120] Use this Figure 6 , the charge accumulation operation and reset operation of the imaging device 100 of this embodiment example are described. The charge accumulation operation refers to the period from the start of irradiating the photoelectric conversion layer 204b with light to generate signal charges and the completion of accumulating the generated signal charges in the charge accumulation region. The charge accumulation operation is an example of the first period during which the signal charges are read from the photoelectric conversion unit 204 to the charge accumulation region. The reset operation is a period during which the signal charges accumulated in the charge accumulation region are discharged and the potential of the charge accumulation region is reset to the potential before charge accumulation. The reset operation is an example of the second period during which the signal charges accumulated in the charge accumulation region are reset. The following is an example using holes in electron-hole pairs as signal charges.

[0121] First, during the charge accumulation operation, a voltage VH higher than that of the second electrode 203 is applied to the first electrode 202, so that the photoelectric conversion layer 204b is in the first voltage range. In other words, the voltage VH is a voltage in the first voltage range. The energy band diagram of the photoelectric conversion unit 204 at this time is shown in FIG. Figure 6 In part (a). If light is incident, photoelectric conversion is performed in the photoelectric conversion layer 204b of the photoelectric conversion unit 204 according to the wavelength and amount of light, generating electron-hole pairs. Among the generated electron-hole pairs, the holes as signal charges are attracted to the second electrode 203 in a lower voltage state and accumulated in the charge accumulation area. At this time, the electrons as a small amount of charge are attracted to the first electrode 202 to which a higher voltage than the second electrode 203 is applied, and are discharged via wiring not shown. As a result, the signal charge generated by the photoelectric conversion layer 204b during the charge accumulation operation is accumulated in the charge accumulation area connected to the second electrode 203, so the potential of the second electrode 203 changes, and the voltage applied to the gate of the amplifier transistor 206 electrically connected to the second electrode 203 changes, thereby detecting a pixel signal. In addition, the pixel signal detected by the amplifier transistor 206 is selectively output to the signal wiring by the selection transistor 207.

[0122] Here, as Figure 6 As shown in part (a), the electron blocking layer 204e blocks the movement of electrons, which are small amounts of charge, from the second electrode 203 to the photoelectric conversion layer 204b with an energy barrier of 1.8 eV or higher. In other words, the electron blocking layer 204e acts as a barrier to the movement of electrons between the second electrode 203 and the photoelectric conversion layer 204b. This prevents electrons from migrating from the second electrode 203 to the first electrode 202 and becoming spurious signal charges (i.e., noise).

[0123] Next, during the reset operation, a voltage VL lower than that of the second electrode 203 is applied to the first electrode 202, so that the photoelectric conversion layer 204b is in the second voltage range. That is, the voltage VL is a voltage in the second voltage range. The energy band diagram of the photoelectric conversion unit 204 at this time is shown in FIG. Figure 6 in part (b).

[0124] like Figure 6As shown in part (b), the energy barrier of the electron blocking layer 204e for the movement of electrons (a small amount of charge) from the photoelectric conversion layer 204b to the second electrode 203 is below 1.6 eV. Consequently, among the electron-hole pairs generated by photoelectric conversion in the photoelectric conversion layer 204b of the photoelectric conversion unit 204, the electrons (a small amount of charge) are hardly blocked by the electron blocking layer 204e and are attracted to the second electrode 203, which is at a higher voltage, and are accumulated in the charge accumulation region. In the charge accumulation region, the incoming electrons cancel out the holes accumulated as signal charge, and the potential of the second electrode drops to the reset potential. As a result, the potential of the charge accumulation region, which is the portion electrically connected from the second electrode 203 to the gate of the amplifier transistor 206, is reset. Meanwhile, the holes are attracted to the first electrode 202, to which a lower voltage than the second electrode 203 is applied, and are discharged via wiring (not shown). As a result, all the signal charges accumulated from the second electrode 203 to the gate of the amplifier transistor 206 , that is, the signal charges accumulated in the charge accumulation region can be discharged to the voltage supply circuit 201 side.

[0125] In this way, by controlling the voltage applied to the first electrode 202, it is possible to switch between the charge accumulation operation and the reset operation. In this case, the electron blocking layer 204e blocks the movement of a small amount of charge from the charge accumulation region connected to the second electrode 203 to the photoelectric conversion layer 204b during the charge accumulation operation, and barely blocks the movement of a small amount of charge from the photoelectric conversion layer 204b to the charge accumulation region during the reset operation. This eliminates the need for the reset transistor previously required in the pixel. Furthermore, the dark current caused by the movement of a small amount of charge from the charge accumulation region to the photoelectric conversion layer during the charge accumulation operation is reliably suppressed, and the movement of a small amount of charge from the photoelectric conversion layer to the charge accumulation region during the reset operation is smoothed.

[0126] Furthermore, in this embodiment, the charge accumulation section 205, which accumulates signal charge, as in conventional imaging devices, can be omitted as a charge accumulation region. In other words, there is no need to form a high-impurity-concentration region on the substrate as a charge accumulation region. This is because the stray capacitance in the region from the second electrode 203 to the gate of the amplifier transistor 206 functions as a charge accumulation region. This structure prevents the influence of dark current caused by the high-impurity-concentration region during the signal charge accumulation period.

[0127] (Drive method)

[0128] Figure 7This is a timing chart of pixel control signals for the imaging device 100 according to Embodiment 1. This diagram illustrates the driving method for the imaging device 100. The diagram shows, from the top, the pixel horizontal synchronization signal HD, the selection signal Vsel for controlling the conduction state of the selection transistor 207, the control signal Vito for the voltage supply circuit 201 applied to the first electrode 202, and the voltage level Vfd of the charge accumulation unit 205.

[0129] In 1H (selection period) from time T1 to time T4, a read operation of a pixel signal of a selected row, a reset operation, and a read operation of a reset signal are performed.

[0130] First, at time T1, Vsel is set to a high voltage, and the voltage of the charge storage unit 205 of the selected row pixel is read out as a pixel signal to the vertical signal line 208 via the amplifier transistor 206 and the select transistor 207. Thereafter, during the selection period, Vsel is maintained at a high voltage. Furthermore, the accumulation period from time T4 to time T2 is an example of the first period during which signal charge is read out from the photoelectric conversion unit 204 to the charge storage region. The operation during this first period corresponds to the first step in which the voltage VH, serving as the first voltage, is supplied to the first electrode 202.

[0131] Next, if Vito changes from a high voltage to a low voltage at time T2, a small amount of charge that is opposite to the signal charge is injected into the charge accumulation unit 205 through the photoelectric conversion layer 204b. This small amount of charge cancels out the signal charge accumulated in the charge accumulation unit 205, and the voltage level of the charge accumulation unit 205 is reset to VL.

[0132] Next, at time T3 , Vfd becomes a Low voltage, and the reset level is read during the period from time T3 to time T4 .

[0133] At time T4, Vsel becomes a low voltage, turning off the select transistor 207. Signal accumulation begins with Vito at a high voltage, and the process repeats thereafter. The reset period from time T2 to time T4 is an example of a second period during which the signal charge accumulated in the charge accumulation region is reset. The operation during this second period corresponds to the second step in which voltage VL, a second voltage different from the first voltage, is supplied to the first electrode 202.

[0134] As described above, according to the imaging device 100 of this embodiment, since signals are read out using a pixel structure that excludes the reset transistor, the pixel size of the imaging device 100 can be miniaturized. Furthermore, since the photoelectric conversion unit 204 includes an electron blocking layer 204e that blocks the movement of a small amount of charge from the charge accumulation region to the photoelectric conversion layer 204b during charge accumulation, the pixel's dark current is reduced. Furthermore, during the reset operation, the movement of a small amount of charge from the photoelectric conversion layer 204b to the charge accumulation region proceeds smoothly.

[0135] Figures 8A to 8C This is a plan view of the first electrode 202 in the imaging region of the imaging device according to the first embodiment and its modified example. Figure 1 The area of the pixel array portion 101 in FIG. 8 to FIG. Figure 8C The shaded area in FIG. 2 represents the first electrode 202 . Figure 8A FIG. 2 is a plan view of the first electrode 202 in the imaging region of the imaging device 100 according to this embodiment. Figure 8A As shown, in this embodiment, the first electrode 202 is formed to a size sufficient to cover the imaging area and is formed uniformly across all pixels. In other words, the first electrode 202 is formed continuously across multiple pixels. This allows the voltage supplied to the first electrode 202 to be controlled simultaneously for all pixels, enabling a global reset operation that simultaneously resets all pixels.

[0136] Alternatively, the first electrode 202 may be formed for each pixel, for each row of pixels, or shared by multiple pixels. Modifications 1 and 2 of the first electrode 202 will be described below.

[0137] [Variation 1]

[0138] Figure 8B : is a plan view of the first electrode 202 in the imaging region of Modification 1. Figure 8B , only a portion of the first electrode 202 is shown. In the first modification, only the structure of the first electrode 202 is changed from that of the first embodiment.

[0139] In modification 1, if Figure 8B As shown, the first electrode 202 is formed for each row of pixels. That is, the first electrode 202 is continuously formed in the pixels located in the same row among the plurality of pixels. Such a first electrode 202 is formed by forming an electrode material on the hole blocking layer 204h and then patterning it.

[0140] In the configuration of Modification 1, independent voltage supply circuits 201 are connected to the first electrodes 202 formed for each row, enabling control of the voltage supplied to the first electrodes 202 for each row. Furthermore, in Modification 1, since the first electrodes 202 can be controlled individually for each row, sensitivity can be adjusted for each row.

[0141] [Variation 2]

[0142] Figure 8C : is a plan view of the first electrode 202 in the imaging region of Modification 2. Figure 8C , only a portion of the first electrode 202 is shown. In the second modification, only the structure of the first electrode 202 is changed from that of the first embodiment.

[0143] In modification 2, if Figure 8C As shown in FIG. 2 , the first electrode 202 is formed for each pixel. That is, the first electrode 202 is formed separately for each horizontal pixel. Such a first electrode 202 is formed by forming an electrode material on the hole blocking layer 204h and then patterning it.

[0144] In the configuration of Modification 2, an independent voltage supply circuit 201 is connected to each first electrode 202 formed for each pixel, making it possible to control the voltage supplied to the first electrode 202 for each pixel. Furthermore, in Modification 2, since the first electrode 202 can be controlled individually for each pixel, sensitivity can be adjusted for each pixel.

[0145] (Implementation Method 2)

[0146] Next, use Figure 9 Embodiment 2 of the present invention will be described. The block diagram of the imaging device 100 according to Embodiment 2 is similar to that shown in Embodiment 1. Figure 1 In addition, the structure of the pixel and the structure of the photoelectric conversion unit are also the same as those shown in the embodiment 1. Figure 2 and Figure 4 It's the same.

[0147] Figure 9 This is a timing chart of pixel control signals related to the imaging device of Embodiment 2. The diagram shows, from the top, the pixel horizontal synchronization signal HD, the selection signal Vsel for controlling the conduction state of the selection transistor 207, the control signal Vito of the voltage supply circuit 201 applied to the first electrode 202, the potential Vsub applied to the substrate 309, and the voltage level Vfd of the charge accumulation unit 205.

[0148] In the 1H (selection period) from time T1 to time T4, the pixel signal reading operation, reset operation and reset signal reading operation of the selected row are performed. Figure 7 The action timing diagram shown is different points.

[0149] Furthermore, the potential Vsub applied to the substrate 309 during the first period, which is the accumulation period, from time T4 to time T2, is an example of the third voltage supplied to the substrate 309 during the first period. The third voltage is lower than the voltage VH, which is the first voltage supplied to the first electrode 202. In this embodiment, the third voltage is the ground potential GND.

[0150] At time T2, when Vito changes from a high voltage to a low voltage, a small amount of charge, which is the opposite charge to the signal charge, is injected into the charge accumulation section 205 via the photoelectric conversion layer 204b. This small amount of charge cancels out the signal charge accumulated in the charge accumulation section 205, resetting the voltage level of the charge accumulation section 205 to VL. It would be beneficial to reduce the range of voltage Vito. Therefore, it is possible to change the potential Vsub applied to the substrate 309. Specifically, at time T2, the substrate potential Vsub is raised in the positive direction from the normal ground potential GND to Vs. Voltage Vs is an example of the fourth voltage supplied to the substrate 309 during the second period, which serves as the reset period. The fourth voltage is greater than voltage VL, which serves as the second voltage. Voltage Vs is, for example, 2V. As a result, the low voltage of Vito can be increased accordingly, and the signal charge can be reset with voltage VL' (=VL+Vs).

[0151] At time T3 , Vfd becomes a completely low voltage, and the reset level is read during the period from time T3 to time T4 .

[0152] At time T4, Vsel becomes a low voltage, and the selection transistor 207 is turned off. Simultaneously, Vito is set to a high voltage to start signal accumulation, and Vsub returns to the ground potential GND. The same process is repeated thereafter.

[0153] As described above, according to this embodiment, the voltage range of the control signal Vito applied by the voltage supply circuit 201 to the first electrode 202 can be narrowed, thereby reducing constraints on the power supply circuit in the imaging device 100. Furthermore, in the first embodiment, the voltage supply circuit 201 applies, for example, 8V to the first electrode 202 during charge accumulation and -2V during resetting. In other words, the polarity of the voltage applied to the first electrode 202 during charge accumulation and resetting differs. In this case, two power supply systems with different polarities are required. However, in the second embodiment, the voltage supply circuit 201 applies, for example, 8V to the first electrode 202 during charge accumulation and 2V during resetting. In other words, the polarity of the voltage applied to the first electrode 202 during charge accumulation and resetting remains the same. In this case, the voltage supply circuit 201 only needs a single power supply system. Therefore, according to the second embodiment, the circuit scale of the imaging device 100 can be reduced compared to the first embodiment.

[0154] While the imaging devices of Embodiments 1 and 2 and their variations have been described above, the present invention is not limited to these Embodiments 1 and 2. For example, the voltage supply circuit 201 can be controlled with a higher degree of freedom by a control signal from outside the chip.

[0155] Furthermore, the pixel 200 of the imaging device 100 in the above embodiment is a pixel using holes as signal charge, but may also be a pixel using electrons as signal charge.

[0156] Figure 10 1 is a diagram schematically showing an example of the structure of the photoelectric conversion unit 1204 of an imaging device having pixels using electrons as signal charges according to another embodiment of the present invention. Figure 4 Compared with the illustrated embodiment 1, the positions of the hole blocking layer 204h and the electron blocking layer 204e are swapped.

[0157] In this example, the ionization potential of the hole blocking layer 204h is greater than the work function of the second electrode 203 by at least 1.8 eV and within 1.6 eV of the ionization potential of the photoelectric conversion layer 204b. Furthermore, the electron affinity of the hole blocking layer 204h is lower than that of the photoelectric conversion layer 204b.

[0158] Figure 11This figure shows an example of an energy band diagram for the photoelectric conversion layer of an imaging device having pixels using electrons as signal charge, according to another embodiment of the present invention. In this type of imaging device, during the charge accumulation operation (the first period), the first voltage supplied to the first electrode 202 is lower than the second voltage supplied to the first electrode 202 during the reset operation (the second period). Furthermore, as mentioned above, the ionization potential of the hole-blocking layer 204h is at least 1.8 eV greater than the work function of the second electrode 203 and within 1.6 eV greater than the ionization potential of the photoelectric conversion layer 204b. In other words, the HOMO level of the hole-blocking layer 204h is at least 1.8 eV lower than the work function of the second electrode 203 and within 1.6 eV lower than the HOMO level of the photoelectric conversion layer 204b. Furthermore, the electron affinity of the hole-blocking layer 204h is lower than that of the photoelectric conversion layer 204b. That is, the LUMO level of the hole blocking layer 204h is higher than the LUMO level of the photoelectric conversion layer 204b.

[0159] Furthermore, the energy band diagram during charge accumulation is Figure 11 As shown in part (a), since the ionization potential of the hole blocking layer 204h is greater than the work function of the second electrode 203 by at least 1.8 eV, the hole blocking layer 204h blocks the movement of holes, which are a small amount of charge, from the second electrode 203 to the photoelectric conversion layer 204b with an energy barrier of at least 1.8 eV. This prevents the holes from moving from the second electrode 203 side to the first electrode 202 side and becoming spurious signal charges, i.e., noise.

[0160] In addition, the energy band diagram during the reset action is Figure 11 As shown in part (b), since the ionization potential of hole-blocking layer 204h is within 1.6 eV greater than that of photoelectric conversion layer 204b, the energy barrier of hole-blocking layer 204h for the movement of small-charge holes from photoelectric conversion layer 204b to second electrode 203 is 1.6 eV or less. Consequently, among the electron-hole pairs generated by photoelectric conversion in photoelectric conversion layer 204b of photoelectric conversion section 204, the small-charge holes are hardly blocked by hole-blocking layer 204h and are attracted to second electrode 203 at a relatively low voltage, thereby being accumulated in the charge accumulation region and resetting the charge accumulation region.

[0161] In this way, the hole blocking layer 204h blocks a small amount of charge from moving from the charge accumulation region connected to the second electrode 203 to the photoelectric conversion layer 204b during charge accumulation. Furthermore, during reset operation, it provides little resistance to the movement of a small amount of charge from the photoelectric conversion layer 204b to the charge accumulation region. This eliminates the need for a reset transistor, which was previously required in pixels. Furthermore, dark current caused by the movement of a small amount of charge from the charge accumulation region to the photoelectric conversion layer during charge accumulation is reliably suppressed, while also facilitating the smooth movement of a small amount of charge from the photoelectric conversion layer to the charge accumulation region during reset operation.

[0162] Furthermore, in an imaging device having pixels that use electrons as signal charge, the potential of the substrate 309 can also be controlled as described in the second embodiment. Specifically, during the first period, which is a charge accumulation operation, a fifth voltage is supplied to the substrate 309, and during the second period, which is a reset operation, a sixth voltage, different from the fifth voltage, is supplied to the substrate 309. In this case, the fifth voltage is greater than the first voltage supplied to the first electrode 202 during the charge accumulation operation, and the sixth voltage is less than the second voltage supplied to the first electrode 202 during the reset operation. This, as in the second embodiment, reduces the voltage range of the control signal Vito from the voltage supply circuit 201 applied to the first electrode 202, thereby minimizing restrictions on the power supply circuit of the imaging device.

[0163] In addition, the camera device according to the above-mentioned embodiment and modified example can also be applied to Figure 12 A block diagram of a camera system 400 is shown. Figure 12 This is a block diagram showing an example of the structure of a camera system 400 including the imaging device 100 according to the present invention. The camera system 400 includes a lens system 401, the imaging device 100, a system controller 402, and a camera signal processing unit 403. The lens system 401 includes, for example, an autofocus lens, a zoom lens, and an aperture. The lens system 401 focuses light onto the imaging surface of the imaging device 100. The system controller 402 can be implemented, for example, by a microcomputer. The camera signal processing unit 403 functions as a signal processing circuit that processes data captured by the imaging device 100 and outputs it as an image or data. The camera signal processing unit 403 performs, for example, gamma correction, color interpolation, spatial interpolation, and white balance processing. The camera signal processing unit 403 can be implemented, for example, by a DSP (Digital Signal Processor). Such a camera system 400 includes the imaging device 100 that has low dark current and can achieve miniaturization of pixels, and thus can be realized as a compact camera with high image quality.

[0164] Furthermore, each processing unit included in the imaging device 100 according to the above embodiment can typically be implemented as an integrated circuit (LSI). They may be formed individually on a single chip, or some or all of them may be formed on a single chip.

[0165] Furthermore, integrated circuits are not limited to LSIs and can also be implemented using dedicated circuits or general-purpose processors. FPGAs (Field Programmable Gate Arrays) that can be programmed after LSI fabrication, or reconfigurable processors that can reconfigure the connections and settings of circuit cells within the LSI, can also be used.

[0166] In addition, in the above-mentioned cross-sectional views, the corners and sides of each component are shown as straight lines, but structures in which the corners and sides are rounded for manufacturing reasons are also included in the present invention.

[0167] Furthermore, at least part of the functions of the imaging devices according to the above-described embodiments and their modified examples may be combined.

[0168] In addition, the numbers used in the above are all exemplified in order to specifically illustrate the present invention, and the present invention is not limited to the exemplified numbers. Furthermore, the logic levels represented by High / Low or the switch states represented by On / Off are exemplified in order to specifically illustrate the present invention, and the same results can be obtained by different combinations of the exemplified logic levels or switch states. In addition, the n-type and p-type transistors, etc. are exemplified in order to specifically illustrate the present invention, and the same results can be obtained by reversing them. In addition, the materials of the various components shown in the above are all exemplified in order to specifically illustrate the present invention, and the present invention is not limited to the exemplified materials. In addition, the connection relationship between the components is exemplified in order to specifically illustrate the present invention, and the connection relationship for realizing the functions of the present invention is not limited thereto.

[0169] Furthermore, in the above description, an example using MOS transistors is shown, but other transistors may also be used.

[0170] Furthermore, various modifications made to the present embodiment within the scope conceivable by those skilled in the art are also included in the present invention as long as they do not depart from the spirit of the present invention.

[0171] Industrial applicability

[0172] The imaging device of the present invention is applicable not only as household products such as digital still cameras and mobile phones, but also as an image sensor in various fields such as vehicle-mounted, surveillance, and medical products.

[0173] Description of labels

[0174] 100 Camera

[0175] 101 Pixel array unit

[0176] 102 vertical scanning unit

[0177] 103 Signal holding unit

[0178] 104 horizontal scanning unit

[0179] 105 Output stage amplifier circuit section

[0180] 200 pixels

[0181] 201 Voltage Supply Circuit

[0182] 202 1st electrode

[0183] 203 Second electrode

[0184] 204, 1204 Photoelectric conversion unit

[0185] 204b Photoelectric conversion layer

[0186] 204e electron blocking layer

[0187] 204h hole blocking layer

[0188] 204n n-type semiconductor layer

[0189] 204p p-type semiconductor layer

[0190] 205 Charge storage unit

[0191] 206 amplifier transistor

[0192] 207 Select transistor

[0193] 208 vertical signal line

[0194] 301 Color Filter

[0195] 302 protective film

[0196] 305 inter-electrode insulating film

[0197] 307 Inter-wiring insulation film

[0198] 308 wiring layer

[0199] 309 substrate

[0200] 310 Trap

[0201] 311 interlayer insulating film

[0202] 400 Camera System

[0203] 401 Lens Optical System

[0204] 402 System Controller

[0205] 403 Camera Signal Processing Unit

Claims

1. A camera device, wherein: have: a photoelectric conversion portion comprising a first electrode, a second electrode opposed to the first electrode, a photoelectric conversion layer located between the first electrode and the second electrode and converting incident light into signal charges, and a blocking layer located between the photoelectric conversion layer and the second electrode; as well as a charge accumulation region connected to the second electrode and configured to accumulate the signal charge; The energy barrier of the blocking layer for the movement of charges having a polarity opposite to that of the signal charges from the second electrode to the photoelectric conversion layer is 1.8 eV or more; An energy barrier of the blocking layer for movement of charges having a polarity opposite to that of the signal charges from the photoelectric conversion layer to the second electrode is 1.6 eV or less.

2. The imaging device according to claim 1, wherein It also has a voltage supply circuit; The voltage supply circuit supplies a first voltage to the first electrode during a first period in which the signal charge is accumulated from the photoelectric conversion portion to the charge accumulation region; The voltage supply circuit supplies a second voltage different from the first voltage to the first electrode during a second period in which the signal charge accumulated in the charge accumulation region is reset.

3. The imaging device according to claim 1, wherein The signal charges mentioned above are holes; The electron affinity of the blocking layer is smaller than the work function of the second electrode, and the difference between the electron affinity of the blocking layer and the work function of the second electrode is greater than 1.8 eV; The electron affinity of the blocking layer is lower than the electron affinity of the photoelectric conversion layer, and the difference between the electron affinity of the blocking layer and the electron affinity of the photoelectric conversion layer is 1.6 eV or less.

4. The imaging device according to claim 3, wherein: The barrier layer has an ionization potential greater than that of the photoelectric conversion layer.

5. The imaging device according to claim 3 or 4, wherein: It also has a voltage supply circuit; The voltage supply circuit supplies a first voltage to the first electrode during a first period in which the signal charge is accumulated from the photoelectric conversion portion to the charge accumulation region; The voltage supply circuit supplies a second voltage, which is lower than the first voltage, to the first electrode during a second period in which the signal charge accumulated in the charge accumulation region is reset.

6. The imaging device according to claim 5, wherein: It also includes a semiconductor substrate having the charge accumulation region; During the first period, a third voltage is supplied to the semiconductor substrate; During the second period, a fourth voltage different from the third voltage is supplied to the semiconductor substrate.

7. The imaging device according to claim 6, wherein: The third voltage is smaller than the first voltage; The fourth voltage is greater than the second voltage.

8. The imaging device according to claim 1, wherein: The signal charges mentioned above are electrons; The ionization potential of the barrier layer is greater than the work function of the second electrode, and the difference between the ionization potential of the barrier layer and the work function of the second electrode is greater than 1.8 eV; The barrier layer has an ionization potential greater than that of the photoelectric conversion layer, and the difference between the ionization potentials of the barrier layer and the photoelectric conversion layer is 1.6 eV or less.

9. The imaging device according to claim 8, wherein: The electron affinity of the blocking layer is lower than the electron affinity of the photoelectric conversion layer.

10. The imaging device according to claim 8 or 9, wherein: It also has a voltage supply circuit; The voltage supply circuit supplies a first voltage to the first electrode during a first period in which the signal charge is accumulated from the photoelectric conversion portion to the charge accumulation region; The voltage supply circuit supplies a second voltage, which is larger than the first voltage, to the first electrode during a second period in which the signal charge accumulated in the charge accumulation region is reset.

11. The imaging device according to claim 10, wherein: It also includes a semiconductor substrate having the charge accumulation region; During the first period, a fifth voltage is supplied to the semiconductor substrate; During the second period, a sixth voltage different from the fifth voltage is supplied to the semiconductor substrate.

12. The imaging device according to claim 11, wherein: The fifth voltage is greater than the first voltage; The sixth voltage is lower than the second voltage.

13. The imaging device according to any one of claims 2, 5 to 7, and 10 to 12, wherein: The photoelectric conversion layer has diode characteristics; The photoelectric conversion unit has a current-voltage characteristic within the following voltage range: In a first voltage range, as the bias voltage applied to the photoelectric conversion layer increases in a direction opposite to the diode characteristic, the absolute value of the output current density of the photoelectric conversion portion increases; In a second voltage range, as the bias voltage increases toward the forward direction of the diode characteristic, the output current density increases; and a third voltage range being between the first voltage range and the second voltage range, and having a smaller absolute value of a rate of change of the output current density with respect to the bias voltage than the first voltage range and the second voltage range; By supplying the first voltage to the first electrode, the bias voltage applied to the photoelectric conversion layer is within the first voltage range; By supplying the second voltage to the first electrode, the bias voltage applied to the photoelectric conversion layer falls within the second voltage range.

14. The imaging device according to any one of claims 1 to 13, wherein: It also has a plurality of pixels arranged in a matrix; The first electrode is disposed continuously with respect to all of the plurality of pixels.

15. The imaging device according to any one of claims 1 to 13, wherein It also has a plurality of pixels arranged in a matrix; The first electrode is disposed continuously with respect to pixels located in the same row among the plurality of pixels.

16. The imaging device according to any one of claims 1 to 13, wherein: It also has a plurality of pixels arranged in a matrix; The first electrode is arranged to be separated from each of the plurality of pixels.

17. The imaging device according to any one of claims 1 to 16, wherein: further comprising an amplifying transistor including a gate connected to the second electrode; The charge accumulation region includes the gate; The gate electrode is not connected to the semiconductor substrate.

Images